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pinctrl-npcm7xx.c
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linux-6.19.14/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright (c) 2016-2018 Nuvoton Technology corporation. 3// Copyright (c) 2016, Dell Inc 4 5#include <linux/device.h> 6#include <linux/gpio/driver.h> 7#include <linux/gpio/generic.h> 8#include <linux/interrupt.h> 9#include <linux/irq.h> 10#include <linux/mfd/syscon.h> 11#include <linux/mod_devicetable.h> 12#include <linux/module.h> 13#include <linux/platform_device.h> 14#include <linux/property.h> 15#include <linux/regmap.h> 16#include <linux/seq_file.h> 17 18#include <linux/pinctrl/consumer.h> 19#include <linux/pinctrl/machine.h> 20#include <linux/pinctrl/pinconf-generic.h> 21#include <linux/pinctrl/pinconf.h> 22#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinmux.h> 24 25/* GCR registers */ 26#define NPCM7XX_GCR_PDID 0x00 27#define NPCM7XX_GCR_MFSEL1 0x0C 28#define NPCM7XX_GCR_MFSEL2 0x10 29#define NPCM7XX_GCR_MFSEL3 0x64 30#define NPCM7XX_GCR_MFSEL4 0xb0 31#define NPCM7XX_GCR_CPCTL 0xD0 32#define NPCM7XX_GCR_CP2BST 0xD4 33#define NPCM7XX_GCR_B2CPNT 0xD8 34#define NPCM7XX_GCR_I2CSEGSEL 0xE0 35#define NPCM7XX_GCR_I2CSEGCTL 0xE4 36#define NPCM7XX_GCR_SRCNT 0x68 37#define NPCM7XX_GCR_FLOCKR1 0x74 38#define NPCM7XX_GCR_DSCNT 0x78 39 40#define SRCNT_ESPI BIT(3) 41 42/* GPIO registers */ 43#define NPCM7XX_GP_N_TLOCK1 0x00 44#define NPCM7XX_GP_N_DIN 0x04 /* Data IN */ 45#define NPCM7XX_GP_N_POL 0x08 /* Polarity */ 46#define NPCM7XX_GP_N_DOUT 0x0c /* Data OUT */ 47#define NPCM7XX_GP_N_OE 0x10 /* Output Enable */ 48#define NPCM7XX_GP_N_OTYP 0x14 49#define NPCM7XX_GP_N_MP 0x18 50#define NPCM7XX_GP_N_PU 0x1c /* Pull-up */ 51#define NPCM7XX_GP_N_PD 0x20 /* Pull-down */ 52#define NPCM7XX_GP_N_DBNC 0x24 /* Debounce */ 53#define NPCM7XX_GP_N_EVTYP 0x28 /* Event Type */ 54#define NPCM7XX_GP_N_EVBE 0x2c /* Event Both Edge */ 55#define NPCM7XX_GP_N_OBL0 0x30 56#define NPCM7XX_GP_N_OBL1 0x34 57#define NPCM7XX_GP_N_OBL2 0x38 58#define NPCM7XX_GP_N_OBL3 0x3c 59#define NPCM7XX_GP_N_EVEN 0x40 /* Event Enable */ 60#define NPCM7XX_GP_N_EVENS 0x44 /* Event Set (enable) */ 61#define NPCM7XX_GP_N_EVENC 0x48 /* Event Clear (disable) */ 62#define NPCM7XX_GP_N_EVST 0x4c /* Event Status */ 63#define NPCM7XX_GP_N_SPLCK 0x50 64#define NPCM7XX_GP_N_MPLCK 0x54 65#define NPCM7XX_GP_N_IEM 0x58 /* Input Enable */ 66#define NPCM7XX_GP_N_OSRC 0x5c 67#define NPCM7XX_GP_N_ODSC 0x60 68#define NPCM7XX_GP_N_DOS 0x68 /* Data OUT Set */ 69#define NPCM7XX_GP_N_DOC 0x6c /* Data OUT Clear */ 70#define NPCM7XX_GP_N_OES 0x70 /* Output Enable Set */ 71#define NPCM7XX_GP_N_OEC 0x74 /* Output Enable Clear */ 72#define NPCM7XX_GP_N_TLOCK2 0x7c 73 74#define NPCM7XX_GPIO_PER_BANK 32 75#define NPCM7XX_GPIO_BANK_NUM 8 76#define NPCM7XX_GCR_NONE 0 77 78/* Structure for register banks */ 79struct npcm7xx_gpio { 80 void __iomem *base; 81 struct gpio_generic_chip chip; 82 int irqbase; 83 int irq; 84 u32 pinctrl_id; 85 int (*direction_input)(struct gpio_chip *chip, unsigned int offset); 86 int (*direction_output)(struct gpio_chip *chip, unsigned int offset, 87 int value); 88 int (*request)(struct gpio_chip *chip, unsigned int offset); 89 void (*free)(struct gpio_chip *chip, unsigned int offset); 90}; 91 92struct npcm7xx_pinctrl { 93 struct pinctrl_dev *pctldev; 94 struct device *dev; 95 struct npcm7xx_gpio gpio_bank[NPCM7XX_GPIO_BANK_NUM]; 96 struct irq_domain *domain; 97 struct regmap *gcr_regmap; 98 void __iomem *regs; 99 u32 bank_num; 100}; 101 102/* GPIO handling in the pinctrl driver */ 103static void npcm_gpio_set(struct gpio_generic_chip *chip, void __iomem *reg, 104 unsigned int pinmask) 105{ 106 unsigned long val; 107 108 guard(gpio_generic_lock_irqsave)(chip); 109 110 val = ioread32(reg) | pinmask; 111 iowrite32(val, reg); 112} 113 114static void npcm_gpio_clr(struct gpio_generic_chip *chip, void __iomem *reg, 115 unsigned int pinmask) 116{ 117 unsigned long val; 118 119 guard(gpio_generic_lock_irqsave)(chip); 120 121 val = ioread32(reg) & ~pinmask; 122 iowrite32(val, reg); 123} 124 125static void npcmgpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 126{ 127 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 128 129 seq_printf(s, "-- module %d [gpio%d - %d]\n", 130 bank->chip.gc.base / bank->chip.gc.ngpio, 131 bank->chip.gc.base, 132 bank->chip.gc.base + bank->chip.gc.ngpio); 133 seq_printf(s, "DIN :%.8x DOUT:%.8x IE :%.8x OE :%.8x\n", 134 ioread32(bank->base + NPCM7XX_GP_N_DIN), 135 ioread32(bank->base + NPCM7XX_GP_N_DOUT), 136 ioread32(bank->base + NPCM7XX_GP_N_IEM), 137 ioread32(bank->base + NPCM7XX_GP_N_OE)); 138 seq_printf(s, "PU :%.8x PD :%.8x DB :%.8x POL :%.8x\n", 139 ioread32(bank->base + NPCM7XX_GP_N_PU), 140 ioread32(bank->base + NPCM7XX_GP_N_PD), 141 ioread32(bank->base + NPCM7XX_GP_N_DBNC), 142 ioread32(bank->base + NPCM7XX_GP_N_POL)); 143 seq_printf(s, "ETYP:%.8x EVBE:%.8x EVEN:%.8x EVST:%.8x\n", 144 ioread32(bank->base + NPCM7XX_GP_N_EVTYP), 145 ioread32(bank->base + NPCM7XX_GP_N_EVBE), 146 ioread32(bank->base + NPCM7XX_GP_N_EVEN), 147 ioread32(bank->base + NPCM7XX_GP_N_EVST)); 148 seq_printf(s, "OTYP:%.8x OSRC:%.8x ODSC:%.8x\n", 149 ioread32(bank->base + NPCM7XX_GP_N_OTYP), 150 ioread32(bank->base + NPCM7XX_GP_N_OSRC), 151 ioread32(bank->base + NPCM7XX_GP_N_ODSC)); 152 seq_printf(s, "OBL0:%.8x OBL1:%.8x OBL2:%.8x OBL3:%.8x\n", 153 ioread32(bank->base + NPCM7XX_GP_N_OBL0), 154 ioread32(bank->base + NPCM7XX_GP_N_OBL1), 155 ioread32(bank->base + NPCM7XX_GP_N_OBL2), 156 ioread32(bank->base + NPCM7XX_GP_N_OBL3)); 157 seq_printf(s, "SLCK:%.8x MLCK:%.8x\n", 158 ioread32(bank->base + NPCM7XX_GP_N_SPLCK), 159 ioread32(bank->base + NPCM7XX_GP_N_MPLCK)); 160} 161 162static int npcmgpio_direction_input(struct gpio_chip *chip, unsigned int offset) 163{ 164 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 165 int ret; 166 167 ret = pinctrl_gpio_direction_input(chip, offset); 168 if (ret) 169 return ret; 170 171 return bank->direction_input(chip, offset); 172} 173 174/* Set GPIO to Output with initial value */ 175static int npcmgpio_direction_output(struct gpio_chip *chip, 176 unsigned int offset, int value) 177{ 178 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 179 int ret; 180 181 dev_dbg(chip->parent, "gpio_direction_output: offset%d = %x\n", offset, 182 value); 183 184 ret = pinctrl_gpio_direction_output(chip, offset); 185 if (ret) 186 return ret; 187 188 return bank->direction_output(chip, offset, value); 189} 190 191static int npcmgpio_gpio_request(struct gpio_chip *chip, unsigned int offset) 192{ 193 struct npcm7xx_gpio *bank = gpiochip_get_data(chip); 194 int ret; 195 196 dev_dbg(chip->parent, "gpio_request: offset%d\n", offset); 197 ret = pinctrl_gpio_request(chip, offset); 198 if (ret) 199 return ret; 200 201 return bank->request(chip, offset); 202} 203 204static void npcmgpio_irq_handler(struct irq_desc *desc) 205{ 206 struct gpio_chip *gc; 207 struct irq_chip *chip; 208 struct npcm7xx_gpio *bank; 209 unsigned long sts, en, bit; 210 211 gc = irq_desc_get_handler_data(desc); 212 bank = gpiochip_get_data(gc); 213 chip = irq_desc_get_chip(desc); 214 215 chained_irq_enter(chip, desc); 216 sts = ioread32(bank->base + NPCM7XX_GP_N_EVST); 217 en = ioread32(bank->base + NPCM7XX_GP_N_EVEN); 218 dev_dbg(bank->chip.gc.parent, "==> got irq sts %.8lx %.8lx\n", sts, 219 en); 220 221 sts &= en; 222 for_each_set_bit(bit, &sts, NPCM7XX_GPIO_PER_BANK) 223 generic_handle_domain_irq(gc->irq.domain, bit); 224 chained_irq_exit(chip, desc); 225} 226 227static int npcmgpio_set_irq_type(struct irq_data *d, unsigned int type) 228{ 229 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 230 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 231 unsigned int gpio = BIT(irqd_to_hwirq(d)); 232 233 dev_dbg(bank->chip.gc.parent, "setirqtype: %u.%u = %u\n", gpio, 234 d->irq, type); 235 switch (type) { 236 case IRQ_TYPE_EDGE_RISING: 237 dev_dbg(bank->chip.gc.parent, "edge.rising\n"); 238 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 239 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 240 break; 241 case IRQ_TYPE_EDGE_FALLING: 242 dev_dbg(bank->chip.gc.parent, "edge.falling\n"); 243 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 244 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 245 break; 246 case IRQ_TYPE_EDGE_BOTH: 247 dev_dbg(bank->chip.gc.parent, "edge.both\n"); 248 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVBE, gpio); 249 break; 250 case IRQ_TYPE_LEVEL_LOW: 251 dev_dbg(bank->chip.gc.parent, "level.low\n"); 252 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 253 break; 254 case IRQ_TYPE_LEVEL_HIGH: 255 dev_dbg(bank->chip.gc.parent, "level.high\n"); 256 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_POL, gpio); 257 break; 258 default: 259 dev_dbg(bank->chip.gc.parent, "invalid irq type\n"); 260 return -EINVAL; 261 } 262 263 if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 264 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 265 irq_set_handler_locked(d, handle_level_irq); 266 } else if (type & (IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_EDGE_RISING 267 | IRQ_TYPE_EDGE_FALLING)) { 268 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_EVTYP, gpio); 269 irq_set_handler_locked(d, handle_edge_irq); 270 } 271 272 return 0; 273} 274 275static void npcmgpio_irq_ack(struct irq_data *d) 276{ 277 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 278 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 279 unsigned int gpio = irqd_to_hwirq(d); 280 281 dev_dbg(bank->chip.gc.parent, "irq_ack: %u.%u\n", gpio, d->irq); 282 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVST); 283} 284 285/* Disable GPIO interrupt */ 286static void npcmgpio_irq_mask(struct irq_data *d) 287{ 288 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 289 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 290 unsigned int gpio = irqd_to_hwirq(d); 291 292 /* Clear events */ 293 dev_dbg(bank->chip.gc.parent, "irq_mask: %u.%u\n", gpio, d->irq); 294 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENC); 295 gpiochip_disable_irq(gc, gpio); 296} 297 298/* Enable GPIO interrupt */ 299static void npcmgpio_irq_unmask(struct irq_data *d) 300{ 301 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 302 struct npcm7xx_gpio *bank = gpiochip_get_data(gc); 303 unsigned int gpio = irqd_to_hwirq(d); 304 305 /* Enable events */ 306 gpiochip_enable_irq(gc, gpio); 307 dev_dbg(bank->chip.gc.parent, "irq_unmask: %u.%u\n", gpio, d->irq); 308 iowrite32(BIT(gpio), bank->base + NPCM7XX_GP_N_EVENS); 309} 310 311static unsigned int npcmgpio_irq_startup(struct irq_data *d) 312{ 313 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 314 unsigned int gpio = irqd_to_hwirq(d); 315 316 /* active-high, input, clear interrupt, enable interrupt */ 317 dev_dbg(gc->parent, "startup: %u.%u\n", gpio, d->irq); 318 npcmgpio_direction_input(gc, gpio); 319 npcmgpio_irq_ack(d); 320 npcmgpio_irq_unmask(d); 321 322 return 0; 323} 324 325static const struct irq_chip npcmgpio_irqchip = { 326 .name = "NPCM7XX-GPIO-IRQ", 327 .irq_ack = npcmgpio_irq_ack, 328 .irq_unmask = npcmgpio_irq_unmask, 329 .irq_mask = npcmgpio_irq_mask, 330 .irq_set_type = npcmgpio_set_irq_type, 331 .irq_startup = npcmgpio_irq_startup, 332 .flags = IRQCHIP_IMMUTABLE, 333 GPIOCHIP_IRQ_RESOURCE_HELPERS, 334}; 335 336/* pinmux handing in the pinctrl driver*/ 337static const int smb0_pins[] = { 115, 114 }; 338static const int smb0b_pins[] = { 195, 194 }; 339static const int smb0c_pins[] = { 202, 196 }; 340static const int smb0d_pins[] = { 198, 199 }; 341static const int smb0den_pins[] = { 197 }; 342 343static const int smb1_pins[] = { 117, 116 }; 344static const int smb1b_pins[] = { 126, 127 }; 345static const int smb1c_pins[] = { 124, 125 }; 346static const int smb1d_pins[] = { 4, 5 }; 347 348static const int smb2_pins[] = { 119, 118 }; 349static const int smb2b_pins[] = { 122, 123 }; 350static const int smb2c_pins[] = { 120, 121 }; 351static const int smb2d_pins[] = { 6, 7 }; 352 353static const int smb3_pins[] = { 30, 31 }; 354static const int smb3b_pins[] = { 39, 40 }; 355static const int smb3c_pins[] = { 37, 38 }; 356static const int smb3d_pins[] = { 59, 60 }; 357 358static const int smb4_pins[] = { 28, 29 }; 359static const int smb4b_pins[] = { 18, 19 }; 360static const int smb4c_pins[] = { 20, 21 }; 361static const int smb4d_pins[] = { 22, 23 }; 362static const int smb4den_pins[] = { 17 }; 363 364static const int smb5_pins[] = { 26, 27 }; 365static const int smb5b_pins[] = { 13, 12 }; 366static const int smb5c_pins[] = { 15, 14 }; 367static const int smb5d_pins[] = { 94, 93 }; 368static const int ga20kbc_pins[] = { 94, 93 }; 369 370static const int smb6_pins[] = { 172, 171 }; 371static const int smb7_pins[] = { 174, 173 }; 372static const int smb8_pins[] = { 129, 128 }; 373static const int smb9_pins[] = { 131, 130 }; 374static const int smb10_pins[] = { 133, 132 }; 375static const int smb11_pins[] = { 135, 134 }; 376static const int smb12_pins[] = { 221, 220 }; 377static const int smb13_pins[] = { 223, 222 }; 378static const int smb14_pins[] = { 22, 23 }; 379static const int smb15_pins[] = { 20, 21 }; 380 381static const int fanin0_pins[] = { 64 }; 382static const int fanin1_pins[] = { 65 }; 383static const int fanin2_pins[] = { 66 }; 384static const int fanin3_pins[] = { 67 }; 385static const int fanin4_pins[] = { 68 }; 386static const int fanin5_pins[] = { 69 }; 387static const int fanin6_pins[] = { 70 }; 388static const int fanin7_pins[] = { 71 }; 389static const int fanin8_pins[] = { 72 }; 390static const int fanin9_pins[] = { 73 }; 391static const int fanin10_pins[] = { 74 }; 392static const int fanin11_pins[] = { 75 }; 393static const int fanin12_pins[] = { 76 }; 394static const int fanin13_pins[] = { 77 }; 395static const int fanin14_pins[] = { 78 }; 396static const int fanin15_pins[] = { 79 }; 397static const int faninx_pins[] = { 175, 176, 177, 203 }; 398 399static const int pwm0_pins[] = { 80 }; 400static const int pwm1_pins[] = { 81 }; 401static const int pwm2_pins[] = { 82 }; 402static const int pwm3_pins[] = { 83 }; 403static const int pwm4_pins[] = { 144 }; 404static const int pwm5_pins[] = { 145 }; 405static const int pwm6_pins[] = { 146 }; 406static const int pwm7_pins[] = { 147 }; 407 408static const int uart1_pins[] = { 43, 44, 45, 46, 47, 61, 62, 63 }; 409static const int uart2_pins[] = { 48, 49, 50, 51, 52, 53, 54, 55 }; 410 411/* RGMII 1 pin group */ 412static const int rg1_pins[] = { 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 413 106, 107 }; 414/* RGMII 1 MD interface pin group */ 415static const int rg1mdio_pins[] = { 108, 109 }; 416 417/* RGMII 2 pin group */ 418static const int rg2_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, 419 213, 214, 215 }; 420/* RGMII 2 MD interface pin group */ 421static const int rg2mdio_pins[] = { 216, 217 }; 422 423static const int ddr_pins[] = { 110, 111, 112, 113, 208, 209, 210, 211, 212, 424 213, 214, 215, 216, 217 }; 425/* Serial I/O Expander 1 */ 426static const int iox1_pins[] = { 0, 1, 2, 3 }; 427/* Serial I/O Expander 2 */ 428static const int iox2_pins[] = { 4, 5, 6, 7 }; 429/* Host Serial I/O Expander 2 */ 430static const int ioxh_pins[] = { 10, 11, 24, 25 }; 431 432static const int mmc_pins[] = { 152, 154, 156, 157, 158, 159 }; 433static const int mmcwp_pins[] = { 153 }; 434static const int mmccd_pins[] = { 155 }; 435static const int mmcrst_pins[] = { 155 }; 436static const int mmc8_pins[] = { 148, 149, 150, 151 }; 437 438/* RMII 1 pin groups */ 439static const int r1_pins[] = { 178, 179, 180, 181, 182, 193, 201 }; 440static const int r1err_pins[] = { 56 }; 441static const int r1md_pins[] = { 57, 58 }; 442 443/* RMII 2 pin groups */ 444static const int r2_pins[] = { 84, 85, 86, 87, 88, 89, 200 }; 445static const int r2err_pins[] = { 90 }; 446static const int r2md_pins[] = { 91, 92 }; 447 448static const int sd1_pins[] = { 136, 137, 138, 139, 140, 141, 142, 143 }; 449static const int sd1pwr_pins[] = { 143 }; 450 451static const int wdog1_pins[] = { 218 }; 452static const int wdog2_pins[] = { 219 }; 453 454/* BMC serial port 0 */ 455static const int bmcuart0a_pins[] = { 41, 42 }; 456static const int bmcuart0b_pins[] = { 48, 49 }; 457 458static const int bmcuart1_pins[] = { 43, 44, 62, 63 }; 459 460/* System Control Interrupt and Power Management Event pin group */ 461static const int scipme_pins[] = { 169 }; 462/* System Management Interrupt pin group */ 463static const int sci_pins[] = { 170 }; 464/* Serial Interrupt Line pin group */ 465static const int serirq_pins[] = { 162 }; 466 467static const int clkout_pins[] = { 160 }; 468static const int clkreq_pins[] = { 231 }; 469 470static const int jtag2_pins[] = { 43, 44, 45, 46, 47 }; 471/* Graphics SPI Clock pin group */ 472static const int gspi_pins[] = { 12, 13, 14, 15 }; 473 474static const int spix_pins[] = { 224, 225, 226, 227, 229, 230 }; 475static const int spixcs1_pins[] = { 228 }; 476 477static const int pspi1_pins[] = { 175, 176, 177 }; 478static const int pspi2_pins[] = { 17, 18, 19 }; 479 480static const int spi0cs1_pins[] = { 32 }; 481 482static const int spi3_pins[] = { 183, 184, 185, 186 }; 483static const int spi3cs1_pins[] = { 187 }; 484static const int spi3quad_pins[] = { 188, 189 }; 485static const int spi3cs2_pins[] = { 188 }; 486static const int spi3cs3_pins[] = { 189 }; 487 488static const int ddc_pins[] = { 204, 205, 206, 207 }; 489 490static const int lpc_pins[] = { 95, 161, 163, 164, 165, 166, 167 }; 491static const int lpcclk_pins[] = { 168 }; 492static const int espi_pins[] = { 95, 161, 163, 164, 165, 166, 167, 168 }; 493 494static const int lkgpo0_pins[] = { 16 }; 495static const int lkgpo1_pins[] = { 8 }; 496static const int lkgpo2_pins[] = { 9 }; 497 498static const int nprd_smi_pins[] = { 190 }; 499 500#define NPCM7XX_GRPS \ 501 NPCM7XX_GRP(smb0), \ 502 NPCM7XX_GRP(smb0b), \ 503 NPCM7XX_GRP(smb0c), \ 504 NPCM7XX_GRP(smb0d), \ 505 NPCM7XX_GRP(smb0den), \ 506 NPCM7XX_GRP(smb1), \ 507 NPCM7XX_GRP(smb1b), \ 508 NPCM7XX_GRP(smb1c), \ 509 NPCM7XX_GRP(smb1d), \ 510 NPCM7XX_GRP(smb2), \ 511 NPCM7XX_GRP(smb2b), \ 512 NPCM7XX_GRP(smb2c), \ 513 NPCM7XX_GRP(smb2d), \ 514 NPCM7XX_GRP(smb3), \ 515 NPCM7XX_GRP(smb3b), \ 516 NPCM7XX_GRP(smb3c), \ 517 NPCM7XX_GRP(smb3d), \ 518 NPCM7XX_GRP(smb4), \ 519 NPCM7XX_GRP(smb4b), \ 520 NPCM7XX_GRP(smb4c), \ 521 NPCM7XX_GRP(smb4d), \ 522 NPCM7XX_GRP(smb4den), \ 523 NPCM7XX_GRP(smb5), \ 524 NPCM7XX_GRP(smb5b), \ 525 NPCM7XX_GRP(smb5c), \ 526 NPCM7XX_GRP(smb5d), \ 527 NPCM7XX_GRP(ga20kbc), \ 528 NPCM7XX_GRP(smb6), \ 529 NPCM7XX_GRP(smb7), \ 530 NPCM7XX_GRP(smb8), \ 531 NPCM7XX_GRP(smb9), \ 532 NPCM7XX_GRP(smb10), \ 533 NPCM7XX_GRP(smb11), \ 534 NPCM7XX_GRP(smb12), \ 535 NPCM7XX_GRP(smb13), \ 536 NPCM7XX_GRP(smb14), \ 537 NPCM7XX_GRP(smb15), \ 538 NPCM7XX_GRP(fanin0), \ 539 NPCM7XX_GRP(fanin1), \ 540 NPCM7XX_GRP(fanin2), \ 541 NPCM7XX_GRP(fanin3), \ 542 NPCM7XX_GRP(fanin4), \ 543 NPCM7XX_GRP(fanin5), \ 544 NPCM7XX_GRP(fanin6), \ 545 NPCM7XX_GRP(fanin7), \ 546 NPCM7XX_GRP(fanin8), \ 547 NPCM7XX_GRP(fanin9), \ 548 NPCM7XX_GRP(fanin10), \ 549 NPCM7XX_GRP(fanin11), \ 550 NPCM7XX_GRP(fanin12), \ 551 NPCM7XX_GRP(fanin13), \ 552 NPCM7XX_GRP(fanin14), \ 553 NPCM7XX_GRP(fanin15), \ 554 NPCM7XX_GRP(faninx), \ 555 NPCM7XX_GRP(pwm0), \ 556 NPCM7XX_GRP(pwm1), \ 557 NPCM7XX_GRP(pwm2), \ 558 NPCM7XX_GRP(pwm3), \ 559 NPCM7XX_GRP(pwm4), \ 560 NPCM7XX_GRP(pwm5), \ 561 NPCM7XX_GRP(pwm6), \ 562 NPCM7XX_GRP(pwm7), \ 563 NPCM7XX_GRP(rg1), \ 564 NPCM7XX_GRP(rg1mdio), \ 565 NPCM7XX_GRP(rg2), \ 566 NPCM7XX_GRP(rg2mdio), \ 567 NPCM7XX_GRP(ddr), \ 568 NPCM7XX_GRP(uart1), \ 569 NPCM7XX_GRP(uart2), \ 570 NPCM7XX_GRP(bmcuart0a), \ 571 NPCM7XX_GRP(bmcuart0b), \ 572 NPCM7XX_GRP(bmcuart1), \ 573 NPCM7XX_GRP(iox1), \ 574 NPCM7XX_GRP(iox2), \ 575 NPCM7XX_GRP(ioxh), \ 576 NPCM7XX_GRP(gspi), \ 577 NPCM7XX_GRP(mmc), \ 578 NPCM7XX_GRP(mmcwp), \ 579 NPCM7XX_GRP(mmccd), \ 580 NPCM7XX_GRP(mmcrst), \ 581 NPCM7XX_GRP(mmc8), \ 582 NPCM7XX_GRP(r1), \ 583 NPCM7XX_GRP(r1err), \ 584 NPCM7XX_GRP(r1md), \ 585 NPCM7XX_GRP(r2), \ 586 NPCM7XX_GRP(r2err), \ 587 NPCM7XX_GRP(r2md), \ 588 NPCM7XX_GRP(sd1), \ 589 NPCM7XX_GRP(sd1pwr), \ 590 NPCM7XX_GRP(wdog1), \ 591 NPCM7XX_GRP(wdog2), \ 592 NPCM7XX_GRP(scipme), \ 593 NPCM7XX_GRP(sci), \ 594 NPCM7XX_GRP(serirq), \ 595 NPCM7XX_GRP(jtag2), \ 596 NPCM7XX_GRP(spix), \ 597 NPCM7XX_GRP(spixcs1), \ 598 NPCM7XX_GRP(pspi1), \ 599 NPCM7XX_GRP(pspi2), \ 600 NPCM7XX_GRP(ddc), \ 601 NPCM7XX_GRP(clkreq), \ 602 NPCM7XX_GRP(clkout), \ 603 NPCM7XX_GRP(spi3), \ 604 NPCM7XX_GRP(spi3cs1), \ 605 NPCM7XX_GRP(spi3quad), \ 606 NPCM7XX_GRP(spi3cs2), \ 607 NPCM7XX_GRP(spi3cs3), \ 608 NPCM7XX_GRP(spi0cs1), \ 609 NPCM7XX_GRP(lpc), \ 610 NPCM7XX_GRP(lpcclk), \ 611 NPCM7XX_GRP(espi), \ 612 NPCM7XX_GRP(lkgpo0), \ 613 NPCM7XX_GRP(lkgpo1), \ 614 NPCM7XX_GRP(lkgpo2), \ 615 NPCM7XX_GRP(nprd_smi), \ 616 \ 617 618enum { 619#define NPCM7XX_GRP(x) fn_ ## x 620 NPCM7XX_GRPS 621 /* add placeholder for none/gpio */ 622 NPCM7XX_GRP(none), 623 NPCM7XX_GRP(gpio), 624#undef NPCM7XX_GRP 625}; 626 627static struct pingroup npcm7xx_groups[] = { 628#define NPCM7XX_GRP(x) PINCTRL_PINGROUP(#x, x ## _pins, ARRAY_SIZE(x ## _pins)) 629 NPCM7XX_GRPS 630#undef NPCM7XX_GRP 631}; 632 633#define NPCM7XX_SFUNC(a) NPCM7XX_FUNC(a, #a) 634#define NPCM7XX_FUNC(a, b...) static const char *a ## _grp[] = { b } 635 636NPCM7XX_SFUNC(smb0); 637NPCM7XX_SFUNC(smb0b); 638NPCM7XX_SFUNC(smb0c); 639NPCM7XX_SFUNC(smb0d); 640NPCM7XX_SFUNC(smb0den); 641NPCM7XX_SFUNC(smb1); 642NPCM7XX_SFUNC(smb1b); 643NPCM7XX_SFUNC(smb1c); 644NPCM7XX_SFUNC(smb1d); 645NPCM7XX_SFUNC(smb2); 646NPCM7XX_SFUNC(smb2b); 647NPCM7XX_SFUNC(smb2c); 648NPCM7XX_SFUNC(smb2d); 649NPCM7XX_SFUNC(smb3); 650NPCM7XX_SFUNC(smb3b); 651NPCM7XX_SFUNC(smb3c); 652NPCM7XX_SFUNC(smb3d); 653NPCM7XX_SFUNC(smb4); 654NPCM7XX_SFUNC(smb4b); 655NPCM7XX_SFUNC(smb4c); 656NPCM7XX_SFUNC(smb4d); 657NPCM7XX_SFUNC(smb4den); 658NPCM7XX_SFUNC(smb5); 659NPCM7XX_SFUNC(smb5b); 660NPCM7XX_SFUNC(smb5c); 661NPCM7XX_SFUNC(smb5d); 662NPCM7XX_SFUNC(ga20kbc); 663NPCM7XX_SFUNC(smb6); 664NPCM7XX_SFUNC(smb7); 665NPCM7XX_SFUNC(smb8); 666NPCM7XX_SFUNC(smb9); 667NPCM7XX_SFUNC(smb10); 668NPCM7XX_SFUNC(smb11); 669NPCM7XX_SFUNC(smb12); 670NPCM7XX_SFUNC(smb13); 671NPCM7XX_SFUNC(smb14); 672NPCM7XX_SFUNC(smb15); 673NPCM7XX_SFUNC(fanin0); 674NPCM7XX_SFUNC(fanin1); 675NPCM7XX_SFUNC(fanin2); 676NPCM7XX_SFUNC(fanin3); 677NPCM7XX_SFUNC(fanin4); 678NPCM7XX_SFUNC(fanin5); 679NPCM7XX_SFUNC(fanin6); 680NPCM7XX_SFUNC(fanin7); 681NPCM7XX_SFUNC(fanin8); 682NPCM7XX_SFUNC(fanin9); 683NPCM7XX_SFUNC(fanin10); 684NPCM7XX_SFUNC(fanin11); 685NPCM7XX_SFUNC(fanin12); 686NPCM7XX_SFUNC(fanin13); 687NPCM7XX_SFUNC(fanin14); 688NPCM7XX_SFUNC(fanin15); 689NPCM7XX_SFUNC(faninx); 690NPCM7XX_SFUNC(pwm0); 691NPCM7XX_SFUNC(pwm1); 692NPCM7XX_SFUNC(pwm2); 693NPCM7XX_SFUNC(pwm3); 694NPCM7XX_SFUNC(pwm4); 695NPCM7XX_SFUNC(pwm5); 696NPCM7XX_SFUNC(pwm6); 697NPCM7XX_SFUNC(pwm7); 698NPCM7XX_SFUNC(rg1); 699NPCM7XX_SFUNC(rg1mdio); 700NPCM7XX_SFUNC(rg2); 701NPCM7XX_SFUNC(rg2mdio); 702NPCM7XX_SFUNC(ddr); 703NPCM7XX_SFUNC(uart1); 704NPCM7XX_SFUNC(uart2); 705NPCM7XX_SFUNC(bmcuart0a); 706NPCM7XX_SFUNC(bmcuart0b); 707NPCM7XX_SFUNC(bmcuart1); 708NPCM7XX_SFUNC(iox1); 709NPCM7XX_SFUNC(iox2); 710NPCM7XX_SFUNC(ioxh); 711NPCM7XX_SFUNC(gspi); 712NPCM7XX_SFUNC(mmc); 713NPCM7XX_SFUNC(mmcwp); 714NPCM7XX_SFUNC(mmccd); 715NPCM7XX_SFUNC(mmcrst); 716NPCM7XX_SFUNC(mmc8); 717NPCM7XX_SFUNC(r1); 718NPCM7XX_SFUNC(r1err); 719NPCM7XX_SFUNC(r1md); 720NPCM7XX_SFUNC(r2); 721NPCM7XX_SFUNC(r2err); 722NPCM7XX_SFUNC(r2md); 723NPCM7XX_SFUNC(sd1); 724NPCM7XX_SFUNC(sd1pwr); 725NPCM7XX_SFUNC(wdog1); 726NPCM7XX_SFUNC(wdog2); 727NPCM7XX_SFUNC(scipme); 728NPCM7XX_SFUNC(sci); 729NPCM7XX_SFUNC(serirq); 730NPCM7XX_SFUNC(jtag2); 731NPCM7XX_SFUNC(spix); 732NPCM7XX_SFUNC(spixcs1); 733NPCM7XX_SFUNC(pspi1); 734NPCM7XX_SFUNC(pspi2); 735NPCM7XX_SFUNC(ddc); 736NPCM7XX_SFUNC(clkreq); 737NPCM7XX_SFUNC(clkout); 738NPCM7XX_SFUNC(spi3); 739NPCM7XX_SFUNC(spi3cs1); 740NPCM7XX_SFUNC(spi3quad); 741NPCM7XX_SFUNC(spi3cs2); 742NPCM7XX_SFUNC(spi3cs3); 743NPCM7XX_SFUNC(spi0cs1); 744NPCM7XX_SFUNC(lpc); 745NPCM7XX_SFUNC(lpcclk); 746NPCM7XX_SFUNC(espi); 747NPCM7XX_SFUNC(lkgpo0); 748NPCM7XX_SFUNC(lkgpo1); 749NPCM7XX_SFUNC(lkgpo2); 750NPCM7XX_SFUNC(nprd_smi); 751 752/* Function names */ 753static struct pinfunction npcm7xx_funcs[] = { 754#define NPCM7XX_MKFUNC(nm) PINCTRL_PINFUNCTION(#nm, nm ## _grp, ARRAY_SIZE(nm ## _grp)) 755 NPCM7XX_MKFUNC(smb0), 756 NPCM7XX_MKFUNC(smb0b), 757 NPCM7XX_MKFUNC(smb0c), 758 NPCM7XX_MKFUNC(smb0d), 759 NPCM7XX_MKFUNC(smb0den), 760 NPCM7XX_MKFUNC(smb1), 761 NPCM7XX_MKFUNC(smb1b), 762 NPCM7XX_MKFUNC(smb1c), 763 NPCM7XX_MKFUNC(smb1d), 764 NPCM7XX_MKFUNC(smb2), 765 NPCM7XX_MKFUNC(smb2b), 766 NPCM7XX_MKFUNC(smb2c), 767 NPCM7XX_MKFUNC(smb2d), 768 NPCM7XX_MKFUNC(smb3), 769 NPCM7XX_MKFUNC(smb3b), 770 NPCM7XX_MKFUNC(smb3c), 771 NPCM7XX_MKFUNC(smb3d), 772 NPCM7XX_MKFUNC(smb4), 773 NPCM7XX_MKFUNC(smb4b), 774 NPCM7XX_MKFUNC(smb4c), 775 NPCM7XX_MKFUNC(smb4d), 776 NPCM7XX_MKFUNC(smb4den), 777 NPCM7XX_MKFUNC(smb5), 778 NPCM7XX_MKFUNC(smb5b), 779 NPCM7XX_MKFUNC(smb5c), 780 NPCM7XX_MKFUNC(smb5d), 781 NPCM7XX_MKFUNC(ga20kbc), 782 NPCM7XX_MKFUNC(smb6), 783 NPCM7XX_MKFUNC(smb7), 784 NPCM7XX_MKFUNC(smb8), 785 NPCM7XX_MKFUNC(smb9), 786 NPCM7XX_MKFUNC(smb10), 787 NPCM7XX_MKFUNC(smb11), 788 NPCM7XX_MKFUNC(smb12), 789 NPCM7XX_MKFUNC(smb13), 790 NPCM7XX_MKFUNC(smb14), 791 NPCM7XX_MKFUNC(smb15), 792 NPCM7XX_MKFUNC(fanin0), 793 NPCM7XX_MKFUNC(fanin1), 794 NPCM7XX_MKFUNC(fanin2), 795 NPCM7XX_MKFUNC(fanin3), 796 NPCM7XX_MKFUNC(fanin4), 797 NPCM7XX_MKFUNC(fanin5), 798 NPCM7XX_MKFUNC(fanin6), 799 NPCM7XX_MKFUNC(fanin7), 800 NPCM7XX_MKFUNC(fanin8), 801 NPCM7XX_MKFUNC(fanin9), 802 NPCM7XX_MKFUNC(fanin10), 803 NPCM7XX_MKFUNC(fanin11), 804 NPCM7XX_MKFUNC(fanin12), 805 NPCM7XX_MKFUNC(fanin13), 806 NPCM7XX_MKFUNC(fanin14), 807 NPCM7XX_MKFUNC(fanin15), 808 NPCM7XX_MKFUNC(faninx), 809 NPCM7XX_MKFUNC(pwm0), 810 NPCM7XX_MKFUNC(pwm1), 811 NPCM7XX_MKFUNC(pwm2), 812 NPCM7XX_MKFUNC(pwm3), 813 NPCM7XX_MKFUNC(pwm4), 814 NPCM7XX_MKFUNC(pwm5), 815 NPCM7XX_MKFUNC(pwm6), 816 NPCM7XX_MKFUNC(pwm7), 817 NPCM7XX_MKFUNC(rg1), 818 NPCM7XX_MKFUNC(rg1mdio), 819 NPCM7XX_MKFUNC(rg2), 820 NPCM7XX_MKFUNC(rg2mdio), 821 NPCM7XX_MKFUNC(ddr), 822 NPCM7XX_MKFUNC(uart1), 823 NPCM7XX_MKFUNC(uart2), 824 NPCM7XX_MKFUNC(bmcuart0a), 825 NPCM7XX_MKFUNC(bmcuart0b), 826 NPCM7XX_MKFUNC(bmcuart1), 827 NPCM7XX_MKFUNC(iox1), 828 NPCM7XX_MKFUNC(iox2), 829 NPCM7XX_MKFUNC(ioxh), 830 NPCM7XX_MKFUNC(gspi), 831 NPCM7XX_MKFUNC(mmc), 832 NPCM7XX_MKFUNC(mmcwp), 833 NPCM7XX_MKFUNC(mmccd), 834 NPCM7XX_MKFUNC(mmcrst), 835 NPCM7XX_MKFUNC(mmc8), 836 NPCM7XX_MKFUNC(r1), 837 NPCM7XX_MKFUNC(r1err), 838 NPCM7XX_MKFUNC(r1md), 839 NPCM7XX_MKFUNC(r2), 840 NPCM7XX_MKFUNC(r2err), 841 NPCM7XX_MKFUNC(r2md), 842 NPCM7XX_MKFUNC(sd1), 843 NPCM7XX_MKFUNC(sd1pwr), 844 NPCM7XX_MKFUNC(wdog1), 845 NPCM7XX_MKFUNC(wdog2), 846 NPCM7XX_MKFUNC(scipme), 847 NPCM7XX_MKFUNC(sci), 848 NPCM7XX_MKFUNC(serirq), 849 NPCM7XX_MKFUNC(jtag2), 850 NPCM7XX_MKFUNC(spix), 851 NPCM7XX_MKFUNC(spixcs1), 852 NPCM7XX_MKFUNC(pspi1), 853 NPCM7XX_MKFUNC(pspi2), 854 NPCM7XX_MKFUNC(ddc), 855 NPCM7XX_MKFUNC(clkreq), 856 NPCM7XX_MKFUNC(clkout), 857 NPCM7XX_MKFUNC(spi3), 858 NPCM7XX_MKFUNC(spi3cs1), 859 NPCM7XX_MKFUNC(spi3quad), 860 NPCM7XX_MKFUNC(spi3cs2), 861 NPCM7XX_MKFUNC(spi3cs3), 862 NPCM7XX_MKFUNC(spi0cs1), 863 NPCM7XX_MKFUNC(lpc), 864 NPCM7XX_MKFUNC(lpcclk), 865 NPCM7XX_MKFUNC(espi), 866 NPCM7XX_MKFUNC(lkgpo0), 867 NPCM7XX_MKFUNC(lkgpo1), 868 NPCM7XX_MKFUNC(lkgpo2), 869 NPCM7XX_MKFUNC(nprd_smi), 870#undef NPCM7XX_MKFUNC 871}; 872 873#define NPCM7XX_PINCFG(a, b, c, d, e, f, g, h, i, j, k) \ 874 [a] = { .fn0 = fn_ ## b, .reg0 = NPCM7XX_GCR_ ## c, .bit0 = d, \ 875 .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \ 876 .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \ 877 .flag = k } 878 879/* Drive strength controlled by NPCM7XX_GP_N_ODSC */ 880#define DRIVE_STRENGTH_LO_SHIFT 8 881#define DRIVE_STRENGTH_HI_SHIFT 12 882#define DRIVE_STRENGTH_MASK 0x0000FF00 883 884#define DSTR(lo, hi) (((lo) << DRIVE_STRENGTH_LO_SHIFT) | \ 885 ((hi) << DRIVE_STRENGTH_HI_SHIFT)) 886#define DSLO(x) (((x) >> DRIVE_STRENGTH_LO_SHIFT) & 0xF) 887#define DSHI(x) (((x) >> DRIVE_STRENGTH_HI_SHIFT) & 0xF) 888 889#define GPI 0x1 /* Not GPO */ 890#define GPO 0x2 /* Not GPI */ 891#define SLEW 0x4 /* Has Slew Control, NPCM7XX_GP_N_OSRC */ 892#define SLEWLPC 0x8 /* Has Slew Control, SRCNT.3 */ 893 894struct npcm7xx_pincfg { 895 int flag; 896 int fn0, reg0, bit0; 897 int fn1, reg1, bit1; 898 int fn2, reg2, bit2; 899}; 900 901static const struct npcm7xx_pincfg pincfg[] = { 902 /* PIN FUNCTION 1 FUNCTION 2 FUNCTION 3 FLAGS */ 903 NPCM7XX_PINCFG(0, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), 904 NPCM7XX_PINCFG(1, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 905 NPCM7XX_PINCFG(2, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 906 NPCM7XX_PINCFG(3, iox1, MFSEL1, 30, none, NONE, 0, none, NONE, 0, 0), 907 NPCM7XX_PINCFG(4, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), 908 NPCM7XX_PINCFG(5, iox2, MFSEL3, 14, smb1d, I2CSEGSEL, 7, none, NONE, 0, SLEW), 909 NPCM7XX_PINCFG(6, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), 910 NPCM7XX_PINCFG(7, iox2, MFSEL3, 14, smb2d, I2CSEGSEL, 10, none, NONE, 0, SLEW), 911 NPCM7XX_PINCFG(8, lkgpo1, FLOCKR1, 4, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 912 NPCM7XX_PINCFG(9, lkgpo2, FLOCKR1, 8, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 913 NPCM7XX_PINCFG(10, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 914 NPCM7XX_PINCFG(11, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 915 NPCM7XX_PINCFG(12, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), 916 NPCM7XX_PINCFG(13, gspi, MFSEL1, 24, smb5b, I2CSEGSEL, 19, none, NONE, 0, SLEW), 917 NPCM7XX_PINCFG(14, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), 918 NPCM7XX_PINCFG(15, gspi, MFSEL1, 24, smb5c, I2CSEGSEL, 20, none, NONE, 0, SLEW), 919 NPCM7XX_PINCFG(16, lkgpo0, FLOCKR1, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 920 NPCM7XX_PINCFG(17, pspi2, MFSEL3, 13, smb4den, I2CSEGSEL, 23, none, NONE, 0, DSTR(8, 12)), 921 NPCM7XX_PINCFG(18, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), 922 NPCM7XX_PINCFG(19, pspi2, MFSEL3, 13, smb4b, I2CSEGSEL, 14, none, NONE, 0, DSTR(8, 12)), 923 NPCM7XX_PINCFG(20, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), 924 NPCM7XX_PINCFG(21, smb4c, I2CSEGSEL, 15, smb15, MFSEL3, 8, none, NONE, 0, 0), 925 NPCM7XX_PINCFG(22, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), 926 NPCM7XX_PINCFG(23, smb4d, I2CSEGSEL, 16, smb14, MFSEL3, 7, none, NONE, 0, 0), 927 NPCM7XX_PINCFG(24, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 928 NPCM7XX_PINCFG(25, ioxh, MFSEL3, 18, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 929 NPCM7XX_PINCFG(26, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), 930 NPCM7XX_PINCFG(27, smb5, MFSEL1, 2, none, NONE, 0, none, NONE, 0, 0), 931 NPCM7XX_PINCFG(28, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), 932 NPCM7XX_PINCFG(29, smb4, MFSEL1, 1, none, NONE, 0, none, NONE, 0, 0), 933 NPCM7XX_PINCFG(30, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), 934 NPCM7XX_PINCFG(31, smb3, MFSEL1, 0, none, NONE, 0, none, NONE, 0, 0), 935 936 NPCM7XX_PINCFG(32, spi0cs1, MFSEL1, 3, none, NONE, 0, none, NONE, 0, 0), 937 NPCM7XX_PINCFG(33, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 938 NPCM7XX_PINCFG(34, none, NONE, 0, none, NONE, 0, none, NONE, 0, SLEW), 939 NPCM7XX_PINCFG(37, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), 940 NPCM7XX_PINCFG(38, smb3c, I2CSEGSEL, 12, none, NONE, 0, none, NONE, 0, SLEW), 941 NPCM7XX_PINCFG(39, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), 942 NPCM7XX_PINCFG(40, smb3b, I2CSEGSEL, 11, none, NONE, 0, none, NONE, 0, SLEW), 943 NPCM7XX_PINCFG(41, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, 0), 944 NPCM7XX_PINCFG(42, bmcuart0a, MFSEL1, 9, none, NONE, 0, none, NONE, 0, DSTR(2, 4) | GPO), 945 NPCM7XX_PINCFG(43, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), 946 NPCM7XX_PINCFG(44, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, bmcuart1, MFSEL3, 24, 0), 947 NPCM7XX_PINCFG(45, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, 0), 948 NPCM7XX_PINCFG(46, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), 949 NPCM7XX_PINCFG(47, uart1, MFSEL1, 10, jtag2, MFSEL4, 0, none, NONE, 0, DSTR(2, 8)), 950 NPCM7XX_PINCFG(48, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, GPO), 951 NPCM7XX_PINCFG(49, uart2, MFSEL1, 11, bmcuart0b, MFSEL4, 1, none, NONE, 0, 0), 952 NPCM7XX_PINCFG(50, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 953 NPCM7XX_PINCFG(51, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO), 954 NPCM7XX_PINCFG(52, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 955 NPCM7XX_PINCFG(53, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, GPO), 956 NPCM7XX_PINCFG(54, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 957 NPCM7XX_PINCFG(55, uart2, MFSEL1, 11, none, NONE, 0, none, NONE, 0, 0), 958 NPCM7XX_PINCFG(56, r1err, MFSEL1, 12, none, NONE, 0, none, NONE, 0, 0), 959 NPCM7XX_PINCFG(57, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 960 NPCM7XX_PINCFG(58, r1md, MFSEL1, 13, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 961 NPCM7XX_PINCFG(59, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), 962 NPCM7XX_PINCFG(60, smb3d, I2CSEGSEL, 13, none, NONE, 0, none, NONE, 0, 0), 963 NPCM7XX_PINCFG(61, uart1, MFSEL1, 10, none, NONE, 0, none, NONE, 0, GPO), 964 NPCM7XX_PINCFG(62, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO), 965 NPCM7XX_PINCFG(63, uart1, MFSEL1, 10, bmcuart1, MFSEL3, 24, none, NONE, 0, GPO), 966 967 NPCM7XX_PINCFG(64, fanin0, MFSEL2, 0, none, NONE, 0, none, NONE, 0, 0), 968 NPCM7XX_PINCFG(65, fanin1, MFSEL2, 1, none, NONE, 0, none, NONE, 0, 0), 969 NPCM7XX_PINCFG(66, fanin2, MFSEL2, 2, none, NONE, 0, none, NONE, 0, 0), 970 NPCM7XX_PINCFG(67, fanin3, MFSEL2, 3, none, NONE, 0, none, NONE, 0, 0), 971 NPCM7XX_PINCFG(68, fanin4, MFSEL2, 4, none, NONE, 0, none, NONE, 0, 0), 972 NPCM7XX_PINCFG(69, fanin5, MFSEL2, 5, none, NONE, 0, none, NONE, 0, 0), 973 NPCM7XX_PINCFG(70, fanin6, MFSEL2, 6, none, NONE, 0, none, NONE, 0, 0), 974 NPCM7XX_PINCFG(71, fanin7, MFSEL2, 7, none, NONE, 0, none, NONE, 0, 0), 975 NPCM7XX_PINCFG(72, fanin8, MFSEL2, 8, none, NONE, 0, none, NONE, 0, 0), 976 NPCM7XX_PINCFG(73, fanin9, MFSEL2, 9, none, NONE, 0, none, NONE, 0, 0), 977 NPCM7XX_PINCFG(74, fanin10, MFSEL2, 10, none, NONE, 0, none, NONE, 0, 0), 978 NPCM7XX_PINCFG(75, fanin11, MFSEL2, 11, none, NONE, 0, none, NONE, 0, 0), 979 NPCM7XX_PINCFG(76, fanin12, MFSEL2, 12, none, NONE, 0, none, NONE, 0, 0), 980 NPCM7XX_PINCFG(77, fanin13, MFSEL2, 13, none, NONE, 0, none, NONE, 0, 0), 981 NPCM7XX_PINCFG(78, fanin14, MFSEL2, 14, none, NONE, 0, none, NONE, 0, 0), 982 NPCM7XX_PINCFG(79, fanin15, MFSEL2, 15, none, NONE, 0, none, NONE, 0, 0), 983 NPCM7XX_PINCFG(80, pwm0, MFSEL2, 16, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 984 NPCM7XX_PINCFG(81, pwm1, MFSEL2, 17, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 985 NPCM7XX_PINCFG(82, pwm2, MFSEL2, 18, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 986 NPCM7XX_PINCFG(83, pwm3, MFSEL2, 19, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 987 NPCM7XX_PINCFG(84, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 988 NPCM7XX_PINCFG(85, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 989 NPCM7XX_PINCFG(86, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 990 NPCM7XX_PINCFG(87, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 991 NPCM7XX_PINCFG(88, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 992 NPCM7XX_PINCFG(89, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 993 NPCM7XX_PINCFG(90, r2err, MFSEL1, 15, none, NONE, 0, none, NONE, 0, 0), 994 NPCM7XX_PINCFG(91, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 995 NPCM7XX_PINCFG(92, r2md, MFSEL1, 16, none, NONE, 0, none, NONE, 0, DSTR(2, 4)), 996 NPCM7XX_PINCFG(93, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), 997 NPCM7XX_PINCFG(94, ga20kbc, MFSEL1, 17, smb5d, I2CSEGSEL, 21, none, NONE, 0, 0), 998 NPCM7XX_PINCFG(95, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), 999 1000 NPCM7XX_PINCFG(96, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1001 NPCM7XX_PINCFG(97, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1002 NPCM7XX_PINCFG(98, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1003 NPCM7XX_PINCFG(99, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1004 NPCM7XX_PINCFG(100, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1005 NPCM7XX_PINCFG(101, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1006 NPCM7XX_PINCFG(102, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1007 NPCM7XX_PINCFG(103, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1008 NPCM7XX_PINCFG(104, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1009 NPCM7XX_PINCFG(105, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1010 NPCM7XX_PINCFG(106, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1011 NPCM7XX_PINCFG(107, rg1, MFSEL4, 22, none, NONE, 0, none, NONE, 0, 0), 1012 NPCM7XX_PINCFG(108, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0), 1013 NPCM7XX_PINCFG(109, rg1mdio, MFSEL4, 21, none, NONE, 0, none, NONE, 0, 0), 1014 NPCM7XX_PINCFG(110, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1015 NPCM7XX_PINCFG(111, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1016 NPCM7XX_PINCFG(112, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1017 NPCM7XX_PINCFG(113, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1018 NPCM7XX_PINCFG(114, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0), 1019 NPCM7XX_PINCFG(115, smb0, MFSEL1, 6, none, NONE, 0, none, NONE, 0, 0), 1020 NPCM7XX_PINCFG(116, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0), 1021 NPCM7XX_PINCFG(117, smb1, MFSEL1, 7, none, NONE, 0, none, NONE, 0, 0), 1022 NPCM7XX_PINCFG(118, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0), 1023 NPCM7XX_PINCFG(119, smb2, MFSEL1, 8, none, NONE, 0, none, NONE, 0, 0), 1024 NPCM7XX_PINCFG(120, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW), 1025 NPCM7XX_PINCFG(121, smb2c, I2CSEGSEL, 9, none, NONE, 0, none, NONE, 0, SLEW), 1026 NPCM7XX_PINCFG(122, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW), 1027 NPCM7XX_PINCFG(123, smb2b, I2CSEGSEL, 8, none, NONE, 0, none, NONE, 0, SLEW), 1028 NPCM7XX_PINCFG(124, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW), 1029 NPCM7XX_PINCFG(125, smb1c, I2CSEGSEL, 6, none, NONE, 0, none, NONE, 0, SLEW), 1030 NPCM7XX_PINCFG(126, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW), 1031 NPCM7XX_PINCFG(127, smb1b, I2CSEGSEL, 5, none, NONE, 0, none, NONE, 0, SLEW), 1032 1033 NPCM7XX_PINCFG(128, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0), 1034 NPCM7XX_PINCFG(129, smb8, MFSEL4, 11, none, NONE, 0, none, NONE, 0, 0), 1035 NPCM7XX_PINCFG(130, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0), 1036 NPCM7XX_PINCFG(131, smb9, MFSEL4, 12, none, NONE, 0, none, NONE, 0, 0), 1037 NPCM7XX_PINCFG(132, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), 1038 NPCM7XX_PINCFG(133, smb10, MFSEL4, 13, none, NONE, 0, none, NONE, 0, 0), 1039 NPCM7XX_PINCFG(134, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), 1040 NPCM7XX_PINCFG(135, smb11, MFSEL4, 14, none, NONE, 0, none, NONE, 0, 0), 1041 NPCM7XX_PINCFG(136, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1042 NPCM7XX_PINCFG(137, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1043 NPCM7XX_PINCFG(138, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1044 NPCM7XX_PINCFG(139, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1045 NPCM7XX_PINCFG(140, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1046 NPCM7XX_PINCFG(141, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, 0), 1047 NPCM7XX_PINCFG(142, sd1, MFSEL3, 12, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1048 NPCM7XX_PINCFG(143, sd1, MFSEL3, 12, sd1pwr, MFSEL4, 5, none, NONE, 0, 0), 1049 NPCM7XX_PINCFG(144, pwm4, MFSEL2, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1050 NPCM7XX_PINCFG(145, pwm5, MFSEL2, 21, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1051 NPCM7XX_PINCFG(146, pwm6, MFSEL2, 22, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1052 NPCM7XX_PINCFG(147, pwm7, MFSEL2, 23, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1053 NPCM7XX_PINCFG(148, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1054 NPCM7XX_PINCFG(149, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1055 NPCM7XX_PINCFG(150, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1056 NPCM7XX_PINCFG(151, mmc8, MFSEL3, 11, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1057 NPCM7XX_PINCFG(152, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1058 NPCM7XX_PINCFG(153, mmcwp, FLOCKR1, 24, none, NONE, 0, none, NONE, 0, 0), /* Z1/A1 */ 1059 NPCM7XX_PINCFG(154, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1060 NPCM7XX_PINCFG(155, mmccd, MFSEL3, 25, mmcrst, MFSEL4, 6, none, NONE, 0, 0), /* Z1/A1 */ 1061 NPCM7XX_PINCFG(156, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1062 NPCM7XX_PINCFG(157, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1063 NPCM7XX_PINCFG(158, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1064 NPCM7XX_PINCFG(159, mmc, MFSEL3, 10, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1065 1066 NPCM7XX_PINCFG(160, clkout, MFSEL1, 21, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1067 NPCM7XX_PINCFG(161, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, DSTR(8, 12)), 1068 NPCM7XX_PINCFG(162, serirq, NONE, 0, gpio, MFSEL1, 31, none, NONE, 0, DSTR(8, 12)), 1069 NPCM7XX_PINCFG(163, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, 0), 1070 NPCM7XX_PINCFG(164, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1071 NPCM7XX_PINCFG(165, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1072 NPCM7XX_PINCFG(166, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1073 NPCM7XX_PINCFG(167, lpc, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL1, 26, SLEWLPC), 1074 NPCM7XX_PINCFG(168, lpcclk, NONE, 0, espi, MFSEL4, 8, gpio, MFSEL3, 16, 0), 1075 NPCM7XX_PINCFG(169, scipme, MFSEL3, 0, none, NONE, 0, none, NONE, 0, 0), 1076 NPCM7XX_PINCFG(170, sci, MFSEL1, 22, none, NONE, 0, none, NONE, 0, 0), 1077 NPCM7XX_PINCFG(171, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), 1078 NPCM7XX_PINCFG(172, smb6, MFSEL3, 1, none, NONE, 0, none, NONE, 0, 0), 1079 NPCM7XX_PINCFG(173, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), 1080 NPCM7XX_PINCFG(174, smb7, MFSEL3, 2, none, NONE, 0, none, NONE, 0, 0), 1081 NPCM7XX_PINCFG(175, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), 1082 NPCM7XX_PINCFG(176, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), 1083 NPCM7XX_PINCFG(177, pspi1, MFSEL3, 4, faninx, MFSEL3, 3, none, NONE, 0, DSTR(8, 12)), 1084 NPCM7XX_PINCFG(178, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1085 NPCM7XX_PINCFG(179, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1086 NPCM7XX_PINCFG(180, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1087 NPCM7XX_PINCFG(181, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1088 NPCM7XX_PINCFG(182, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1089 NPCM7XX_PINCFG(183, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1090 NPCM7XX_PINCFG(184, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1091 NPCM7XX_PINCFG(185, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1092 NPCM7XX_PINCFG(186, spi3, MFSEL4, 16, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1093 NPCM7XX_PINCFG(187, spi3cs1, MFSEL4, 17, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1094 NPCM7XX_PINCFG(188, spi3quad, MFSEL4, 20, spi3cs2, MFSEL4, 18, none, NONE, 0, DSTR(8, 12) | SLEW), 1095 NPCM7XX_PINCFG(189, spi3quad, MFSEL4, 20, spi3cs3, MFSEL4, 19, none, NONE, 0, DSTR(8, 12) | SLEW), 1096 NPCM7XX_PINCFG(190, gpio, FLOCKR1, 20, nprd_smi, NONE, 0, none, NONE, 0, DSTR(2, 4)), 1097 NPCM7XX_PINCFG(191, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ 1098 1099 NPCM7XX_PINCFG(192, none, NONE, 0, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), /* XX */ 1100 NPCM7XX_PINCFG(193, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1101 NPCM7XX_PINCFG(194, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), 1102 NPCM7XX_PINCFG(195, smb0b, I2CSEGSEL, 0, none, NONE, 0, none, NONE, 0, 0), 1103 NPCM7XX_PINCFG(196, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), 1104 NPCM7XX_PINCFG(197, smb0den, I2CSEGSEL, 22, none, NONE, 0, none, NONE, 0, SLEW), 1105 NPCM7XX_PINCFG(198, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0), 1106 NPCM7XX_PINCFG(199, smb0d, I2CSEGSEL, 2, none, NONE, 0, none, NONE, 0, 0), 1107 NPCM7XX_PINCFG(200, r2, MFSEL1, 14, none, NONE, 0, none, NONE, 0, 0), 1108 NPCM7XX_PINCFG(201, r1, MFSEL3, 9, none, NONE, 0, none, NONE, 0, 0), 1109 NPCM7XX_PINCFG(202, smb0c, I2CSEGSEL, 1, none, NONE, 0, none, NONE, 0, 0), 1110 NPCM7XX_PINCFG(203, faninx, MFSEL3, 3, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1111 NPCM7XX_PINCFG(204, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), 1112 NPCM7XX_PINCFG(205, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, SLEW), 1113 NPCM7XX_PINCFG(206, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), 1114 NPCM7XX_PINCFG(207, ddc, NONE, 0, gpio, MFSEL3, 22, none, NONE, 0, DSTR(4, 8)), 1115 NPCM7XX_PINCFG(208, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1116 NPCM7XX_PINCFG(209, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1117 NPCM7XX_PINCFG(210, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1118 NPCM7XX_PINCFG(211, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1119 NPCM7XX_PINCFG(212, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1120 NPCM7XX_PINCFG(213, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1121 NPCM7XX_PINCFG(214, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1122 NPCM7XX_PINCFG(215, rg2, MFSEL4, 24, ddr, MFSEL3, 26, none, NONE, 0, 0), 1123 NPCM7XX_PINCFG(216, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), 1124 NPCM7XX_PINCFG(217, rg2mdio, MFSEL4, 23, ddr, MFSEL3, 26, none, NONE, 0, 0), 1125 NPCM7XX_PINCFG(218, wdog1, MFSEL3, 19, none, NONE, 0, none, NONE, 0, 0), 1126 NPCM7XX_PINCFG(219, wdog2, MFSEL3, 20, none, NONE, 0, none, NONE, 0, DSTR(4, 8)), 1127 NPCM7XX_PINCFG(220, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), 1128 NPCM7XX_PINCFG(221, smb12, MFSEL3, 5, none, NONE, 0, none, NONE, 0, 0), 1129 NPCM7XX_PINCFG(222, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), 1130 NPCM7XX_PINCFG(223, smb13, MFSEL3, 6, none, NONE, 0, none, NONE, 0, 0), 1131 1132 NPCM7XX_PINCFG(224, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, SLEW), 1133 NPCM7XX_PINCFG(225, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1134 NPCM7XX_PINCFG(226, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW | GPO), 1135 NPCM7XX_PINCFG(227, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1136 NPCM7XX_PINCFG(228, spixcs1, MFSEL4, 28, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1137 NPCM7XX_PINCFG(229, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1138 NPCM7XX_PINCFG(230, spix, MFSEL4, 27, none, NONE, 0, none, NONE, 0, DSTR(8, 12) | SLEW), 1139 NPCM7XX_PINCFG(231, clkreq, MFSEL4, 9, none, NONE, 0, none, NONE, 0, DSTR(8, 12)), 1140 NPCM7XX_PINCFG(253, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC1 power */ 1141 NPCM7XX_PINCFG(254, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* SDHC2 power */ 1142 NPCM7XX_PINCFG(255, none, NONE, 0, none, NONE, 0, none, NONE, 0, GPI), /* DACOSEL */ 1143}; 1144 1145/* number, name, drv_data */ 1146static const struct pinctrl_pin_desc npcm7xx_pins[] = { 1147 PINCTRL_PIN(0, "GPIO0/IOX1DI"), 1148 PINCTRL_PIN(1, "GPIO1/IOX1LD"), 1149 PINCTRL_PIN(2, "GPIO2/IOX1CK"), 1150 PINCTRL_PIN(3, "GPIO3/IOX1D0"), 1151 PINCTRL_PIN(4, "GPIO4/IOX2DI/SMB1DSDA"), 1152 PINCTRL_PIN(5, "GPIO5/IOX2LD/SMB1DSCL"), 1153 PINCTRL_PIN(6, "GPIO6/IOX2CK/SMB2DSDA"), 1154 PINCTRL_PIN(7, "GPIO7/IOX2D0/SMB2DSCL"), 1155 PINCTRL_PIN(8, "GPIO8/LKGPO1"), 1156 PINCTRL_PIN(9, "GPIO9/LKGPO2"), 1157 PINCTRL_PIN(10, "GPIO10/IOXHLD"), 1158 PINCTRL_PIN(11, "GPIO11/IOXHCK"), 1159 PINCTRL_PIN(12, "GPIO12/GSPICK/SMB5BSCL"), 1160 PINCTRL_PIN(13, "GPIO13/GSPIDO/SMB5BSDA"), 1161 PINCTRL_PIN(14, "GPIO14/GSPIDI/SMB5CSCL"), 1162 PINCTRL_PIN(15, "GPIO15/GSPICS/SMB5CSDA"), 1163 PINCTRL_PIN(16, "GPIO16/LKGPO0"), 1164 PINCTRL_PIN(17, "GPIO17/PSPI2DI/SMB4DEN"), 1165 PINCTRL_PIN(18, "GPIO18/PSPI2D0/SMB4BSDA"), 1166 PINCTRL_PIN(19, "GPIO19/PSPI2CK/SMB4BSCL"), 1167 PINCTRL_PIN(20, "GPIO20/SMB4CSDA/SMB15SDA"), 1168 PINCTRL_PIN(21, "GPIO21/SMB4CSCL/SMB15SCL"), 1169 PINCTRL_PIN(22, "GPIO22/SMB4DSDA/SMB14SDA"), 1170 PINCTRL_PIN(23, "GPIO23/SMB4DSCL/SMB14SCL"), 1171 PINCTRL_PIN(24, "GPIO24/IOXHDO"), 1172 PINCTRL_PIN(25, "GPIO25/IOXHDI"), 1173 PINCTRL_PIN(26, "GPIO26/SMB5SDA"), 1174 PINCTRL_PIN(27, "GPIO27/SMB5SCL"), 1175 PINCTRL_PIN(28, "GPIO28/SMB4SDA"), 1176 PINCTRL_PIN(29, "GPIO29/SMB4SCL"), 1177 PINCTRL_PIN(30, "GPIO30/SMB3SDA"), 1178 PINCTRL_PIN(31, "GPIO31/SMB3SCL"), 1179 1180 PINCTRL_PIN(32, "GPIO32/nSPI0CS1"), 1181 PINCTRL_PIN(33, "SPI0D2"), 1182 PINCTRL_PIN(34, "SPI0D3"), 1183 PINCTRL_PIN(37, "GPIO37/SMB3CSDA"), 1184 PINCTRL_PIN(38, "GPIO38/SMB3CSCL"), 1185 PINCTRL_PIN(39, "GPIO39/SMB3BSDA"), 1186 PINCTRL_PIN(40, "GPIO40/SMB3BSCL"), 1187 PINCTRL_PIN(41, "GPIO41/BSPRXD"), 1188 PINCTRL_PIN(42, "GPO42/BSPTXD/STRAP11"), 1189 PINCTRL_PIN(43, "GPIO43/RXD1/JTMS2/BU1RXD"), 1190 PINCTRL_PIN(44, "GPIO44/nCTS1/JTDI2/BU1CTS"), 1191 PINCTRL_PIN(45, "GPIO45/nDCD1/JTDO2"), 1192 PINCTRL_PIN(46, "GPIO46/nDSR1/JTCK2"), 1193 PINCTRL_PIN(47, "GPIO47/nRI1/JCP_RDY2"), 1194 PINCTRL_PIN(48, "GPIO48/TXD2/BSPTXD"), 1195 PINCTRL_PIN(49, "GPIO49/RXD2/BSPRXD"), 1196 PINCTRL_PIN(50, "GPIO50/nCTS2"), 1197 PINCTRL_PIN(51, "GPO51/nRTS2/STRAP2"), 1198 PINCTRL_PIN(52, "GPIO52/nDCD2"), 1199 PINCTRL_PIN(53, "GPO53/nDTR2_BOUT2/STRAP1"), 1200 PINCTRL_PIN(54, "GPIO54/nDSR2"), 1201 PINCTRL_PIN(55, "GPIO55/nRI2"), 1202 PINCTRL_PIN(56, "GPIO56/R1RXERR"), 1203 PINCTRL_PIN(57, "GPIO57/R1MDC"), 1204 PINCTRL_PIN(58, "GPIO58/R1MDIO"), 1205 PINCTRL_PIN(59, "GPIO59/SMB3DSDA"), 1206 PINCTRL_PIN(60, "GPIO60/SMB3DSCL"), 1207 PINCTRL_PIN(61, "GPO61/nDTR1_BOUT1/STRAP6"), 1208 PINCTRL_PIN(62, "GPO62/nRTST1/STRAP5"), 1209 PINCTRL_PIN(63, "GPO63/TXD1/STRAP4"), 1210 1211 PINCTRL_PIN(64, "GPIO64/FANIN0"), 1212 PINCTRL_PIN(65, "GPIO65/FANIN1"), 1213 PINCTRL_PIN(66, "GPIO66/FANIN2"), 1214 PINCTRL_PIN(67, "GPIO67/FANIN3"), 1215 PINCTRL_PIN(68, "GPIO68/FANIN4"), 1216 PINCTRL_PIN(69, "GPIO69/FANIN5"), 1217 PINCTRL_PIN(70, "GPIO70/FANIN6"), 1218 PINCTRL_PIN(71, "GPIO71/FANIN7"), 1219 PINCTRL_PIN(72, "GPIO72/FANIN8"), 1220 PINCTRL_PIN(73, "GPIO73/FANIN9"), 1221 PINCTRL_PIN(74, "GPIO74/FANIN10"), 1222 PINCTRL_PIN(75, "GPIO75/FANIN11"), 1223 PINCTRL_PIN(76, "GPIO76/FANIN12"), 1224 PINCTRL_PIN(77, "GPIO77/FANIN13"), 1225 PINCTRL_PIN(78, "GPIO78/FANIN14"), 1226 PINCTRL_PIN(79, "GPIO79/FANIN15"), 1227 PINCTRL_PIN(80, "GPIO80/PWM0"), 1228 PINCTRL_PIN(81, "GPIO81/PWM1"), 1229 PINCTRL_PIN(82, "GPIO82/PWM2"), 1230 PINCTRL_PIN(83, "GPIO83/PWM3"), 1231 PINCTRL_PIN(84, "GPIO84/R2TXD0"), 1232 PINCTRL_PIN(85, "GPIO85/R2TXD1"), 1233 PINCTRL_PIN(86, "GPIO86/R2TXEN"), 1234 PINCTRL_PIN(87, "GPIO87/R2RXD0"), 1235 PINCTRL_PIN(88, "GPIO88/R2RXD1"), 1236 PINCTRL_PIN(89, "GPIO89/R2CRSDV"), 1237 PINCTRL_PIN(90, "GPIO90/R2RXERR"), 1238 PINCTRL_PIN(91, "GPIO91/R2MDC"), 1239 PINCTRL_PIN(92, "GPIO92/R2MDIO"), 1240 PINCTRL_PIN(93, "GPIO93/GA20/SMB5DSCL"), 1241 PINCTRL_PIN(94, "GPIO94/nKBRST/SMB5DSDA"), 1242 PINCTRL_PIN(95, "GPIO95/nLRESET/nESPIRST"), 1243 1244 PINCTRL_PIN(96, "GPIO96/RG1TXD0"), 1245 PINCTRL_PIN(97, "GPIO97/RG1TXD1"), 1246 PINCTRL_PIN(98, "GPIO98/RG1TXD2"), 1247 PINCTRL_PIN(99, "GPIO99/RG1TXD3"), 1248 PINCTRL_PIN(100, "GPIO100/RG1TXC"), 1249 PINCTRL_PIN(101, "GPIO101/RG1TXCTL"), 1250 PINCTRL_PIN(102, "GPIO102/RG1RXD0"), 1251 PINCTRL_PIN(103, "GPIO103/RG1RXD1"), 1252 PINCTRL_PIN(104, "GPIO104/RG1RXD2"), 1253 PINCTRL_PIN(105, "GPIO105/RG1RXD3"), 1254 PINCTRL_PIN(106, "GPIO106/RG1RXC"), 1255 PINCTRL_PIN(107, "GPIO107/RG1RXCTL"), 1256 PINCTRL_PIN(108, "GPIO108/RG1MDC"), 1257 PINCTRL_PIN(109, "GPIO109/RG1MDIO"), 1258 PINCTRL_PIN(110, "GPIO110/RG2TXD0/DDRV0"), 1259 PINCTRL_PIN(111, "GPIO111/RG2TXD1/DDRV1"), 1260 PINCTRL_PIN(112, "GPIO112/RG2TXD2/DDRV2"), 1261 PINCTRL_PIN(113, "GPIO113/RG2TXD3/DDRV3"), 1262 PINCTRL_PIN(114, "GPIO114/SMB0SCL"), 1263 PINCTRL_PIN(115, "GPIO115/SMB0SDA"), 1264 PINCTRL_PIN(116, "GPIO116/SMB1SCL"), 1265 PINCTRL_PIN(117, "GPIO117/SMB1SDA"), 1266 PINCTRL_PIN(118, "GPIO118/SMB2SCL"), 1267 PINCTRL_PIN(119, "GPIO119/SMB2SDA"), 1268 PINCTRL_PIN(120, "GPIO120/SMB2CSDA"), 1269 PINCTRL_PIN(121, "GPIO121/SMB2CSCL"), 1270 PINCTRL_PIN(122, "GPIO122/SMB2BSDA"), 1271 PINCTRL_PIN(123, "GPIO123/SMB2BSCL"), 1272 PINCTRL_PIN(124, "GPIO124/SMB1CSDA"), 1273 PINCTRL_PIN(125, "GPIO125/SMB1CSCL"), 1274 PINCTRL_PIN(126, "GPIO126/SMB1BSDA"), 1275 PINCTRL_PIN(127, "GPIO127/SMB1BSCL"), 1276 1277 PINCTRL_PIN(128, "GPIO128/SMB8SCL"), 1278 PINCTRL_PIN(129, "GPIO129/SMB8SDA"), 1279 PINCTRL_PIN(130, "GPIO130/SMB9SCL"), 1280 PINCTRL_PIN(131, "GPIO131/SMB9SDA"), 1281 PINCTRL_PIN(132, "GPIO132/SMB10SCL"), 1282 PINCTRL_PIN(133, "GPIO133/SMB10SDA"), 1283 PINCTRL_PIN(134, "GPIO134/SMB11SCL"), 1284 PINCTRL_PIN(135, "GPIO135/SMB11SDA"), 1285 PINCTRL_PIN(136, "GPIO136/SD1DT0"), 1286 PINCTRL_PIN(137, "GPIO137/SD1DT1"), 1287 PINCTRL_PIN(138, "GPIO138/SD1DT2"), 1288 PINCTRL_PIN(139, "GPIO139/SD1DT3"), 1289 PINCTRL_PIN(140, "GPIO140/SD1CLK"), 1290 PINCTRL_PIN(141, "GPIO141/SD1WP"), 1291 PINCTRL_PIN(142, "GPIO142/SD1CMD"), 1292 PINCTRL_PIN(143, "GPIO143/SD1CD/SD1PWR"), 1293 PINCTRL_PIN(144, "GPIO144/PWM4"), 1294 PINCTRL_PIN(145, "GPIO145/PWM5"), 1295 PINCTRL_PIN(146, "GPIO146/PWM6"), 1296 PINCTRL_PIN(147, "GPIO147/PWM7"), 1297 PINCTRL_PIN(148, "GPIO148/MMCDT4"), 1298 PINCTRL_PIN(149, "GPIO149/MMCDT5"), 1299 PINCTRL_PIN(150, "GPIO150/MMCDT6"), 1300 PINCTRL_PIN(151, "GPIO151/MMCDT7"), 1301 PINCTRL_PIN(152, "GPIO152/MMCCLK"), 1302 PINCTRL_PIN(153, "GPIO153/MMCWP"), 1303 PINCTRL_PIN(154, "GPIO154/MMCCMD"), 1304 PINCTRL_PIN(155, "GPIO155/nMMCCD/nMMCRST"), 1305 PINCTRL_PIN(156, "GPIO156/MMCDT0"), 1306 PINCTRL_PIN(157, "GPIO157/MMCDT1"), 1307 PINCTRL_PIN(158, "GPIO158/MMCDT2"), 1308 PINCTRL_PIN(159, "GPIO159/MMCDT3"), 1309 1310 PINCTRL_PIN(160, "GPIO160/CLKOUT/RNGOSCOUT"), 1311 PINCTRL_PIN(161, "GPIO161/nLFRAME/nESPICS"), 1312 PINCTRL_PIN(162, "GPIO162/SERIRQ"), 1313 PINCTRL_PIN(163, "GPIO163/LCLK/ESPICLK"), 1314 PINCTRL_PIN(164, "GPIO164/LAD0/ESPI_IO0"/*dscnt6*/), 1315 PINCTRL_PIN(165, "GPIO165/LAD1/ESPI_IO1"/*dscnt6*/), 1316 PINCTRL_PIN(166, "GPIO166/LAD2/ESPI_IO2"/*dscnt6*/), 1317 PINCTRL_PIN(167, "GPIO167/LAD3/ESPI_IO3"/*dscnt6*/), 1318 PINCTRL_PIN(168, "GPIO168/nCLKRUN/nESPIALERT"), 1319 PINCTRL_PIN(169, "GPIO169/nSCIPME"), 1320 PINCTRL_PIN(170, "GPIO170/nSMI"), 1321 PINCTRL_PIN(171, "GPIO171/SMB6SCL"), 1322 PINCTRL_PIN(172, "GPIO172/SMB6SDA"), 1323 PINCTRL_PIN(173, "GPIO173/SMB7SCL"), 1324 PINCTRL_PIN(174, "GPIO174/SMB7SDA"), 1325 PINCTRL_PIN(175, "GPIO175/PSPI1CK/FANIN19"), 1326 PINCTRL_PIN(176, "GPIO176/PSPI1DO/FANIN18"), 1327 PINCTRL_PIN(177, "GPIO177/PSPI1DI/FANIN17"), 1328 PINCTRL_PIN(178, "GPIO178/R1TXD0"), 1329 PINCTRL_PIN(179, "GPIO179/R1TXD1"), 1330 PINCTRL_PIN(180, "GPIO180/R1TXEN"), 1331 PINCTRL_PIN(181, "GPIO181/R1RXD0"), 1332 PINCTRL_PIN(182, "GPIO182/R1RXD1"), 1333 PINCTRL_PIN(183, "GPIO183/SPI3CK"), 1334 PINCTRL_PIN(184, "GPO184/SPI3D0/STRAP9"), 1335 PINCTRL_PIN(185, "GPO185/SPI3D1/STRAP10"), 1336 PINCTRL_PIN(186, "GPIO186/nSPI3CS0"), 1337 PINCTRL_PIN(187, "GPIO187/nSPI3CS1"), 1338 PINCTRL_PIN(188, "GPIO188/SPI3D2/nSPI3CS2"), 1339 PINCTRL_PIN(189, "GPIO189/SPI3D3/nSPI3CS3"), 1340 PINCTRL_PIN(190, "GPIO190/nPRD_SMI"), 1341 PINCTRL_PIN(191, "GPIO191"), 1342 1343 PINCTRL_PIN(192, "GPIO192"), 1344 PINCTRL_PIN(193, "GPIO193/R1CRSDV"), 1345 PINCTRL_PIN(194, "GPIO194/SMB0BSCL"), 1346 PINCTRL_PIN(195, "GPIO195/SMB0BSDA"), 1347 PINCTRL_PIN(196, "GPIO196/SMB0CSCL"), 1348 PINCTRL_PIN(197, "GPIO197/SMB0DEN"), 1349 PINCTRL_PIN(198, "GPIO198/SMB0DSDA"), 1350 PINCTRL_PIN(199, "GPIO199/SMB0DSCL"), 1351 PINCTRL_PIN(200, "GPIO200/R2CK"), 1352 PINCTRL_PIN(201, "GPIO201/R1CK"), 1353 PINCTRL_PIN(202, "GPIO202/SMB0CSDA"), 1354 PINCTRL_PIN(203, "GPIO203/FANIN16"), 1355 PINCTRL_PIN(204, "GPIO204/DDC2SCL"), 1356 PINCTRL_PIN(205, "GPIO205/DDC2SDA"), 1357 PINCTRL_PIN(206, "GPIO206/HSYNC2"), 1358 PINCTRL_PIN(207, "GPIO207/VSYNC2"), 1359 PINCTRL_PIN(208, "GPIO208/RG2TXC/DVCK"), 1360 PINCTRL_PIN(209, "GPIO209/RG2TXCTL/DDRV4"), 1361 PINCTRL_PIN(210, "GPIO210/RG2RXD0/DDRV5"), 1362 PINCTRL_PIN(211, "GPIO211/RG2RXD1/DDRV6"), 1363 PINCTRL_PIN(212, "GPIO212/RG2RXD2/DDRV7"), 1364 PINCTRL_PIN(213, "GPIO213/RG2RXD3/DDRV8"), 1365 PINCTRL_PIN(214, "GPIO214/RG2RXC/DDRV9"), 1366 PINCTRL_PIN(215, "GPIO215/RG2RXCTL/DDRV10"), 1367 PINCTRL_PIN(216, "GPIO216/RG2MDC/DDRV11"), 1368 PINCTRL_PIN(217, "GPIO217/RG2MDIO/DVHSYNC"), 1369 PINCTRL_PIN(218, "GPIO218/nWDO1"), 1370 PINCTRL_PIN(219, "GPIO219/nWDO2"), 1371 PINCTRL_PIN(220, "GPIO220/SMB12SCL"), 1372 PINCTRL_PIN(221, "GPIO221/SMB12SDA"), 1373 PINCTRL_PIN(222, "GPIO222/SMB13SCL"), 1374 PINCTRL_PIN(223, "GPIO223/SMB13SDA"), 1375 1376 PINCTRL_PIN(224, "GPIO224/SPIXCK"), 1377 PINCTRL_PIN(225, "GPO225/SPIXD0/STRAP12"), 1378 PINCTRL_PIN(226, "GPO226/SPIXD1/STRAP13"), 1379 PINCTRL_PIN(227, "GPIO227/nSPIXCS0"), 1380 PINCTRL_PIN(228, "GPIO228/nSPIXCS1"), 1381 PINCTRL_PIN(229, "GPO229/SPIXD2/STRAP3"), 1382 PINCTRL_PIN(230, "GPIO230/SPIXD3"), 1383 PINCTRL_PIN(231, "GPIO231/nCLKREQ"), 1384 PINCTRL_PIN(255, "GPI255/DACOSEL"), 1385}; 1386 1387/* Enable mode in pin group */ 1388static void npcm7xx_setfunc(struct regmap *gcr_regmap, const unsigned int *pin, 1389 int pin_number, int mode) 1390{ 1391 const struct npcm7xx_pincfg *cfg; 1392 int i; 1393 1394 for (i = 0 ; i < pin_number ; i++) { 1395 cfg = &pincfg[pin[i]]; 1396 if (mode == fn_gpio || cfg->fn0 == mode || cfg->fn1 == mode || cfg->fn2 == mode) { 1397 if (cfg->reg0) 1398 regmap_update_bits(gcr_regmap, cfg->reg0, 1399 BIT(cfg->bit0), 1400 !!(cfg->fn0 == mode) ? 1401 BIT(cfg->bit0) : 0); 1402 if (cfg->reg1) 1403 regmap_update_bits(gcr_regmap, cfg->reg1, 1404 BIT(cfg->bit1), 1405 !!(cfg->fn1 == mode) ? 1406 BIT(cfg->bit1) : 0); 1407 if (cfg->reg2) 1408 regmap_update_bits(gcr_regmap, cfg->reg2, 1409 BIT(cfg->bit2), 1410 !!(cfg->fn2 == mode) ? 1411 BIT(cfg->bit2) : 0); 1412 } 1413 } 1414} 1415 1416/* Get slew rate of pin (high/low) */ 1417static int npcm7xx_get_slew_rate(struct npcm7xx_gpio *bank, 1418 struct regmap *gcr_regmap, unsigned int pin) 1419{ 1420 u32 val; 1421 int gpio = (pin % bank->chip.gc.ngpio); 1422 unsigned long pinmask = BIT(gpio); 1423 1424 if (pincfg[pin].flag & SLEW) 1425 return ioread32(bank->base + NPCM7XX_GP_N_OSRC) 1426 & pinmask; 1427 /* LPC Slew rate in SRCNT register */ 1428 if (pincfg[pin].flag & SLEWLPC) { 1429 regmap_read(gcr_regmap, NPCM7XX_GCR_SRCNT, &val); 1430 return !!(val & SRCNT_ESPI); 1431 } 1432 1433 return -EINVAL; 1434} 1435 1436/* Set slew rate of pin (high/low) */ 1437static int npcm7xx_set_slew_rate(struct npcm7xx_gpio *bank, 1438 struct regmap *gcr_regmap, unsigned int pin, 1439 int arg) 1440{ 1441 int gpio = BIT(pin % bank->chip.gc.ngpio); 1442 1443 if (pincfg[pin].flag & SLEW) { 1444 switch (arg) { 1445 case 0: 1446 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, 1447 gpio); 1448 return 0; 1449 case 1: 1450 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OSRC, 1451 gpio); 1452 return 0; 1453 default: 1454 return -EINVAL; 1455 } 1456 } 1457 /* LPC Slew rate in SRCNT register */ 1458 if (pincfg[pin].flag & SLEWLPC) { 1459 switch (arg) { 1460 case 0: 1461 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT, 1462 SRCNT_ESPI, 0); 1463 return 0; 1464 case 1: 1465 regmap_update_bits(gcr_regmap, NPCM7XX_GCR_SRCNT, 1466 SRCNT_ESPI, SRCNT_ESPI); 1467 return 0; 1468 default: 1469 return -EINVAL; 1470 } 1471 } 1472 1473 return -EINVAL; 1474} 1475 1476/* Get drive strength for a pin, if supported */ 1477static int npcm7xx_get_drive_strength(struct pinctrl_dev *pctldev, 1478 unsigned int pin) 1479{ 1480 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1481 struct npcm7xx_gpio *bank = 1482 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1483 int gpio = (pin % bank->chip.gc.ngpio); 1484 unsigned long pinmask = BIT(gpio); 1485 u32 ds = 0; 1486 int flg, val; 1487 1488 flg = pincfg[pin].flag; 1489 if (flg & DRIVE_STRENGTH_MASK) { 1490 /* Get standard reading */ 1491 val = ioread32(bank->base + NPCM7XX_GP_N_ODSC) 1492 & pinmask; 1493 ds = val ? DSHI(flg) : DSLO(flg); 1494 dev_dbg(bank->chip.gc.parent, 1495 "pin %d strength %d = %d\n", pin, val, ds); 1496 return ds; 1497 } 1498 1499 return -EINVAL; 1500} 1501 1502/* Set drive strength for a pin, if supported */ 1503static int npcm7xx_set_drive_strength(struct npcm7xx_pinctrl *npcm, 1504 unsigned int pin, int nval) 1505{ 1506 int v; 1507 struct npcm7xx_gpio *bank = 1508 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1509 int gpio = BIT(pin % bank->chip.gc.ngpio); 1510 1511 v = (pincfg[pin].flag & DRIVE_STRENGTH_MASK); 1512 if (!nval || !v) 1513 return -ENOTSUPP; 1514 if (DSLO(v) == nval) { 1515 dev_dbg(bank->chip.gc.parent, 1516 "setting pin %d to low strength [%d]\n", pin, nval); 1517 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1518 return 0; 1519 } else if (DSHI(v) == nval) { 1520 dev_dbg(bank->chip.gc.parent, 1521 "setting pin %d to high strength [%d]\n", pin, nval); 1522 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_ODSC, gpio); 1523 return 0; 1524 } 1525 1526 return -ENOTSUPP; 1527} 1528 1529/* pinctrl_ops */ 1530static void npcm7xx_pin_dbg_show(struct pinctrl_dev *pctldev, 1531 struct seq_file *s, unsigned int offset) 1532{ 1533 seq_printf(s, "pinctrl_ops.dbg: %d", offset); 1534} 1535 1536static int npcm7xx_get_groups_count(struct pinctrl_dev *pctldev) 1537{ 1538 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1539 1540 dev_dbg(npcm->dev, "group size: %zu\n", ARRAY_SIZE(npcm7xx_groups)); 1541 return ARRAY_SIZE(npcm7xx_groups); 1542} 1543 1544static const char *npcm7xx_get_group_name(struct pinctrl_dev *pctldev, 1545 unsigned int selector) 1546{ 1547 return npcm7xx_groups[selector].name; 1548} 1549 1550static int npcm7xx_get_group_pins(struct pinctrl_dev *pctldev, 1551 unsigned int selector, 1552 const unsigned int **pins, 1553 unsigned int *npins) 1554{ 1555 *npins = npcm7xx_groups[selector].npins; 1556 *pins = npcm7xx_groups[selector].pins; 1557 1558 return 0; 1559} 1560 1561static void npcm7xx_dt_free_map(struct pinctrl_dev *pctldev, 1562 struct pinctrl_map *map, u32 num_maps) 1563{ 1564 kfree(map); 1565} 1566 1567static const struct pinctrl_ops npcm7xx_pinctrl_ops = { 1568 .get_groups_count = npcm7xx_get_groups_count, 1569 .get_group_name = npcm7xx_get_group_name, 1570 .get_group_pins = npcm7xx_get_group_pins, 1571 .pin_dbg_show = npcm7xx_pin_dbg_show, 1572 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 1573 .dt_free_map = npcm7xx_dt_free_map, 1574}; 1575 1576/* pinmux_ops */ 1577static int npcm7xx_get_functions_count(struct pinctrl_dev *pctldev) 1578{ 1579 return ARRAY_SIZE(npcm7xx_funcs); 1580} 1581 1582static const char *npcm7xx_get_function_name(struct pinctrl_dev *pctldev, 1583 unsigned int function) 1584{ 1585 return npcm7xx_funcs[function].name; 1586} 1587 1588static int npcm7xx_get_function_groups(struct pinctrl_dev *pctldev, 1589 unsigned int function, 1590 const char * const **groups, 1591 unsigned int * const ngroups) 1592{ 1593 *ngroups = npcm7xx_funcs[function].ngroups; 1594 *groups = npcm7xx_funcs[function].groups; 1595 1596 return 0; 1597} 1598 1599static int npcm7xx_pinmux_set_mux(struct pinctrl_dev *pctldev, 1600 unsigned int function, 1601 unsigned int group) 1602{ 1603 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1604 1605 dev_dbg(npcm->dev, "set_mux: %d, %d[%s]\n", function, group, 1606 npcm7xx_groups[group].name); 1607 1608 npcm7xx_setfunc(npcm->gcr_regmap, npcm7xx_groups[group].pins, 1609 npcm7xx_groups[group].npins, group); 1610 1611 return 0; 1612} 1613 1614static int npcm7xx_gpio_request_enable(struct pinctrl_dev *pctldev, 1615 struct pinctrl_gpio_range *range, 1616 unsigned int offset) 1617{ 1618 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1619 1620 if (!range) { 1621 dev_err(npcm->dev, "invalid range\n"); 1622 return -EINVAL; 1623 } 1624 if (!range->gc) { 1625 dev_err(npcm->dev, "invalid gpiochip\n"); 1626 return -EINVAL; 1627 } 1628 1629 npcm7xx_setfunc(npcm->gcr_regmap, &offset, 1, fn_gpio); 1630 1631 return 0; 1632} 1633 1634/* Release GPIO back to pinctrl mode */ 1635static void npcm7xx_gpio_request_free(struct pinctrl_dev *pctldev, 1636 struct pinctrl_gpio_range *range, 1637 unsigned int offset) 1638{ 1639 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1640 int virq; 1641 1642 virq = irq_find_mapping(npcm->domain, offset); 1643 if (virq) 1644 irq_dispose_mapping(virq); 1645} 1646 1647/* Set GPIO direction */ 1648static int npcm_gpio_set_direction(struct pinctrl_dev *pctldev, 1649 struct pinctrl_gpio_range *range, 1650 unsigned int offset, bool input) 1651{ 1652 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1653 struct npcm7xx_gpio *bank = 1654 &npcm->gpio_bank[offset / NPCM7XX_GPIO_PER_BANK]; 1655 int gpio = BIT(offset % bank->chip.gc.ngpio); 1656 1657 dev_dbg(bank->chip.gc.parent, "GPIO Set Direction: %d = %d\n", offset, 1658 input); 1659 if (input) 1660 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); 1661 else 1662 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); 1663 1664 return 0; 1665} 1666 1667static const struct pinmux_ops npcm7xx_pinmux_ops = { 1668 .get_functions_count = npcm7xx_get_functions_count, 1669 .get_function_name = npcm7xx_get_function_name, 1670 .get_function_groups = npcm7xx_get_function_groups, 1671 .set_mux = npcm7xx_pinmux_set_mux, 1672 .gpio_request_enable = npcm7xx_gpio_request_enable, 1673 .gpio_disable_free = npcm7xx_gpio_request_free, 1674 .gpio_set_direction = npcm_gpio_set_direction, 1675}; 1676 1677/* pinconf_ops */ 1678static int npcm7xx_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 1679 unsigned long *config) 1680{ 1681 enum pin_config_param param = pinconf_to_config_param(*config); 1682 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1683 struct npcm7xx_gpio *bank = 1684 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1685 int gpio = (pin % bank->chip.gc.ngpio); 1686 unsigned long pinmask = BIT(gpio); 1687 u32 ie, oe, pu, pd; 1688 int rc = 0; 1689 1690 switch (param) { 1691 case PIN_CONFIG_BIAS_DISABLE: 1692 case PIN_CONFIG_BIAS_PULL_UP: 1693 case PIN_CONFIG_BIAS_PULL_DOWN: 1694 pu = ioread32(bank->base + NPCM7XX_GP_N_PU) & pinmask; 1695 pd = ioread32(bank->base + NPCM7XX_GP_N_PD) & pinmask; 1696 if (param == PIN_CONFIG_BIAS_DISABLE) 1697 rc = (!pu && !pd); 1698 else if (param == PIN_CONFIG_BIAS_PULL_UP) 1699 rc = (pu && !pd); 1700 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 1701 rc = (!pu && pd); 1702 break; 1703 case PIN_CONFIG_LEVEL: 1704 case PIN_CONFIG_INPUT_ENABLE: 1705 ie = ioread32(bank->base + NPCM7XX_GP_N_IEM) & pinmask; 1706 oe = ioread32(bank->base + NPCM7XX_GP_N_OE) & pinmask; 1707 if (param == PIN_CONFIG_INPUT_ENABLE) 1708 rc = (ie && !oe); 1709 else if (param == PIN_CONFIG_LEVEL) 1710 rc = (!ie && oe); 1711 break; 1712 case PIN_CONFIG_DRIVE_PUSH_PULL: 1713 rc = !(ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask); 1714 break; 1715 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1716 rc = ioread32(bank->base + NPCM7XX_GP_N_OTYP) & pinmask; 1717 break; 1718 case PIN_CONFIG_INPUT_DEBOUNCE: 1719 rc = ioread32(bank->base + NPCM7XX_GP_N_DBNC) & pinmask; 1720 break; 1721 case PIN_CONFIG_DRIVE_STRENGTH: 1722 rc = npcm7xx_get_drive_strength(pctldev, pin); 1723 if (rc) 1724 *config = pinconf_to_config_packed(param, rc); 1725 break; 1726 case PIN_CONFIG_SLEW_RATE: 1727 rc = npcm7xx_get_slew_rate(bank, npcm->gcr_regmap, pin); 1728 if (rc >= 0) 1729 *config = pinconf_to_config_packed(param, rc); 1730 break; 1731 default: 1732 return -ENOTSUPP; 1733 } 1734 1735 if (!rc) 1736 return -EINVAL; 1737 1738 return 0; 1739} 1740 1741static int npcm7xx_config_set_one(struct npcm7xx_pinctrl *npcm, 1742 unsigned int pin, unsigned long config) 1743{ 1744 enum pin_config_param param = pinconf_to_config_param(config); 1745 u16 arg = pinconf_to_config_argument(config); 1746 struct npcm7xx_gpio *bank = 1747 &npcm->gpio_bank[pin / NPCM7XX_GPIO_PER_BANK]; 1748 int gpio = BIT(pin % bank->chip.gc.ngpio); 1749 1750 dev_dbg(bank->chip.gc.parent, "param=%d %d[GPIO]\n", param, pin); 1751 switch (param) { 1752 case PIN_CONFIG_BIAS_DISABLE: 1753 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1754 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1755 break; 1756 case PIN_CONFIG_BIAS_PULL_DOWN: 1757 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1758 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1759 break; 1760 case PIN_CONFIG_BIAS_PULL_UP: 1761 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_PD, gpio); 1762 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_PU, gpio); 1763 break; 1764 case PIN_CONFIG_INPUT_ENABLE: 1765 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OEC); 1766 bank->direction_input(&bank->chip.gc, pin % bank->chip.gc.ngpio); 1767 break; 1768 case PIN_CONFIG_LEVEL: 1769 bank->direction_output(&bank->chip.gc, pin % bank->chip.gc.ngpio, arg); 1770 iowrite32(gpio, bank->base + NPCM7XX_GP_N_OES); 1771 break; 1772 case PIN_CONFIG_DRIVE_PUSH_PULL: 1773 npcm_gpio_clr(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1774 break; 1775 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1776 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_OTYP, gpio); 1777 break; 1778 case PIN_CONFIG_INPUT_DEBOUNCE: 1779 npcm_gpio_set(&bank->chip, bank->base + NPCM7XX_GP_N_DBNC, gpio); 1780 break; 1781 case PIN_CONFIG_SLEW_RATE: 1782 return npcm7xx_set_slew_rate(bank, npcm->gcr_regmap, pin, arg); 1783 case PIN_CONFIG_DRIVE_STRENGTH: 1784 return npcm7xx_set_drive_strength(npcm, pin, arg); 1785 default: 1786 return -ENOTSUPP; 1787 } 1788 1789 return 0; 1790} 1791 1792/* Set multiple configuration settings for a pin */ 1793static int npcm7xx_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 1794 unsigned long *configs, unsigned int num_configs) 1795{ 1796 struct npcm7xx_pinctrl *npcm = pinctrl_dev_get_drvdata(pctldev); 1797 int rc; 1798 1799 while (num_configs--) { 1800 rc = npcm7xx_config_set_one(npcm, pin, *configs++); 1801 if (rc) 1802 return rc; 1803 } 1804 1805 return 0; 1806} 1807 1808static const struct pinconf_ops npcm7xx_pinconf_ops = { 1809 .is_generic = true, 1810 .pin_config_get = npcm7xx_config_get, 1811 .pin_config_set = npcm7xx_config_set, 1812}; 1813 1814/* pinctrl_desc */ 1815static const struct pinctrl_desc npcm7xx_pinctrl_desc = { 1816 .name = "npcm7xx-pinctrl", 1817 .pins = npcm7xx_pins, 1818 .npins = ARRAY_SIZE(npcm7xx_pins), 1819 .pctlops = &npcm7xx_pinctrl_ops, 1820 .pmxops = &npcm7xx_pinmux_ops, 1821 .confops = &npcm7xx_pinconf_ops, 1822 .owner = THIS_MODULE, 1823}; 1824 1825static int npcm7xx_gpio_of(struct npcm7xx_pinctrl *pctrl) 1826{ 1827 struct gpio_generic_chip_config config; 1828 int ret = -ENXIO; 1829 struct device *dev = pctrl->dev; 1830 struct fwnode_reference_args args; 1831 struct fwnode_handle *child; 1832 int id = 0; 1833 1834 for_each_gpiochip_node(dev, child) { 1835 pctrl->gpio_bank[id].base = fwnode_iomap(child, 0); 1836 if (!pctrl->gpio_bank[id].base) 1837 return -EINVAL; 1838 1839 config = (struct gpio_generic_chip_config) { 1840 .dev = dev, 1841 .sz = 4, 1842 .dat = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DIN, 1843 .set = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_DOUT, 1844 .dirin = pctrl->gpio_bank[id].base + NPCM7XX_GP_N_IEM, 1845 .flags = GPIO_GENERIC_READ_OUTPUT_REG_SET, 1846 }; 1847 1848 ret = gpio_generic_chip_init(&pctrl->gpio_bank[id].chip, &config); 1849 if (ret) { 1850 dev_err(dev, "failed to initialize the generic GPIO chip\n"); 1851 return ret; 1852 } 1853 1854 ret = fwnode_property_get_reference_args(child, "gpio-ranges", NULL, 3, 0, &args); 1855 if (ret < 0) { 1856 dev_err(dev, "gpio-ranges fail for GPIO bank %u\n", id); 1857 return ret; 1858 } 1859 1860 ret = fwnode_irq_get(child, 0); 1861 if (!ret) { 1862 dev_err(dev, "No IRQ for GPIO bank %u\n", id); 1863 return -EINVAL; 1864 } 1865 pctrl->gpio_bank[id].irq = ret; 1866 pctrl->gpio_bank[id].irqbase = id * NPCM7XX_GPIO_PER_BANK; 1867 pctrl->gpio_bank[id].pinctrl_id = args.args[0]; 1868 pctrl->gpio_bank[id].chip.gc.base = args.args[1]; 1869 pctrl->gpio_bank[id].chip.gc.ngpio = args.args[2]; 1870 pctrl->gpio_bank[id].chip.gc.owner = THIS_MODULE; 1871 pctrl->gpio_bank[id].chip.gc.parent = dev; 1872 pctrl->gpio_bank[id].chip.gc.fwnode = child; 1873 pctrl->gpio_bank[id].chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%pfw", child); 1874 if (pctrl->gpio_bank[id].chip.gc.label == NULL) 1875 return -ENOMEM; 1876 1877 pctrl->gpio_bank[id].chip.gc.dbg_show = npcmgpio_dbg_show; 1878 pctrl->gpio_bank[id].direction_input = pctrl->gpio_bank[id].chip.gc.direction_input; 1879 pctrl->gpio_bank[id].chip.gc.direction_input = npcmgpio_direction_input; 1880 pctrl->gpio_bank[id].direction_output = pctrl->gpio_bank[id].chip.gc.direction_output; 1881 pctrl->gpio_bank[id].chip.gc.direction_output = npcmgpio_direction_output; 1882 pctrl->gpio_bank[id].request = pctrl->gpio_bank[id].chip.gc.request; 1883 pctrl->gpio_bank[id].chip.gc.request = npcmgpio_gpio_request; 1884 pctrl->gpio_bank[id].chip.gc.free = pinctrl_gpio_free; 1885 id++; 1886 } 1887 1888 pctrl->bank_num = id; 1889 return ret; 1890} 1891 1892static int npcm7xx_gpio_register(struct npcm7xx_pinctrl *pctrl) 1893{ 1894 int ret, id; 1895 1896 for (id = 0 ; id < pctrl->bank_num ; id++) { 1897 struct gpio_irq_chip *girq; 1898 1899 girq = &pctrl->gpio_bank[id].chip.gc.irq; 1900 gpio_irq_chip_set_chip(girq, &npcmgpio_irqchip); 1901 girq->parent_handler = npcmgpio_irq_handler; 1902 girq->num_parents = 1; 1903 girq->parents = devm_kcalloc(pctrl->dev, 1, 1904 sizeof(*girq->parents), 1905 GFP_KERNEL); 1906 if (!girq->parents) { 1907 ret = -ENOMEM; 1908 goto err_register; 1909 } 1910 girq->parents[0] = pctrl->gpio_bank[id].irq; 1911 girq->default_type = IRQ_TYPE_NONE; 1912 girq->handler = handle_level_irq; 1913 ret = devm_gpiochip_add_data(pctrl->dev, 1914 &pctrl->gpio_bank[id].chip.gc, 1915 &pctrl->gpio_bank[id]); 1916 if (ret) { 1917 dev_err(pctrl->dev, "Failed to add GPIO chip %u\n", id); 1918 goto err_register; 1919 } 1920 1921 ret = gpiochip_add_pin_range(&pctrl->gpio_bank[id].chip.gc, 1922 dev_name(pctrl->dev), 1923 pctrl->gpio_bank[id].pinctrl_id, 1924 pctrl->gpio_bank[id].chip.gc.base, 1925 pctrl->gpio_bank[id].chip.gc.ngpio); 1926 if (ret < 0) { 1927 dev_err(pctrl->dev, "Failed to add GPIO bank %u\n", id); 1928 gpiochip_remove(&pctrl->gpio_bank[id].chip.gc); 1929 goto err_register; 1930 } 1931 } 1932 1933 return 0; 1934 1935err_register: 1936 for (; id > 0; id--) 1937 gpiochip_remove(&pctrl->gpio_bank[id - 1].chip.gc); 1938 1939 return ret; 1940} 1941 1942static int npcm7xx_pinctrl_probe(struct platform_device *pdev) 1943{ 1944 struct npcm7xx_pinctrl *pctrl; 1945 int ret; 1946 1947 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); 1948 if (!pctrl) 1949 return -ENOMEM; 1950 1951 pctrl->dev = &pdev->dev; 1952 dev_set_drvdata(&pdev->dev, pctrl); 1953 1954 pctrl->gcr_regmap = 1955 syscon_regmap_lookup_by_compatible("nuvoton,npcm750-gcr"); 1956 if (IS_ERR(pctrl->gcr_regmap)) { 1957 dev_err(pctrl->dev, "didn't find nuvoton,npcm750-gcr\n"); 1958 return PTR_ERR(pctrl->gcr_regmap); 1959 } 1960 1961 ret = npcm7xx_gpio_of(pctrl); 1962 if (ret < 0) { 1963 dev_err(pctrl->dev, "Failed to gpio dt-binding %u\n", ret); 1964 return ret; 1965 } 1966 1967 pctrl->pctldev = devm_pinctrl_register(&pdev->dev, 1968 &npcm7xx_pinctrl_desc, pctrl); 1969 if (IS_ERR(pctrl->pctldev)) { 1970 dev_err(&pdev->dev, "Failed to register pinctrl device\n"); 1971 return PTR_ERR(pctrl->pctldev); 1972 } 1973 1974 ret = npcm7xx_gpio_register(pctrl); 1975 if (ret < 0) { 1976 dev_err(pctrl->dev, "Failed to register gpio %u\n", ret); 1977 return ret; 1978 } 1979 1980 pr_info("NPCM7xx Pinctrl driver probed\n"); 1981 return 0; 1982} 1983 1984static const struct of_device_id npcm7xx_pinctrl_match[] = { 1985 { .compatible = "nuvoton,npcm750-pinctrl" }, 1986 { }, 1987}; 1988MODULE_DEVICE_TABLE(of, npcm7xx_pinctrl_match); 1989 1990static struct platform_driver npcm7xx_pinctrl_driver = { 1991 .probe = npcm7xx_pinctrl_probe, 1992 .driver = { 1993 .name = "npcm7xx-pinctrl", 1994 .of_match_table = npcm7xx_pinctrl_match, 1995 .suppress_bind_attrs = true, 1996 }, 1997}; 1998 1999static int __init npcm7xx_pinctrl_register(void) 2000{ 2001 return platform_driver_register(&npcm7xx_pinctrl_driver); 2002} 2003arch_initcall(npcm7xx_pinctrl_register); 2004 2005MODULE_AUTHOR("jordan_hargrave@dell.com"); 2006MODULE_AUTHOR("tomer.maimon@nuvoton.com"); 2007MODULE_DESCRIPTION("Nuvoton NPCM7XX Pinctrl and GPIO driver");
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