pinctrl-ma35.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (C) 2024 Nuvoton Technology Corp.
   4 *
   5 * Author: Shan-Chun Hung <schung@nuvoton.com>
   6 * *       Jacky Huang <ychuang3@nuvoton.com>
   7 */
   8
   9#include <linux/bitfield.h>
  10#include <linux/bitops.h>
  11#include <linux/cleanup.h>
  12#include <linux/clk.h>
  13#include <linux/gpio/driver.h>
  14#include <linux/mfd/syscon.h>
  15#include <linux/of.h>
  16#include <linux/platform_device.h>
  17#include <linux/property.h>
  18#include <linux/regmap.h>
  19
  20#include <linux/pinctrl/pinconf.h>
  21#include <linux/pinctrl/pinctrl.h>
  22#include "../core.h"
  23#include "../pinconf.h"
  24#include "pinctrl-ma35.h"
  25
  26#define MA35_MFP_REG_BASE		0x80
  27#define MA35_MFP_REG_SZ_PER_BANK	8
  28#define MA35_MFP_BITS_PER_PORT		4
  29
  30#define MA35_GPIO_BANK_MAX		14
  31#define MA35_GPIO_PORT_MAX		16
  32
  33/* GPIO control registers */
  34#define MA35_GP_REG_MODE		0x00
  35#define MA35_GP_REG_DINOFF		0x04
  36#define MA35_GP_REG_DOUT		0x08
  37#define MA35_GP_REG_DATMSK		0x0c
  38#define MA35_GP_REG_PIN			0x10
  39#define MA35_GP_REG_DBEN		0x14
  40#define MA35_GP_REG_INTTYPE		0x18
  41#define MA35_GP_REG_INTEN		0x1c
  42#define MA35_GP_REG_INTSRC		0x20
  43#define MA35_GP_REG_SMTEN		0x24
  44#define MA35_GP_REG_SLEWCTL		0x28
  45#define MA35_GP_REG_SPW			0x2c
  46#define MA35_GP_REG_PUSEL		0x30
  47#define MA35_GP_REG_DSL			0x38
  48#define MA35_GP_REG_DSH			0x3c
  49
  50/* GPIO mode control */
  51#define MA35_GP_MODE_INPUT		0x0
  52#define MA35_GP_MODE_OUTPUT		0x1
  53#define MA35_GP_MODE_OPEN_DRAIN		0x2
  54#define MA35_GP_MODE_QUASI		0x3
  55#define MA35_GP_MODE_MASK(n)		GENMASK(n * 2 + 1, n * 2)
  56
  57#define MA35_GP_SLEWCTL_MASK(n)		GENMASK(n * 2 + 1, n * 2)
  58
  59/* GPIO pull-up and pull-down selection control */
  60#define MA35_GP_PUSEL_DISABLE		0x0
  61#define MA35_GP_PUSEL_PULL_UP		0x1
  62#define MA35_GP_PUSEL_PULL_DOWN		0x2
  63#define MA35_GP_PUSEL_MASK(n)		GENMASK(n * 2 + 1, n * 2)
  64
  65/*
  66 * The MA35_GP_REG_INTEN bits 0 ~ 15 control low-level or falling edge trigger,
  67 * while bits 16 ~ 31 control high-level or rising edge trigger.
  68 */
  69#define MA35_GP_INTEN_L(n)		BIT(n)
  70#define MA35_GP_INTEN_H(n)		BIT(n + 16)
  71#define MA35_GP_INTEN_BOTH(n)		(MA35_GP_INTEN_H(n) | MA35_GP_INTEN_L(n))
  72
  73/*
  74 * The MA35_GP_REG_DSL register controls ports 0 to 7, while the MA35_GP_REG_DSH
  75 * register controls ports 8 to 15. Each port occupies a width of 4 bits, with 3
  76 * bits being effective.
  77 */
  78#define MA35_GP_DS_REG(n)		(n < 8 ? MA35_GP_REG_DSL : MA35_GP_REG_DSH)
  79#define MA35_GP_DS_MASK(n)		GENMASK((n % 8) * 4 + 3, (n % 8) * 4)
  80
  81#define MVOLT_1800			0
  82#define MVOLT_3300			1
  83
  84static const char * const gpio_group_name[] = {
  85	"gpioa", "gpiob", "gpioc", "gpiod", "gpioe", "gpiof", "gpiog",
  86	"gpioh", "gpioi", "gpioj", "gpiok", "gpiol", "gpiom", "gpion",
  87};
  88
  89static const u32 ds_1800mv_tbl[] = {
  90	2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000,
  91};
  92
  93static const u32 ds_3300mv_tbl[] = {
  94	17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000,
  95};
  96
  97struct ma35_pin_setting {
  98	u32			offset;
  99	u32			shift;
 100	u32			muxval;
 101	unsigned long		*configs;
 102	unsigned int		nconfigs;
 103};
 104
 105struct ma35_pin_bank {
 106	void __iomem		*reg_base;
 107	struct clk		*clk;
 108	int			irq;
 109	u8			bank_num;
 110	u8			nr_pins;
 111	bool			valid;
 112	const char		*name;
 113	struct fwnode_handle	*fwnode;
 114	struct gpio_chip	chip;
 115	u32			irqtype;
 116	u32			irqinten;
 117	struct regmap		*regmap;
 118	struct device		*dev;
 119};
 120
 121struct ma35_pin_ctrl {
 122	struct ma35_pin_bank	*pin_banks;
 123	u32			nr_banks;
 124	u32			nr_pins;
 125};
 126
 127struct ma35_pinctrl {
 128	struct device		*dev;
 129	struct ma35_pin_ctrl	*ctrl;
 130	struct pinctrl_dev	*pctl;
 131	const struct ma35_pinctrl_soc_info *info;
 132	struct regmap		*regmap;
 133	struct group_desc	*groups;
 134	unsigned int		ngroups;
 135	struct pinfunction	*functions;
 136	unsigned int		nfunctions;
 137};
 138
 139static DEFINE_RAW_SPINLOCK(ma35_lock);
 140
 141static int ma35_get_groups_count(struct pinctrl_dev *pctldev)
 142{
 143	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 144
 145	return npctl->ngroups;
 146}
 147
 148static const char *ma35_get_group_name(struct pinctrl_dev *pctldev, unsigned int selector)
 149{
 150	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 151
 152	return npctl->groups[selector].grp.name;
 153}
 154
 155static int ma35_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
 156			       const unsigned int **pins, unsigned int *npins)
 157{
 158	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 159
 160	if (selector >= npctl->ngroups)
 161		return -EINVAL;
 162
 163	*pins = npctl->groups[selector].grp.pins;
 164	*npins = npctl->groups[selector].grp.npins;
 165
 166	return 0;
 167}
 168
 169static struct group_desc *
 170ma35_pinctrl_find_group_by_name(const struct ma35_pinctrl *npctl, const char *name)
 171{
 172	int i;
 173
 174	for (i = 0; i < npctl->ngroups; i++) {
 175		if (!strcmp(npctl->groups[i].grp.name, name))
 176			return &npctl->groups[i];
 177	}
 178	return NULL;
 179}
 180
 181static int ma35_pinctrl_dt_node_to_map_func(struct pinctrl_dev *pctldev,
 182					    struct device_node *np,
 183					    struct pinctrl_map **map,
 184					    unsigned int *num_maps)
 185{
 186	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 187	struct ma35_pin_setting *setting;
 188	struct pinctrl_map *new_map;
 189	struct device_node *parent;
 190	struct group_desc *grp;
 191	int map_num = 1;
 192	int i;
 193
 194	/*
 195	 * first find the group of this node and check if we need create
 196	 * config maps for pins
 197	 */
 198	grp = ma35_pinctrl_find_group_by_name(npctl, np->name);
 199	if (!grp) {
 200		dev_err(npctl->dev, "unable to find group for node %s\n", np->name);
 201		return -EINVAL;
 202	}
 203
 204	map_num += grp->grp.npins;
 205	new_map = kcalloc(map_num, sizeof(*new_map), GFP_KERNEL);
 206	if (!new_map)
 207		return -ENOMEM;
 208
 209	*map = new_map;
 210	*num_maps = map_num;
 211	/* create mux map */
 212	parent = of_get_parent(np);
 213	if (!parent)
 214		return -EINVAL;
 215
 216	setting = grp->data;
 217
 218	new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
 219	new_map[0].data.mux.function = parent->name;
 220	new_map[0].data.mux.group = np->name;
 221	of_node_put(parent);
 222
 223	new_map++;
 224	for (i = 0; i < grp->grp.npins; i++) {
 225		new_map[i].type = PIN_MAP_TYPE_CONFIGS_PIN;
 226		new_map[i].data.configs.group_or_pin = pin_get_name(pctldev, grp->grp.pins[i]);
 227		new_map[i].data.configs.configs = setting[i].configs;
 228		new_map[i].data.configs.num_configs = setting[i].nconfigs;
 229	}
 230	dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
 231		(*map)->data.mux.function, (*map)->data.mux.group, map_num);
 232
 233	return 0;
 234}
 235
 236static const struct pinctrl_ops ma35_pctrl_ops = {
 237	.get_groups_count = ma35_get_groups_count,
 238	.get_group_name = ma35_get_group_name,
 239	.get_group_pins = ma35_get_group_pins,
 240	.dt_node_to_map = ma35_pinctrl_dt_node_to_map_func,
 241	.dt_free_map = pinconf_generic_dt_free_map,
 242};
 243
 244static int ma35_pinmux_get_func_count(struct pinctrl_dev *pctldev)
 245{
 246	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 247
 248	return npctl->nfunctions;
 249}
 250
 251static const char *ma35_pinmux_get_func_name(struct pinctrl_dev *pctldev,
 252					     unsigned int selector)
 253{
 254	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 255
 256	return npctl->functions[selector].name;
 257}
 258
 259static int ma35_pinmux_get_func_groups(struct pinctrl_dev *pctldev,
 260				       unsigned int function,
 261				       const char *const **groups,
 262				       unsigned int *const num_groups)
 263{
 264	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 265
 266	*groups = npctl->functions[function].groups;
 267	*num_groups = npctl->functions[function].ngroups;
 268
 269	return 0;
 270}
 271
 272static int ma35_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int selector,
 273			       unsigned int group)
 274{
 275	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 276	struct group_desc *grp = &npctl->groups[group];
 277	struct ma35_pin_setting *setting = grp->data;
 278	u32 i, regval;
 279
 280	dev_dbg(npctl->dev, "enable function %s group %s\n",
 281		npctl->functions[selector].name, grp->grp.name);
 282
 283	for (i = 0; i < grp->grp.npins; i++) {
 284		regmap_read(npctl->regmap, setting->offset, &regval);
 285		regval &= ~GENMASK(setting->shift + MA35_MFP_BITS_PER_PORT - 1,
 286				   setting->shift);
 287		regval |= setting->muxval << setting->shift;
 288		regmap_write(npctl->regmap, setting->offset, regval);
 289		setting++;
 290	}
 291	return 0;
 292}
 293
 294static const struct pinmux_ops ma35_pmx_ops = {
 295	.get_functions_count = ma35_pinmux_get_func_count,
 296	.get_function_name = ma35_pinmux_get_func_name,
 297	.get_function_groups = ma35_pinmux_get_func_groups,
 298	.set_mux = ma35_pinmux_set_mux,
 299	.strict = true,
 300};
 301
 302static void ma35_gpio_set_mode(void __iomem *reg_mode, unsigned int gpio, u32 mode)
 303{
 304	u32 regval = readl(reg_mode);
 305
 306	regval &= ~MA35_GP_MODE_MASK(gpio);
 307	regval |= field_prep(MA35_GP_MODE_MASK(gpio), mode);
 308
 309	writel(regval, reg_mode);
 310}
 311
 312static u32 ma35_gpio_get_mode(void __iomem *reg_mode, unsigned int gpio)
 313{
 314	u32 regval = readl(reg_mode);
 315
 316	return field_get(MA35_GP_MODE_MASK(gpio), regval);
 317}
 318
 319static int ma35_gpio_core_direction_in(struct gpio_chip *gc, unsigned int gpio)
 320{
 321	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
 322	void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
 323
 324	guard(raw_spinlock_irqsave)(&ma35_lock);
 325
 326	ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_INPUT);
 327
 328	return 0;
 329}
 330
 331static int ma35_gpio_core_direction_out(struct gpio_chip *gc, unsigned int gpio, int val)
 332{
 333	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
 334	void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
 335	void __iomem *reg_mode = bank->reg_base + MA35_GP_REG_MODE;
 336	unsigned int regval;
 337
 338	guard(raw_spinlock_irqsave)(&ma35_lock);
 339
 340	regval = readl(reg_dout);
 341	if (val)
 342		regval |= BIT(gpio);
 343	else
 344		regval &= ~BIT(gpio);
 345	writel(regval, reg_dout);
 346
 347	ma35_gpio_set_mode(reg_mode, gpio, MA35_GP_MODE_OUTPUT);
 348
 349	return 0;
 350}
 351
 352static int ma35_gpio_core_get(struct gpio_chip *gc, unsigned int gpio)
 353{
 354	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
 355	void __iomem *reg_pin = bank->reg_base + MA35_GP_REG_PIN;
 356
 357	return !!(readl(reg_pin) & BIT(gpio));
 358}
 359
 360static int ma35_gpio_core_set(struct gpio_chip *gc, unsigned int gpio, int val)
 361{
 362	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
 363	void __iomem *reg_dout = bank->reg_base + MA35_GP_REG_DOUT;
 364	u32 regval;
 365
 366	if (val)
 367		regval = readl(reg_dout) | BIT(gpio);
 368	else
 369		regval = readl(reg_dout) & ~BIT(gpio);
 370
 371	writel(regval, reg_dout);
 372
 373	return 0;
 374}
 375
 376static int ma35_gpio_core_to_request(struct gpio_chip *gc, unsigned int gpio)
 377{
 378	struct ma35_pin_bank *bank = gpiochip_get_data(gc);
 379	u32 reg_offs, bit_offs, regval;
 380
 381	if (gpio < 8) {
 382		/* The MFP low register controls port 0 ~ 7 */
 383		reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK;
 384		bit_offs = gpio * MA35_MFP_BITS_PER_PORT;
 385	} else {
 386		/* The MFP high register controls port 8 ~ 15 */
 387		reg_offs = bank->bank_num * MA35_MFP_REG_SZ_PER_BANK + 4;
 388		bit_offs = (gpio - 8) * MA35_MFP_BITS_PER_PORT;
 389	}
 390
 391	regmap_read(bank->regmap, MA35_MFP_REG_BASE + reg_offs, &regval);
 392	regval &= ~GENMASK(bit_offs + MA35_MFP_BITS_PER_PORT - 1, bit_offs);
 393	regmap_write(bank->regmap, MA35_MFP_REG_BASE + reg_offs, regval);
 394
 395	return 0;
 396}
 397
 398static void ma35_irq_gpio_ack(struct irq_data *d)
 399{
 400	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
 401	void __iomem *reg_intsrc = bank->reg_base + MA35_GP_REG_INTSRC;
 402	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 403
 404	writel(BIT(hwirq), reg_intsrc);
 405}
 406
 407static void ma35_irq_gpio_mask(struct irq_data *d)
 408{
 409	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
 410	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
 411	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 412	u32 regval;
 413
 414	regval = readl(reg_ien);
 415
 416	regval &= ~MA35_GP_INTEN_BOTH(hwirq);
 417
 418	writel(regval, reg_ien);
 419}
 420
 421static void ma35_irq_gpio_unmask(struct irq_data *d)
 422{
 423	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
 424	void __iomem *reg_itype = bank->reg_base + MA35_GP_REG_INTTYPE;
 425	void __iomem *reg_ien = bank->reg_base + MA35_GP_REG_INTEN;
 426	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 427	u32 bval, regval;
 428
 429	bval = bank->irqtype & BIT(hwirq);
 430	regval = readl(reg_itype);
 431	regval &= ~BIT(hwirq);
 432	writel(regval | bval, reg_itype);
 433
 434	bval = bank->irqinten & MA35_GP_INTEN_BOTH(hwirq);
 435	regval = readl(reg_ien);
 436	regval &= ~MA35_GP_INTEN_BOTH(hwirq);
 437	writel(regval | bval, reg_ien);
 438}
 439
 440static int ma35_irq_irqtype(struct irq_data *d, unsigned int type)
 441{
 442	struct ma35_pin_bank *bank = gpiochip_get_data(irq_data_get_irq_chip_data(d));
 443	irq_hw_number_t hwirq = irqd_to_hwirq(d);
 444
 445	switch (type) {
 446	case IRQ_TYPE_EDGE_BOTH:
 447		irq_set_handler_locked(d, handle_edge_irq);
 448		bank->irqtype &= ~BIT(hwirq);
 449		bank->irqinten |= MA35_GP_INTEN_BOTH(hwirq);
 450		break;
 451	case IRQ_TYPE_EDGE_RISING:
 452	case IRQ_TYPE_LEVEL_HIGH:
 453		irq_set_handler_locked(d, handle_edge_irq);
 454		bank->irqtype &= ~BIT(hwirq);
 455		bank->irqinten |= MA35_GP_INTEN_H(hwirq);
 456		bank->irqinten &= ~MA35_GP_INTEN_L(hwirq);
 457		break;
 458	case IRQ_TYPE_EDGE_FALLING:
 459	case IRQ_TYPE_LEVEL_LOW:
 460		irq_set_handler_locked(d, handle_edge_irq);
 461		bank->irqtype &= ~BIT(hwirq);
 462		bank->irqinten |= MA35_GP_INTEN_L(hwirq);
 463		bank->irqinten &= ~MA35_GP_INTEN_H(hwirq);
 464		break;
 465	default:
 466		return -EINVAL;
 467	}
 468
 469	writel(bank->irqtype, bank->reg_base + MA35_GP_REG_INTTYPE);
 470	writel(bank->irqinten, bank->reg_base + MA35_GP_REG_INTEN);
 471
 472	return 0;
 473}
 474
 475static struct irq_chip ma35_gpio_irqchip = {
 476	.name = "MA35-GPIO-IRQ",
 477	.irq_disable = ma35_irq_gpio_mask,
 478	.irq_enable = ma35_irq_gpio_unmask,
 479	.irq_ack = ma35_irq_gpio_ack,
 480	.irq_mask = ma35_irq_gpio_mask,
 481	.irq_unmask = ma35_irq_gpio_unmask,
 482	.irq_set_type = ma35_irq_irqtype,
 483	.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE,
 484	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 485};
 486
 487static void ma35_irq_demux_intgroup(struct irq_desc *desc)
 488{
 489	struct ma35_pin_bank *bank = gpiochip_get_data(irq_desc_get_handler_data(desc));
 490	struct irq_domain *irqdomain = bank->chip.irq.domain;
 491	struct irq_chip *irqchip = irq_desc_get_chip(desc);
 492	unsigned long isr;
 493	int offset;
 494
 495	chained_irq_enter(irqchip, desc);
 496
 497	isr = readl(bank->reg_base + MA35_GP_REG_INTSRC);
 498
 499	for_each_set_bit(offset, &isr, bank->nr_pins)
 500		generic_handle_irq(irq_find_mapping(irqdomain, offset));
 501
 502	chained_irq_exit(irqchip, desc);
 503}
 504
 505static int ma35_gpiolib_register(struct platform_device *pdev, struct ma35_pinctrl *npctl)
 506{
 507	struct ma35_pin_ctrl *ctrl = npctl->ctrl;
 508	struct ma35_pin_bank *bank = ctrl->pin_banks;
 509	int ret;
 510	int i;
 511
 512	for (i = 0; i < ctrl->nr_banks; i++, bank++) {
 513		if (!bank->valid) {
 514			dev_warn(&pdev->dev, "%pfw: bank is not valid\n", bank->fwnode);
 515			continue;
 516		}
 517		bank->irqtype = 0;
 518		bank->irqinten = 0;
 519		bank->chip.label = bank->name;
 520		bank->chip.parent = &pdev->dev;
 521		bank->chip.request = ma35_gpio_core_to_request;
 522		bank->chip.direction_input = ma35_gpio_core_direction_in;
 523		bank->chip.direction_output = ma35_gpio_core_direction_out;
 524		bank->chip.get = ma35_gpio_core_get;
 525		bank->chip.set = ma35_gpio_core_set;
 526		bank->chip.base = -1;
 527		bank->chip.ngpio = bank->nr_pins;
 528		bank->chip.can_sleep = false;
 529
 530		if (bank->irq > 0) {
 531			struct gpio_irq_chip *girq;
 532
 533			girq = &bank->chip.irq;
 534			gpio_irq_chip_set_chip(girq, &ma35_gpio_irqchip);
 535			girq->parent_handler = ma35_irq_demux_intgroup;
 536			girq->num_parents = 1;
 537
 538			girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents,
 539						     sizeof(*girq->parents), GFP_KERNEL);
 540			if (!girq->parents)
 541				return -ENOMEM;
 542
 543			girq->parents[0] = bank->irq;
 544			girq->default_type = IRQ_TYPE_NONE;
 545			girq->handler = handle_bad_irq;
 546		}
 547
 548		ret = devm_gpiochip_add_data(&pdev->dev, &bank->chip, bank);
 549		if (ret) {
 550			dev_err(&pdev->dev, "failed to register gpio_chip %s, error code: %d\n",
 551				bank->chip.label, ret);
 552			return ret;
 553		}
 554	}
 555	return 0;
 556}
 557
 558static int ma35_get_bank_data(struct ma35_pin_bank *bank)
 559{
 560	bank->reg_base = fwnode_iomap(bank->fwnode, 0);
 561	if (!bank->reg_base)
 562		return -ENOMEM;
 563
 564	bank->irq = fwnode_irq_get(bank->fwnode, 0);
 565
 566	bank->nr_pins = MA35_GPIO_PORT_MAX;
 567
 568	bank->clk = of_clk_get(to_of_node(bank->fwnode), 0);
 569	if (IS_ERR(bank->clk))
 570		return PTR_ERR(bank->clk);
 571
 572	return clk_prepare_enable(bank->clk);
 573}
 574
 575static int ma35_pinctrl_get_soc_data(struct ma35_pinctrl *pctl, struct platform_device *pdev)
 576{
 577	struct fwnode_handle *child;
 578	struct ma35_pin_ctrl *ctrl;
 579	struct ma35_pin_bank *bank;
 580	int i, id = 0;
 581
 582	ctrl = pctl->ctrl;
 583	ctrl->nr_banks = MA35_GPIO_BANK_MAX;
 584
 585	ctrl->pin_banks = devm_kcalloc(&pdev->dev, ctrl->nr_banks,
 586				       sizeof(*ctrl->pin_banks), GFP_KERNEL);
 587	if (!ctrl->pin_banks)
 588		return -ENOMEM;
 589
 590	for (i = 0; i < ctrl->nr_banks; i++) {
 591		ctrl->pin_banks[i].bank_num = i;
 592		ctrl->pin_banks[i].name = gpio_group_name[i];
 593	}
 594
 595	for_each_gpiochip_node(&pdev->dev, child) {
 596		bank = &ctrl->pin_banks[id];
 597		bank->fwnode = child;
 598		bank->regmap = pctl->regmap;
 599		bank->dev = &pdev->dev;
 600		if (!ma35_get_bank_data(bank))
 601			bank->valid = true;
 602		id++;
 603	}
 604	return 0;
 605}
 606
 607static void ma35_gpio_cla_port(unsigned int gpio_num, unsigned int *group,
 608			       unsigned int *num)
 609{
 610	*group = gpio_num / MA35_GPIO_PORT_MAX;
 611	*num = gpio_num % MA35_GPIO_PORT_MAX;
 612}
 613
 614static int ma35_pinconf_set_pull(struct ma35_pinctrl *npctl, unsigned int pin,
 615				 int pull_up)
 616{
 617	unsigned int port, group_num;
 618	void __iomem *base;
 619	u32 regval, pull_sel = MA35_GP_PUSEL_DISABLE;
 620
 621	ma35_gpio_cla_port(pin, &group_num, &port);
 622	base = npctl->ctrl->pin_banks[group_num].reg_base;
 623
 624	regval = readl(base + MA35_GP_REG_PUSEL);
 625	regval &= ~MA35_GP_PUSEL_MASK(port);
 626
 627	switch (pull_up) {
 628	case PIN_CONFIG_BIAS_PULL_UP:
 629		pull_sel = MA35_GP_PUSEL_PULL_UP;
 630		break;
 631
 632	case PIN_CONFIG_BIAS_PULL_DOWN:
 633		pull_sel = MA35_GP_PUSEL_PULL_DOWN;
 634		break;
 635
 636	case PIN_CONFIG_BIAS_DISABLE:
 637		pull_sel = MA35_GP_PUSEL_DISABLE;
 638		break;
 639	}
 640
 641	regval |= field_prep(MA35_GP_PUSEL_MASK(port), pull_sel);
 642	writel(regval, base + MA35_GP_REG_PUSEL);
 643
 644	return 0;
 645}
 646
 647static int ma35_pinconf_get_output(struct ma35_pinctrl *npctl, unsigned int pin)
 648{
 649	unsigned int port, group_num;
 650	void __iomem *base;
 651	u32 mode;
 652
 653	ma35_gpio_cla_port(pin, &group_num, &port);
 654	base = npctl->ctrl->pin_banks[group_num].reg_base;
 655
 656	mode = ma35_gpio_get_mode(base + MA35_GP_REG_MODE, port);
 657	if (mode == MA35_GP_MODE_OUTPUT)
 658		return 1;
 659
 660	return 0;
 661}
 662
 663static int ma35_pinconf_get_pull(struct ma35_pinctrl *npctl, unsigned int pin)
 664{
 665	unsigned int port, group_num;
 666	void __iomem *base;
 667	u32 regval, pull_sel;
 668
 669	ma35_gpio_cla_port(pin, &group_num, &port);
 670	base = npctl->ctrl->pin_banks[group_num].reg_base;
 671
 672	regval = readl(base + MA35_GP_REG_PUSEL);
 673
 674	pull_sel = field_get(MA35_GP_PUSEL_MASK(port), regval);
 675
 676	switch (pull_sel) {
 677	case MA35_GP_PUSEL_PULL_UP:
 678		return PIN_CONFIG_BIAS_PULL_UP;
 679
 680	case MA35_GP_PUSEL_PULL_DOWN:
 681		return PIN_CONFIG_BIAS_PULL_DOWN;
 682
 683	case MA35_GP_PUSEL_DISABLE:
 684		return PIN_CONFIG_BIAS_DISABLE;
 685	}
 686
 687	return PIN_CONFIG_BIAS_DISABLE;
 688}
 689
 690static int ma35_pinconf_set_output(struct ma35_pinctrl *npctl, unsigned int pin, bool out)
 691{
 692	unsigned int port, group_num;
 693	void __iomem *base;
 694
 695	ma35_gpio_cla_port(pin, &group_num, &port);
 696	base = npctl->ctrl->pin_banks[group_num].reg_base;
 697
 698	ma35_gpio_set_mode(base + MA35_GP_REG_MODE, port, MA35_GP_MODE_OUTPUT);
 699
 700	return 0;
 701}
 702
 703static int ma35_pinconf_get_power_source(struct ma35_pinctrl *npctl, unsigned int pin)
 704{
 705	unsigned int port, group_num;
 706	void __iomem *base;
 707	u32 regval;
 708
 709	ma35_gpio_cla_port(pin, &group_num, &port);
 710	base = npctl->ctrl->pin_banks[group_num].reg_base;
 711
 712	regval = readl(base + MA35_GP_REG_SPW);
 713
 714	if (regval & BIT(port))
 715		return MVOLT_3300;
 716	else
 717		return MVOLT_1800;
 718}
 719
 720static int ma35_pinconf_set_power_source(struct ma35_pinctrl *npctl,
 721					 unsigned int pin, int arg)
 722{
 723	unsigned int port, group_num;
 724	void __iomem *base;
 725	u32 regval;
 726
 727	if ((arg != MVOLT_1800) && (arg != MVOLT_3300))
 728		return -EINVAL;
 729
 730	ma35_gpio_cla_port(pin, &group_num, &port);
 731	base = npctl->ctrl->pin_banks[group_num].reg_base;
 732
 733	regval = readl(base + MA35_GP_REG_SPW);
 734
 735	if (arg == MVOLT_1800)
 736		regval &= ~BIT(port);
 737	else
 738		regval |= BIT(port);
 739
 740	writel(regval, base + MA35_GP_REG_SPW);
 741
 742	return 0;
 743}
 744
 745static int ma35_pinconf_get_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
 746					   u32 *strength)
 747{
 748	unsigned int port, group_num;
 749	void __iomem *base;
 750	u32 regval, ds_val;
 751
 752	ma35_gpio_cla_port(pin, &group_num, &port);
 753	base = npctl->ctrl->pin_banks[group_num].reg_base;
 754
 755	regval = readl(base + MA35_GP_DS_REG(port));
 756	ds_val = field_get(MA35_GP_DS_MASK(port), regval);
 757
 758	if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800)
 759		*strength = ds_1800mv_tbl[ds_val];
 760	else
 761		*strength = ds_3300mv_tbl[ds_val];
 762
 763	return 0;
 764}
 765
 766static int ma35_pinconf_set_drive_strength(struct ma35_pinctrl *npctl, unsigned int pin,
 767					   int strength)
 768{
 769	unsigned int port, group_num;
 770	void __iomem *base;
 771	int i, ds_val = -1;
 772	u32 regval;
 773
 774	if (ma35_pinconf_get_power_source(npctl, pin) == MVOLT_1800) {
 775		for (i = 0; i < ARRAY_SIZE(ds_1800mv_tbl); i++) {
 776			if (ds_1800mv_tbl[i] == strength) {
 777				ds_val = i;
 778				break;
 779			}
 780		}
 781	} else {
 782		for (i = 0; i < ARRAY_SIZE(ds_3300mv_tbl); i++) {
 783			if (ds_3300mv_tbl[i] == strength) {
 784				ds_val = i;
 785				break;
 786			}
 787		}
 788	}
 789	if (ds_val == -1)
 790		return -EINVAL;
 791
 792	ma35_gpio_cla_port(pin, &group_num, &port);
 793	base = npctl->ctrl->pin_banks[group_num].reg_base;
 794
 795	regval = readl(base + MA35_GP_DS_REG(port));
 796	regval &= ~MA35_GP_DS_MASK(port);
 797	regval |= field_prep(MA35_GP_DS_MASK(port), ds_val);
 798
 799	writel(regval, base + MA35_GP_DS_REG(port));
 800
 801	return 0;
 802}
 803
 804static int ma35_pinconf_get_schmitt_enable(struct ma35_pinctrl *npctl, unsigned int pin)
 805{
 806	unsigned int port, group_num;
 807	void __iomem *base;
 808	u32 regval;
 809
 810	ma35_gpio_cla_port(pin, &group_num, &port);
 811	base = npctl->ctrl->pin_banks[group_num].reg_base;
 812
 813	regval = readl(base + MA35_GP_REG_SMTEN);
 814
 815	return !!(regval & BIT(port));
 816}
 817
 818static int ma35_pinconf_set_schmitt(struct ma35_pinctrl *npctl, unsigned int pin, int enable)
 819{
 820	unsigned int port, group_num;
 821	void __iomem *base;
 822	u32 regval;
 823
 824	ma35_gpio_cla_port(pin, &group_num, &port);
 825	base = npctl->ctrl->pin_banks[group_num].reg_base;
 826
 827	regval = readl(base + MA35_GP_REG_SMTEN);
 828
 829	if (enable)
 830		regval |= BIT(port);
 831	else
 832		regval &= ~BIT(port);
 833
 834	writel(regval, base + MA35_GP_REG_SMTEN);
 835
 836	return 0;
 837}
 838
 839static int ma35_pinconf_get_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin)
 840{
 841	unsigned int port, group_num;
 842	void __iomem *base;
 843	u32 regval;
 844
 845	ma35_gpio_cla_port(pin, &group_num, &port);
 846	base = npctl->ctrl->pin_banks[group_num].reg_base;
 847
 848	regval = readl(base + MA35_GP_REG_SLEWCTL);
 849
 850	return field_get(MA35_GP_SLEWCTL_MASK(port), regval);
 851}
 852
 853static int ma35_pinconf_set_slew_rate(struct ma35_pinctrl *npctl, unsigned int pin, int rate)
 854{
 855	unsigned int port, group_num;
 856	void __iomem *base;
 857	u32 regval;
 858
 859	ma35_gpio_cla_port(pin, &group_num, &port);
 860	base = npctl->ctrl->pin_banks[group_num].reg_base;
 861
 862	regval = readl(base + MA35_GP_REG_SLEWCTL);
 863	regval &= ~MA35_GP_SLEWCTL_MASK(port);
 864	regval |= field_prep(MA35_GP_SLEWCTL_MASK(port), rate);
 865
 866	writel(regval, base + MA35_GP_REG_SLEWCTL);
 867
 868	return 0;
 869}
 870
 871static int ma35_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin, unsigned long *config)
 872{
 873	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 874	enum pin_config_param param = pinconf_to_config_param(*config);
 875	u32 arg;
 876	int ret;
 877
 878	switch (param) {
 879	case PIN_CONFIG_BIAS_DISABLE:
 880	case PIN_CONFIG_BIAS_PULL_DOWN:
 881	case PIN_CONFIG_BIAS_PULL_UP:
 882		if (ma35_pinconf_get_pull(npctl, pin) != param)
 883			return -EINVAL;
 884		arg = 1;
 885		break;
 886
 887	case PIN_CONFIG_DRIVE_STRENGTH:
 888		ret = ma35_pinconf_get_drive_strength(npctl, pin, &arg);
 889		if (ret)
 890			return ret;
 891		break;
 892
 893	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 894		arg = ma35_pinconf_get_schmitt_enable(npctl, pin);
 895		break;
 896
 897	case PIN_CONFIG_SLEW_RATE:
 898		arg = ma35_pinconf_get_slew_rate(npctl, pin);
 899		break;
 900
 901	case PIN_CONFIG_OUTPUT_ENABLE:
 902		arg = ma35_pinconf_get_output(npctl, pin);
 903		break;
 904
 905	case PIN_CONFIG_POWER_SOURCE:
 906		arg = ma35_pinconf_get_power_source(npctl, pin);
 907		break;
 908
 909	default:
 910		return -EINVAL;
 911	}
 912	*config = pinconf_to_config_packed(param, arg);
 913
 914	return 0;
 915}
 916
 917static int ma35_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 918			    unsigned long *configs, unsigned int num_configs)
 919{
 920	struct ma35_pinctrl *npctl = pinctrl_dev_get_drvdata(pctldev);
 921	enum pin_config_param param;
 922	unsigned int arg = 0;
 923	int i, ret = 0;
 924
 925	for (i = 0; i < num_configs; i++) {
 926		param = pinconf_to_config_param(configs[i]);
 927		arg = pinconf_to_config_argument(configs[i]);
 928
 929		switch (param) {
 930		case PIN_CONFIG_BIAS_DISABLE:
 931		case PIN_CONFIG_BIAS_PULL_UP:
 932		case PIN_CONFIG_BIAS_PULL_DOWN:
 933			ret = ma35_pinconf_set_pull(npctl, pin, param);
 934			break;
 935
 936		case PIN_CONFIG_DRIVE_STRENGTH:
 937			ret = ma35_pinconf_set_drive_strength(npctl, pin, arg);
 938			break;
 939
 940		case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
 941			ret = ma35_pinconf_set_schmitt(npctl, pin, 1);
 942			break;
 943
 944		case PIN_CONFIG_INPUT_SCHMITT:
 945			ret = ma35_pinconf_set_schmitt(npctl, pin, arg);
 946			break;
 947
 948		case PIN_CONFIG_SLEW_RATE:
 949			ret = ma35_pinconf_set_slew_rate(npctl, pin, arg);
 950			break;
 951
 952		case PIN_CONFIG_OUTPUT_ENABLE:
 953			ret = ma35_pinconf_set_output(npctl, pin, arg);
 954			break;
 955
 956		case PIN_CONFIG_POWER_SOURCE:
 957			ret = ma35_pinconf_set_power_source(npctl, pin, arg);
 958			break;
 959
 960		default:
 961			return -EINVAL;
 962		}
 963
 964		if (ret)
 965			break;
 966	}
 967	return ret;
 968}
 969
 970static const struct pinconf_ops ma35_pinconf_ops = {
 971	.pin_config_get = ma35_pinconf_get,
 972	.pin_config_set = ma35_pinconf_set,
 973	.is_generic = true,
 974};
 975
 976static int ma35_pinctrl_parse_groups(struct fwnode_handle *fwnode, struct group_desc *grp,
 977				     struct ma35_pinctrl *npctl, u32 index)
 978{
 979	struct device_node *np = to_of_node(fwnode);
 980	struct ma35_pin_setting *pin;
 981	unsigned long *configs;
 982	unsigned int nconfigs;
 983	unsigned int *pins;
 984	int i, j, count, ret;
 985	u32 *elems;
 986
 987	ret = pinconf_generic_parse_dt_config(np, NULL, &configs, &nconfigs);
 988	if (ret)
 989		return ret;
 990
 991	count = fwnode_property_count_u32(fwnode, "nuvoton,pins");
 992	if (!count || count % 3)
 993		return -EINVAL;
 994
 995	elems = devm_kmalloc_array(npctl->dev, count, sizeof(u32), GFP_KERNEL);
 996	if (!elems)
 997		return -ENOMEM;
 998
 999	grp->grp.name = np->name;
1000
1001	ret = fwnode_property_read_u32_array(fwnode, "nuvoton,pins", elems, count);
1002	if (ret)
1003		return -EINVAL;
1004	grp->grp.npins = count / 3;
1005
1006	pins = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pins), GFP_KERNEL);
1007	if (!pins)
1008		return -ENOMEM;
1009	grp->grp.pins = pins;
1010
1011	pin = devm_kcalloc(npctl->dev, grp->grp.npins, sizeof(*pin), GFP_KERNEL);
1012	if (!pin)
1013		return -ENOMEM;
1014	grp->data = pin;
1015
1016	for (i = 0, j = 0; i < count; i += 3, j++) {
1017		pin->offset = elems[i] * MA35_MFP_REG_SZ_PER_BANK + MA35_MFP_REG_BASE;
1018		pin->shift = (elems[i + 1] * MA35_MFP_BITS_PER_PORT) % 32;
1019		pin->muxval = elems[i + 2];
1020		pin->configs = configs;
1021		pin->nconfigs = nconfigs;
1022		pins[j] = npctl->info->get_pin_num(pin->offset, pin->shift);
1023		pin++;
1024	}
1025	return 0;
1026}
1027
1028static int ma35_pinctrl_parse_functions(struct fwnode_handle *fwnode, struct ma35_pinctrl *npctl,
1029					u32 index)
1030{
1031	struct device_node *np = to_of_node(fwnode);
1032	struct fwnode_handle *child;
1033	struct pinfunction *func;
1034	struct group_desc *grp;
1035	static u32 grp_index;
1036	const char **groups;
1037	u32 i = 0;
1038	int ret;
1039
1040	dev_dbg(npctl->dev, "parse function(%d): %s\n", index, np->name);
1041
1042	func = &npctl->functions[index];
1043	func->name = np->name;
1044	func->ngroups = of_get_child_count(np);
1045
1046	if (func->ngroups <= 0)
1047		return 0;
1048
1049	groups = devm_kcalloc(npctl->dev, func->ngroups, sizeof(*groups), GFP_KERNEL);
1050	if (!groups)
1051		return -ENOMEM;
1052
1053	fwnode_for_each_child_node(fwnode, child) {
1054		struct device_node *node = to_of_node(child);
1055
1056		groups[i] = node->name;
1057		grp = &npctl->groups[grp_index++];
1058		ret = ma35_pinctrl_parse_groups(child, grp, npctl, i++);
1059		if (ret) {
1060			fwnode_handle_put(child);
1061			return ret;
1062		}
1063	}
1064
1065	func->groups = groups;
1066	return 0;
1067}
1068
1069static int ma35_pinctrl_probe_dt(struct platform_device *pdev, struct ma35_pinctrl *npctl)
1070{
1071	struct device *dev = &pdev->dev;
1072	struct fwnode_handle *child;
1073	u32 idx = 0;
1074	int ret;
1075
1076	device_for_each_child_node(dev, child) {
1077		if (fwnode_property_present(child, "gpio-controller"))
1078			continue;
1079
1080		npctl->nfunctions++;
1081		npctl->ngroups += of_get_child_count(to_of_node(child));
1082	}
1083
1084	if (!npctl->nfunctions)
1085		return -EINVAL;
1086
1087	npctl->functions = devm_kcalloc(&pdev->dev, npctl->nfunctions,
1088					sizeof(*npctl->functions), GFP_KERNEL);
1089	if (!npctl->functions)
1090		return -ENOMEM;
1091
1092	npctl->groups = devm_kcalloc(&pdev->dev, npctl->ngroups,
1093				     sizeof(*npctl->groups), GFP_KERNEL);
1094	if (!npctl->groups)
1095		return -ENOMEM;
1096
1097	device_for_each_child_node(dev, child) {
1098		if (fwnode_property_present(child, "gpio-controller"))
1099			continue;
1100
1101		ret = ma35_pinctrl_parse_functions(child, npctl, idx++);
1102		if (ret) {
1103			fwnode_handle_put(child);
1104			dev_err(&pdev->dev, "failed to parse function\n");
1105			return ret;
1106		}
1107	}
1108	return 0;
1109}
1110
1111int ma35_pinctrl_probe(struct platform_device *pdev, const struct ma35_pinctrl_soc_info *info)
1112{
1113	struct pinctrl_desc *ma35_pinctrl_desc;
1114	struct device *dev = &pdev->dev;
1115	struct ma35_pinctrl *npctl;
1116	int ret;
1117
1118	if (!info || !info->pins || !info->npins) {
1119		dev_err(&pdev->dev, "wrong pinctrl info\n");
1120		return -EINVAL;
1121	}
1122
1123	npctl = devm_kzalloc(&pdev->dev, sizeof(*npctl), GFP_KERNEL);
1124	if (!npctl)
1125		return -ENOMEM;
1126
1127	ma35_pinctrl_desc = devm_kzalloc(&pdev->dev, sizeof(*ma35_pinctrl_desc), GFP_KERNEL);
1128	if (!ma35_pinctrl_desc)
1129		return -ENOMEM;
1130
1131	npctl->ctrl = devm_kzalloc(&pdev->dev, sizeof(*npctl->ctrl), GFP_KERNEL);
1132	if (!npctl->ctrl)
1133		return -ENOMEM;
1134
1135	ma35_pinctrl_desc->name = dev_name(&pdev->dev);
1136	ma35_pinctrl_desc->pins = info->pins;
1137	ma35_pinctrl_desc->npins = info->npins;
1138	ma35_pinctrl_desc->pctlops = &ma35_pctrl_ops;
1139	ma35_pinctrl_desc->pmxops = &ma35_pmx_ops;
1140	ma35_pinctrl_desc->confops = &ma35_pinconf_ops;
1141	ma35_pinctrl_desc->owner = THIS_MODULE;
1142
1143	npctl->info = info;
1144	npctl->dev = &pdev->dev;
1145
1146	npctl->regmap = syscon_regmap_lookup_by_phandle(dev_of_node(dev), "nuvoton,sys");
1147	if (IS_ERR(npctl->regmap))
1148		return dev_err_probe(&pdev->dev, PTR_ERR(npctl->regmap),
1149				     "No syscfg phandle specified\n");
1150
1151	ret = ma35_pinctrl_get_soc_data(npctl, pdev);
1152	if (ret)
1153		return dev_err_probe(&pdev->dev, ret, "fail to get soc data\n");
1154
1155	platform_set_drvdata(pdev, npctl);
1156
1157	ret = ma35_pinctrl_probe_dt(pdev, npctl);
1158	if (ret)
1159		return dev_err_probe(&pdev->dev, ret, "fail to probe MA35 pinctrl dt\n");
1160
1161	ret = devm_pinctrl_register_and_init(dev, ma35_pinctrl_desc, npctl, &npctl->pctl);
1162	if (ret)
1163		return dev_err_probe(&pdev->dev, ret, "fail to register MA35 pinctrl\n");
1164
1165	ret = pinctrl_enable(npctl->pctl);
1166	if (ret)
1167		return dev_err_probe(&pdev->dev, ret, "fail to enable MA35 pinctrl\n");
1168
1169	return ma35_gpiolib_register(pdev, npctl);
1170}
1171
1172int ma35_pinctrl_suspend(struct device *dev)
1173{
1174	struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
1175
1176	return pinctrl_force_sleep(npctl->pctl);
1177}
1178
1179int ma35_pinctrl_resume(struct device *dev)
1180{
1181	struct ma35_pinctrl *npctl = dev_get_drvdata(dev);
1182
1183	return pinctrl_force_default(npctl->pctl);
1184}