pinctrl-nomadik.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Pinmux & pinconf driver for the IP block found in the Nomadik SoC. This
   4 * depends on gpio-nomadik and some handling is intertwined; see nmk_gpio_chips
   5 * which is used by this driver to access the GPIO banks array.
   6 *
   7 * Copyright (C) 2008,2009 STMicroelectronics
   8 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
   9 *   Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
  10 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
  11 */
  12
  13#include <linux/bitops.h>
  14#include <linux/cleanup.h>
  15#include <linux/clk.h>
  16#include <linux/device.h>
  17#include <linux/err.h>
  18#include <linux/gpio/driver.h>
  19#include <linux/init.h>
  20#include <linux/interrupt.h>
  21#include <linux/io.h>
  22#include <linux/kernel.h>
  23#include <linux/of.h>
  24#include <linux/of_address.h>
  25#include <linux/of_platform.h>
  26#include <linux/platform_device.h>
  27#include <linux/property.h>
  28#include <linux/seq_file.h>
  29#include <linux/slab.h>
  30#include <linux/spinlock.h>
  31#include <linux/string_choices.h>
  32#include <linux/types.h>
  33
  34/* Since we request GPIOs from ourself */
  35#include <linux/pinctrl/consumer.h>
  36#include <linux/pinctrl/machine.h>
  37#include <linux/pinctrl/pinconf.h>
  38#include <linux/pinctrl/pinctrl.h>
  39#include <linux/pinctrl/pinmux.h>
  40
  41#include "../core.h"
  42#include "../pinctrl-utils.h"
  43
  44#include <linux/gpio/gpio-nomadik.h>
  45
  46/*
  47 * pin configurations are represented by 32-bit integers:
  48 *
  49 *	bit  0.. 8 - Pin Number (512 Pins Maximum)
  50 *	bit  9..10 - Alternate Function Selection
  51 *	bit 11..12 - Pull up/down state
  52 *	bit     13 - Sleep mode behaviour
  53 *	bit     14 - Direction
  54 *	bit     15 - Value (if output)
  55 *	bit 16..18 - SLPM pull up/down state
  56 *	bit 19..20 - SLPM direction
  57 *	bit 21..22 - SLPM Value (if output)
  58 *	bit 23..25 - PDIS value (if input)
  59 *	bit	26 - Gpio mode
  60 *	bit	27 - Sleep mode
  61 *
  62 * to facilitate the definition, the following macros are provided
  63 *
  64 * PIN_CFG_DEFAULT - default config (0):
  65 *		     pull up/down = disabled
  66 *		     sleep mode = input/wakeup
  67 *		     direction = input
  68 *		     value = low
  69 *		     SLPM direction = same as normal
  70 *		     SLPM pull = same as normal
  71 *		     SLPM value = same as normal
  72 *
  73 * PIN_CFG	   - default config with alternate function
  74 */
  75
  76#define PIN_NUM_MASK		0x1ff
  77#define PIN_NUM(x)		((x) & PIN_NUM_MASK)
  78
  79#define PIN_ALT_SHIFT		9
  80#define PIN_ALT_MASK		(0x3 << PIN_ALT_SHIFT)
  81#define PIN_ALT(x)		(((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
  82#define PIN_GPIO		(NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
  83#define PIN_ALT_A		(NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
  84#define PIN_ALT_B		(NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
  85#define PIN_ALT_C		(NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
  86
  87#define PIN_PULL_SHIFT		11
  88#define PIN_PULL_MASK		(0x3 << PIN_PULL_SHIFT)
  89#define PIN_PULL(x)		(((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
  90#define PIN_PULL_NONE		(NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
  91#define PIN_PULL_UP		(NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
  92#define PIN_PULL_DOWN		(NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
  93
  94#define PIN_SLPM_SHIFT		13
  95#define PIN_SLPM_MASK		(0x1 << PIN_SLPM_SHIFT)
  96#define PIN_SLPM(x)		(((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
  97#define PIN_SLPM_MAKE_INPUT	(NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
  98#define PIN_SLPM_NOCHANGE	(NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
  99/* These two replace the above in DB8500v2+ */
 100#define PIN_SLPM_WAKEUP_ENABLE	(NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
 101#define PIN_SLPM_WAKEUP_DISABLE	(NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
 102#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
 103
 104#define PIN_SLPM_GPIO  PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
 105#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
 106
 107#define PIN_DIR_SHIFT		14
 108#define PIN_DIR_MASK		(0x1 << PIN_DIR_SHIFT)
 109#define PIN_DIR(x)		(((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
 110#define PIN_DIR_INPUT		(0 << PIN_DIR_SHIFT)
 111#define PIN_DIR_OUTPUT		(1 << PIN_DIR_SHIFT)
 112
 113#define PIN_VAL_SHIFT		15
 114#define PIN_VAL_MASK		(0x1 << PIN_VAL_SHIFT)
 115#define PIN_VAL(x)		(((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
 116#define PIN_VAL_LOW		(0 << PIN_VAL_SHIFT)
 117#define PIN_VAL_HIGH		(1 << PIN_VAL_SHIFT)
 118
 119#define PIN_SLPM_PULL_SHIFT	16
 120#define PIN_SLPM_PULL_MASK	(0x7 << PIN_SLPM_PULL_SHIFT)
 121#define PIN_SLPM_PULL(x)	\
 122	(((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
 123#define PIN_SLPM_PULL_NONE	\
 124	((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
 125#define PIN_SLPM_PULL_UP	\
 126	((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
 127#define PIN_SLPM_PULL_DOWN	\
 128	((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
 129
 130#define PIN_SLPM_DIR_SHIFT	19
 131#define PIN_SLPM_DIR_MASK	(0x3 << PIN_SLPM_DIR_SHIFT)
 132#define PIN_SLPM_DIR(x)		\
 133	(((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
 134#define PIN_SLPM_DIR_INPUT	((1 + 0) << PIN_SLPM_DIR_SHIFT)
 135#define PIN_SLPM_DIR_OUTPUT	((1 + 1) << PIN_SLPM_DIR_SHIFT)
 136
 137#define PIN_SLPM_VAL_SHIFT	21
 138#define PIN_SLPM_VAL_MASK	(0x3 << PIN_SLPM_VAL_SHIFT)
 139#define PIN_SLPM_VAL(x)		\
 140	(((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
 141#define PIN_SLPM_VAL_LOW	((1 + 0) << PIN_SLPM_VAL_SHIFT)
 142#define PIN_SLPM_VAL_HIGH	((1 + 1) << PIN_SLPM_VAL_SHIFT)
 143
 144#define PIN_SLPM_PDIS_SHIFT		23
 145#define PIN_SLPM_PDIS_MASK		(0x3 << PIN_SLPM_PDIS_SHIFT)
 146#define PIN_SLPM_PDIS(x)	\
 147	(((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
 148#define PIN_SLPM_PDIS_NO_CHANGE		(0 << PIN_SLPM_PDIS_SHIFT)
 149#define PIN_SLPM_PDIS_DISABLED		(1 << PIN_SLPM_PDIS_SHIFT)
 150#define PIN_SLPM_PDIS_ENABLED		(2 << PIN_SLPM_PDIS_SHIFT)
 151
 152#define PIN_LOWEMI_SHIFT	25
 153#define PIN_LOWEMI_MASK		(0x1 << PIN_LOWEMI_SHIFT)
 154#define PIN_LOWEMI(x)		(((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
 155#define PIN_LOWEMI_DISABLED	(0 << PIN_LOWEMI_SHIFT)
 156#define PIN_LOWEMI_ENABLED	(1 << PIN_LOWEMI_SHIFT)
 157
 158#define PIN_GPIOMODE_SHIFT	26
 159#define PIN_GPIOMODE_MASK	(0x1 << PIN_GPIOMODE_SHIFT)
 160#define PIN_GPIOMODE(x)		(((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
 161#define PIN_GPIOMODE_DISABLED	(0 << PIN_GPIOMODE_SHIFT)
 162#define PIN_GPIOMODE_ENABLED	(1 << PIN_GPIOMODE_SHIFT)
 163
 164#define PIN_SLEEPMODE_SHIFT	27
 165#define PIN_SLEEPMODE_MASK	(0x1 << PIN_SLEEPMODE_SHIFT)
 166#define PIN_SLEEPMODE(x)	(((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
 167#define PIN_SLEEPMODE_DISABLED	(0 << PIN_SLEEPMODE_SHIFT)
 168#define PIN_SLEEPMODE_ENABLED	(1 << PIN_SLEEPMODE_SHIFT)
 169
 170/* Shortcuts.  Use these instead of separate DIR, PULL, and VAL.  */
 171#define PIN_INPUT_PULLDOWN	(PIN_DIR_INPUT | PIN_PULL_DOWN)
 172#define PIN_INPUT_PULLUP	(PIN_DIR_INPUT | PIN_PULL_UP)
 173#define PIN_INPUT_NOPULL	(PIN_DIR_INPUT | PIN_PULL_NONE)
 174#define PIN_OUTPUT_LOW		(PIN_DIR_OUTPUT | PIN_VAL_LOW)
 175#define PIN_OUTPUT_HIGH		(PIN_DIR_OUTPUT | PIN_VAL_HIGH)
 176
 177#define PIN_SLPM_INPUT_PULLDOWN	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
 178#define PIN_SLPM_INPUT_PULLUP	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
 179#define PIN_SLPM_INPUT_NOPULL	(PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
 180#define PIN_SLPM_OUTPUT_LOW	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
 181#define PIN_SLPM_OUTPUT_HIGH	(PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
 182
 183#define PIN_CFG_DEFAULT		(0)
 184
 185#define PIN_CFG(num, alt)		\
 186	(PIN_CFG_DEFAULT |\
 187	 (PIN_NUM(num) | PIN_##alt))
 188
 189#define PIN_CFG_INPUT(num, alt, pull)		\
 190	(PIN_CFG_DEFAULT |\
 191	 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
 192
 193#define PIN_CFG_OUTPUT(num, alt, val)		\
 194	(PIN_CFG_DEFAULT |\
 195	 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
 196
 197/**
 198 * struct nmk_pinctrl - state container for the Nomadik pin controller
 199 * @dev: containing device pointer
 200 * @pctl: corresponding pin controller device
 201 * @soc: SoC data for this specific chip
 202 * @prcm_base: PRCM register range virtual base
 203 */
 204struct nmk_pinctrl {
 205	struct device *dev;
 206	struct pinctrl_dev *pctl;
 207	const struct nmk_pinctrl_soc_data *soc;
 208	void __iomem *prcm_base;
 209};
 210
 211/* See nmk_gpio_populate_chip() that fills this array. */
 212struct nmk_gpio_chip *nmk_gpio_chips[NMK_MAX_BANKS];
 213
 214DEFINE_SPINLOCK(nmk_gpio_slpm_lock);
 215
 216static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip,
 217				unsigned int offset, int gpio_mode)
 218{
 219	u32 afunc, bfunc;
 220
 221	afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~BIT(offset);
 222	bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~BIT(offset);
 223	if (gpio_mode & NMK_GPIO_ALT_A)
 224		afunc |= BIT(offset);
 225	if (gpio_mode & NMK_GPIO_ALT_B)
 226		bfunc |= BIT(offset);
 227	writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA);
 228	writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB);
 229}
 230
 231static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip,
 232				unsigned int offset, enum nmk_gpio_pull pull)
 233{
 234	u32 pdis;
 235
 236	pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS);
 237	if (pull == NMK_GPIO_PULL_NONE) {
 238		pdis |= BIT(offset);
 239		nmk_chip->pull_up &= ~BIT(offset);
 240	} else {
 241		pdis &= ~BIT(offset);
 242	}
 243
 244	writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS);
 245
 246	if (pull == NMK_GPIO_PULL_UP) {
 247		nmk_chip->pull_up |= BIT(offset);
 248		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS);
 249	} else if (pull == NMK_GPIO_PULL_DOWN) {
 250		nmk_chip->pull_up &= ~BIT(offset);
 251		writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC);
 252	}
 253}
 254
 255static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip,
 256				  unsigned int offset, bool lowemi)
 257{
 258	bool enabled = nmk_chip->lowemi & BIT(offset);
 259
 260	if (lowemi == enabled)
 261		return;
 262
 263	if (lowemi)
 264		nmk_chip->lowemi |= BIT(offset);
 265	else
 266		nmk_chip->lowemi &= ~BIT(offset);
 267
 268	writel_relaxed(nmk_chip->lowemi,
 269		       nmk_chip->addr + NMK_GPIO_LOWEMI);
 270}
 271
 272static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip,
 273				  unsigned int offset)
 274{
 275	writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC);
 276}
 277
 278static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip,
 279				     unsigned int offset, int gpio_mode,
 280				     bool glitch)
 281{
 282	u32 rwimsc = nmk_chip->rwimsc;
 283	u32 fwimsc = nmk_chip->fwimsc;
 284
 285	if (glitch && nmk_chip->set_ioforce) {
 286		u32 bit = BIT(offset);
 287
 288		/* Prevent spurious wakeups */
 289		writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC);
 290		writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC);
 291
 292		nmk_chip->set_ioforce(true);
 293	}
 294
 295	__nmk_gpio_set_mode(nmk_chip, offset, gpio_mode);
 296
 297	if (glitch && nmk_chip->set_ioforce) {
 298		nmk_chip->set_ioforce(false);
 299
 300		writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC);
 301		writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC);
 302	}
 303}
 304
 305static void
 306nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned int offset)
 307{
 308	u32 falling = nmk_chip->fimsc & BIT(offset);
 309	u32 rising = nmk_chip->rimsc & BIT(offset);
 310	int gpio = nmk_chip->chip.base + offset;
 311	int irq = irq_find_mapping(nmk_chip->chip.irq.domain, offset);
 312	struct irq_data *d = irq_get_irq_data(irq);
 313
 314	if (!rising && !falling)
 315		return;
 316
 317	if (!d || !irqd_irq_disabled(d))
 318		return;
 319
 320	if (rising) {
 321		nmk_chip->rimsc &= ~BIT(offset);
 322		writel_relaxed(nmk_chip->rimsc,
 323			       nmk_chip->addr + NMK_GPIO_RIMSC);
 324	}
 325
 326	if (falling) {
 327		nmk_chip->fimsc &= ~BIT(offset);
 328		writel_relaxed(nmk_chip->fimsc,
 329			       nmk_chip->addr + NMK_GPIO_FIMSC);
 330	}
 331
 332	dev_dbg(nmk_chip->chip.parent, "%d: clearing interrupt mask\n", gpio);
 333}
 334
 335static void nmk_write_masked(void __iomem *reg, u32 mask, u32 value)
 336{
 337	u32 val;
 338
 339	val = readl(reg);
 340	val = ((val & ~mask) | (value & mask));
 341	writel(val, reg);
 342}
 343
 344static void nmk_prcm_altcx_set_mode(struct nmk_pinctrl *npct,
 345				    unsigned int offset, unsigned int alt_num)
 346{
 347	int i;
 348	u16 reg;
 349	u8 bit;
 350	u8 alt_index;
 351	const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 352	const u16 *gpiocr_regs;
 353
 354	if (!npct->prcm_base)
 355		return;
 356
 357	if (alt_num > PRCM_IDX_GPIOCR_ALTC_MAX) {
 358		dev_err(npct->dev, "PRCM GPIOCR: alternate-C%i is invalid\n",
 359			alt_num);
 360		return;
 361	}
 362
 363	for (i = 0 ; i < npct->soc->npins_altcx ; i++) {
 364		if (npct->soc->altcx_pins[i].pin == offset)
 365			break;
 366	}
 367	if (i == npct->soc->npins_altcx) {
 368		dev_dbg(npct->dev, "PRCM GPIOCR: pin %i is not found\n",
 369			offset);
 370		return;
 371	}
 372
 373	pin_desc = npct->soc->altcx_pins + i;
 374	gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 375
 376	/*
 377	 * If alt_num is NULL, just clear current ALTCx selection
 378	 * to make sure we come back to a pure ALTC selection
 379	 */
 380	if (!alt_num) {
 381		for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 382			if (pin_desc->altcx[i].used) {
 383				reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 384				bit = pin_desc->altcx[i].control_bit;
 385				if (readl(npct->prcm_base + reg) & BIT(bit)) {
 386					nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
 387					dev_dbg(npct->dev,
 388						"PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 389						offset, i + 1);
 390				}
 391			}
 392		}
 393		return;
 394	}
 395
 396	alt_index = alt_num - 1;
 397	if (!pin_desc->altcx[alt_index].used) {
 398		dev_warn(npct->dev,
 399			 "PRCM GPIOCR: pin %i: alternate-C%i does not exist\n",
 400			 offset, alt_num);
 401		return;
 402	}
 403
 404	/*
 405	 * Check if any other ALTCx functions are activated on this pin
 406	 * and disable it first.
 407	 */
 408	for (i = 0 ; i < PRCM_IDX_GPIOCR_ALTC_MAX ; i++) {
 409		if (i == alt_index)
 410			continue;
 411		if (pin_desc->altcx[i].used) {
 412			reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 413			bit = pin_desc->altcx[i].control_bit;
 414			if (readl(npct->prcm_base + reg) & BIT(bit)) {
 415				nmk_write_masked(npct->prcm_base + reg, BIT(bit), 0);
 416				dev_dbg(npct->dev,
 417					"PRCM GPIOCR: pin %i: alternate-C%i has been disabled\n",
 418					offset, i + 1);
 419			}
 420		}
 421	}
 422
 423	reg = gpiocr_regs[pin_desc->altcx[alt_index].reg_index];
 424	bit = pin_desc->altcx[alt_index].control_bit;
 425	dev_dbg(npct->dev, "PRCM GPIOCR: pin %i: alternate-C%i has been selected\n",
 426		offset, alt_index + 1);
 427	nmk_write_masked(npct->prcm_base + reg, BIT(bit), BIT(bit));
 428}
 429
 430/*
 431 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 432 *  - Save SLPM registers
 433 *  - Set SLPM=0 for the IOs you want to switch and others to 1
 434 *  - Configure the GPIO registers for the IOs that are being switched
 435 *  - Set IOFORCE=1
 436 *  - Modify the AFLSA/B registers for the IOs that are being switched
 437 *  - Set IOFORCE=0
 438 *  - Restore SLPM registers
 439 *  - Any spurious wake up event during switch sequence to be ignored and
 440 *    cleared
 441 */
 442static int nmk_gpio_glitch_slpm_init(unsigned int *slpm)
 443{
 444	int i, j, ret;
 445
 446	for (i = 0; i < NMK_MAX_BANKS; i++) {
 447		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 448		unsigned int temp = slpm[i];
 449
 450		if (!chip)
 451			break;
 452
 453		ret = clk_enable(chip->clk);
 454		if (ret) {
 455			for (j = 0; j < i; j++) {
 456				chip = nmk_gpio_chips[j];
 457				clk_disable(chip->clk);
 458			}
 459
 460			return ret;
 461		}
 462
 463		slpm[i] = readl(chip->addr + NMK_GPIO_SLPC);
 464		writel(temp, chip->addr + NMK_GPIO_SLPC);
 465	}
 466
 467	return 0;
 468}
 469
 470static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm)
 471{
 472	int i;
 473
 474	for (i = 0; i < NMK_MAX_BANKS; i++) {
 475		struct nmk_gpio_chip *chip = nmk_gpio_chips[i];
 476
 477		if (!chip)
 478			break;
 479
 480		writel(slpm[i], chip->addr + NMK_GPIO_SLPC);
 481
 482		clk_disable(chip->clk);
 483	}
 484}
 485
 486/* Only called by gpio-nomadik but requires knowledge of struct nmk_pinctrl. */
 487int __maybe_unused nmk_prcm_gpiocr_get_mode(struct pinctrl_dev *pctldev, int gpio)
 488{
 489	int i;
 490	u16 reg;
 491	u8 bit;
 492	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 493	const struct prcm_gpiocr_altcx_pin_desc *pin_desc;
 494	const u16 *gpiocr_regs;
 495
 496	if (!npct->prcm_base)
 497		return NMK_GPIO_ALT_C;
 498
 499	for (i = 0; i < npct->soc->npins_altcx; i++) {
 500		if (npct->soc->altcx_pins[i].pin == gpio)
 501			break;
 502	}
 503	if (i == npct->soc->npins_altcx)
 504		return NMK_GPIO_ALT_C;
 505
 506	pin_desc = npct->soc->altcx_pins + i;
 507	gpiocr_regs = npct->soc->prcm_gpiocr_registers;
 508	for (i = 0; i < PRCM_IDX_GPIOCR_ALTC_MAX; i++) {
 509		if (pin_desc->altcx[i].used) {
 510			reg = gpiocr_regs[pin_desc->altcx[i].reg_index];
 511			bit = pin_desc->altcx[i].control_bit;
 512			if (readl(npct->prcm_base + reg) & BIT(bit))
 513				return NMK_GPIO_ALT_C + i + 1;
 514		}
 515	}
 516	return NMK_GPIO_ALT_C;
 517}
 518
 519static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev)
 520{
 521	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 522
 523	return npct->soc->ngroups;
 524}
 525
 526static const char *nmk_get_group_name(struct pinctrl_dev *pctldev,
 527				      unsigned int selector)
 528{
 529	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 530
 531	return npct->soc->groups[selector].grp.name;
 532}
 533
 534static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned int selector,
 535			      const unsigned int **pins,
 536			      unsigned int *num_pins)
 537{
 538	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 539
 540	*pins = npct->soc->groups[selector].grp.pins;
 541	*num_pins = npct->soc->groups[selector].grp.npins;
 542	return 0;
 543}
 544
 545/* This makes the mapping from pin number to a GPIO chip. We also return the pin
 546 * offset in the GPIO chip for convenience (and to avoid a second loop).
 547 */
 548static struct nmk_gpio_chip *find_nmk_gpio_from_pin(unsigned int pin,
 549						    unsigned int *offset)
 550{
 551	int i, j = 0;
 552	struct nmk_gpio_chip *nmk_gpio;
 553
 554	/* We assume that pins are allocated in bank order. */
 555	for (i = 0; i < NMK_MAX_BANKS; i++) {
 556		nmk_gpio = nmk_gpio_chips[i];
 557		if (!nmk_gpio)
 558			continue;
 559		if (pin >= j && pin < j + nmk_gpio->chip.ngpio) {
 560			if (offset)
 561				*offset = pin - j;
 562			return nmk_gpio;
 563		}
 564		j += nmk_gpio->chip.ngpio;
 565	}
 566	return NULL;
 567}
 568
 569static struct gpio_chip *find_gc_from_pin(unsigned int pin)
 570{
 571	struct nmk_gpio_chip *nmk_gpio = find_nmk_gpio_from_pin(pin, NULL);
 572
 573	if (nmk_gpio)
 574		return &nmk_gpio->chip;
 575	return NULL;
 576}
 577
 578static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
 579			     unsigned int offset)
 580{
 581	struct gpio_chip *chip = find_gc_from_pin(offset);
 582
 583	if (!chip) {
 584		seq_printf(s, "invalid pin offset");
 585		return;
 586	}
 587	nmk_gpio_dbg_show_one(s, pctldev, chip, offset - chip->base);
 588}
 589
 590static int nmk_dt_add_map_mux(struct pinctrl_map **map, unsigned int *reserved_maps,
 591			      unsigned int *num_maps, const char *group,
 592			      const char *function)
 593{
 594	if (*num_maps == *reserved_maps)
 595		return -ENOSPC;
 596
 597	(*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
 598	(*map)[*num_maps].data.mux.group = group;
 599	(*map)[*num_maps].data.mux.function = function;
 600	(*num_maps)++;
 601
 602	return 0;
 603}
 604
 605static int nmk_dt_add_map_configs(struct pinctrl_map **map,
 606				  unsigned int *reserved_maps,
 607				  unsigned int *num_maps, const char *group,
 608				  unsigned long *configs, unsigned int num_configs)
 609{
 610	unsigned long *dup_configs;
 611
 612	if (*num_maps == *reserved_maps)
 613		return -ENOSPC;
 614
 615	dup_configs = kmemdup_array(configs, num_configs, sizeof(*dup_configs), GFP_KERNEL);
 616	if (!dup_configs)
 617		return -ENOMEM;
 618
 619	(*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_PIN;
 620
 621	(*map)[*num_maps].data.configs.group_or_pin = group;
 622	(*map)[*num_maps].data.configs.configs = dup_configs;
 623	(*map)[*num_maps].data.configs.num_configs = num_configs;
 624	(*num_maps)++;
 625
 626	return 0;
 627}
 628
 629#define NMK_CONFIG_PIN(x, y) { .property = x, .config = y, }
 630#define NMK_CONFIG_PIN_ARRAY(x, y) { .property = x, .choice = y, \
 631	.size = ARRAY_SIZE(y), }
 632
 633static const unsigned long nmk_pin_input_modes[] = {
 634	PIN_INPUT_NOPULL,
 635	PIN_INPUT_PULLUP,
 636	PIN_INPUT_PULLDOWN,
 637};
 638
 639static const unsigned long nmk_pin_output_modes[] = {
 640	PIN_OUTPUT_LOW,
 641	PIN_OUTPUT_HIGH,
 642	PIN_DIR_OUTPUT,
 643};
 644
 645static const unsigned long nmk_pin_sleep_modes[] = {
 646	PIN_SLEEPMODE_DISABLED,
 647	PIN_SLEEPMODE_ENABLED,
 648};
 649
 650static const unsigned long nmk_pin_sleep_input_modes[] = {
 651	PIN_SLPM_INPUT_NOPULL,
 652	PIN_SLPM_INPUT_PULLUP,
 653	PIN_SLPM_INPUT_PULLDOWN,
 654	PIN_SLPM_DIR_INPUT,
 655};
 656
 657static const unsigned long nmk_pin_sleep_output_modes[] = {
 658	PIN_SLPM_OUTPUT_LOW,
 659	PIN_SLPM_OUTPUT_HIGH,
 660	PIN_SLPM_DIR_OUTPUT,
 661};
 662
 663static const unsigned long nmk_pin_sleep_wakeup_modes[] = {
 664	PIN_SLPM_WAKEUP_DISABLE,
 665	PIN_SLPM_WAKEUP_ENABLE,
 666};
 667
 668static const unsigned long nmk_pin_gpio_modes[] = {
 669	PIN_GPIOMODE_DISABLED,
 670	PIN_GPIOMODE_ENABLED,
 671};
 672
 673static const unsigned long nmk_pin_sleep_pdis_modes[] = {
 674	PIN_SLPM_PDIS_DISABLED,
 675	PIN_SLPM_PDIS_ENABLED,
 676};
 677
 678struct nmk_cfg_param {
 679	const char *property;
 680	unsigned long config;
 681	const unsigned long *choice;
 682	int size;
 683};
 684
 685static const struct nmk_cfg_param nmk_cfg_params[] = {
 686	NMK_CONFIG_PIN_ARRAY("ste,input",		nmk_pin_input_modes),
 687	NMK_CONFIG_PIN_ARRAY("ste,output",		nmk_pin_output_modes),
 688	NMK_CONFIG_PIN_ARRAY("ste,sleep",		nmk_pin_sleep_modes),
 689	NMK_CONFIG_PIN_ARRAY("ste,sleep-input",		nmk_pin_sleep_input_modes),
 690	NMK_CONFIG_PIN_ARRAY("ste,sleep-output",	nmk_pin_sleep_output_modes),
 691	NMK_CONFIG_PIN_ARRAY("ste,sleep-wakeup",	nmk_pin_sleep_wakeup_modes),
 692	NMK_CONFIG_PIN_ARRAY("ste,gpio",		nmk_pin_gpio_modes),
 693	NMK_CONFIG_PIN_ARRAY("ste,sleep-pull-disable",	nmk_pin_sleep_pdis_modes),
 694};
 695
 696static int nmk_dt_pin_config(int index, int val, unsigned long *config)
 697{
 698	if (!nmk_cfg_params[index].choice) {
 699		*config = nmk_cfg_params[index].config;
 700	} else {
 701		/* test if out of range */
 702		if  (val < nmk_cfg_params[index].size) {
 703			*config = nmk_cfg_params[index].config |
 704				nmk_cfg_params[index].choice[val];
 705		}
 706	}
 707	return 0;
 708}
 709
 710static const char *nmk_find_pin_name(struct pinctrl_dev *pctldev, const char *pin_name)
 711{
 712	int i, pin_number;
 713	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 714
 715	if (sscanf((char *)pin_name, "GPIO%d", &pin_number) == 1)
 716		for (i = 0; i < npct->soc->npins; i++)
 717			if (npct->soc->pins[i].number == pin_number)
 718				return npct->soc->pins[i].name;
 719	return NULL;
 720}
 721
 722static bool nmk_pinctrl_dt_get_config(struct device_node *np,
 723				      unsigned long *configs)
 724{
 725	bool has_config = 0;
 726	unsigned long cfg = 0;
 727	int i, val, ret;
 728
 729	for (i = 0; i < ARRAY_SIZE(nmk_cfg_params); i++) {
 730		ret = of_property_read_u32(np, nmk_cfg_params[i].property, &val);
 731		if (ret != -EINVAL) {
 732			if (nmk_dt_pin_config(i, val, &cfg) == 0) {
 733				*configs |= cfg;
 734				has_config = 1;
 735			}
 736		}
 737	}
 738
 739	return has_config;
 740}
 741
 742static int nmk_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
 743					 struct device_node *np,
 744					 struct pinctrl_map **map,
 745					 unsigned int *reserved_maps,
 746					 unsigned int *num_maps)
 747{
 748	int ret;
 749	const char *function = NULL;
 750	unsigned long configs = 0;
 751	bool has_config = 0;
 752	struct property *prop;
 753	struct device_node *np_config;
 754
 755	ret = of_property_read_string(np, "function", &function);
 756	if (ret >= 0) {
 757		const char *group;
 758
 759		ret = of_property_count_strings(np, "groups");
 760		if (ret < 0)
 761			goto exit;
 762
 763		ret = pinctrl_utils_reserve_map(pctldev, map,
 764						reserved_maps,
 765						num_maps, ret);
 766		if (ret < 0)
 767			goto exit;
 768
 769		of_property_for_each_string(np, "groups", prop, group) {
 770			ret = nmk_dt_add_map_mux(map, reserved_maps, num_maps,
 771						 group, function);
 772			if (ret < 0)
 773				goto exit;
 774		}
 775	}
 776
 777	has_config = nmk_pinctrl_dt_get_config(np, &configs);
 778	np_config = of_parse_phandle(np, "ste,config", 0);
 779	if (np_config) {
 780		has_config |= nmk_pinctrl_dt_get_config(np_config, &configs);
 781		of_node_put(np_config);
 782	}
 783	if (has_config) {
 784		const char *gpio_name;
 785		const char *pin;
 786
 787		ret = of_property_count_strings(np, "pins");
 788		if (ret < 0)
 789			goto exit;
 790		ret = pinctrl_utils_reserve_map(pctldev, map,
 791						reserved_maps,
 792						num_maps, ret);
 793		if (ret < 0)
 794			goto exit;
 795
 796		of_property_for_each_string(np, "pins", prop, pin) {
 797			gpio_name = nmk_find_pin_name(pctldev, pin);
 798
 799			ret = nmk_dt_add_map_configs(map, reserved_maps,
 800						     num_maps,
 801						     gpio_name, &configs, 1);
 802			if (ret < 0)
 803				goto exit;
 804		}
 805	}
 806
 807exit:
 808	return ret;
 809}
 810
 811static int nmk_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
 812				      struct device_node *np_config,
 813				      struct pinctrl_map **map,
 814				      unsigned int *num_maps)
 815{
 816	unsigned int reserved_maps;
 817	int ret;
 818
 819	reserved_maps = 0;
 820	*map = NULL;
 821	*num_maps = 0;
 822
 823	for_each_child_of_node_scoped(np_config, np) {
 824		ret = nmk_pinctrl_dt_subnode_to_map(pctldev, np, map,
 825						    &reserved_maps, num_maps);
 826		if (ret < 0) {
 827			pinctrl_utils_free_map(pctldev, *map, *num_maps);
 828			return ret;
 829		}
 830	}
 831
 832	return 0;
 833}
 834
 835static const struct pinctrl_ops nmk_pinctrl_ops = {
 836	.get_groups_count = nmk_get_groups_cnt,
 837	.get_group_name = nmk_get_group_name,
 838	.get_group_pins = nmk_get_group_pins,
 839	.pin_dbg_show = nmk_pin_dbg_show,
 840	.dt_node_to_map = nmk_pinctrl_dt_node_to_map,
 841	.dt_free_map = pinctrl_utils_free_map,
 842};
 843
 844static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
 845{
 846	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 847
 848	return npct->soc->nfunctions;
 849}
 850
 851static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev,
 852					 unsigned int function)
 853{
 854	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 855
 856	return npct->soc->functions[function].name;
 857}
 858
 859static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
 860				   unsigned int function,
 861				   const char * const **groups,
 862				   unsigned * const num_groups)
 863{
 864	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 865
 866	*groups = npct->soc->functions[function].groups;
 867	*num_groups = npct->soc->functions[function].ngroups;
 868
 869	return 0;
 870}
 871
 872static int nmk_pmx_set(struct pinctrl_dev *pctldev, unsigned int function,
 873		       unsigned int group)
 874{
 875	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
 876	const struct nmk_pingroup *g;
 877	static unsigned int slpm[NMK_MAX_BANKS];
 878	unsigned long flags = 0;
 879	bool glitch;
 880	int ret = -EINVAL;
 881	int i;
 882
 883	g = &npct->soc->groups[group];
 884
 885	if (g->altsetting < 0)
 886		return -EINVAL;
 887
 888	dev_dbg(npct->dev, "enable group %s, %zu pins\n", g->grp.name, g->grp.npins);
 889
 890	/*
 891	 * If we're setting altfunc C by setting both AFSLA and AFSLB to 1,
 892	 * we may pass through an undesired state. In this case we take
 893	 * some extra care.
 894	 *
 895	 * Safe sequence used to switch IOs between GPIO and Alternate-C mode:
 896	 *  - Save SLPM registers (since we have a shadow register in the
 897	 *    nmk_chip we're using that as backup)
 898	 *  - Set SLPM=0 for the IOs you want to switch and others to 1
 899	 *  - Configure the GPIO registers for the IOs that are being switched
 900	 *  - Set IOFORCE=1
 901	 *  - Modify the AFLSA/B registers for the IOs that are being switched
 902	 *  - Set IOFORCE=0
 903	 *  - Restore SLPM registers
 904	 *  - Any spurious wake up event during switch sequence to be ignored
 905	 *    and cleared
 906	 *
 907	 * We REALLY need to save ALL slpm registers, because the external
 908	 * IOFORCE will switch *all* ports to their sleepmode setting to as
 909	 * to avoid glitches. (Not just one port!)
 910	 */
 911	glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C);
 912
 913	if (glitch) {
 914		spin_lock_irqsave(&nmk_gpio_slpm_lock, flags);
 915
 916		/* Initially don't put any pins to sleep when switching */
 917		memset(slpm, 0xff, sizeof(slpm));
 918
 919		/*
 920		 * Then mask the pins that need to be sleeping now when we're
 921		 * switching to the ALT C function.
 922		 */
 923		for (i = 0; i < g->grp.npins; i++) {
 924			struct nmk_gpio_chip *nmk_chip;
 925			unsigned int bit;
 926
 927			nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i], &bit);
 928			if (!nmk_chip) {
 929				dev_err(npct->dev,
 930					"invalid pin offset %d in group %s at index %d\n",
 931					g->grp.pins[i], g->grp.name, i);
 932				goto out_pre_slpm_init;
 933			}
 934
 935			slpm[nmk_chip->bank] &= ~BIT(bit);
 936		}
 937		ret = nmk_gpio_glitch_slpm_init(slpm);
 938		if (ret)
 939			goto out_pre_slpm_init;
 940	}
 941
 942	for (i = 0; i < g->grp.npins; i++) {
 943		struct nmk_gpio_chip *nmk_chip;
 944		unsigned int bit;
 945
 946		nmk_chip = find_nmk_gpio_from_pin(g->grp.pins[i], &bit);
 947		if (!nmk_chip) {
 948			dev_err(npct->dev,
 949				"invalid pin offset %d in group %s at index %d\n",
 950				g->grp.pins[i], g->grp.name, i);
 951			goto out_glitch;
 952		}
 953		dev_dbg(npct->dev, "setting pin %d to altsetting %d\n",
 954			g->grp.pins[i], g->altsetting);
 955
 956		ret = clk_enable(nmk_chip->clk);
 957		if (ret)
 958			goto out_glitch;
 959
 960		/*
 961		 * If the pin is switching to altfunc, and there was an
 962		 * interrupt installed on it which has been lazy disabled,
 963		 * actually mask the interrupt to prevent spurious interrupts
 964		 * that would occur while the pin is under control of the
 965		 * peripheral. Only SKE does this.
 966		 */
 967		nmk_gpio_disable_lazy_irq(nmk_chip, bit);
 968
 969		__nmk_gpio_set_mode_safe(nmk_chip, bit,
 970					 (g->altsetting & NMK_GPIO_ALT_C), glitch);
 971		clk_disable(nmk_chip->clk);
 972
 973		/*
 974		 * Call PRCM GPIOCR config function in case ALTC
 975		 * has been selected:
 976		 * - If selection is a ALTCx, some bits in PRCM GPIOCR registers
 977		 *   must be set.
 978		 * - If selection is pure ALTC and previous selection was ALTCx,
 979		 *   then some bits in PRCM GPIOCR registers must be cleared.
 980		 */
 981		if ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C)
 982			nmk_prcm_altcx_set_mode(npct, g->grp.pins[i],
 983						g->altsetting >> NMK_GPIO_ALT_CX_SHIFT);
 984	}
 985
 986	/* When all pins are successfully reconfigured we get here */
 987	ret = 0;
 988
 989out_glitch:
 990	if (glitch)
 991		nmk_gpio_glitch_slpm_restore(slpm);
 992out_pre_slpm_init:
 993	if (glitch)
 994		spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags);
 995
 996	return ret;
 997}
 998
 999static int nmk_gpio_request_enable(struct pinctrl_dev *pctldev,
1000				   struct pinctrl_gpio_range *range,
1001				   unsigned int pin)
1002{
1003	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1004	struct nmk_gpio_chip *nmk_chip;
1005	struct gpio_chip *chip;
1006	unsigned int bit;
1007	int ret;
1008
1009	if (!range) {
1010		dev_err(npct->dev, "invalid range\n");
1011		return -EINVAL;
1012	}
1013	if (!range->gc) {
1014		dev_err(npct->dev, "missing GPIO chip in range\n");
1015		return -EINVAL;
1016	}
1017	chip = range->gc;
1018	nmk_chip = gpiochip_get_data(chip);
1019
1020	dev_dbg(npct->dev, "enable pin %u as GPIO\n", pin);
1021
1022	find_nmk_gpio_from_pin(pin, &bit);
1023
1024	ret = clk_enable(nmk_chip->clk);
1025	if (ret)
1026		return ret;
1027	/* There is no glitch when converting any pin to GPIO */
1028	__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1029	clk_disable(nmk_chip->clk);
1030
1031	return 0;
1032}
1033
1034static void nmk_gpio_disable_free(struct pinctrl_dev *pctldev,
1035				  struct pinctrl_gpio_range *range,
1036				  unsigned int pin)
1037{
1038	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1039
1040	dev_dbg(npct->dev, "disable pin %u as GPIO\n", pin);
1041	/* Set the pin to some default state, GPIO is usually default */
1042}
1043
1044static const struct pinmux_ops nmk_pinmux_ops = {
1045	.get_functions_count = nmk_pmx_get_funcs_cnt,
1046	.get_function_name = nmk_pmx_get_func_name,
1047	.get_function_groups = nmk_pmx_get_func_groups,
1048	.set_mux = nmk_pmx_set,
1049	.gpio_request_enable = nmk_gpio_request_enable,
1050	.gpio_disable_free = nmk_gpio_disable_free,
1051	.strict = true,
1052};
1053
1054static int nmk_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
1055			      unsigned long *config)
1056{
1057	/* Not implemented */
1058	return -EINVAL;
1059}
1060
1061static int nmk_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
1062			      unsigned long *configs, unsigned int num_configs)
1063{
1064	static const char * const pullnames[] = {
1065		[NMK_GPIO_PULL_NONE]	= "none",
1066		[NMK_GPIO_PULL_UP]	= "up",
1067		[NMK_GPIO_PULL_DOWN]	= "down",
1068		[3] /* illegal */	= "??"
1069	};
1070	static const char * const slpmnames[] = {
1071		[NMK_GPIO_SLPM_INPUT]		= "input/wakeup",
1072		[NMK_GPIO_SLPM_NOCHANGE]	= "no-change/no-wakeup",
1073	};
1074	struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev);
1075	struct nmk_gpio_chip *nmk_chip;
1076	unsigned int bit;
1077	unsigned long cfg;
1078	int pull, slpm, output, val, i;
1079	bool lowemi, gpiomode, sleep;
1080	int ret;
1081
1082	nmk_chip = find_nmk_gpio_from_pin(pin, &bit);
1083	if (!nmk_chip) {
1084		dev_err(npct->dev,
1085			"invalid pin offset %d\n", pin);
1086		return -EINVAL;
1087	}
1088
1089	for (i = 0; i < num_configs; i++) {
1090		/*
1091		 * The pin config contains pin number and altfunction fields,
1092		 * here we just ignore that part. It's being handled by the
1093		 * framework and pinmux callback respectively.
1094		 */
1095		cfg = configs[i];
1096		pull = PIN_PULL(cfg);
1097		slpm = PIN_SLPM(cfg);
1098		output = PIN_DIR(cfg);
1099		val = PIN_VAL(cfg);
1100		lowemi = PIN_LOWEMI(cfg);
1101		gpiomode = PIN_GPIOMODE(cfg);
1102		sleep = PIN_SLEEPMODE(cfg);
1103
1104		if (sleep) {
1105			int slpm_pull = PIN_SLPM_PULL(cfg);
1106			int slpm_output = PIN_SLPM_DIR(cfg);
1107			int slpm_val = PIN_SLPM_VAL(cfg);
1108
1109			/* All pins go into GPIO mode at sleep */
1110			gpiomode = true;
1111
1112			/*
1113			 * The SLPM_* values are normal values + 1 to allow zero
1114			 * to mean "same as normal".
1115			 */
1116			if (slpm_pull)
1117				pull = slpm_pull - 1;
1118			if (slpm_output)
1119				output = slpm_output - 1;
1120			if (slpm_val)
1121				val = slpm_val - 1;
1122
1123			dev_dbg(nmk_chip->chip.parent,
1124				"pin %d: sleep pull %s, dir %s, val %s\n",
1125				pin,
1126				slpm_pull ? pullnames[pull] : "same",
1127				slpm_output ? (output ? "output" : "input")
1128				: "same",
1129				slpm_val ? str_high_low(val) : "same");
1130		}
1131
1132		dev_dbg(nmk_chip->chip.parent,
1133			"pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n",
1134			pin, cfg, pullnames[pull], slpmnames[slpm],
1135			output ? "output " : "input",
1136			output ? str_high_low(val) : "",
1137			str_on_off(lowemi));
1138
1139		ret = clk_enable(nmk_chip->clk);
1140		if (ret)
1141			return ret;
1142		if (gpiomode)
1143			/* No glitch when going to GPIO mode */
1144			__nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO);
1145		if (output) {
1146			__nmk_gpio_make_output(nmk_chip, bit, val);
1147		} else {
1148			__nmk_gpio_make_input(nmk_chip, bit);
1149			__nmk_gpio_set_pull(nmk_chip, bit, pull);
1150		}
1151		/* TODO: isn't this only applicable on output pins? */
1152		__nmk_gpio_set_lowemi(nmk_chip, bit, lowemi);
1153
1154		__nmk_gpio_set_slpm(nmk_chip, bit, slpm);
1155		clk_disable(nmk_chip->clk);
1156	} /* for each config */
1157
1158	return 0;
1159}
1160
1161static const struct pinconf_ops nmk_pinconf_ops = {
1162	.pin_config_get = nmk_pin_config_get,
1163	.pin_config_set = nmk_pin_config_set,
1164};
1165
1166static struct pinctrl_desc nmk_pinctrl_desc = {
1167	.name = "pinctrl-nomadik",
1168	.pctlops = &nmk_pinctrl_ops,
1169	.pmxops = &nmk_pinmux_ops,
1170	.confops = &nmk_pinconf_ops,
1171	.owner = THIS_MODULE,
1172};
1173
1174static const struct of_device_id nmk_pinctrl_match[] = {
1175	{
1176		.compatible = "stericsson,stn8815-pinctrl",
1177		.data = (void *)PINCTRL_NMK_STN8815,
1178	},
1179	{
1180		.compatible = "stericsson,db8500-pinctrl",
1181		.data = (void *)PINCTRL_NMK_DB8500,
1182	},
1183	{},
1184};
1185
1186#ifdef CONFIG_PM_SLEEP
1187static int nmk_pinctrl_suspend(struct device *dev)
1188{
1189	struct nmk_pinctrl *npct;
1190
1191	npct = dev_get_drvdata(dev);
1192	if (!npct)
1193		return -EINVAL;
1194
1195	return pinctrl_force_sleep(npct->pctl);
1196}
1197
1198static int nmk_pinctrl_resume(struct device *dev)
1199{
1200	struct nmk_pinctrl *npct;
1201
1202	npct = dev_get_drvdata(dev);
1203	if (!npct)
1204		return -EINVAL;
1205
1206	return pinctrl_force_default(npct->pctl);
1207}
1208#endif
1209
1210static int nmk_pinctrl_probe(struct platform_device *pdev)
1211{
1212	struct fwnode_handle *fwnode = dev_fwnode(&pdev->dev);
1213	struct fwnode_handle *prcm_fwnode;
1214	struct nmk_pinctrl *npct;
1215	uintptr_t version = 0;
1216	int i;
1217
1218	npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL);
1219	if (!npct)
1220		return -ENOMEM;
1221
1222	version = (uintptr_t)device_get_match_data(&pdev->dev);
1223
1224	/* Poke in other ASIC variants here */
1225	if (version == PINCTRL_NMK_STN8815)
1226		nmk_pinctrl_stn8815_init(&npct->soc);
1227	if (version == PINCTRL_NMK_DB8500)
1228		nmk_pinctrl_db8500_init(&npct->soc);
1229
1230	/*
1231	 * Since we depend on the GPIO chips to provide clock and register base
1232	 * for the pin control operations, make sure that we have these
1233	 * populated before we continue. Follow the phandles to instantiate
1234	 * them. The GPIO portion of the actual hardware may be probed before
1235	 * or after this point: it shouldn't matter as the APIs are orthogonal.
1236	 */
1237	for (i = 0; i < NMK_MAX_BANKS; i++) {
1238		struct fwnode_handle *gpio_fwnode;
1239		struct nmk_gpio_chip *nmk_chip;
1240
1241		gpio_fwnode = fwnode_find_reference(fwnode, "nomadik-gpio-chips", i);
1242		if (IS_ERR(gpio_fwnode))
1243			continue;
1244
1245		dev_info(&pdev->dev, "populate NMK GPIO %d \"%pfwP\"\n", i, gpio_fwnode);
1246		nmk_chip = nmk_gpio_populate_chip(gpio_fwnode, pdev);
1247		if (IS_ERR(nmk_chip))
1248			dev_err(&pdev->dev,
1249				"could not populate nmk chip struct - continue anyway\n");
1250		else
1251			/* We are NOT compatible with mobileye,eyeq5-gpio. */
1252			BUG_ON(nmk_chip->is_mobileye_soc);
1253		fwnode_handle_put(gpio_fwnode);
1254	}
1255
1256	prcm_fwnode = fwnode_find_reference(fwnode, "prcm", 0);
1257	if (!IS_ERR(prcm_fwnode)) {
1258		npct->prcm_base = fwnode_iomap(prcm_fwnode, 0);
1259		fwnode_handle_put(prcm_fwnode);
1260	}
1261	if (!npct->prcm_base) {
1262		if (version == PINCTRL_NMK_STN8815) {
1263			dev_info(&pdev->dev,
1264				 "No PRCM base, assuming no ALT-Cx control is available\n");
1265		} else {
1266			dev_err(&pdev->dev, "missing PRCM base address\n");
1267			return -EINVAL;
1268		}
1269	}
1270
1271	nmk_pinctrl_desc.pins = npct->soc->pins;
1272	nmk_pinctrl_desc.npins = npct->soc->npins;
1273	npct->dev = &pdev->dev;
1274
1275	npct->pctl = devm_pinctrl_register(&pdev->dev, &nmk_pinctrl_desc, npct);
1276	if (IS_ERR(npct->pctl)) {
1277		dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n");
1278		return PTR_ERR(npct->pctl);
1279	}
1280
1281	platform_set_drvdata(pdev, npct);
1282	dev_info(&pdev->dev, "initialized Nomadik pin control driver\n");
1283
1284	return 0;
1285}
1286
1287static SIMPLE_DEV_PM_OPS(nmk_pinctrl_pm_ops,
1288			nmk_pinctrl_suspend,
1289			nmk_pinctrl_resume);
1290
1291static struct platform_driver nmk_pinctrl_driver = {
1292	.driver = {
1293		.name = "pinctrl-nomadik",
1294		.of_match_table = nmk_pinctrl_match,
1295		.pm = &nmk_pinctrl_pm_ops,
1296	},
1297	.probe = nmk_pinctrl_probe,
1298};
1299
1300static int __init nmk_pinctrl_init(void)
1301{
1302	return platform_driver_register(&nmk_pinctrl_driver);
1303}
1304core_initcall(nmk_pinctrl_init);