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pinctrl-armada-37xx.c
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linux-6.19.14/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
1/* 2 * Marvell 37xx SoC pinctrl driver 3 * 4 * Copyright (C) 2017 Marvell 5 * 6 * Gregory CLEMENT <gregory.clement@free-electrons.com> 7 * 8 * This file is licensed under the terms of the GNU General Public 9 * License version 2 or later. This program is licensed "as is" 10 * without any warranty of any kind, whether express or implied. 11 */ 12 13#include <linux/gpio/driver.h> 14#include <linux/mfd/syscon.h> 15#include <linux/of.h> 16#include <linux/of_irq.h> 17#include <linux/pinctrl/pinconf-generic.h> 18#include <linux/pinctrl/pinconf.h> 19#include <linux/pinctrl/pinctrl.h> 20#include <linux/pinctrl/pinmux.h> 21#include <linux/platform_device.h> 22#include <linux/property.h> 23#include <linux/regmap.h> 24#include <linux/seq_file.h> 25#include <linux/slab.h> 26#include <linux/string_helpers.h> 27 28#include "../pinctrl-utils.h" 29 30#define OUTPUT_EN 0x0 31#define INPUT_VAL 0x10 32#define OUTPUT_VAL 0x18 33#define OUTPUT_CTL 0x20 34#define SELECTION 0x30 35 36#define IRQ_EN 0x0 37#define IRQ_POL 0x08 38#define IRQ_STATUS 0x10 39#define IRQ_WKUP 0x18 40 41#define NB_FUNCS 3 42#define GPIO_PER_REG 32 43 44/** 45 * struct armada_37xx_pin_group: represents group of pins of a pinmux function. 46 * The pins of a pinmux groups are composed of one or two groups of contiguous 47 * pins. 48 * @name: Name of the pin group, used to lookup the group. 49 * @start_pin: Index of the first pin of the main range of pins belonging to 50 * the group 51 * @npins: Number of pins included in the first range 52 * @reg_mask: Bit mask matching the group in the selection register 53 * @val: Value to write to the registers for a given function 54 * @extra_pin: Index of the first pin of the optional second range of pins 55 * belonging to the group 56 * @extra_npins:Number of pins included in the second optional range 57 * @funcs: A list of pinmux functions that can be selected for this group. 58 * @pins: List of the pins included in the group 59 */ 60struct armada_37xx_pin_group { 61 const char *name; 62 unsigned int start_pin; 63 unsigned int npins; 64 u32 reg_mask; 65 u32 val[NB_FUNCS]; 66 unsigned int extra_pin; 67 unsigned int extra_npins; 68 const char *funcs[NB_FUNCS]; 69 unsigned int *pins; 70}; 71 72struct armada_37xx_pin_data { 73 u8 nr_pins; 74 char *name; 75 struct armada_37xx_pin_group *groups; 76 int ngroups; 77}; 78 79struct armada_37xx_pmx_func { 80 const char *name; 81 const char **groups; 82 unsigned int ngroups; 83}; 84 85struct armada_37xx_pm_state { 86 u32 out_en_l; 87 u32 out_en_h; 88 u32 out_val_l; 89 u32 out_val_h; 90 u32 irq_en_l; 91 u32 irq_en_h; 92 u32 irq_pol_l; 93 u32 irq_pol_h; 94 u32 selection; 95}; 96 97struct armada_37xx_pinctrl { 98 struct regmap *regmap; 99 void __iomem *base; 100 const struct armada_37xx_pin_data *data; 101 struct device *dev; 102 struct gpio_chip gpio_chip; 103 raw_spinlock_t irq_lock; 104 struct pinctrl_desc pctl; 105 struct pinctrl_dev *pctl_dev; 106 struct armada_37xx_pin_group *groups; 107 unsigned int ngroups; 108 struct armada_37xx_pmx_func *funcs; 109 unsigned int nfuncs; 110 struct armada_37xx_pm_state pm; 111}; 112 113#define PIN_GRP_GPIO_0(_name, _start, _nr) \ 114 { \ 115 .name = _name, \ 116 .start_pin = _start, \ 117 .npins = _nr, \ 118 .reg_mask = 0, \ 119 .val = {0}, \ 120 .funcs = {"gpio"} \ 121 } 122 123#define PIN_GRP_GPIO(_name, _start, _nr, _mask, _func1) \ 124 { \ 125 .name = _name, \ 126 .start_pin = _start, \ 127 .npins = _nr, \ 128 .reg_mask = _mask, \ 129 .val = {0, _mask}, \ 130 .funcs = {_func1, "gpio"} \ 131 } 132 133#define PIN_GRP_GPIO_2(_name, _start, _nr, _mask, _val1, _val2, _func1) \ 134 { \ 135 .name = _name, \ 136 .start_pin = _start, \ 137 .npins = _nr, \ 138 .reg_mask = _mask, \ 139 .val = {_val1, _val2}, \ 140 .funcs = {_func1, "gpio"} \ 141 } 142 143#define PIN_GRP_GPIO_3(_name, _start, _nr, _mask, _v1, _v2, _v3, _f1, _f2) \ 144 { \ 145 .name = _name, \ 146 .start_pin = _start, \ 147 .npins = _nr, \ 148 .reg_mask = _mask, \ 149 .val = {_v1, _v2, _v3}, \ 150 .funcs = {_f1, _f2, "gpio"} \ 151 } 152 153#define PIN_GRP_EXTRA(_name, _start, _nr, _mask, _v1, _v2, _start2, _nr2, \ 154 _f1, _f2) \ 155 { \ 156 .name = _name, \ 157 .start_pin = _start, \ 158 .npins = _nr, \ 159 .reg_mask = _mask, \ 160 .val = {_v1, _v2}, \ 161 .extra_pin = _start2, \ 162 .extra_npins = _nr2, \ 163 .funcs = {_f1, _f2} \ 164 } 165 166static struct armada_37xx_pin_group armada_37xx_nb_groups[] = { 167 PIN_GRP_GPIO("jtag", 20, 5, BIT(0), "jtag"), 168 PIN_GRP_GPIO("sdio0", 8, 3, BIT(1), "sdio"), 169 PIN_GRP_GPIO("emmc_nb", 27, 9, BIT(2), "emmc"), 170 PIN_GRP_GPIO_3("pwm0", 11, 1, BIT(3) | BIT(20), 0, BIT(20), BIT(3), 171 "pwm", "led"), 172 PIN_GRP_GPIO_3("pwm1", 12, 1, BIT(4) | BIT(21), 0, BIT(21), BIT(4), 173 "pwm", "led"), 174 PIN_GRP_GPIO_3("pwm2", 13, 1, BIT(5) | BIT(22), 0, BIT(22), BIT(5), 175 "pwm", "led"), 176 PIN_GRP_GPIO_3("pwm3", 14, 1, BIT(6) | BIT(23), 0, BIT(23), BIT(6), 177 "pwm", "led"), 178 PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"), 179 PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"), 180 PIN_GRP_GPIO_0("gpio1_5", 5, 1), 181 PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"), 182 PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"), 183 PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"), 184 PIN_GRP_GPIO_2("spi_cs2", 18, 1, BIT(13) | BIT(19), 0, BIT(13), "spi"), 185 PIN_GRP_GPIO_2("spi_cs3", 19, 1, BIT(14) | BIT(19), 0, BIT(14), "spi"), 186 PIN_GRP_GPIO("onewire", 4, 1, BIT(16), "onewire"), 187 PIN_GRP_GPIO("uart1", 25, 2, BIT(17), "uart"), 188 PIN_GRP_GPIO("spi_quad", 15, 2, BIT(18), "spi"), 189 PIN_GRP_EXTRA("uart2", 9, 2, BIT(1) | BIT(13) | BIT(14) | BIT(19), 190 BIT(1) | BIT(13) | BIT(14), BIT(1) | BIT(19), 191 18, 2, "gpio", "uart"), 192}; 193 194static struct armada_37xx_pin_group armada_37xx_sb_groups[] = { 195 PIN_GRP_GPIO("usb32_drvvbus0", 0, 1, BIT(0), "drvbus"), 196 PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"), 197 PIN_GRP_GPIO_0("gpio2_2", 2, 1), 198 PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"), 199 PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"), 200 PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"), 201 PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"), /* this actually controls "pcie1_reset" */ 202 PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"), 203 PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"), 204 PIN_GRP_GPIO("ptp", 20, 1, BIT(11), "ptp"), 205 PIN_GRP_GPIO_3("ptp_clk", 21, 1, BIT(6) | BIT(12), 0, BIT(6), BIT(12), 206 "ptp", "mii"), 207 PIN_GRP_GPIO_3("ptp_trig", 22, 1, BIT(7) | BIT(13), 0, BIT(7), BIT(13), 208 "ptp", "mii"), 209 PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14), 210 "mii", "mii_err"), 211}; 212 213static const struct armada_37xx_pin_data armada_37xx_pin_nb = { 214 .nr_pins = 36, 215 .name = "GPIO1", 216 .groups = armada_37xx_nb_groups, 217 .ngroups = ARRAY_SIZE(armada_37xx_nb_groups), 218}; 219 220static const struct armada_37xx_pin_data armada_37xx_pin_sb = { 221 .nr_pins = 30, 222 .name = "GPIO2", 223 .groups = armada_37xx_sb_groups, 224 .ngroups = ARRAY_SIZE(armada_37xx_sb_groups), 225}; 226 227static inline void armada_37xx_update_reg(unsigned int *reg, 228 unsigned int *offset) 229{ 230 /* We never have more than 2 registers */ 231 if (*offset >= GPIO_PER_REG) { 232 *offset -= GPIO_PER_REG; 233 *reg += sizeof(u32); 234 } 235} 236 237static struct armada_37xx_pin_group *armada_37xx_find_next_grp_by_pin( 238 struct armada_37xx_pinctrl *info, int pin, int *grp) 239{ 240 while (*grp < info->ngroups) { 241 struct armada_37xx_pin_group *group = &info->groups[*grp]; 242 int j; 243 244 *grp = *grp + 1; 245 for (j = 0; j < (group->npins + group->extra_npins); j++) 246 if (group->pins[j] == pin) 247 return group; 248 } 249 return NULL; 250} 251 252static int armada_37xx_pin_config_group_get(struct pinctrl_dev *pctldev, 253 unsigned int selector, unsigned long *config) 254{ 255 return -ENOTSUPP; 256} 257 258static int armada_37xx_pin_config_group_set(struct pinctrl_dev *pctldev, 259 unsigned int selector, unsigned long *configs, 260 unsigned int num_configs) 261{ 262 return -ENOTSUPP; 263} 264 265static const struct pinconf_ops armada_37xx_pinconf_ops = { 266 .is_generic = true, 267 .pin_config_group_get = armada_37xx_pin_config_group_get, 268 .pin_config_group_set = armada_37xx_pin_config_group_set, 269}; 270 271static int armada_37xx_get_groups_count(struct pinctrl_dev *pctldev) 272{ 273 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 274 275 return info->ngroups; 276} 277 278static const char *armada_37xx_get_group_name(struct pinctrl_dev *pctldev, 279 unsigned int group) 280{ 281 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 282 283 return info->groups[group].name; 284} 285 286static int armada_37xx_get_group_pins(struct pinctrl_dev *pctldev, 287 unsigned int selector, 288 const unsigned int **pins, 289 unsigned int *npins) 290{ 291 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 292 293 if (selector >= info->ngroups) 294 return -EINVAL; 295 296 *pins = info->groups[selector].pins; 297 *npins = info->groups[selector].npins + 298 info->groups[selector].extra_npins; 299 300 return 0; 301} 302 303static const struct pinctrl_ops armada_37xx_pctrl_ops = { 304 .get_groups_count = armada_37xx_get_groups_count, 305 .get_group_name = armada_37xx_get_group_name, 306 .get_group_pins = armada_37xx_get_group_pins, 307 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 308 .dt_free_map = pinctrl_utils_free_map, 309}; 310 311/* 312 * Pinmux_ops handling 313 */ 314 315static int armada_37xx_pmx_get_funcs_count(struct pinctrl_dev *pctldev) 316{ 317 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 318 319 return info->nfuncs; 320} 321 322static const char *armada_37xx_pmx_get_func_name(struct pinctrl_dev *pctldev, 323 unsigned int selector) 324{ 325 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 326 327 return info->funcs[selector].name; 328} 329 330static int armada_37xx_pmx_get_groups(struct pinctrl_dev *pctldev, 331 unsigned int selector, 332 const char * const **groups, 333 unsigned int * const num_groups) 334{ 335 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 336 337 *groups = info->funcs[selector].groups; 338 *num_groups = info->funcs[selector].ngroups; 339 340 return 0; 341} 342 343static int armada_37xx_pmx_set_by_name(struct pinctrl_dev *pctldev, 344 const char *name, 345 struct armada_37xx_pin_group *grp) 346{ 347 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 348 struct device *dev = info->dev; 349 unsigned int reg = SELECTION; 350 unsigned int mask = grp->reg_mask; 351 int func, val; 352 353 dev_dbg(dev, "enable function %s group %s\n", name, grp->name); 354 355 func = match_string(grp->funcs, NB_FUNCS, name); 356 if (func < 0) 357 return -ENOTSUPP; 358 359 val = grp->val[func]; 360 361 return regmap_update_bits(info->regmap, reg, mask, val); 362} 363 364static int armada_37xx_pmx_set(struct pinctrl_dev *pctldev, 365 unsigned int selector, 366 unsigned int group) 367{ 368 369 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 370 struct armada_37xx_pin_group *grp = &info->groups[group]; 371 const char *name = info->funcs[selector].name; 372 373 return armada_37xx_pmx_set_by_name(pctldev, name, grp); 374} 375 376static inline void armada_37xx_irq_update_reg(unsigned int *reg, 377 struct irq_data *d) 378{ 379 int offset = irqd_to_hwirq(d); 380 381 armada_37xx_update_reg(reg, &offset); 382} 383 384static int armada_37xx_gpio_direction_input(struct gpio_chip *chip, 385 unsigned int offset) 386{ 387 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 388 unsigned int reg = OUTPUT_EN; 389 unsigned int mask; 390 391 armada_37xx_update_reg(®, &offset); 392 mask = BIT(offset); 393 394 return regmap_update_bits(info->regmap, reg, mask, 0); 395} 396 397static int armada_37xx_gpio_get_direction(struct gpio_chip *chip, 398 unsigned int offset) 399{ 400 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 401 unsigned int reg = OUTPUT_EN; 402 unsigned int val, mask; 403 int ret; 404 405 armada_37xx_update_reg(®, &offset); 406 mask = BIT(offset); 407 ret = regmap_read(info->regmap, reg, &val); 408 if (ret) 409 return ret; 410 411 if (val & mask) 412 return GPIO_LINE_DIRECTION_OUT; 413 414 return GPIO_LINE_DIRECTION_IN; 415} 416 417static int armada_37xx_gpio_direction_output(struct gpio_chip *chip, 418 unsigned int offset, int value) 419{ 420 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 421 unsigned int en_offset = offset; 422 unsigned int reg = OUTPUT_VAL; 423 unsigned int mask, val; 424 int ret; 425 426 armada_37xx_update_reg(®, &offset); 427 mask = BIT(offset); 428 val = value ? mask : 0; 429 430 ret = regmap_update_bits(info->regmap, reg, mask, val); 431 if (ret) 432 return ret; 433 434 reg = OUTPUT_EN; 435 armada_37xx_update_reg(®, &en_offset); 436 437 return regmap_update_bits(info->regmap, reg, mask, mask); 438} 439 440static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset) 441{ 442 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 443 unsigned int reg = INPUT_VAL; 444 unsigned int val, mask; 445 int ret; 446 447 armada_37xx_update_reg(®, &offset); 448 mask = BIT(offset); 449 450 ret = regmap_read(info->regmap, reg, &val); 451 if (ret) 452 return ret; 453 454 return (val & mask) != 0; 455} 456 457static int armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset, 458 int value) 459{ 460 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 461 unsigned int reg = OUTPUT_VAL; 462 unsigned int mask, val; 463 464 armada_37xx_update_reg(®, &offset); 465 mask = BIT(offset); 466 val = value ? mask : 0; 467 468 return regmap_update_bits(info->regmap, reg, mask, val); 469} 470 471static int armada_37xx_pmx_gpio_set_direction(struct pinctrl_dev *pctldev, 472 struct pinctrl_gpio_range *range, 473 unsigned int offset, bool input) 474{ 475 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 476 struct gpio_chip *chip = range->gc; 477 int ret; 478 479 dev_dbg(info->dev, "gpio_direction for pin %u as %s-%d to %s\n", 480 offset, range->name, offset, input ? "input" : "output"); 481 482 if (input) 483 ret = armada_37xx_gpio_direction_input(chip, offset); 484 else 485 ret = armada_37xx_gpio_direction_output(chip, offset, 0); 486 487 return ret; 488} 489 490static int armada_37xx_gpio_request_enable(struct pinctrl_dev *pctldev, 491 struct pinctrl_gpio_range *range, 492 unsigned int offset) 493{ 494 struct armada_37xx_pinctrl *info = pinctrl_dev_get_drvdata(pctldev); 495 struct armada_37xx_pin_group *group; 496 int grp = 0; 497 int ret; 498 499 dev_dbg(info->dev, "requesting gpio %d\n", offset); 500 501 while ((group = armada_37xx_find_next_grp_by_pin(info, offset, &grp))) { 502 ret = armada_37xx_pmx_set_by_name(pctldev, "gpio", group); 503 if (ret) 504 return ret; 505 } 506 507 return 0; 508} 509 510static const struct pinmux_ops armada_37xx_pmx_ops = { 511 .get_functions_count = armada_37xx_pmx_get_funcs_count, 512 .get_function_name = armada_37xx_pmx_get_func_name, 513 .get_function_groups = armada_37xx_pmx_get_groups, 514 .set_mux = armada_37xx_pmx_set, 515 .gpio_request_enable = armada_37xx_gpio_request_enable, 516 .gpio_set_direction = armada_37xx_pmx_gpio_set_direction, 517}; 518 519static const struct gpio_chip armada_37xx_gpiolib_chip = { 520 .request = gpiochip_generic_request, 521 .free = gpiochip_generic_free, 522 .set = armada_37xx_gpio_set, 523 .get = armada_37xx_gpio_get, 524 .get_direction = armada_37xx_gpio_get_direction, 525 .direction_input = armada_37xx_gpio_direction_input, 526 .direction_output = armada_37xx_gpio_direction_output, 527 .owner = THIS_MODULE, 528}; 529 530static void armada_37xx_irq_ack(struct irq_data *d) 531{ 532 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 533 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 534 u32 reg = IRQ_STATUS; 535 unsigned long flags; 536 537 armada_37xx_irq_update_reg(®, d); 538 raw_spin_lock_irqsave(&info->irq_lock, flags); 539 writel(d->mask, info->base + reg); 540 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 541} 542 543static void armada_37xx_irq_mask(struct irq_data *d) 544{ 545 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 546 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 547 u32 val, reg = IRQ_EN; 548 unsigned long flags; 549 550 armada_37xx_irq_update_reg(®, d); 551 raw_spin_lock_irqsave(&info->irq_lock, flags); 552 val = readl(info->base + reg); 553 writel(val & ~d->mask, info->base + reg); 554 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 555 gpiochip_disable_irq(chip, irqd_to_hwirq(d)); 556} 557 558static void armada_37xx_irq_unmask(struct irq_data *d) 559{ 560 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 561 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 562 u32 val, reg = IRQ_EN; 563 unsigned long flags; 564 565 gpiochip_enable_irq(chip, irqd_to_hwirq(d)); 566 armada_37xx_irq_update_reg(®, d); 567 raw_spin_lock_irqsave(&info->irq_lock, flags); 568 val = readl(info->base + reg); 569 writel(val | d->mask, info->base + reg); 570 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 571} 572 573static int armada_37xx_irq_set_wake(struct irq_data *d, unsigned int on) 574{ 575 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 576 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 577 u32 val, reg = IRQ_WKUP; 578 unsigned long flags; 579 580 armada_37xx_irq_update_reg(®, d); 581 raw_spin_lock_irqsave(&info->irq_lock, flags); 582 val = readl(info->base + reg); 583 if (on) 584 val |= (BIT(d->hwirq % GPIO_PER_REG)); 585 else 586 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 587 writel(val, info->base + reg); 588 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 589 590 return 0; 591} 592 593static int armada_37xx_irq_set_type(struct irq_data *d, unsigned int type) 594{ 595 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 596 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 597 u32 val, reg = IRQ_POL; 598 unsigned long flags; 599 600 raw_spin_lock_irqsave(&info->irq_lock, flags); 601 armada_37xx_irq_update_reg(®, d); 602 val = readl(info->base + reg); 603 switch (type) { 604 case IRQ_TYPE_EDGE_RISING: 605 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); 606 break; 607 case IRQ_TYPE_EDGE_FALLING: 608 val |= (BIT(d->hwirq % GPIO_PER_REG)); 609 break; 610 case IRQ_TYPE_EDGE_BOTH: { 611 u32 in_val, in_reg = INPUT_VAL; 612 613 armada_37xx_irq_update_reg(&in_reg, d); 614 regmap_read(info->regmap, in_reg, &in_val); 615 616 /* Set initial polarity based on current input level. */ 617 if (in_val & BIT(d->hwirq % GPIO_PER_REG)) 618 val |= BIT(d->hwirq % GPIO_PER_REG); /* falling */ 619 else 620 val &= ~(BIT(d->hwirq % GPIO_PER_REG)); /* rising */ 621 break; 622 } 623 default: 624 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 625 return -EINVAL; 626 } 627 writel(val, info->base + reg); 628 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 629 630 return 0; 631} 632 633static int armada_37xx_edge_both_irq_swap_pol(struct armada_37xx_pinctrl *info, 634 u32 pin_idx) 635{ 636 u32 reg_idx = pin_idx / GPIO_PER_REG; 637 u32 bit_num = pin_idx % GPIO_PER_REG; 638 unsigned long flags; 639 u32 p, l; 640 int ret; 641 642 regmap_read(info->regmap, INPUT_VAL + 4*reg_idx, &l); 643 644 raw_spin_lock_irqsave(&info->irq_lock, flags); 645 p = readl(info->base + IRQ_POL + 4 * reg_idx); 646 if ((p ^ l) & (1 << bit_num)) { 647 /* 648 * For the gpios which are used for both-edge irqs, when their 649 * interrupts happen, their input levels are changed, 650 * yet their interrupt polarities are kept in old values, we 651 * should synchronize their interrupt polarities; for example, 652 * at first a gpio's input level is low and its interrupt 653 * polarity control is "Detect rising edge", then the gpio has 654 * a interrupt , its level turns to high, we should change its 655 * polarity control to "Detect falling edge" correspondingly. 656 */ 657 p ^= 1 << bit_num; 658 writel(p, info->base + IRQ_POL + 4 * reg_idx); 659 ret = 0; 660 } else { 661 /* Spurious irq */ 662 ret = -1; 663 } 664 665 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 666 return ret; 667} 668 669static void armada_37xx_irq_handler(struct irq_desc *desc) 670{ 671 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 672 struct irq_chip *chip = irq_desc_get_chip(desc); 673 struct armada_37xx_pinctrl *info = gpiochip_get_data(gc); 674 struct irq_domain *d = gc->irq.domain; 675 int i; 676 677 chained_irq_enter(chip, desc); 678 for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) { 679 u32 status; 680 unsigned long flags; 681 682 raw_spin_lock_irqsave(&info->irq_lock, flags); 683 status = readl_relaxed(info->base + IRQ_STATUS + 4 * i); 684 /* Manage only the interrupt that was enabled */ 685 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 686 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 687 while (status) { 688 u32 hwirq = ffs(status) - 1; 689 u32 virq = irq_find_mapping(d, hwirq + 690 i * GPIO_PER_REG); 691 u32 t = irq_get_trigger_type(virq); 692 693 if ((t & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 694 /* Swap polarity (race with GPIO line) */ 695 if (armada_37xx_edge_both_irq_swap_pol(info, 696 hwirq + i * GPIO_PER_REG)) { 697 /* 698 * For spurious irq, which gpio level 699 * is not as expected after incoming 700 * edge, just ack the gpio irq. 701 */ 702 writel(1 << hwirq, 703 info->base + 704 IRQ_STATUS + 4 * i); 705 goto update_status; 706 } 707 } 708 709 generic_handle_irq(virq); 710 711update_status: 712 /* Update status in case a new IRQ appears */ 713 raw_spin_lock_irqsave(&info->irq_lock, flags); 714 status = readl_relaxed(info->base + 715 IRQ_STATUS + 4 * i); 716 /* Manage only the interrupt that was enabled */ 717 status &= readl_relaxed(info->base + IRQ_EN + 4 * i); 718 raw_spin_unlock_irqrestore(&info->irq_lock, flags); 719 } 720 } 721 chained_irq_exit(chip, desc); 722} 723 724static unsigned int armada_37xx_irq_startup(struct irq_data *d) 725{ 726 /* 727 * The mask field is a "precomputed bitmask for accessing the 728 * chip registers" which was introduced for the generic 729 * irqchip framework. As we don't use this framework, we can 730 * reuse this field for our own usage. 731 */ 732 d->mask = BIT(d->hwirq % GPIO_PER_REG); 733 734 armada_37xx_irq_unmask(d); 735 736 return 0; 737} 738 739static void armada_37xx_irq_print_chip(struct irq_data *d, struct seq_file *p) 740{ 741 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 742 struct armada_37xx_pinctrl *info = gpiochip_get_data(chip); 743 744 seq_puts(p, info->data->name); 745} 746 747static const struct irq_chip armada_37xx_irqchip = { 748 .irq_ack = armada_37xx_irq_ack, 749 .irq_mask = armada_37xx_irq_mask, 750 .irq_unmask = armada_37xx_irq_unmask, 751 .irq_set_wake = armada_37xx_irq_set_wake, 752 .irq_set_type = armada_37xx_irq_set_type, 753 .irq_startup = armada_37xx_irq_startup, 754 .irq_print_chip = armada_37xx_irq_print_chip, 755 .flags = IRQCHIP_IMMUTABLE, 756 GPIOCHIP_IRQ_RESOURCE_HELPERS, 757}; 758 759static int armada_37xx_irqchip_register(struct platform_device *pdev, 760 struct armada_37xx_pinctrl *info) 761{ 762 struct gpio_chip *gc = &info->gpio_chip; 763 struct gpio_irq_chip *girq = &gc->irq; 764 struct device_node *np = to_of_node(gc->fwnode); 765 struct device *dev = &pdev->dev; 766 unsigned int i, nr_irq_parent; 767 768 raw_spin_lock_init(&info->irq_lock); 769 770 nr_irq_parent = of_irq_count(np); 771 if (!nr_irq_parent) { 772 dev_err(dev, "invalid or no IRQ\n"); 773 return 0; 774 } 775 776 info->base = devm_platform_ioremap_resource(pdev, 1); 777 if (IS_ERR(info->base)) 778 return PTR_ERR(info->base); 779 780 gpio_irq_chip_set_chip(girq, &armada_37xx_irqchip); 781 girq->parent_handler = armada_37xx_irq_handler; 782 /* 783 * Many interrupts are connected to the parent interrupt 784 * controller. But we do not take advantage of this and use 785 * the chained irq with all of them. 786 */ 787 girq->num_parents = nr_irq_parent; 788 girq->parents = devm_kcalloc(dev, nr_irq_parent, sizeof(*girq->parents), GFP_KERNEL); 789 if (!girq->parents) 790 return -ENOMEM; 791 for (i = 0; i < nr_irq_parent; i++) { 792 int irq = irq_of_parse_and_map(np, i); 793 794 if (!irq) 795 continue; 796 girq->parents[i] = irq; 797 } 798 girq->default_type = IRQ_TYPE_NONE; 799 girq->handler = handle_edge_irq; 800 801 return 0; 802} 803 804static int armada_37xx_gpiochip_register(struct platform_device *pdev, 805 struct armada_37xx_pinctrl *info) 806{ 807 struct device *dev = &pdev->dev; 808 struct fwnode_handle *fwnode; 809 struct gpio_chip *gc; 810 int ret; 811 812 fwnode = gpiochip_node_get_first(dev); 813 if (!fwnode) 814 return -ENODEV; 815 816 info->gpio_chip = armada_37xx_gpiolib_chip; 817 818 gc = &info->gpio_chip; 819 gc->ngpio = info->data->nr_pins; 820 gc->parent = dev; 821 gc->base = -1; 822 gc->fwnode = fwnode; 823 gc->label = info->data->name; 824 825 ret = armada_37xx_irqchip_register(pdev, info); 826 if (ret) 827 return ret; 828 829 return devm_gpiochip_add_data(dev, gc, info); 830} 831 832/** 833 * armada_37xx_add_function() - Add a new function to the list 834 * @funcs: array of function to add the new one 835 * @funcsize: size of the remaining space for the function 836 * @name: name of the function to add 837 * 838 * If it is a new function then create it by adding its name else 839 * increment the number of group associated to this function. 840 */ 841static int armada_37xx_add_function(struct armada_37xx_pmx_func *funcs, 842 int *funcsize, const char *name) 843{ 844 if (*funcsize <= 0) 845 return -EOVERFLOW; 846 847 while (funcs->ngroups) { 848 /* function already there */ 849 if (strcmp(funcs->name, name) == 0) { 850 funcs->ngroups++; 851 852 return -EEXIST; 853 } 854 funcs++; 855 } 856 857 /* append new unique function */ 858 funcs->name = name; 859 funcs->ngroups = 1; 860 (*funcsize)--; 861 862 return 0; 863} 864 865/** 866 * armada_37xx_fill_group() - complete the group array 867 * @info: info driver instance 868 * 869 * Based on the data available from the armada_37xx_pin_group array 870 * completes the last member of the struct for each function: the list 871 * of the groups associated to this function. 872 * 873 */ 874static int armada_37xx_fill_group(struct armada_37xx_pinctrl *info) 875{ 876 int n, num = 0, funcsize = info->data->nr_pins; 877 struct device *dev = info->dev; 878 879 for (n = 0; n < info->ngroups; n++) { 880 struct armada_37xx_pin_group *grp = &info->groups[n]; 881 int i, j, f; 882 883 grp->pins = devm_kcalloc(dev, grp->npins + grp->extra_npins, 884 sizeof(*grp->pins), 885 GFP_KERNEL); 886 if (!grp->pins) 887 return -ENOMEM; 888 889 for (i = 0; i < grp->npins; i++) 890 grp->pins[i] = grp->start_pin + i; 891 892 for (j = 0; j < grp->extra_npins; j++) 893 grp->pins[i+j] = grp->extra_pin + j; 894 895 for (f = 0; (f < NB_FUNCS) && grp->funcs[f]; f++) { 896 int ret; 897 /* check for unique functions and count groups */ 898 ret = armada_37xx_add_function(info->funcs, &funcsize, 899 grp->funcs[f]); 900 if (ret == -EOVERFLOW) 901 dev_err(dev, "More functions than pins(%d)\n", 902 info->data->nr_pins); 903 if (ret < 0) 904 continue; 905 num++; 906 } 907 } 908 909 info->nfuncs = num; 910 911 return 0; 912} 913 914/** 915 * armada_37xx_fill_func() - complete the funcs array 916 * @info: info driver instance 917 * 918 * Based on the data available from the armada_37xx_pin_group array 919 * completes the last two member of the struct for each group: 920 * - the list of the pins included in the group 921 * - the list of pinmux functions that can be selected for this group 922 * 923 */ 924static int armada_37xx_fill_func(struct armada_37xx_pinctrl *info) 925{ 926 struct armada_37xx_pmx_func *funcs = info->funcs; 927 struct device *dev = info->dev; 928 int n; 929 930 for (n = 0; n < info->nfuncs; n++) { 931 const char *name = funcs[n].name; 932 const char **groups; 933 int g; 934 935 funcs[n].groups = devm_kcalloc(dev, funcs[n].ngroups, 936 sizeof(*(funcs[n].groups)), 937 GFP_KERNEL); 938 if (!funcs[n].groups) 939 return -ENOMEM; 940 941 groups = funcs[n].groups; 942 943 for (g = 0; g < info->ngroups; g++) { 944 struct armada_37xx_pin_group *gp = &info->groups[g]; 945 int f; 946 947 f = match_string(gp->funcs, NB_FUNCS, name); 948 if (f < 0) 949 continue; 950 951 *groups = gp->name; 952 groups++; 953 } 954 } 955 return 0; 956} 957 958static int armada_37xx_pinctrl_register(struct platform_device *pdev, 959 struct armada_37xx_pinctrl *info) 960{ 961 const struct armada_37xx_pin_data *pin_data = info->data; 962 struct pinctrl_desc *ctrldesc = &info->pctl; 963 struct pinctrl_pin_desc *pindesc, *pdesc; 964 struct device *dev = &pdev->dev; 965 char **pin_names; 966 int pin, ret; 967 968 info->groups = pin_data->groups; 969 info->ngroups = pin_data->ngroups; 970 971 ctrldesc->name = "armada_37xx-pinctrl"; 972 ctrldesc->owner = THIS_MODULE; 973 ctrldesc->pctlops = &armada_37xx_pctrl_ops; 974 ctrldesc->pmxops = &armada_37xx_pmx_ops; 975 ctrldesc->confops = &armada_37xx_pinconf_ops; 976 977 pindesc = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*pindesc), GFP_KERNEL); 978 if (!pindesc) 979 return -ENOMEM; 980 981 ctrldesc->pins = pindesc; 982 ctrldesc->npins = pin_data->nr_pins; 983 984 pin_names = devm_kasprintf_strarray(dev, pin_data->name, pin_data->nr_pins); 985 if (IS_ERR(pin_names)) 986 return PTR_ERR(pin_names); 987 988 pdesc = pindesc; 989 for (pin = 0; pin < pin_data->nr_pins; pin++) { 990 pdesc->number = pin; 991 pdesc->name = pin_names[pin]; 992 pdesc++; 993 } 994 995 /* 996 * we allocate functions for number of pins and hope there are 997 * fewer unique functions than pins available 998 */ 999 info->funcs = devm_kcalloc(dev, pin_data->nr_pins, sizeof(*info->funcs), GFP_KERNEL); 1000 if (!info->funcs) 1001 return -ENOMEM; 1002 1003 ret = armada_37xx_fill_group(info); 1004 if (ret) 1005 return ret; 1006 1007 ret = armada_37xx_fill_func(info); 1008 if (ret) 1009 return ret; 1010 1011 info->pctl_dev = devm_pinctrl_register(dev, ctrldesc, info); 1012 if (IS_ERR(info->pctl_dev)) 1013 return dev_err_probe(dev, PTR_ERR(info->pctl_dev), "could not register pinctrl driver\n"); 1014 1015 return 0; 1016} 1017 1018static int armada_3700_pinctrl_suspend(struct device *dev) 1019{ 1020 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1021 1022 /* Save GPIO state */ 1023 regmap_read(info->regmap, OUTPUT_EN, &info->pm.out_en_l); 1024 regmap_read(info->regmap, OUTPUT_EN + sizeof(u32), &info->pm.out_en_h); 1025 regmap_read(info->regmap, OUTPUT_VAL, &info->pm.out_val_l); 1026 regmap_read(info->regmap, OUTPUT_VAL + sizeof(u32), 1027 &info->pm.out_val_h); 1028 1029 info->pm.irq_en_l = readl(info->base + IRQ_EN); 1030 info->pm.irq_en_h = readl(info->base + IRQ_EN + sizeof(u32)); 1031 info->pm.irq_pol_l = readl(info->base + IRQ_POL); 1032 info->pm.irq_pol_h = readl(info->base + IRQ_POL + sizeof(u32)); 1033 1034 /* Save pinctrl state */ 1035 regmap_read(info->regmap, SELECTION, &info->pm.selection); 1036 1037 return 0; 1038} 1039 1040static int armada_3700_pinctrl_resume(struct device *dev) 1041{ 1042 struct armada_37xx_pinctrl *info = dev_get_drvdata(dev); 1043 struct gpio_chip *gc; 1044 struct irq_domain *d; 1045 int i; 1046 1047 /* Restore GPIO state */ 1048 regmap_write(info->regmap, OUTPUT_EN, info->pm.out_en_l); 1049 regmap_write(info->regmap, OUTPUT_EN + sizeof(u32), 1050 info->pm.out_en_h); 1051 regmap_write(info->regmap, OUTPUT_VAL, info->pm.out_val_l); 1052 regmap_write(info->regmap, OUTPUT_VAL + sizeof(u32), 1053 info->pm.out_val_h); 1054 1055 /* 1056 * Input levels may change during suspend, which is not monitored at 1057 * that time. GPIOs used for both-edge IRQs may not be synchronized 1058 * anymore with their polarities (rising/falling edge) and must be 1059 * re-configured manually. 1060 */ 1061 gc = &info->gpio_chip; 1062 d = gc->irq.domain; 1063 for (i = 0; i < gc->ngpio; i++) { 1064 u32 irq_bit = BIT(i % GPIO_PER_REG); 1065 u32 mask, *irq_pol, input_reg, virq, type, level; 1066 1067 if (i < GPIO_PER_REG) { 1068 mask = info->pm.irq_en_l; 1069 irq_pol = &info->pm.irq_pol_l; 1070 input_reg = INPUT_VAL; 1071 } else { 1072 mask = info->pm.irq_en_h; 1073 irq_pol = &info->pm.irq_pol_h; 1074 input_reg = INPUT_VAL + sizeof(u32); 1075 } 1076 1077 if (!(mask & irq_bit)) 1078 continue; 1079 1080 virq = irq_find_mapping(d, i); 1081 type = irq_get_trigger_type(virq); 1082 1083 /* 1084 * Synchronize level and polarity for both-edge irqs: 1085 * - a high input level expects a falling edge, 1086 * - a low input level exepects a rising edge. 1087 */ 1088 if ((type & IRQ_TYPE_SENSE_MASK) == 1089 IRQ_TYPE_EDGE_BOTH) { 1090 regmap_read(info->regmap, input_reg, &level); 1091 if ((*irq_pol ^ level) & irq_bit) 1092 *irq_pol ^= irq_bit; 1093 } 1094 } 1095 1096 writel(info->pm.irq_en_l, info->base + IRQ_EN); 1097 writel(info->pm.irq_en_h, info->base + IRQ_EN + sizeof(u32)); 1098 writel(info->pm.irq_pol_l, info->base + IRQ_POL); 1099 writel(info->pm.irq_pol_h, info->base + IRQ_POL + sizeof(u32)); 1100 1101 /* Restore pinctrl state */ 1102 regmap_write(info->regmap, SELECTION, info->pm.selection); 1103 1104 return 0; 1105} 1106 1107/* 1108 * Since pinctrl is an infrastructure module, its resume should be issued prior 1109 * to other IO drivers. 1110 */ 1111static DEFINE_NOIRQ_DEV_PM_OPS(armada_3700_pinctrl_pm_ops, 1112 armada_3700_pinctrl_suspend, armada_3700_pinctrl_resume); 1113 1114static const struct of_device_id armada_37xx_pinctrl_of_match[] = { 1115 { 1116 .compatible = "marvell,armada3710-sb-pinctrl", 1117 .data = &armada_37xx_pin_sb, 1118 }, 1119 { 1120 .compatible = "marvell,armada3710-nb-pinctrl", 1121 .data = &armada_37xx_pin_nb, 1122 }, 1123 { }, 1124}; 1125 1126static const struct regmap_config armada_37xx_pinctrl_regmap_config = { 1127 .reg_bits = 32, 1128 .val_bits = 32, 1129 .reg_stride = 4, 1130 .use_raw_spinlock = true, 1131}; 1132 1133static int __init armada_37xx_pinctrl_probe(struct platform_device *pdev) 1134{ 1135 struct armada_37xx_pinctrl *info; 1136 struct device *dev = &pdev->dev; 1137 struct regmap *regmap; 1138 void __iomem *base; 1139 int ret; 1140 1141 base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL); 1142 if (IS_ERR(base)) { 1143 dev_err(dev, "failed to ioremap base address: %pe\n", base); 1144 return PTR_ERR(base); 1145 } 1146 1147 regmap = devm_regmap_init_mmio(dev, base, 1148 &armada_37xx_pinctrl_regmap_config); 1149 if (IS_ERR(regmap)) { 1150 dev_err(dev, "failed to create regmap: %pe\n", regmap); 1151 return PTR_ERR(regmap); 1152 } 1153 1154 info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL); 1155 if (!info) 1156 return -ENOMEM; 1157 1158 info->dev = dev; 1159 info->regmap = regmap; 1160 info->data = of_device_get_match_data(dev); 1161 1162 ret = armada_37xx_pinctrl_register(pdev, info); 1163 if (ret) 1164 return ret; 1165 1166 ret = armada_37xx_gpiochip_register(pdev, info); 1167 if (ret) 1168 return ret; 1169 1170 platform_set_drvdata(pdev, info); 1171 1172 return 0; 1173} 1174 1175static struct platform_driver armada_37xx_pinctrl_driver = { 1176 .driver = { 1177 .name = "armada-37xx-pinctrl", 1178 .of_match_table = armada_37xx_pinctrl_of_match, 1179 .pm = pm_sleep_ptr(&armada_3700_pinctrl_pm_ops), 1180 }, 1181}; 1182 1183builtin_platform_driver_probe(armada_37xx_pinctrl_driver, 1184 armada_37xx_pinctrl_probe);
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