pinctrl-amlogic-a4.c

   1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
   2/*
   3 * Copyright (c) 2024 Amlogic, Inc. All rights reserved.
   4 * Author: Xianwei Zhao <xianwei.zhao@amlogic.com>
   5 */
   6
   7#include <linux/err.h>
   8#include <linux/gpio/driver.h>
   9#include <linux/init.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/of.h>
  13#include <linux/of_address.h>
  14#include <linux/platform_device.h>
  15#include <linux/regmap.h>
  16#include <linux/seq_file.h>
  17#include <linux/slab.h>
  18#include <linux/string_helpers.h>
  19
  20#include <linux/pinctrl/consumer.h>
  21#include <linux/pinctrl/pinconf.h>
  22#include <linux/pinctrl/pinctrl.h>
  23#include <linux/pinctrl/pinmux.h>
  24#include <dt-bindings/pinctrl/amlogic,pinctrl.h>
  25
  26#include "../core.h"
  27#include "../pinctrl-utils.h"
  28#include "../pinconf.h"
  29
  30#define gpio_chip_to_bank(chip) \
  31		container_of(chip, struct aml_gpio_bank, gpio_chip)
  32
  33#define AML_REG_PULLEN		0
  34#define AML_REG_PULL		1
  35#define AML_REG_DIR		2
  36#define AML_REG_OUT		3
  37#define AML_REG_IN		4
  38#define AML_REG_DS		5
  39#define AML_NUM_REG		6
  40
  41enum aml_pinconf_drv {
  42	PINCONF_DRV_500UA,
  43	PINCONF_DRV_2500UA,
  44	PINCONF_DRV_3000UA,
  45	PINCONF_DRV_4000UA,
  46};
  47
  48struct aml_pio_control {
  49	u32 gpio_offset;
  50	u32 reg_offset[AML_NUM_REG];
  51	u32 bit_offset[AML_NUM_REG];
  52};
  53
  54/*
  55 * partial bank(subordinate) pins mux config use other bank(main) mux registgers
  56 * m_bank_id:	the main bank which pin_id from 0, but register bit not from bit 0
  57 * m_bit_offs:	bit offset the main bank mux register
  58 * sid:         start pin_id of subordinate bank
  59 * eid:         end pin_id of subordinate bank
  60 */
  61struct multi_mux {
  62	unsigned int m_bank_id;
  63	unsigned int m_bit_offs;
  64	unsigned int sid;
  65	unsigned int eid;
  66};
  67
  68struct aml_pctl_data {
  69	unsigned int number;
  70	const struct multi_mux *p_mux;
  71};
  72
  73struct aml_pmx_func {
  74	const char	*name;
  75	const char	**groups;
  76	unsigned int	ngroups;
  77};
  78
  79struct aml_pctl_group {
  80	const char		*name;
  81	unsigned int		npins;
  82	unsigned int		*pins;
  83	unsigned int		*func;
  84};
  85
  86struct aml_gpio_bank {
  87	struct gpio_chip		gpio_chip;
  88	struct aml_pio_control		pc;
  89	u32				bank_id;
  90	u32				mux_bit_offs;
  91	unsigned int			pin_base;
  92	struct regmap			*reg_mux;
  93	struct regmap			*reg_gpio;
  94	struct regmap			*reg_ds;
  95	const struct multi_mux		*p_mux;
  96};
  97
  98struct aml_pinctrl {
  99	struct device			*dev;
 100	struct pinctrl_dev		*pctl;
 101	struct aml_gpio_bank		*banks;
 102	int				nbanks;
 103	struct aml_pmx_func		*functions;
 104	int				nfunctions;
 105	struct aml_pctl_group		*groups;
 106	int				ngroups;
 107
 108	const struct aml_pctl_data	*data;
 109};
 110
 111static const unsigned int aml_bit_strides[AML_NUM_REG] = {
 112	1, 1, 1, 1, 1, 2
 113};
 114
 115static const unsigned int aml_def_regoffs[AML_NUM_REG] = {
 116	3, 4, 2, 1, 0, 7
 117};
 118
 119static const char *aml_bank_name[31] = {
 120"GPIOA", "GPIOB", "GPIOC", "GPIOD", "GPIOE", "GPIOF", "GPIOG",
 121"GPIOH", "GPIOI", "GPIOJ", "GPIOK", "GPIOL", "GPIOM", "GPION",
 122"GPIOO", "GPIOP", "GPIOQ", "GPIOR", "GPIOS", "GPIOT", "GPIOU",
 123"GPIOV", "GPIOW", "GPIOX", "GPIOY", "GPIOZ", "GPIODV", "GPIOAO",
 124"GPIOCC", "TEST_N", "ANALOG"
 125};
 126
 127static const struct multi_mux multi_mux_s7[] = {
 128	{
 129		.m_bank_id = AMLOGIC_GPIO_CC,
 130		.m_bit_offs = 24,
 131		.sid = (AMLOGIC_GPIO_X << 8) + 16,
 132		.eid = (AMLOGIC_GPIO_X << 8) + 19,
 133	},
 134};
 135
 136static const struct aml_pctl_data s7_priv_data = {
 137	.number = ARRAY_SIZE(multi_mux_s7),
 138	.p_mux = multi_mux_s7,
 139};
 140
 141static const struct multi_mux multi_mux_s6[] = {
 142	{
 143		.m_bank_id = AMLOGIC_GPIO_CC,
 144		.m_bit_offs = 24,
 145		.sid = (AMLOGIC_GPIO_X << 8) + 16,
 146		.eid = (AMLOGIC_GPIO_X << 8) + 19,
 147	}, {
 148		.m_bank_id = AMLOGIC_GPIO_F,
 149		.m_bit_offs = 4,
 150		.sid = (AMLOGIC_GPIO_D << 8) + 6,
 151		.eid = (AMLOGIC_GPIO_D << 8) + 6,
 152	},
 153};
 154
 155static const struct aml_pctl_data s6_priv_data = {
 156	.number = ARRAY_SIZE(multi_mux_s6),
 157	.p_mux = multi_mux_s6,
 158};
 159
 160static int aml_pmx_calc_reg_and_offset(struct pinctrl_gpio_range *range,
 161				       unsigned int pin, unsigned int *reg,
 162				       unsigned int *offset)
 163{
 164	unsigned int shift;
 165
 166	shift = ((pin - range->pin_base) << 2) + *offset;
 167	*reg = (shift / 32) * 4;
 168	*offset = shift % 32;
 169
 170	return 0;
 171}
 172
 173static int aml_pctl_set_function(struct aml_pinctrl *info,
 174				 struct pinctrl_gpio_range *range,
 175				 int pin_id, int func)
 176{
 177	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 178	unsigned int shift;
 179	int reg;
 180	int i;
 181	unsigned int offset = bank->mux_bit_offs;
 182	const struct multi_mux *p_mux;
 183
 184	/* peculiar mux reg set */
 185	if (bank->p_mux) {
 186		p_mux = bank->p_mux;
 187		if (pin_id >= p_mux->sid && pin_id <= p_mux->eid) {
 188			bank = NULL;
 189			for (i = 0; i < info->nbanks; i++) {
 190				if (info->banks[i].bank_id == p_mux->m_bank_id) {
 191					bank = &info->banks[i];
 192						break;
 193				}
 194			}
 195
 196			if (!bank || !bank->reg_mux)
 197				return -EINVAL;
 198
 199			shift = (pin_id - p_mux->sid) << 2;
 200			reg = (shift / 32) * 4;
 201			offset = shift % 32;
 202			return regmap_update_bits(bank->reg_mux, reg,
 203					0xf << offset, (func & 0xf) << offset);
 204		}
 205	}
 206
 207	/* normal mux reg set */
 208	if (!bank->reg_mux)
 209		return 0;
 210
 211	aml_pmx_calc_reg_and_offset(range, pin_id, &reg, &offset);
 212	return regmap_update_bits(bank->reg_mux, reg,
 213			0xf << offset, (func & 0xf) << offset);
 214}
 215
 216static int aml_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
 217{
 218	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 219
 220	return info->nfunctions;
 221}
 222
 223static const char *aml_pmx_get_fname(struct pinctrl_dev *pctldev,
 224				     unsigned int selector)
 225{
 226	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 227
 228	return info->functions[selector].name;
 229}
 230
 231static int aml_pmx_get_groups(struct pinctrl_dev *pctldev,
 232			      unsigned int selector,
 233			      const char * const **grps,
 234			      unsigned * const ngrps)
 235{
 236	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 237
 238	*grps = info->functions[selector].groups;
 239	*ngrps = info->functions[selector].ngroups;
 240
 241	return 0;
 242}
 243
 244static int aml_pmx_set_mux(struct pinctrl_dev *pctldev, unsigned int fselector,
 245			   unsigned int group_id)
 246{
 247	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 248	struct aml_pctl_group *group = &info->groups[group_id];
 249	struct pinctrl_gpio_range *range;
 250	int i;
 251
 252	for (i = 0; i < group->npins; i++) {
 253		range =  pinctrl_find_gpio_range_from_pin(pctldev, group->pins[i]);
 254		aml_pctl_set_function(info, range, group->pins[i], group->func[i]);
 255	}
 256
 257	return 0;
 258}
 259
 260static int aml_pmx_request_gpio(struct pinctrl_dev *pctldev,
 261				struct pinctrl_gpio_range *range,
 262				unsigned int pin)
 263{
 264	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 265
 266	return aml_pctl_set_function(info, range, pin, 0);
 267}
 268
 269static const struct pinmux_ops aml_pmx_ops = {
 270	.set_mux		= aml_pmx_set_mux,
 271	.get_functions_count	= aml_pmx_get_funcs_count,
 272	.get_function_name	= aml_pmx_get_fname,
 273	.get_function_groups	= aml_pmx_get_groups,
 274	.gpio_request_enable	= aml_pmx_request_gpio,
 275};
 276
 277static int aml_calc_reg_and_bit(struct pinctrl_gpio_range *range,
 278				unsigned int pin,
 279				unsigned int reg_type,
 280				unsigned int *reg, unsigned int *bit)
 281{
 282	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 283
 284	*bit = (pin - range->pin_base) * aml_bit_strides[reg_type]
 285		+ bank->pc.bit_offset[reg_type];
 286	*reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4;
 287	*bit &= 0x1f;
 288
 289	return 0;
 290}
 291
 292static int aml_pinconf_get_pull(struct aml_pinctrl *info, unsigned int pin)
 293{
 294	struct pinctrl_gpio_range *range =
 295			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 296	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 297	unsigned int reg, bit, val;
 298	int ret, conf;
 299
 300	aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, &reg, &bit);
 301
 302	ret = regmap_read(bank->reg_gpio, reg, &val);
 303	if (ret)
 304		return ret;
 305
 306	if (!(val & BIT(bit))) {
 307		conf = PIN_CONFIG_BIAS_DISABLE;
 308	} else {
 309		aml_calc_reg_and_bit(range, pin, AML_REG_PULL, &reg, &bit);
 310
 311		ret = regmap_read(bank->reg_gpio, reg, &val);
 312		if (ret)
 313			return ret;
 314
 315		if (val & BIT(bit))
 316			conf = PIN_CONFIG_BIAS_PULL_UP;
 317		else
 318			conf = PIN_CONFIG_BIAS_PULL_DOWN;
 319	}
 320
 321	return conf;
 322}
 323
 324static int aml_pinconf_get_drive_strength(struct aml_pinctrl *info,
 325					  unsigned int pin,
 326					  u16 *drive_strength_ua)
 327{
 328	struct pinctrl_gpio_range *range =
 329			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 330	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 331	unsigned int reg, bit;
 332	unsigned int val;
 333	int ret;
 334
 335	if (!bank->reg_ds)
 336		return -EOPNOTSUPP;
 337
 338	aml_calc_reg_and_bit(range, pin, AML_REG_DS, &reg, &bit);
 339	ret = regmap_read(bank->reg_ds, reg, &val);
 340	if (ret)
 341		return ret;
 342
 343	switch ((val >> bit) & 0x3) {
 344	case PINCONF_DRV_500UA:
 345		*drive_strength_ua = 500;
 346		break;
 347	case PINCONF_DRV_2500UA:
 348		*drive_strength_ua = 2500;
 349		break;
 350	case PINCONF_DRV_3000UA:
 351		*drive_strength_ua = 3000;
 352		break;
 353	case PINCONF_DRV_4000UA:
 354		*drive_strength_ua = 4000;
 355		break;
 356	default:
 357		return -EINVAL;
 358	}
 359
 360	return 0;
 361}
 362
 363static int aml_pinconf_get_gpio_bit(struct aml_pinctrl *info,
 364				    unsigned int pin,
 365				    unsigned int reg_type)
 366{
 367	struct pinctrl_gpio_range *range =
 368			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 369	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 370	unsigned int reg, bit, val;
 371	int ret;
 372
 373	aml_calc_reg_and_bit(range, pin, reg_type, &reg, &bit);
 374	ret = regmap_read(bank->reg_gpio, reg, &val);
 375	if (ret)
 376		return ret;
 377
 378	return BIT(bit) & val ? 1 : 0;
 379}
 380
 381static int aml_pinconf_get_output(struct aml_pinctrl *info,
 382				  unsigned int pin)
 383{
 384	int ret = aml_pinconf_get_gpio_bit(info, pin, AML_REG_DIR);
 385
 386	if (ret < 0)
 387		return ret;
 388
 389	return !ret;
 390}
 391
 392static int aml_pinconf_get_drive(struct aml_pinctrl *info,
 393				 unsigned int pin)
 394{
 395	return aml_pinconf_get_gpio_bit(info, pin, AML_REG_OUT);
 396}
 397
 398static int aml_pinconf_get(struct pinctrl_dev *pcdev, unsigned int pin,
 399			   unsigned long *config)
 400{
 401	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev);
 402	enum pin_config_param param = pinconf_to_config_param(*config);
 403	u16 arg;
 404	int ret;
 405
 406	switch (param) {
 407	case PIN_CONFIG_BIAS_DISABLE:
 408	case PIN_CONFIG_BIAS_PULL_DOWN:
 409	case PIN_CONFIG_BIAS_PULL_UP:
 410		if (aml_pinconf_get_pull(info, pin) == param)
 411			arg = 1;
 412		else
 413			return -EINVAL;
 414		break;
 415	case PIN_CONFIG_DRIVE_STRENGTH_UA:
 416		ret = aml_pinconf_get_drive_strength(info, pin, &arg);
 417		if (ret)
 418			return ret;
 419		break;
 420	case PIN_CONFIG_OUTPUT_ENABLE:
 421		ret = aml_pinconf_get_output(info, pin);
 422		if (ret <= 0)
 423			return -EINVAL;
 424		arg = 1;
 425		break;
 426	case PIN_CONFIG_LEVEL:
 427		ret = aml_pinconf_get_output(info, pin);
 428		if (ret <= 0)
 429			return -EINVAL;
 430
 431		ret = aml_pinconf_get_drive(info, pin);
 432		if (ret < 0)
 433			return -EINVAL;
 434
 435		arg = ret;
 436		break;
 437
 438	default:
 439		return -ENOTSUPP;
 440	}
 441
 442	*config = pinconf_to_config_packed(param, arg);
 443	dev_dbg(info->dev, "pinconf for pin %u is %lu\n", pin, *config);
 444
 445	return 0;
 446}
 447
 448static int aml_pinconf_disable_bias(struct aml_pinctrl *info,
 449				    unsigned int pin)
 450{
 451	struct pinctrl_gpio_range *range =
 452			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 453	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 454	unsigned int reg, bit = 0;
 455
 456	aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, &reg, &bit);
 457
 458	return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0);
 459}
 460
 461static int aml_pinconf_enable_bias(struct aml_pinctrl *info, unsigned int pin,
 462				   bool pull_up)
 463{
 464	struct pinctrl_gpio_range *range =
 465			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 466	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 467	unsigned int reg, bit, val = 0;
 468	int ret;
 469
 470	aml_calc_reg_and_bit(range, pin, AML_REG_PULL, &reg, &bit);
 471	if (pull_up)
 472		val = BIT(bit);
 473
 474	ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), val);
 475	if (ret)
 476		return ret;
 477
 478	aml_calc_reg_and_bit(range, pin, AML_REG_PULLEN, &reg, &bit);
 479	return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit));
 480}
 481
 482static int aml_pinconf_set_drive_strength(struct aml_pinctrl *info,
 483					  unsigned int pin,
 484					  u16 drive_strength_ua)
 485{
 486	struct pinctrl_gpio_range *range =
 487			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 488	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 489	unsigned int reg, bit, ds_val;
 490
 491	if (!bank->reg_ds) {
 492		dev_err(info->dev, "drive-strength not supported\n");
 493		return -EOPNOTSUPP;
 494	}
 495
 496	aml_calc_reg_and_bit(range, pin, AML_REG_DS, &reg, &bit);
 497
 498	if (drive_strength_ua <= 500) {
 499		ds_val = PINCONF_DRV_500UA;
 500	} else if (drive_strength_ua <= 2500) {
 501		ds_val = PINCONF_DRV_2500UA;
 502	} else if (drive_strength_ua <= 3000) {
 503		ds_val = PINCONF_DRV_3000UA;
 504	} else if (drive_strength_ua <= 4000) {
 505		ds_val = PINCONF_DRV_4000UA;
 506	} else {
 507		dev_warn_once(info->dev,
 508			      "pin %u: invalid drive-strength : %d , default to 4mA\n",
 509			      pin, drive_strength_ua);
 510		ds_val = PINCONF_DRV_4000UA;
 511	}
 512
 513	return regmap_update_bits(bank->reg_ds, reg, 0x3 << bit, ds_val << bit);
 514}
 515
 516static int aml_pinconf_set_gpio_bit(struct aml_pinctrl *info,
 517				    unsigned int pin,
 518				    unsigned int reg_type,
 519				    bool arg)
 520{
 521	struct pinctrl_gpio_range *range =
 522			 pinctrl_find_gpio_range_from_pin(info->pctl, pin);
 523	struct aml_gpio_bank *bank = gpio_chip_to_bank(range->gc);
 524	unsigned int reg, bit;
 525
 526	aml_calc_reg_and_bit(range, pin, reg_type, &reg, &bit);
 527	return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
 528				  arg ? BIT(bit) : 0);
 529}
 530
 531static int aml_pinconf_set_output(struct aml_pinctrl *info,
 532				  unsigned int pin,
 533				  bool out)
 534{
 535	return aml_pinconf_set_gpio_bit(info, pin, AML_REG_DIR, !out);
 536}
 537
 538static int aml_pinconf_set_drive(struct aml_pinctrl *info,
 539				 unsigned int pin,
 540				 bool high)
 541{
 542	return aml_pinconf_set_gpio_bit(info, pin, AML_REG_OUT, high);
 543}
 544
 545static int aml_pinconf_set_output_drive(struct aml_pinctrl *info,
 546					unsigned int pin,
 547					bool high)
 548{
 549	int ret;
 550
 551	ret = aml_pinconf_set_output(info, pin, true);
 552	if (ret)
 553		return ret;
 554
 555	return aml_pinconf_set_drive(info, pin, high);
 556}
 557
 558static int aml_pinconf_set(struct pinctrl_dev *pcdev, unsigned int pin,
 559			   unsigned long *configs, unsigned int num_configs)
 560{
 561	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev);
 562	enum pin_config_param param;
 563	unsigned int arg = 0;
 564	int i, ret;
 565
 566	for (i = 0; i < num_configs; i++) {
 567		param = pinconf_to_config_param(configs[i]);
 568
 569		switch (param) {
 570		case PIN_CONFIG_DRIVE_STRENGTH_UA:
 571		case PIN_CONFIG_OUTPUT_ENABLE:
 572		case PIN_CONFIG_LEVEL:
 573			arg = pinconf_to_config_argument(configs[i]);
 574			break;
 575
 576		default:
 577			break;
 578		}
 579
 580		switch (param) {
 581		case PIN_CONFIG_BIAS_DISABLE:
 582			ret = aml_pinconf_disable_bias(info, pin);
 583			break;
 584		case PIN_CONFIG_BIAS_PULL_UP:
 585			ret = aml_pinconf_enable_bias(info, pin, true);
 586			break;
 587		case PIN_CONFIG_BIAS_PULL_DOWN:
 588			ret = aml_pinconf_enable_bias(info, pin, false);
 589			break;
 590		case PIN_CONFIG_DRIVE_STRENGTH_UA:
 591			ret = aml_pinconf_set_drive_strength(info, pin, arg);
 592			break;
 593		case PIN_CONFIG_OUTPUT_ENABLE:
 594			ret = aml_pinconf_set_output(info, pin, arg);
 595			break;
 596		case PIN_CONFIG_LEVEL:
 597			ret = aml_pinconf_set_output_drive(info, pin, arg);
 598			break;
 599		default:
 600			ret = -ENOTSUPP;
 601		}
 602
 603		if (ret)
 604			return ret;
 605	}
 606
 607	return 0;
 608}
 609
 610static int aml_pinconf_group_set(struct pinctrl_dev *pcdev,
 611				 unsigned int num_group,
 612				 unsigned long *configs,
 613				 unsigned int num_configs)
 614{
 615	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pcdev);
 616	int i;
 617
 618	for (i = 0; i < info->groups[num_group].npins; i++) {
 619		aml_pinconf_set(pcdev, info->groups[num_group].pins[i], configs,
 620				num_configs);
 621	}
 622
 623	return 0;
 624}
 625
 626static int aml_pinconf_group_get(struct pinctrl_dev *pcdev,
 627				 unsigned int group, unsigned long *config)
 628{
 629	return -EOPNOTSUPP;
 630}
 631
 632static const struct pinconf_ops aml_pinconf_ops = {
 633	.pin_config_get		= aml_pinconf_get,
 634	.pin_config_set		= aml_pinconf_set,
 635	.pin_config_group_get	= aml_pinconf_group_get,
 636	.pin_config_group_set	= aml_pinconf_group_set,
 637	.is_generic		= true,
 638};
 639
 640static int aml_get_groups_count(struct pinctrl_dev *pctldev)
 641{
 642	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 643
 644	return info->ngroups;
 645}
 646
 647static const char *aml_get_group_name(struct pinctrl_dev *pctldev,
 648				      unsigned int selector)
 649{
 650	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 651
 652	return info->groups[selector].name;
 653}
 654
 655static int aml_get_group_pins(struct pinctrl_dev *pctldev,
 656			      unsigned int selector, const unsigned int **pins,
 657			      unsigned int *npins)
 658{
 659	struct aml_pinctrl *info = pinctrl_dev_get_drvdata(pctldev);
 660
 661	if (selector >= info->ngroups)
 662		return -EINVAL;
 663
 664	*pins = info->groups[selector].pins;
 665	*npins = info->groups[selector].npins;
 666
 667	return 0;
 668}
 669
 670static void aml_pin_dbg_show(struct pinctrl_dev *pcdev, struct seq_file *s,
 671			     unsigned int offset)
 672{
 673	seq_printf(s, " %s", dev_name(pcdev->dev));
 674}
 675
 676static int aml_dt_node_to_map_pinmux(struct pinctrl_dev *pctldev,
 677				     struct device_node *np,
 678				     struct pinctrl_map **map,
 679				     unsigned int *num_maps)
 680{
 681	struct device *dev = pctldev->dev;
 682	unsigned long *configs = NULL;
 683	unsigned int num_configs = 0;
 684	struct property *prop;
 685	unsigned int reserved_maps;
 686	int reserve;
 687	int ret;
 688
 689	prop = of_find_property(np, "pinmux", NULL);
 690	if (!prop) {
 691		dev_info(dev, "Missing pinmux property\n");
 692		return -ENOENT;
 693	}
 694
 695	struct device_node *pnode __free(device_node) = of_get_parent(np);
 696	if (!pnode) {
 697		dev_info(dev, "Missing function node\n");
 698		return -EINVAL;
 699	}
 700
 701	reserved_maps = 0;
 702	*map = NULL;
 703	*num_maps = 0;
 704
 705	ret = pinconf_generic_parse_dt_config(np, pctldev, &configs,
 706					      &num_configs);
 707	if (ret < 0) {
 708		dev_err(dev, "%pOF: could not parse node property\n", np);
 709		return ret;
 710	}
 711
 712	reserve = 1;
 713	if (num_configs)
 714		reserve++;
 715
 716	ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps,
 717					num_maps, reserve);
 718	if (ret < 0)
 719		goto exit;
 720
 721	ret = pinctrl_utils_add_map_mux(pctldev, map,
 722					&reserved_maps, num_maps, np->name,
 723					pnode->name);
 724	if (ret < 0)
 725		goto exit;
 726
 727	if (num_configs) {
 728		ret = pinctrl_utils_add_map_configs(pctldev, map, &reserved_maps,
 729						    num_maps, np->name, configs,
 730						    num_configs, PIN_MAP_TYPE_CONFIGS_GROUP);
 731		if (ret < 0)
 732			goto exit;
 733	}
 734
 735exit:
 736	kfree(configs);
 737	if (ret)
 738		pinctrl_utils_free_map(pctldev, *map, *num_maps);
 739
 740	return ret;
 741}
 742
 743static const struct pinctrl_ops aml_pctrl_ops = {
 744	.get_groups_count	= aml_get_groups_count,
 745	.get_group_name		= aml_get_group_name,
 746	.get_group_pins		= aml_get_group_pins,
 747	.dt_node_to_map		= aml_dt_node_to_map_pinmux,
 748	.dt_free_map		= pinconf_generic_dt_free_map,
 749	.pin_dbg_show		= aml_pin_dbg_show,
 750};
 751
 752static int aml_pctl_parse_functions(struct device_node *np,
 753				    struct aml_pinctrl *info, u32 index,
 754				    int *grp_index)
 755{
 756	struct device *dev = info->dev;
 757	struct aml_pmx_func *func;
 758	struct aml_pctl_group *grp;
 759	int ret, i;
 760
 761	func = &info->functions[index];
 762	func->name = np->name;
 763	func->ngroups = of_get_child_count(np);
 764	if (func->ngroups == 0)
 765		return dev_err_probe(dev, -EINVAL, "No groups defined\n");
 766
 767	func->groups = devm_kcalloc(dev, func->ngroups, sizeof(*func->groups), GFP_KERNEL);
 768	if (!func->groups)
 769		return -ENOMEM;
 770
 771	i = 0;
 772	for_each_child_of_node_scoped(np, child) {
 773		func->groups[i++] = child->name;
 774		grp = &info->groups[*grp_index];
 775		grp->name = child->name;
 776		*grp_index += 1;
 777		ret = pinconf_generic_parse_dt_pinmux(child, dev, &grp->pins,
 778						      &grp->func, &grp->npins);
 779		if (ret) {
 780			dev_err(dev, "function :%s, groups:%s fail\n", func->name, child->name);
 781			return ret;
 782		}
 783	}
 784	dev_dbg(dev, "Function[%d\t name:%s,\tgroups:%d]\n", index, func->name, func->ngroups);
 785
 786	return 0;
 787}
 788
 789static u32 aml_bank_pins(struct device_node *np)
 790{
 791	struct of_phandle_args of_args;
 792
 793	if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
 794					     0, &of_args))
 795		return 0;
 796
 797	of_node_put(of_args.np);
 798	return of_args.args[2];
 799}
 800
 801static int aml_bank_number(struct device_node *np)
 802{
 803	struct of_phandle_args of_args;
 804
 805	if (of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
 806					     0, &of_args))
 807		return -EINVAL;
 808
 809	of_node_put(of_args.np);
 810	return of_args.args[1] >> 8;
 811}
 812
 813static unsigned int aml_count_pins(struct device_node *np)
 814{
 815	struct device_node *child;
 816	unsigned int pins = 0;
 817
 818	for_each_child_of_node(np, child) {
 819		if (of_property_read_bool(child, "gpio-controller"))
 820			pins += aml_bank_pins(child);
 821	}
 822
 823	return pins;
 824}
 825
 826/*
 827 * A pinctrl device contains two types of nodes. The one named GPIO
 828 * bank which includes gpio-controller property. The other one named
 829 * function which includes one or more pin groups. The pin group
 830 * include pinmux property(global index in pinctrl dev, and mux vlaue
 831 * in mux reg) and pin configuration properties.
 832 */
 833static void aml_pctl_dt_child_count(struct aml_pinctrl *info,
 834				    struct device_node *np)
 835{
 836	struct device_node *child;
 837
 838	for_each_child_of_node(np, child) {
 839		if (of_property_read_bool(child, "gpio-controller")) {
 840			info->nbanks++;
 841		} else {
 842			info->nfunctions++;
 843			info->ngroups += of_get_child_count(child);
 844		}
 845	}
 846}
 847
 848static struct regmap *aml_map_resource(struct device *dev, unsigned int id,
 849				       struct device_node *node, char *name)
 850{
 851	struct resource res;
 852	void __iomem *base;
 853	int i;
 854
 855	struct regmap_config aml_regmap_config = {
 856		.reg_bits = 32,
 857		.val_bits = 32,
 858		.reg_stride = 4,
 859	};
 860
 861	i = of_property_match_string(node, "reg-names", name);
 862	if (i < 0)
 863		return NULL;
 864	if (of_address_to_resource(node, i, &res))
 865		return NULL;
 866	base = devm_ioremap_resource(dev, &res);
 867	if (IS_ERR(base))
 868		return ERR_CAST(base);
 869
 870	aml_regmap_config.max_register = resource_size(&res) - 4;
 871	aml_regmap_config.name = devm_kasprintf(dev, GFP_KERNEL,
 872						"%s-%s", aml_bank_name[id], name);
 873	if (!aml_regmap_config.name)
 874		return ERR_PTR(-ENOMEM);
 875
 876	return devm_regmap_init_mmio(dev, base, &aml_regmap_config);
 877}
 878
 879static inline int aml_gpio_calc_reg_and_bit(struct aml_gpio_bank *bank,
 880					    unsigned int reg_type,
 881					    unsigned int gpio,
 882					    unsigned int *reg,
 883					    unsigned int *bit)
 884{
 885	*bit = gpio * aml_bit_strides[reg_type] + bank->pc.bit_offset[reg_type];
 886	*reg = (bank->pc.reg_offset[reg_type] + (*bit / 32)) * 4;
 887	*bit &= 0x1f;
 888
 889	return 0;
 890}
 891
 892static int aml_gpio_get_direction(struct gpio_chip *chip, unsigned int gpio)
 893{
 894	struct aml_gpio_bank *bank = gpiochip_get_data(chip);
 895	unsigned int bit, reg, val;
 896	int ret;
 897
 898	aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);
 899
 900	ret = regmap_read(bank->reg_gpio, reg, &val);
 901	if (ret)
 902		return ret;
 903
 904	return BIT(bit) & val ? GPIO_LINE_DIRECTION_IN : GPIO_LINE_DIRECTION_OUT;
 905}
 906
 907static int aml_gpio_direction_input(struct gpio_chip *chip, unsigned int gpio)
 908{
 909	struct aml_gpio_bank *bank = gpiochip_get_data(chip);
 910	unsigned int bit, reg;
 911
 912	aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);
 913
 914	return regmap_update_bits(bank->reg_gpio, reg, BIT(bit), BIT(bit));
 915}
 916
 917static int aml_gpio_direction_output(struct gpio_chip *chip, unsigned int gpio,
 918				     int value)
 919{
 920	struct aml_gpio_bank *bank = gpiochip_get_data(chip);
 921	unsigned int bit, reg;
 922	int ret;
 923
 924	aml_gpio_calc_reg_and_bit(bank, AML_REG_DIR, gpio, &reg, &bit);
 925	ret = regmap_update_bits(bank->reg_gpio, reg, BIT(bit), 0);
 926	if (ret < 0)
 927		return ret;
 928
 929	aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, &reg, &bit);
 930
 931	return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
 932				  value ? BIT(bit) : 0);
 933}
 934
 935static int aml_gpio_set(struct gpio_chip *chip, unsigned int gpio, int value)
 936{
 937	struct aml_gpio_bank *bank = gpiochip_get_data(chip);
 938	unsigned int bit, reg;
 939
 940	aml_gpio_calc_reg_and_bit(bank, AML_REG_OUT, gpio, &reg, &bit);
 941
 942	return regmap_update_bits(bank->reg_gpio, reg, BIT(bit),
 943				  value ? BIT(bit) : 0);
 944}
 945
 946static int aml_gpio_get(struct gpio_chip *chip, unsigned int gpio)
 947{
 948	struct aml_gpio_bank *bank = gpiochip_get_data(chip);
 949	unsigned int reg, bit, val;
 950
 951	aml_gpio_calc_reg_and_bit(bank, AML_REG_IN, gpio, &reg, &bit);
 952	regmap_read(bank->reg_gpio, reg, &val);
 953
 954	return !!(val & BIT(bit));
 955}
 956
 957static const struct gpio_chip aml_gpio_template = {
 958	.request		= gpiochip_generic_request,
 959	.free			= gpiochip_generic_free,
 960	.set_config		= gpiochip_generic_config,
 961	.set			= aml_gpio_set,
 962	.get			= aml_gpio_get,
 963	.direction_input	= aml_gpio_direction_input,
 964	.direction_output	= aml_gpio_direction_output,
 965	.get_direction		= aml_gpio_get_direction,
 966	.can_sleep		= true,
 967};
 968
 969static void init_bank_register_bit(struct aml_pinctrl *info,
 970				   struct aml_gpio_bank *bank)
 971{
 972	const struct aml_pctl_data *data = info->data;
 973	const struct multi_mux *p_mux;
 974	int i;
 975
 976	for (i = 0; i < AML_NUM_REG; i++) {
 977		bank->pc.reg_offset[i] = aml_def_regoffs[i];
 978		bank->pc.bit_offset[i] = 0;
 979	}
 980
 981	bank->mux_bit_offs = 0;
 982
 983	if (data) {
 984		for (i = 0; i < data->number; i++) {
 985			p_mux = &data->p_mux[i];
 986			if (bank->bank_id == p_mux->m_bank_id) {
 987				bank->mux_bit_offs = p_mux->m_bit_offs;
 988				break;
 989			}
 990			if (p_mux->sid >> 8 == bank->bank_id) {
 991				bank->p_mux = p_mux;
 992				break;
 993			}
 994		}
 995	}
 996}
 997
 998static int aml_gpiolib_register_bank(struct aml_pinctrl *info,
 999				     int bank_nr, struct device_node *np)
1000{
1001	struct aml_gpio_bank *bank = &info->banks[bank_nr];
1002	struct device *dev = info->dev;
1003	int ret = 0;
1004
1005	ret = aml_bank_number(np);
1006	if (ret < 0) {
1007		dev_err(dev, "get num=%d bank identity fail\n", bank_nr);
1008		return -EINVAL;
1009	}
1010	bank->bank_id = ret;
1011
1012	bank->reg_mux = aml_map_resource(dev, bank->bank_id, np, "mux");
1013	if (IS_ERR_OR_NULL(bank->reg_mux)) {
1014		if (bank->bank_id == AMLOGIC_GPIO_TEST_N ||
1015		    bank->bank_id == AMLOGIC_GPIO_ANALOG)
1016			bank->reg_mux = NULL;
1017		else
1018			return dev_err_probe(dev, bank->reg_mux ? PTR_ERR(bank->reg_mux) : -ENOENT,
1019					     "mux registers not found\n");
1020	}
1021
1022	bank->reg_gpio = aml_map_resource(dev, bank->bank_id, np, "gpio");
1023	if (IS_ERR_OR_NULL(bank->reg_gpio))
1024		return dev_err_probe(dev, bank->reg_gpio ? PTR_ERR(bank->reg_gpio) : -ENOENT,
1025				     "gpio registers not found\n");
1026
1027	bank->reg_ds = aml_map_resource(dev, bank->bank_id, np, "ds");
1028	if (IS_ERR_OR_NULL(bank->reg_ds)) {
1029		dev_dbg(info->dev, "ds registers not found - skipping\n");
1030		bank->reg_ds = bank->reg_gpio;
1031	}
1032
1033	bank->gpio_chip = aml_gpio_template;
1034	bank->gpio_chip.base = -1;
1035	bank->gpio_chip.ngpio = aml_bank_pins(np);
1036	bank->gpio_chip.fwnode = of_fwnode_handle(np);
1037	bank->gpio_chip.parent = dev;
1038
1039	init_bank_register_bit(info, bank);
1040	bank->gpio_chip.label = aml_bank_name[bank->bank_id];
1041
1042	bank->pin_base = bank->bank_id << 8;
1043
1044	return 0;
1045}
1046
1047static int aml_pctl_probe_dt(struct platform_device *pdev,
1048			     struct pinctrl_desc *pctl_desc,
1049			     struct aml_pinctrl *info)
1050{
1051	struct device *dev = &pdev->dev;
1052	struct pinctrl_pin_desc *pdesc;
1053	struct device_node *np = dev->of_node;
1054	int grp_index = 0;
1055	int i = 0, j = 0, k = 0, bank;
1056	int ret = 0;
1057
1058	aml_pctl_dt_child_count(info, np);
1059	if (!info->nbanks)
1060		return dev_err_probe(dev, -EINVAL, "you need at least one gpio bank\n");
1061
1062	dev_dbg(dev, "nbanks = %d\n", info->nbanks);
1063	dev_dbg(dev, "nfunctions = %d\n", info->nfunctions);
1064	dev_dbg(dev, "ngroups = %d\n", info->ngroups);
1065
1066	info->functions = devm_kcalloc(dev, info->nfunctions, sizeof(*info->functions), GFP_KERNEL);
1067
1068	info->groups = devm_kcalloc(dev, info->ngroups, sizeof(*info->groups), GFP_KERNEL);
1069
1070	info->banks = devm_kcalloc(dev, info->nbanks, sizeof(*info->banks), GFP_KERNEL);
1071
1072	if (!info->functions || !info->groups || !info->banks)
1073		return -ENOMEM;
1074
1075	info->data = (struct aml_pctl_data *)of_device_get_match_data(dev);
1076
1077	pctl_desc->npins = aml_count_pins(np);
1078
1079	pdesc =	devm_kcalloc(dev, pctl_desc->npins, sizeof(*pdesc), GFP_KERNEL);
1080	if (!pdesc)
1081		return -ENOMEM;
1082
1083	pctl_desc->pins = pdesc;
1084
1085	bank = 0;
1086	for_each_child_of_node_scoped(np, child) {
1087		if (of_property_read_bool(child, "gpio-controller")) {
1088			const char *bank_name = NULL;
1089			char **pin_names;
1090
1091			ret = aml_gpiolib_register_bank(info, bank, child);
1092			if (ret)
1093				return ret;
1094
1095			k = info->banks[bank].pin_base;
1096			bank_name = info->banks[bank].gpio_chip.label;
1097
1098			pin_names = devm_kasprintf_strarray(dev, bank_name,
1099							    info->banks[bank].gpio_chip.ngpio);
1100			if (IS_ERR(pin_names))
1101				return PTR_ERR(pin_names);
1102
1103			for (j = 0; j < info->banks[bank].gpio_chip.ngpio; j++, k++) {
1104				pdesc->number = k;
1105				pdesc->name = pin_names[j];
1106				pdesc++;
1107			}
1108			bank++;
1109		} else {
1110			ret = aml_pctl_parse_functions(child, info,
1111						       i++, &grp_index);
1112			if (ret)
1113				return ret;
1114		}
1115	}
1116
1117	return 0;
1118}
1119
1120static int aml_pctl_probe(struct platform_device *pdev)
1121{
1122	struct device *dev = &pdev->dev;
1123	struct aml_pinctrl *info;
1124	struct pinctrl_desc *pctl_desc;
1125	int ret, i;
1126
1127	pctl_desc = devm_kzalloc(dev, sizeof(*pctl_desc), GFP_KERNEL);
1128	if (!pctl_desc)
1129		return -ENOMEM;
1130
1131	info = devm_kzalloc(dev, sizeof(*info), GFP_KERNEL);
1132	if (!info)
1133		return -ENOMEM;
1134
1135	info->dev = dev;
1136	platform_set_drvdata(pdev, info);
1137	ret = aml_pctl_probe_dt(pdev, pctl_desc, info);
1138	if (ret)
1139		return ret;
1140
1141	pctl_desc->owner	= THIS_MODULE;
1142	pctl_desc->pctlops	= &aml_pctrl_ops;
1143	pctl_desc->pmxops	= &aml_pmx_ops;
1144	pctl_desc->confops	= &aml_pinconf_ops;
1145	pctl_desc->name		= dev_name(dev);
1146
1147	info->pctl = devm_pinctrl_register(dev, pctl_desc, info);
1148	if (IS_ERR(info->pctl))
1149		return dev_err_probe(dev, PTR_ERR(info->pctl), "Failed pinctrl registration\n");
1150
1151	for (i = 0; i < info->nbanks; i++) {
1152		ret  = gpiochip_add_data(&info->banks[i].gpio_chip, &info->banks[i]);
1153		if (ret)
1154			return dev_err_probe(dev, ret, "Failed to add gpiochip(%d)!\n", i);
1155	}
1156
1157	return 0;
1158}
1159
1160static const struct of_device_id aml_pctl_of_match[] = {
1161	{ .compatible = "amlogic,pinctrl-a4", },
1162	{ .compatible = "amlogic,pinctrl-s7", .data = &s7_priv_data, },
1163	{ .compatible = "amlogic,pinctrl-s6", .data = &s6_priv_data, },
1164	{ /* sentinel */ }
1165};
1166MODULE_DEVICE_TABLE(of, aml_pctl_of_match);
1167
1168static struct platform_driver aml_pctl_driver = {
1169	.driver = {
1170		.name = "amlogic-pinctrl",
1171		.of_match_table = aml_pctl_of_match,
1172	},
1173	.probe = aml_pctl_probe,
1174};
1175module_platform_driver(aml_pctl_driver);
1176
1177MODULE_AUTHOR("Xianwei Zhao <xianwei.zhao@amlogic.com>");
1178MODULE_DESCRIPTION("Pin controller and GPIO driver for Amlogic SoC");
1179MODULE_LICENSE("Dual BSD/GPL");