FILE
pinctrl-mt7988.c
File preview with syntax highlighting.
linux-6.19.14/drivers/pinctrl/mediatek/pinctrl-mt7988.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * The MT7988 driver based on Linux generic pinctrl binding. 4 * 5 * Copyright (C) 2020 MediaTek Inc. 6 * Author: Sam Shih <sam.shih@mediatek.com> 7 */ 8 9#include "pinctrl-moore.h" 10 11enum mt7988_pinctrl_reg_page { 12 GPIO_BASE, 13 IOCFG_TR_BASE, 14 IOCFG_BR_BASE, 15 IOCFG_RB_BASE, 16 IOCFG_LB_BASE, 17 IOCFG_TL_BASE, 18}; 19 20#define MT7988_PIN(_number, _name) MTK_PIN(_number, _name, 0, _number, DRV_GRP4) 21 22#define PIN_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ 23 _x_bits) \ 24 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ 25 _x_bits, 32, 0) 26 27#define PINS_FIELD_BASE(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ 28 _x_bits) \ 29 PIN_FIELD_CALC(_s_pin, _e_pin, _i_base, _s_addr, _x_addrs, _s_bit, \ 30 _x_bits, 32, 1) 31 32static const struct mtk_pin_field_calc mt7988_pin_mode_range[] = { 33 PIN_FIELD(0, 83, 0x300, 0x10, 0, 4), 34}; 35 36static const struct mtk_pin_field_calc mt7988_pin_dir_range[] = { 37 PIN_FIELD(0, 83, 0x0, 0x10, 0, 1), 38}; 39 40static const struct mtk_pin_field_calc mt7988_pin_di_range[] = { 41 PIN_FIELD(0, 83, 0x200, 0x10, 0, 1), 42}; 43 44static const struct mtk_pin_field_calc mt7988_pin_do_range[] = { 45 PIN_FIELD(0, 83, 0x100, 0x10, 0, 1), 46}; 47 48static const struct mtk_pin_field_calc mt7988_pin_ies_range[] = { 49 PIN_FIELD_BASE(0, 0, 5, 0x30, 0x10, 13, 1), 50 PIN_FIELD_BASE(1, 1, 5, 0x30, 0x10, 14, 1), 51 PIN_FIELD_BASE(2, 2, 5, 0x30, 0x10, 11, 1), 52 PIN_FIELD_BASE(3, 3, 5, 0x30, 0x10, 12, 1), 53 PIN_FIELD_BASE(4, 4, 5, 0x30, 0x10, 0, 1), 54 PIN_FIELD_BASE(5, 5, 5, 0x30, 0x10, 9, 1), 55 PIN_FIELD_BASE(6, 6, 5, 0x30, 0x10, 10, 1), 56 57 PIN_FIELD_BASE(7, 7, 4, 0x30, 0x10, 8, 1), 58 PIN_FIELD_BASE(8, 8, 4, 0x30, 0x10, 6, 1), 59 PIN_FIELD_BASE(9, 9, 4, 0x30, 0x10, 5, 1), 60 PIN_FIELD_BASE(10, 10, 4, 0x30, 0x10, 3, 1), 61 62 PIN_FIELD_BASE(11, 11, 1, 0x40, 0x10, 0, 1), 63 PIN_FIELD_BASE(12, 12, 1, 0x40, 0x10, 21, 1), 64 PIN_FIELD_BASE(13, 13, 1, 0x40, 0x10, 1, 1), 65 PIN_FIELD_BASE(14, 14, 1, 0x40, 0x10, 2, 1), 66 67 PIN_FIELD_BASE(15, 15, 5, 0x30, 0x10, 7, 1), 68 PIN_FIELD_BASE(16, 16, 5, 0x30, 0x10, 8, 1), 69 PIN_FIELD_BASE(17, 17, 5, 0x30, 0x10, 3, 1), 70 PIN_FIELD_BASE(18, 18, 5, 0x30, 0x10, 4, 1), 71 72 PIN_FIELD_BASE(19, 19, 4, 0x30, 0x10, 7, 1), 73 PIN_FIELD_BASE(20, 20, 4, 0x30, 0x10, 4, 1), 74 75 PIN_FIELD_BASE(21, 21, 3, 0x50, 0x10, 17, 1), 76 PIN_FIELD_BASE(22, 22, 3, 0x50, 0x10, 23, 1), 77 PIN_FIELD_BASE(23, 23, 3, 0x50, 0x10, 20, 1), 78 PIN_FIELD_BASE(24, 24, 3, 0x50, 0x10, 19, 1), 79 PIN_FIELD_BASE(25, 25, 3, 0x50, 0x10, 21, 1), 80 PIN_FIELD_BASE(26, 26, 3, 0x50, 0x10, 22, 1), 81 PIN_FIELD_BASE(27, 27, 3, 0x50, 0x10, 18, 1), 82 PIN_FIELD_BASE(28, 28, 3, 0x50, 0x10, 25, 1), 83 PIN_FIELD_BASE(29, 29, 3, 0x50, 0x10, 26, 1), 84 PIN_FIELD_BASE(30, 30, 3, 0x50, 0x10, 27, 1), 85 PIN_FIELD_BASE(31, 31, 3, 0x50, 0x10, 24, 1), 86 PIN_FIELD_BASE(32, 32, 3, 0x50, 0x10, 28, 1), 87 PIN_FIELD_BASE(33, 33, 3, 0x60, 0x10, 0, 1), 88 PIN_FIELD_BASE(34, 34, 3, 0x50, 0x10, 31, 1), 89 PIN_FIELD_BASE(35, 35, 3, 0x50, 0x10, 29, 1), 90 PIN_FIELD_BASE(36, 36, 3, 0x50, 0x10, 30, 1), 91 PIN_FIELD_BASE(37, 37, 3, 0x60, 0x10, 1, 1), 92 PIN_FIELD_BASE(38, 38, 3, 0x50, 0x10, 11, 1), 93 PIN_FIELD_BASE(39, 39, 3, 0x50, 0x10, 10, 1), 94 PIN_FIELD_BASE(40, 40, 3, 0x50, 0x10, 0, 1), 95 PIN_FIELD_BASE(41, 41, 3, 0x50, 0x10, 1, 1), 96 PIN_FIELD_BASE(42, 42, 3, 0x50, 0x10, 9, 1), 97 PIN_FIELD_BASE(43, 43, 3, 0x50, 0x10, 8, 1), 98 PIN_FIELD_BASE(44, 44, 3, 0x50, 0x10, 7, 1), 99 PIN_FIELD_BASE(45, 45, 3, 0x50, 0x10, 6, 1), 100 PIN_FIELD_BASE(46, 46, 3, 0x50, 0x10, 5, 1), 101 PIN_FIELD_BASE(47, 47, 3, 0x50, 0x10, 4, 1), 102 PIN_FIELD_BASE(48, 48, 3, 0x50, 0x10, 3, 1), 103 PIN_FIELD_BASE(49, 49, 3, 0x50, 0x10, 2, 1), 104 PIN_FIELD_BASE(50, 50, 3, 0x50, 0x10, 15, 1), 105 PIN_FIELD_BASE(51, 51, 3, 0x50, 0x10, 12, 1), 106 PIN_FIELD_BASE(52, 52, 3, 0x50, 0x10, 13, 1), 107 PIN_FIELD_BASE(53, 53, 3, 0x50, 0x10, 14, 1), 108 PIN_FIELD_BASE(54, 54, 3, 0x50, 0x10, 16, 1), 109 110 PIN_FIELD_BASE(55, 55, 1, 0x40, 0x10, 14, 1), 111 PIN_FIELD_BASE(56, 56, 1, 0x40, 0x10, 15, 1), 112 PIN_FIELD_BASE(57, 57, 1, 0x40, 0x10, 13, 1), 113 PIN_FIELD_BASE(58, 58, 1, 0x40, 0x10, 4, 1), 114 PIN_FIELD_BASE(59, 59, 1, 0x40, 0x10, 5, 1), 115 PIN_FIELD_BASE(60, 60, 1, 0x40, 0x10, 6, 1), 116 PIN_FIELD_BASE(61, 61, 1, 0x40, 0x10, 3, 1), 117 PIN_FIELD_BASE(62, 62, 1, 0x40, 0x10, 7, 1), 118 PIN_FIELD_BASE(63, 63, 1, 0x40, 0x10, 20, 1), 119 PIN_FIELD_BASE(64, 64, 1, 0x40, 0x10, 8, 1), 120 PIN_FIELD_BASE(65, 65, 1, 0x40, 0x10, 9, 1), 121 PIN_FIELD_BASE(66, 66, 1, 0x40, 0x10, 10, 1), 122 PIN_FIELD_BASE(67, 67, 1, 0x40, 0x10, 11, 1), 123 PIN_FIELD_BASE(68, 68, 1, 0x40, 0x10, 12, 1), 124 125 PIN_FIELD_BASE(69, 69, 5, 0x30, 0x10, 1, 1), 126 PIN_FIELD_BASE(70, 70, 5, 0x30, 0x10, 2, 1), 127 PIN_FIELD_BASE(71, 71, 5, 0x30, 0x10, 5, 1), 128 PIN_FIELD_BASE(72, 72, 5, 0x30, 0x10, 6, 1), 129 130 PIN_FIELD_BASE(73, 73, 4, 0x30, 0x10, 10, 1), 131 PIN_FIELD_BASE(74, 74, 4, 0x30, 0x10, 1, 1), 132 PIN_FIELD_BASE(75, 75, 4, 0x30, 0x10, 11, 1), 133 PIN_FIELD_BASE(76, 76, 4, 0x30, 0x10, 9, 1), 134 PIN_FIELD_BASE(77, 77, 4, 0x30, 0x10, 2, 1), 135 PIN_FIELD_BASE(78, 78, 4, 0x30, 0x10, 0, 1), 136 PIN_FIELD_BASE(79, 79, 4, 0x30, 0x10, 12, 1), 137 138 PIN_FIELD_BASE(80, 80, 1, 0x40, 0x10, 18, 1), 139 PIN_FIELD_BASE(81, 81, 1, 0x40, 0x10, 19, 1), 140 PIN_FIELD_BASE(82, 82, 1, 0x40, 0x10, 16, 1), 141 PIN_FIELD_BASE(83, 83, 1, 0x40, 0x10, 17, 1), 142}; 143 144static const struct mtk_pin_field_calc mt7988_pin_smt_range[] = { 145 PIN_FIELD_BASE(0, 0, 5, 0xc0, 0x10, 13, 1), 146 PIN_FIELD_BASE(1, 1, 5, 0xc0, 0x10, 14, 1), 147 PIN_FIELD_BASE(2, 2, 5, 0xc0, 0x10, 11, 1), 148 PIN_FIELD_BASE(3, 3, 5, 0xc0, 0x10, 12, 1), 149 PIN_FIELD_BASE(4, 4, 5, 0xc0, 0x10, 0, 1), 150 PIN_FIELD_BASE(5, 5, 5, 0xc0, 0x10, 9, 1), 151 PIN_FIELD_BASE(6, 6, 5, 0xc0, 0x10, 10, 1), 152 153 PIN_FIELD_BASE(7, 7, 4, 0xb0, 0x10, 8, 1), 154 PIN_FIELD_BASE(8, 8, 4, 0xb0, 0x10, 6, 1), 155 PIN_FIELD_BASE(9, 9, 4, 0xb0, 0x10, 5, 1), 156 PIN_FIELD_BASE(10, 10, 4, 0xb0, 0x10, 3, 1), 157 158 PIN_FIELD_BASE(11, 11, 1, 0xe0, 0x10, 0, 1), 159 PIN_FIELD_BASE(12, 12, 1, 0xe0, 0x10, 21, 1), 160 PIN_FIELD_BASE(13, 13, 1, 0xe0, 0x10, 1, 1), 161 PIN_FIELD_BASE(14, 14, 1, 0xe0, 0x10, 2, 1), 162 163 PIN_FIELD_BASE(15, 15, 5, 0xc0, 0x10, 7, 1), 164 PIN_FIELD_BASE(16, 16, 5, 0xc0, 0x10, 8, 1), 165 PIN_FIELD_BASE(17, 17, 5, 0xc0, 0x10, 3, 1), 166 PIN_FIELD_BASE(18, 18, 5, 0xc0, 0x10, 4, 1), 167 168 PIN_FIELD_BASE(19, 19, 4, 0xb0, 0x10, 7, 1), 169 PIN_FIELD_BASE(20, 20, 4, 0xb0, 0x10, 4, 1), 170 171 PIN_FIELD_BASE(21, 21, 3, 0x140, 0x10, 17, 1), 172 PIN_FIELD_BASE(22, 22, 3, 0x140, 0x10, 23, 1), 173 PIN_FIELD_BASE(23, 23, 3, 0x140, 0x10, 20, 1), 174 PIN_FIELD_BASE(24, 24, 3, 0x140, 0x10, 19, 1), 175 PIN_FIELD_BASE(25, 25, 3, 0x140, 0x10, 21, 1), 176 PIN_FIELD_BASE(26, 26, 3, 0x140, 0x10, 22, 1), 177 PIN_FIELD_BASE(27, 27, 3, 0x140, 0x10, 18, 1), 178 PIN_FIELD_BASE(28, 28, 3, 0x140, 0x10, 25, 1), 179 PIN_FIELD_BASE(29, 29, 3, 0x140, 0x10, 26, 1), 180 PIN_FIELD_BASE(30, 30, 3, 0x140, 0x10, 27, 1), 181 PIN_FIELD_BASE(31, 31, 3, 0x140, 0x10, 24, 1), 182 PIN_FIELD_BASE(32, 32, 3, 0x140, 0x10, 28, 1), 183 PIN_FIELD_BASE(33, 33, 3, 0x150, 0x10, 0, 1), 184 PIN_FIELD_BASE(34, 34, 3, 0x140, 0x10, 31, 1), 185 PIN_FIELD_BASE(35, 35, 3, 0x140, 0x10, 29, 1), 186 PIN_FIELD_BASE(36, 36, 3, 0x140, 0x10, 30, 1), 187 PIN_FIELD_BASE(37, 37, 3, 0x150, 0x10, 1, 1), 188 PIN_FIELD_BASE(38, 38, 3, 0x140, 0x10, 11, 1), 189 PIN_FIELD_BASE(39, 39, 3, 0x140, 0x10, 10, 1), 190 PIN_FIELD_BASE(40, 40, 3, 0x140, 0x10, 0, 1), 191 PIN_FIELD_BASE(41, 41, 3, 0x140, 0x10, 1, 1), 192 PIN_FIELD_BASE(42, 42, 3, 0x140, 0x10, 9, 1), 193 PIN_FIELD_BASE(43, 43, 3, 0x140, 0x10, 8, 1), 194 PIN_FIELD_BASE(44, 44, 3, 0x140, 0x10, 7, 1), 195 PIN_FIELD_BASE(45, 45, 3, 0x140, 0x10, 6, 1), 196 PIN_FIELD_BASE(46, 46, 3, 0x140, 0x10, 5, 1), 197 PIN_FIELD_BASE(47, 47, 3, 0x140, 0x10, 4, 1), 198 PIN_FIELD_BASE(48, 48, 3, 0x140, 0x10, 3, 1), 199 PIN_FIELD_BASE(49, 49, 3, 0x140, 0x10, 2, 1), 200 PIN_FIELD_BASE(50, 50, 3, 0x140, 0x10, 15, 1), 201 PIN_FIELD_BASE(51, 51, 3, 0x140, 0x10, 12, 1), 202 PIN_FIELD_BASE(52, 52, 3, 0x140, 0x10, 13, 1), 203 PIN_FIELD_BASE(53, 53, 3, 0x140, 0x10, 14, 1), 204 PIN_FIELD_BASE(54, 54, 3, 0x140, 0x10, 16, 1), 205 206 PIN_FIELD_BASE(55, 55, 1, 0xe0, 0x10, 14, 1), 207 PIN_FIELD_BASE(56, 56, 1, 0xe0, 0x10, 15, 1), 208 PIN_FIELD_BASE(57, 57, 1, 0xe0, 0x10, 13, 1), 209 PIN_FIELD_BASE(58, 58, 1, 0xe0, 0x10, 4, 1), 210 PIN_FIELD_BASE(59, 59, 1, 0xe0, 0x10, 5, 1), 211 PIN_FIELD_BASE(60, 60, 1, 0xe0, 0x10, 6, 1), 212 PIN_FIELD_BASE(61, 61, 1, 0xe0, 0x10, 3, 1), 213 PIN_FIELD_BASE(62, 62, 1, 0xe0, 0x10, 7, 1), 214 PIN_FIELD_BASE(63, 63, 1, 0xe0, 0x10, 20, 1), 215 PIN_FIELD_BASE(64, 64, 1, 0xe0, 0x10, 8, 1), 216 PIN_FIELD_BASE(65, 65, 1, 0xe0, 0x10, 9, 1), 217 PIN_FIELD_BASE(66, 66, 1, 0xe0, 0x10, 10, 1), 218 PIN_FIELD_BASE(67, 67, 1, 0xe0, 0x10, 11, 1), 219 PIN_FIELD_BASE(68, 68, 1, 0xe0, 0x10, 12, 1), 220 221 PIN_FIELD_BASE(69, 69, 5, 0xc0, 0x10, 1, 1), 222 PIN_FIELD_BASE(70, 70, 5, 0xc0, 0x10, 2, 1), 223 PIN_FIELD_BASE(71, 71, 5, 0xc0, 0x10, 5, 1), 224 PIN_FIELD_BASE(72, 72, 5, 0xc0, 0x10, 6, 1), 225 226 PIN_FIELD_BASE(73, 73, 4, 0xb0, 0x10, 10, 1), 227 PIN_FIELD_BASE(74, 74, 4, 0xb0, 0x10, 1, 1), 228 PIN_FIELD_BASE(75, 75, 4, 0xb0, 0x10, 11, 1), 229 PIN_FIELD_BASE(76, 76, 4, 0xb0, 0x10, 9, 1), 230 PIN_FIELD_BASE(77, 77, 4, 0xb0, 0x10, 2, 1), 231 PIN_FIELD_BASE(78, 78, 4, 0xb0, 0x10, 0, 1), 232 PIN_FIELD_BASE(79, 79, 4, 0xb0, 0x10, 12, 1), 233 234 PIN_FIELD_BASE(80, 80, 1, 0xe0, 0x10, 18, 1), 235 PIN_FIELD_BASE(81, 81, 1, 0xe0, 0x10, 19, 1), 236 PIN_FIELD_BASE(82, 82, 1, 0xe0, 0x10, 16, 1), 237 PIN_FIELD_BASE(83, 83, 1, 0xe0, 0x10, 17, 1), 238}; 239 240static const struct mtk_pin_field_calc mt7988_pin_pu_range[] = { 241 PIN_FIELD_BASE(7, 7, 4, 0x60, 0x10, 5, 1), 242 PIN_FIELD_BASE(8, 8, 4, 0x60, 0x10, 4, 1), 243 PIN_FIELD_BASE(9, 9, 4, 0x60, 0x10, 3, 1), 244 PIN_FIELD_BASE(10, 10, 4, 0x60, 0x10, 2, 1), 245 246 PIN_FIELD_BASE(13, 13, 1, 0x70, 0x10, 0, 1), 247 PIN_FIELD_BASE(14, 14, 1, 0x70, 0x10, 1, 1), 248 PIN_FIELD_BASE(63, 63, 1, 0x70, 0x10, 2, 1), 249 250 PIN_FIELD_BASE(75, 75, 4, 0x60, 0x10, 7, 1), 251 PIN_FIELD_BASE(76, 76, 4, 0x60, 0x10, 6, 1), 252 PIN_FIELD_BASE(77, 77, 4, 0x60, 0x10, 1, 1), 253 PIN_FIELD_BASE(78, 78, 4, 0x60, 0x10, 0, 1), 254 PIN_FIELD_BASE(79, 79, 4, 0x60, 0x10, 8, 1), 255}; 256 257static const struct mtk_pin_field_calc mt7988_pin_pd_range[] = { 258 PIN_FIELD_BASE(7, 7, 4, 0x40, 0x10, 5, 1), 259 PIN_FIELD_BASE(8, 8, 4, 0x40, 0x10, 4, 1), 260 PIN_FIELD_BASE(9, 9, 4, 0x40, 0x10, 3, 1), 261 PIN_FIELD_BASE(10, 10, 4, 0x40, 0x10, 2, 1), 262 263 PIN_FIELD_BASE(13, 13, 1, 0x50, 0x10, 0, 1), 264 PIN_FIELD_BASE(14, 14, 1, 0x50, 0x10, 1, 1), 265 266 PIN_FIELD_BASE(15, 15, 5, 0x40, 0x10, 4, 1), 267 PIN_FIELD_BASE(16, 16, 5, 0x40, 0x10, 5, 1), 268 PIN_FIELD_BASE(17, 17, 5, 0x40, 0x10, 0, 1), 269 PIN_FIELD_BASE(18, 18, 5, 0x40, 0x10, 1, 1), 270 271 PIN_FIELD_BASE(63, 63, 1, 0x50, 0x10, 2, 1), 272 PIN_FIELD_BASE(71, 71, 5, 0x40, 0x10, 2, 1), 273 PIN_FIELD_BASE(72, 72, 5, 0x40, 0x10, 3, 1), 274 275 PIN_FIELD_BASE(75, 75, 4, 0x40, 0x10, 7, 1), 276 PIN_FIELD_BASE(76, 76, 4, 0x40, 0x10, 6, 1), 277 PIN_FIELD_BASE(77, 77, 4, 0x40, 0x10, 1, 1), 278 PIN_FIELD_BASE(78, 78, 4, 0x40, 0x10, 0, 1), 279 PIN_FIELD_BASE(79, 79, 4, 0x40, 0x10, 8, 1), 280}; 281 282static const struct mtk_pin_field_calc mt7988_pin_drv_range[] = { 283 PIN_FIELD_BASE(0, 0, 5, 0x00, 0x10, 21, 3), 284 PIN_FIELD_BASE(1, 1, 5, 0x00, 0x10, 24, 3), 285 PIN_FIELD_BASE(2, 2, 5, 0x00, 0x10, 15, 3), 286 PIN_FIELD_BASE(3, 3, 5, 0x00, 0x10, 18, 3), 287 PIN_FIELD_BASE(4, 4, 5, 0x00, 0x10, 0, 3), 288 PIN_FIELD_BASE(5, 5, 5, 0x00, 0x10, 9, 3), 289 PIN_FIELD_BASE(6, 6, 5, 0x00, 0x10, 12, 3), 290 291 PIN_FIELD_BASE(7, 7, 4, 0x00, 0x10, 24, 3), 292 PIN_FIELD_BASE(8, 8, 4, 0x00, 0x10, 28, 3), 293 PIN_FIELD_BASE(9, 9, 4, 0x00, 0x10, 15, 3), 294 PIN_FIELD_BASE(10, 10, 4, 0x00, 0x10, 9, 3), 295 296 PIN_FIELD_BASE(11, 11, 1, 0x00, 0x10, 0, 3), 297 PIN_FIELD_BASE(12, 12, 1, 0x20, 0x10, 3, 3), 298 PIN_FIELD_BASE(13, 13, 1, 0x00, 0x10, 3, 3), 299 PIN_FIELD_BASE(14, 14, 1, 0x00, 0x10, 6, 3), 300 301 PIN_FIELD_BASE(19, 19, 4, 0x00, 0x10, 21, 3), 302 PIN_FIELD_BASE(20, 20, 4, 0x00, 0x10, 12, 3), 303 304 PIN_FIELD_BASE(21, 21, 3, 0x10, 0x10, 21, 3), 305 PIN_FIELD_BASE(22, 22, 3, 0x20, 0x10, 9, 3), 306 PIN_FIELD_BASE(23, 23, 3, 0x20, 0x10, 0, 3), 307 PIN_FIELD_BASE(24, 24, 3, 0x10, 0x10, 27, 3), 308 PIN_FIELD_BASE(25, 25, 3, 0x20, 0x10, 3, 3), 309 PIN_FIELD_BASE(26, 26, 3, 0x20, 0x10, 6, 3), 310 PIN_FIELD_BASE(27, 27, 3, 0x10, 0x10, 24, 3), 311 PIN_FIELD_BASE(28, 28, 3, 0x20, 0x10, 15, 3), 312 PIN_FIELD_BASE(29, 29, 3, 0x20, 0x10, 18, 3), 313 PIN_FIELD_BASE(30, 30, 3, 0x20, 0x10, 21, 3), 314 PIN_FIELD_BASE(31, 31, 3, 0x20, 0x10, 12, 3), 315 PIN_FIELD_BASE(32, 32, 3, 0x20, 0x10, 24, 3), 316 PIN_FIELD_BASE(33, 33, 3, 0x30, 0x10, 6, 3), 317 PIN_FIELD_BASE(34, 34, 3, 0x30, 0x10, 3, 3), 318 PIN_FIELD_BASE(35, 35, 3, 0x20, 0x10, 27, 3), 319 PIN_FIELD_BASE(36, 36, 3, 0x30, 0x10, 0, 3), 320 PIN_FIELD_BASE(37, 37, 3, 0x30, 0x10, 9, 3), 321 PIN_FIELD_BASE(38, 38, 3, 0x10, 0x10, 3, 3), 322 PIN_FIELD_BASE(39, 39, 3, 0x10, 0x10, 0, 3), 323 PIN_FIELD_BASE(40, 40, 3, 0x00, 0x10, 0, 3), 324 PIN_FIELD_BASE(41, 41, 3, 0x00, 0x10, 3, 3), 325 PIN_FIELD_BASE(42, 42, 3, 0x00, 0x10, 27, 3), 326 PIN_FIELD_BASE(43, 43, 3, 0x00, 0x10, 24, 3), 327 PIN_FIELD_BASE(44, 44, 3, 0x00, 0x10, 21, 3), 328 PIN_FIELD_BASE(45, 45, 3, 0x00, 0x10, 18, 3), 329 PIN_FIELD_BASE(46, 46, 3, 0x00, 0x10, 15, 3), 330 PIN_FIELD_BASE(47, 47, 3, 0x00, 0x10, 12, 3), 331 PIN_FIELD_BASE(48, 48, 3, 0x00, 0x10, 9, 3), 332 PIN_FIELD_BASE(49, 49, 3, 0x00, 0x10, 6, 3), 333 PIN_FIELD_BASE(50, 50, 3, 0x10, 0x10, 15, 3), 334 PIN_FIELD_BASE(51, 51, 3, 0x10, 0x10, 6, 3), 335 PIN_FIELD_BASE(52, 52, 3, 0x10, 0x10, 9, 3), 336 PIN_FIELD_BASE(53, 53, 3, 0x10, 0x10, 12, 3), 337 PIN_FIELD_BASE(54, 54, 3, 0x10, 0x10, 18, 3), 338 339 PIN_FIELD_BASE(55, 55, 1, 0x10, 0x10, 12, 3), 340 PIN_FIELD_BASE(56, 56, 1, 0x10, 0x10, 15, 3), 341 PIN_FIELD_BASE(57, 57, 1, 0x10, 0x10, 9, 3), 342 PIN_FIELD_BASE(58, 58, 1, 0x00, 0x10, 12, 3), 343 PIN_FIELD_BASE(59, 59, 1, 0x00, 0x10, 15, 3), 344 PIN_FIELD_BASE(60, 60, 1, 0x00, 0x10, 18, 3), 345 PIN_FIELD_BASE(61, 61, 1, 0x00, 0x10, 9, 3), 346 PIN_FIELD_BASE(62, 62, 1, 0x00, 0x10, 21, 3), 347 PIN_FIELD_BASE(63, 63, 1, 0x20, 0x10, 0, 3), 348 PIN_FIELD_BASE(64, 64, 1, 0x00, 0x10, 24, 3), 349 PIN_FIELD_BASE(65, 65, 1, 0x00, 0x10, 27, 3), 350 PIN_FIELD_BASE(66, 66, 1, 0x10, 0x10, 0, 3), 351 PIN_FIELD_BASE(67, 67, 1, 0x10, 0x10, 3, 3), 352 PIN_FIELD_BASE(68, 68, 1, 0x10, 0x10, 6, 3), 353 354 PIN_FIELD_BASE(69, 69, 5, 0x00, 0x10, 3, 3), 355 PIN_FIELD_BASE(70, 70, 5, 0x00, 0x10, 6, 3), 356 357 PIN_FIELD_BASE(73, 73, 4, 0x10, 0x10, 0, 3), 358 PIN_FIELD_BASE(74, 74, 4, 0x00, 0x10, 3, 3), 359 PIN_FIELD_BASE(75, 75, 4, 0x10, 0x10, 3, 3), 360 PIN_FIELD_BASE(76, 76, 4, 0x00, 0x10, 27, 3), 361 PIN_FIELD_BASE(77, 77, 4, 0x00, 0x10, 6, 3), 362 PIN_FIELD_BASE(78, 78, 4, 0x00, 0x10, 0, 3), 363 PIN_FIELD_BASE(79, 79, 4, 0x10, 0x10, 6, 3), 364 365 PIN_FIELD_BASE(80, 80, 1, 0x10, 0x10, 24, 3), 366 PIN_FIELD_BASE(81, 81, 1, 0x10, 0x10, 27, 3), 367 PIN_FIELD_BASE(82, 82, 1, 0x10, 0x10, 18, 3), 368 PIN_FIELD_BASE(83, 83, 1, 0x10, 0x10, 21, 3), 369}; 370 371static const struct mtk_pin_field_calc mt7988_pin_pupd_range[] = { 372 PIN_FIELD_BASE(0, 0, 5, 0x50, 0x10, 7, 1), 373 PIN_FIELD_BASE(1, 1, 5, 0x50, 0x10, 8, 1), 374 PIN_FIELD_BASE(2, 2, 5, 0x50, 0x10, 5, 1), 375 PIN_FIELD_BASE(3, 3, 5, 0x50, 0x10, 6, 1), 376 PIN_FIELD_BASE(4, 4, 5, 0x50, 0x10, 0, 1), 377 PIN_FIELD_BASE(5, 5, 5, 0x50, 0x10, 3, 1), 378 PIN_FIELD_BASE(6, 6, 5, 0x50, 0x10, 4, 1), 379 380 PIN_FIELD_BASE(11, 11, 1, 0x60, 0x10, 0, 1), 381 PIN_FIELD_BASE(12, 12, 1, 0x60, 0x10, 18, 1), 382 383 PIN_FIELD_BASE(19, 19, 4, 0x50, 0x10, 2, 1), 384 PIN_FIELD_BASE(20, 20, 4, 0x50, 0x10, 1, 1), 385 386 PIN_FIELD_BASE(21, 21, 3, 0x70, 0x10, 17, 1), 387 PIN_FIELD_BASE(22, 22, 3, 0x70, 0x10, 23, 1), 388 PIN_FIELD_BASE(23, 23, 3, 0x70, 0x10, 20, 1), 389 PIN_FIELD_BASE(24, 24, 3, 0x70, 0x10, 19, 1), 390 PIN_FIELD_BASE(25, 25, 3, 0x70, 0x10, 21, 1), 391 PIN_FIELD_BASE(26, 26, 3, 0x70, 0x10, 22, 1), 392 PIN_FIELD_BASE(27, 27, 3, 0x70, 0x10, 18, 1), 393 PIN_FIELD_BASE(28, 28, 3, 0x70, 0x10, 25, 1), 394 PIN_FIELD_BASE(29, 29, 3, 0x70, 0x10, 26, 1), 395 PIN_FIELD_BASE(30, 30, 3, 0x70, 0x10, 27, 1), 396 PIN_FIELD_BASE(31, 31, 3, 0x70, 0x10, 24, 1), 397 PIN_FIELD_BASE(32, 32, 3, 0x70, 0x10, 28, 1), 398 PIN_FIELD_BASE(33, 33, 3, 0x80, 0x10, 0, 1), 399 PIN_FIELD_BASE(34, 34, 3, 0x70, 0x10, 31, 1), 400 PIN_FIELD_BASE(35, 35, 3, 0x70, 0x10, 29, 1), 401 PIN_FIELD_BASE(36, 36, 3, 0x70, 0x10, 30, 1), 402 PIN_FIELD_BASE(37, 37, 3, 0x80, 0x10, 1, 1), 403 PIN_FIELD_BASE(38, 38, 3, 0x70, 0x10, 11, 1), 404 PIN_FIELD_BASE(39, 39, 3, 0x70, 0x10, 10, 1), 405 PIN_FIELD_BASE(40, 40, 3, 0x70, 0x10, 0, 1), 406 PIN_FIELD_BASE(41, 41, 3, 0x70, 0x10, 1, 1), 407 PIN_FIELD_BASE(42, 42, 3, 0x70, 0x10, 9, 1), 408 PIN_FIELD_BASE(43, 43, 3, 0x70, 0x10, 8, 1), 409 PIN_FIELD_BASE(44, 44, 3, 0x70, 0x10, 7, 1), 410 PIN_FIELD_BASE(45, 45, 3, 0x70, 0x10, 6, 1), 411 PIN_FIELD_BASE(46, 46, 3, 0x70, 0x10, 5, 1), 412 PIN_FIELD_BASE(47, 47, 3, 0x70, 0x10, 4, 1), 413 PIN_FIELD_BASE(48, 48, 3, 0x70, 0x10, 3, 1), 414 PIN_FIELD_BASE(49, 49, 3, 0x70, 0x10, 2, 1), 415 PIN_FIELD_BASE(50, 50, 3, 0x70, 0x10, 15, 1), 416 PIN_FIELD_BASE(51, 51, 3, 0x70, 0x10, 12, 1), 417 PIN_FIELD_BASE(52, 52, 3, 0x70, 0x10, 13, 1), 418 PIN_FIELD_BASE(53, 53, 3, 0x70, 0x10, 14, 1), 419 PIN_FIELD_BASE(54, 54, 3, 0x70, 0x10, 16, 1), 420 421 PIN_FIELD_BASE(55, 55, 1, 0x60, 0x10, 12, 1), 422 PIN_FIELD_BASE(56, 56, 1, 0x60, 0x10, 13, 1), 423 PIN_FIELD_BASE(57, 57, 1, 0x60, 0x10, 11, 1), 424 PIN_FIELD_BASE(58, 58, 1, 0x60, 0x10, 2, 1), 425 PIN_FIELD_BASE(59, 59, 1, 0x60, 0x10, 3, 1), 426 PIN_FIELD_BASE(60, 60, 1, 0x60, 0x10, 4, 1), 427 PIN_FIELD_BASE(61, 61, 1, 0x60, 0x10, 1, 1), 428 PIN_FIELD_BASE(62, 62, 1, 0x60, 0x10, 5, 1), 429 PIN_FIELD_BASE(64, 64, 1, 0x60, 0x10, 6, 1), 430 PIN_FIELD_BASE(65, 65, 1, 0x60, 0x10, 7, 1), 431 PIN_FIELD_BASE(66, 66, 1, 0x60, 0x10, 8, 1), 432 PIN_FIELD_BASE(67, 67, 1, 0x60, 0x10, 9, 1), 433 PIN_FIELD_BASE(68, 68, 1, 0x60, 0x10, 10, 1), 434 435 PIN_FIELD_BASE(69, 69, 5, 0x50, 0x10, 1, 1), 436 PIN_FIELD_BASE(70, 70, 5, 0x50, 0x10, 2, 1), 437 438 PIN_FIELD_BASE(73, 73, 4, 0x50, 0x10, 3, 1), 439 PIN_FIELD_BASE(74, 74, 4, 0x50, 0x10, 0, 1), 440 441 PIN_FIELD_BASE(80, 80, 1, 0x60, 0x10, 16, 1), 442 PIN_FIELD_BASE(81, 81, 1, 0x60, 0x10, 17, 1), 443 PIN_FIELD_BASE(82, 82, 1, 0x60, 0x10, 14, 1), 444 PIN_FIELD_BASE(83, 83, 1, 0x60, 0x10, 15, 1), 445}; 446 447static const struct mtk_pin_field_calc mt7988_pin_r0_range[] = { 448 PIN_FIELD_BASE(0, 0, 5, 0x60, 0x10, 7, 1), 449 PIN_FIELD_BASE(1, 1, 5, 0x60, 0x10, 8, 1), 450 PIN_FIELD_BASE(2, 2, 5, 0x60, 0x10, 5, 1), 451 PIN_FIELD_BASE(3, 3, 5, 0x60, 0x10, 6, 1), 452 PIN_FIELD_BASE(4, 4, 5, 0x60, 0x10, 0, 1), 453 PIN_FIELD_BASE(5, 5, 5, 0x60, 0x10, 3, 1), 454 PIN_FIELD_BASE(6, 6, 5, 0x60, 0x10, 4, 1), 455 456 PIN_FIELD_BASE(11, 11, 1, 0x80, 0x10, 0, 1), 457 PIN_FIELD_BASE(12, 12, 1, 0x80, 0x10, 18, 1), 458 459 PIN_FIELD_BASE(19, 19, 4, 0x70, 0x10, 2, 1), 460 PIN_FIELD_BASE(20, 20, 4, 0x70, 0x10, 1, 1), 461 462 PIN_FIELD_BASE(21, 21, 3, 0x90, 0x10, 17, 1), 463 PIN_FIELD_BASE(22, 22, 3, 0x90, 0x10, 23, 1), 464 PIN_FIELD_BASE(23, 23, 3, 0x90, 0x10, 20, 1), 465 PIN_FIELD_BASE(24, 24, 3, 0x90, 0x10, 19, 1), 466 PIN_FIELD_BASE(25, 25, 3, 0x90, 0x10, 21, 1), 467 PIN_FIELD_BASE(26, 26, 3, 0x90, 0x10, 22, 1), 468 PIN_FIELD_BASE(27, 27, 3, 0x90, 0x10, 18, 1), 469 PIN_FIELD_BASE(28, 28, 3, 0x90, 0x10, 25, 1), 470 PIN_FIELD_BASE(29, 29, 3, 0x90, 0x10, 26, 1), 471 PIN_FIELD_BASE(30, 30, 3, 0x90, 0x10, 27, 1), 472 PIN_FIELD_BASE(31, 31, 3, 0x90, 0x10, 24, 1), 473 PIN_FIELD_BASE(32, 32, 3, 0x90, 0x10, 28, 1), 474 PIN_FIELD_BASE(33, 33, 3, 0xa0, 0x10, 0, 1), 475 PIN_FIELD_BASE(34, 34, 3, 0x90, 0x10, 31, 1), 476 PIN_FIELD_BASE(35, 35, 3, 0x90, 0x10, 29, 1), 477 PIN_FIELD_BASE(36, 36, 3, 0x90, 0x10, 30, 1), 478 PIN_FIELD_BASE(37, 37, 3, 0xa0, 0x10, 1, 1), 479 PIN_FIELD_BASE(38, 38, 3, 0x90, 0x10, 11, 1), 480 PIN_FIELD_BASE(39, 39, 3, 0x90, 0x10, 10, 1), 481 PIN_FIELD_BASE(40, 40, 3, 0x90, 0x10, 0, 1), 482 PIN_FIELD_BASE(41, 41, 3, 0x90, 0x10, 1, 1), 483 PIN_FIELD_BASE(42, 42, 3, 0x90, 0x10, 9, 1), 484 PIN_FIELD_BASE(43, 43, 3, 0x90, 0x10, 8, 1), 485 PIN_FIELD_BASE(44, 44, 3, 0x90, 0x10, 7, 1), 486 PIN_FIELD_BASE(45, 45, 3, 0x90, 0x10, 6, 1), 487 PIN_FIELD_BASE(46, 46, 3, 0x90, 0x10, 5, 1), 488 PIN_FIELD_BASE(47, 47, 3, 0x90, 0x10, 4, 1), 489 PIN_FIELD_BASE(48, 48, 3, 0x90, 0x10, 3, 1), 490 PIN_FIELD_BASE(49, 49, 3, 0x90, 0x10, 2, 1), 491 PIN_FIELD_BASE(50, 50, 3, 0x90, 0x10, 15, 1), 492 PIN_FIELD_BASE(51, 51, 3, 0x90, 0x10, 12, 1), 493 PIN_FIELD_BASE(52, 52, 3, 0x90, 0x10, 13, 1), 494 PIN_FIELD_BASE(53, 53, 3, 0x90, 0x10, 14, 1), 495 PIN_FIELD_BASE(54, 54, 3, 0x90, 0x10, 16, 1), 496 497 PIN_FIELD_BASE(55, 55, 1, 0x80, 0x10, 12, 1), 498 PIN_FIELD_BASE(56, 56, 1, 0x80, 0x10, 13, 1), 499 PIN_FIELD_BASE(57, 57, 1, 0x80, 0x10, 11, 1), 500 PIN_FIELD_BASE(58, 58, 1, 0x80, 0x10, 2, 1), 501 PIN_FIELD_BASE(59, 59, 1, 0x80, 0x10, 3, 1), 502 PIN_FIELD_BASE(60, 60, 1, 0x80, 0x10, 4, 1), 503 PIN_FIELD_BASE(61, 61, 1, 0x80, 0x10, 1, 1), 504 PIN_FIELD_BASE(62, 62, 1, 0x80, 0x10, 5, 1), 505 PIN_FIELD_BASE(64, 64, 1, 0x80, 0x10, 6, 1), 506 PIN_FIELD_BASE(65, 65, 1, 0x80, 0x10, 7, 1), 507 PIN_FIELD_BASE(66, 66, 1, 0x80, 0x10, 8, 1), 508 PIN_FIELD_BASE(67, 67, 1, 0x80, 0x10, 9, 1), 509 PIN_FIELD_BASE(68, 68, 1, 0x80, 0x10, 10, 1), 510 511 PIN_FIELD_BASE(69, 69, 5, 0x60, 0x10, 1, 1), 512 PIN_FIELD_BASE(70, 70, 5, 0x60, 0x10, 2, 1), 513 514 PIN_FIELD_BASE(73, 73, 4, 0x70, 0x10, 3, 1), 515 PIN_FIELD_BASE(74, 74, 4, 0x70, 0x10, 0, 1), 516 517 PIN_FIELD_BASE(80, 80, 1, 0x80, 0x10, 16, 1), 518 PIN_FIELD_BASE(81, 81, 1, 0x80, 0x10, 17, 1), 519 PIN_FIELD_BASE(82, 82, 1, 0x80, 0x10, 14, 1), 520 PIN_FIELD_BASE(83, 83, 1, 0x80, 0x10, 15, 1), 521}; 522 523static const struct mtk_pin_field_calc mt7988_pin_r1_range[] = { 524 PIN_FIELD_BASE(0, 0, 5, 0x70, 0x10, 7, 1), 525 PIN_FIELD_BASE(1, 1, 5, 0x70, 0x10, 8, 1), 526 PIN_FIELD_BASE(2, 2, 5, 0x70, 0x10, 5, 1), 527 PIN_FIELD_BASE(3, 3, 5, 0x70, 0x10, 6, 1), 528 PIN_FIELD_BASE(4, 4, 5, 0x70, 0x10, 0, 1), 529 PIN_FIELD_BASE(5, 5, 5, 0x70, 0x10, 3, 1), 530 PIN_FIELD_BASE(6, 6, 5, 0x70, 0x10, 4, 1), 531 532 PIN_FIELD_BASE(11, 11, 1, 0x90, 0x10, 0, 1), 533 PIN_FIELD_BASE(12, 12, 1, 0x90, 0x10, 18, 1), 534 535 PIN_FIELD_BASE(19, 19, 4, 0x80, 0x10, 2, 1), 536 PIN_FIELD_BASE(20, 20, 4, 0x80, 0x10, 1, 1), 537 538 PIN_FIELD_BASE(21, 21, 3, 0xb0, 0x10, 17, 1), 539 PIN_FIELD_BASE(22, 22, 3, 0xb0, 0x10, 23, 1), 540 PIN_FIELD_BASE(23, 23, 3, 0xb0, 0x10, 20, 1), 541 PIN_FIELD_BASE(24, 24, 3, 0xb0, 0x10, 19, 1), 542 PIN_FIELD_BASE(25, 25, 3, 0xb0, 0x10, 21, 1), 543 PIN_FIELD_BASE(26, 26, 3, 0xb0, 0x10, 22, 1), 544 PIN_FIELD_BASE(27, 27, 3, 0xb0, 0x10, 18, 1), 545 PIN_FIELD_BASE(28, 28, 3, 0xb0, 0x10, 25, 1), 546 PIN_FIELD_BASE(29, 29, 3, 0xb0, 0x10, 26, 1), 547 PIN_FIELD_BASE(30, 30, 3, 0xb0, 0x10, 27, 1), 548 PIN_FIELD_BASE(31, 31, 3, 0xb0, 0x10, 24, 1), 549 PIN_FIELD_BASE(32, 32, 3, 0xb0, 0x10, 28, 1), 550 PIN_FIELD_BASE(33, 33, 3, 0xc0, 0x10, 0, 1), 551 PIN_FIELD_BASE(34, 34, 3, 0xb0, 0x10, 31, 1), 552 PIN_FIELD_BASE(35, 35, 3, 0xb0, 0x10, 29, 1), 553 PIN_FIELD_BASE(36, 36, 3, 0xb0, 0x10, 30, 1), 554 PIN_FIELD_BASE(37, 37, 3, 0xc0, 0x10, 1, 1), 555 PIN_FIELD_BASE(38, 38, 3, 0xb0, 0x10, 11, 1), 556 PIN_FIELD_BASE(39, 39, 3, 0xb0, 0x10, 10, 1), 557 PIN_FIELD_BASE(40, 40, 3, 0xb0, 0x10, 0, 1), 558 PIN_FIELD_BASE(41, 41, 3, 0xb0, 0x10, 1, 1), 559 PIN_FIELD_BASE(42, 42, 3, 0xb0, 0x10, 9, 1), 560 PIN_FIELD_BASE(43, 43, 3, 0xb0, 0x10, 8, 1), 561 PIN_FIELD_BASE(44, 44, 3, 0xb0, 0x10, 7, 1), 562 PIN_FIELD_BASE(45, 45, 3, 0xb0, 0x10, 6, 1), 563 PIN_FIELD_BASE(46, 46, 3, 0xb0, 0x10, 5, 1), 564 PIN_FIELD_BASE(47, 47, 3, 0xb0, 0x10, 4, 1), 565 PIN_FIELD_BASE(48, 48, 3, 0xb0, 0x10, 3, 1), 566 PIN_FIELD_BASE(49, 49, 3, 0xb0, 0x10, 2, 1), 567 PIN_FIELD_BASE(50, 50, 3, 0xb0, 0x10, 15, 1), 568 PIN_FIELD_BASE(51, 51, 3, 0xb0, 0x10, 12, 1), 569 PIN_FIELD_BASE(52, 52, 3, 0xb0, 0x10, 13, 1), 570 PIN_FIELD_BASE(53, 53, 3, 0xb0, 0x10, 14, 1), 571 PIN_FIELD_BASE(54, 54, 3, 0xb0, 0x10, 16, 1), 572 573 PIN_FIELD_BASE(55, 55, 1, 0x90, 0x10, 12, 1), 574 PIN_FIELD_BASE(56, 56, 1, 0x90, 0x10, 13, 1), 575 PIN_FIELD_BASE(57, 57, 1, 0x90, 0x10, 11, 1), 576 PIN_FIELD_BASE(58, 58, 1, 0x90, 0x10, 2, 1), 577 PIN_FIELD_BASE(59, 59, 1, 0x90, 0x10, 3, 1), 578 PIN_FIELD_BASE(60, 60, 1, 0x90, 0x10, 4, 1), 579 PIN_FIELD_BASE(61, 61, 1, 0x90, 0x10, 1, 1), 580 PIN_FIELD_BASE(62, 62, 1, 0x90, 0x10, 5, 1), 581 PIN_FIELD_BASE(64, 64, 1, 0x90, 0x10, 6, 1), 582 PIN_FIELD_BASE(65, 65, 1, 0x90, 0x10, 7, 1), 583 PIN_FIELD_BASE(66, 66, 1, 0x90, 0x10, 8, 1), 584 PIN_FIELD_BASE(67, 67, 1, 0x90, 0x10, 9, 1), 585 PIN_FIELD_BASE(68, 68, 1, 0x90, 0x10, 10, 1), 586 587 PIN_FIELD_BASE(69, 69, 5, 0x70, 0x10, 1, 1), 588 PIN_FIELD_BASE(70, 70, 5, 0x70, 0x10, 2, 1), 589 590 PIN_FIELD_BASE(73, 73, 4, 0x80, 0x10, 3, 1), 591 PIN_FIELD_BASE(74, 74, 4, 0x80, 0x10, 0, 1), 592 593 PIN_FIELD_BASE(80, 80, 1, 0x90, 0x10, 16, 1), 594 PIN_FIELD_BASE(81, 81, 1, 0x90, 0x10, 17, 1), 595 PIN_FIELD_BASE(82, 82, 1, 0x90, 0x10, 14, 1), 596 PIN_FIELD_BASE(83, 83, 1, 0x90, 0x10, 15, 1), 597}; 598 599static const unsigned int mt7988_pull_type[] = { 600 MTK_PULL_PUPD_R1R0_TYPE,/*0*/ MTK_PULL_PUPD_R1R0_TYPE,/*1*/ 601 MTK_PULL_PUPD_R1R0_TYPE,/*2*/ MTK_PULL_PUPD_R1R0_TYPE,/*3*/ 602 MTK_PULL_PUPD_R1R0_TYPE,/*4*/ MTK_PULL_PUPD_R1R0_TYPE,/*5*/ 603 MTK_PULL_PUPD_R1R0_TYPE,/*6*/ MTK_PULL_PU_PD_TYPE, /*7*/ 604 MTK_PULL_PU_PD_TYPE, /*8*/ MTK_PULL_PU_PD_TYPE, /*9*/ 605 MTK_PULL_PU_PD_TYPE, /*10*/ MTK_PULL_PUPD_R1R0_TYPE,/*11*/ 606 MTK_PULL_PUPD_R1R0_TYPE,/*12*/ MTK_PULL_PU_PD_TYPE, /*13*/ 607 MTK_PULL_PU_PD_TYPE, /*14*/ MTK_PULL_PD_TYPE, /*15*/ 608 MTK_PULL_PD_TYPE, /*16*/ MTK_PULL_PD_TYPE, /*17*/ 609 MTK_PULL_PD_TYPE, /*18*/ MTK_PULL_PUPD_R1R0_TYPE,/*19*/ 610 MTK_PULL_PUPD_R1R0_TYPE,/*20*/ MTK_PULL_PUPD_R1R0_TYPE,/*21*/ 611 MTK_PULL_PUPD_R1R0_TYPE,/*22*/ MTK_PULL_PUPD_R1R0_TYPE,/*23*/ 612 MTK_PULL_PUPD_R1R0_TYPE,/*24*/ MTK_PULL_PUPD_R1R0_TYPE,/*25*/ 613 MTK_PULL_PUPD_R1R0_TYPE,/*26*/ MTK_PULL_PUPD_R1R0_TYPE,/*27*/ 614 MTK_PULL_PUPD_R1R0_TYPE,/*28*/ MTK_PULL_PUPD_R1R0_TYPE,/*29*/ 615 MTK_PULL_PUPD_R1R0_TYPE,/*30*/ MTK_PULL_PUPD_R1R0_TYPE,/*31*/ 616 MTK_PULL_PUPD_R1R0_TYPE,/*32*/ MTK_PULL_PUPD_R1R0_TYPE,/*33*/ 617 MTK_PULL_PUPD_R1R0_TYPE,/*34*/ MTK_PULL_PUPD_R1R0_TYPE,/*35*/ 618 MTK_PULL_PUPD_R1R0_TYPE,/*36*/ MTK_PULL_PUPD_R1R0_TYPE,/*37*/ 619 MTK_PULL_PUPD_R1R0_TYPE,/*38*/ MTK_PULL_PUPD_R1R0_TYPE,/*39*/ 620 MTK_PULL_PUPD_R1R0_TYPE,/*40*/ MTK_PULL_PUPD_R1R0_TYPE,/*41*/ 621 MTK_PULL_PUPD_R1R0_TYPE,/*42*/ MTK_PULL_PUPD_R1R0_TYPE,/*43*/ 622 MTK_PULL_PUPD_R1R0_TYPE,/*44*/ MTK_PULL_PUPD_R1R0_TYPE,/*45*/ 623 MTK_PULL_PUPD_R1R0_TYPE,/*46*/ MTK_PULL_PUPD_R1R0_TYPE,/*47*/ 624 MTK_PULL_PUPD_R1R0_TYPE,/*48*/ MTK_PULL_PUPD_R1R0_TYPE,/*49*/ 625 MTK_PULL_PUPD_R1R0_TYPE,/*50*/ MTK_PULL_PUPD_R1R0_TYPE,/*51*/ 626 MTK_PULL_PUPD_R1R0_TYPE,/*52*/ MTK_PULL_PUPD_R1R0_TYPE,/*53*/ 627 MTK_PULL_PUPD_R1R0_TYPE,/*54*/ MTK_PULL_PUPD_R1R0_TYPE,/*55*/ 628 MTK_PULL_PUPD_R1R0_TYPE,/*56*/ MTK_PULL_PUPD_R1R0_TYPE,/*57*/ 629 MTK_PULL_PUPD_R1R0_TYPE,/*58*/ MTK_PULL_PUPD_R1R0_TYPE,/*59*/ 630 MTK_PULL_PUPD_R1R0_TYPE,/*60*/ MTK_PULL_PUPD_R1R0_TYPE,/*61*/ 631 MTK_PULL_PUPD_R1R0_TYPE,/*62*/ MTK_PULL_PU_PD_TYPE, /*63*/ 632 MTK_PULL_PUPD_R1R0_TYPE,/*64*/ MTK_PULL_PUPD_R1R0_TYPE,/*65*/ 633 MTK_PULL_PUPD_R1R0_TYPE,/*66*/ MTK_PULL_PUPD_R1R0_TYPE,/*67*/ 634 MTK_PULL_PUPD_R1R0_TYPE,/*68*/ MTK_PULL_PUPD_R1R0_TYPE,/*69*/ 635 MTK_PULL_PUPD_R1R0_TYPE,/*70*/ MTK_PULL_PD_TYPE, /*71*/ 636 MTK_PULL_PD_TYPE, /*72*/ MTK_PULL_PUPD_R1R0_TYPE,/*73*/ 637 MTK_PULL_PUPD_R1R0_TYPE,/*74*/ MTK_PULL_PU_PD_TYPE, /*75*/ 638 MTK_PULL_PU_PD_TYPE, /*76*/ MTK_PULL_PU_PD_TYPE, /*77*/ 639 MTK_PULL_PU_PD_TYPE, /*78*/ MTK_PULL_PU_PD_TYPE, /*79*/ 640 MTK_PULL_PUPD_R1R0_TYPE,/*80*/ MTK_PULL_PUPD_R1R0_TYPE,/*81*/ 641 MTK_PULL_PUPD_R1R0_TYPE,/*82*/ MTK_PULL_PUPD_R1R0_TYPE,/*83*/ 642}; 643 644static const struct mtk_pin_reg_calc mt7988_reg_cals[] = { 645 [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7988_pin_mode_range), 646 [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7988_pin_dir_range), 647 [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7988_pin_di_range), 648 [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7988_pin_do_range), 649 [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7988_pin_smt_range), 650 [PINCTRL_PIN_REG_IES] = MTK_RANGE(mt7988_pin_ies_range), 651 [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7988_pin_pu_range), 652 [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7988_pin_pd_range), 653 [PINCTRL_PIN_REG_DRV] = MTK_RANGE(mt7988_pin_drv_range), 654 [PINCTRL_PIN_REG_PUPD] = MTK_RANGE(mt7988_pin_pupd_range), 655 [PINCTRL_PIN_REG_R0] = MTK_RANGE(mt7988_pin_r0_range), 656 [PINCTRL_PIN_REG_R1] = MTK_RANGE(mt7988_pin_r1_range), 657}; 658 659static const struct mtk_pin_desc mt7988_pins[] = { 660 MT7988_PIN(0, "UART2_RXD"), 661 MT7988_PIN(1, "UART2_TXD"), 662 MT7988_PIN(2, "UART2_CTS"), 663 MT7988_PIN(3, "UART2_RTS"), 664 MT7988_PIN(4, "GPIO_A"), 665 MT7988_PIN(5, "SMI_0_MDC"), 666 MT7988_PIN(6, "SMI_0_MDIO"), 667 MT7988_PIN(7, "PCIE30_2L_0_WAKE_N"), 668 MT7988_PIN(8, "PCIE30_2L_0_CLKREQ_N"), 669 MT7988_PIN(9, "PCIE30_1L_1_WAKE_N"), 670 MT7988_PIN(10, "PCIE30_1L_1_CLKREQ_N"), 671 MT7988_PIN(11, "GPIO_P"), 672 MT7988_PIN(12, "WATCHDOG"), 673 MT7988_PIN(13, "GPIO_RESET"), 674 MT7988_PIN(14, "GPIO_WPS"), 675 MT7988_PIN(15, "PMIC_I2C_SCL"), 676 MT7988_PIN(16, "PMIC_I2C_SDA"), 677 MT7988_PIN(17, "I2C_1_SCL"), 678 MT7988_PIN(18, "I2C_1_SDA"), 679 MT7988_PIN(19, "PCIE30_2L_0_PRESET_N"), 680 MT7988_PIN(20, "PCIE30_1L_1_PRESET_N"), 681 MT7988_PIN(21, "PWMD1"), 682 MT7988_PIN(22, "SPI0_WP"), 683 MT7988_PIN(23, "SPI0_HOLD"), 684 MT7988_PIN(24, "SPI0_CSB"), 685 MT7988_PIN(25, "SPI0_MISO"), 686 MT7988_PIN(26, "SPI0_MOSI"), 687 MT7988_PIN(27, "SPI0_CLK"), 688 MT7988_PIN(28, "SPI1_CSB"), 689 MT7988_PIN(29, "SPI1_MISO"), 690 MT7988_PIN(30, "SPI1_MOSI"), 691 MT7988_PIN(31, "SPI1_CLK"), 692 MT7988_PIN(32, "SPI2_CLK"), 693 MT7988_PIN(33, "SPI2_MOSI"), 694 MT7988_PIN(34, "SPI2_MISO"), 695 MT7988_PIN(35, "SPI2_CSB"), 696 MT7988_PIN(36, "SPI2_HOLD"), 697 MT7988_PIN(37, "SPI2_WP"), 698 MT7988_PIN(38, "EMMC_RSTB"), 699 MT7988_PIN(39, "EMMC_DSL"), 700 MT7988_PIN(40, "EMMC_CK"), 701 MT7988_PIN(41, "EMMC_CMD"), 702 MT7988_PIN(42, "EMMC_DATA_7"), 703 MT7988_PIN(43, "EMMC_DATA_6"), 704 MT7988_PIN(44, "EMMC_DATA_5"), 705 MT7988_PIN(45, "EMMC_DATA_4"), 706 MT7988_PIN(46, "EMMC_DATA_3"), 707 MT7988_PIN(47, "EMMC_DATA_2"), 708 MT7988_PIN(48, "EMMC_DATA_1"), 709 MT7988_PIN(49, "EMMC_DATA_0"), 710 MT7988_PIN(50, "PCM_FS_I2S_LRCK"), 711 MT7988_PIN(51, "PCM_CLK_I2S_BCLK"), 712 MT7988_PIN(52, "PCM_DRX_I2S_DIN"), 713 MT7988_PIN(53, "PCM_DTX_I2S_DOUT"), 714 MT7988_PIN(54, "PCM_MCK_I2S_MCLK"), 715 MT7988_PIN(55, "UART0_RXD"), 716 MT7988_PIN(56, "UART0_TXD"), 717 MT7988_PIN(57, "PWMD0"), 718 MT7988_PIN(58, "JTAG_JTDI"), 719 MT7988_PIN(59, "JTAG_JTDO"), 720 MT7988_PIN(60, "JTAG_JTMS"), 721 MT7988_PIN(61, "JTAG_JTCLK"), 722 MT7988_PIN(62, "JTAG_JTRST_N"), 723 MT7988_PIN(63, "USB_DRV_VBUS_P1"), 724 MT7988_PIN(64, "LED_A"), 725 MT7988_PIN(65, "LED_B"), 726 MT7988_PIN(66, "LED_C"), 727 MT7988_PIN(67, "LED_D"), 728 MT7988_PIN(68, "LED_E"), 729 MT7988_PIN(69, "GPIO_B"), 730 MT7988_PIN(70, "GPIO_C"), 731 MT7988_PIN(71, "I2C_2_SCL"), 732 MT7988_PIN(72, "I2C_2_SDA"), 733 MT7988_PIN(73, "PCIE30_2L_1_PRESET_N"), 734 MT7988_PIN(74, "PCIE30_1L_0_PRESET_N"), 735 MT7988_PIN(75, "PCIE30_2L_1_WAKE_N"), 736 MT7988_PIN(76, "PCIE30_2L_1_CLKREQ_N"), 737 MT7988_PIN(77, "PCIE30_1L_0_WAKE_N"), 738 MT7988_PIN(78, "PCIE30_1L_0_CLKREQ_N"), 739 MT7988_PIN(79, "USB_DRV_VBUS_P0"), 740 MT7988_PIN(80, "UART1_RXD"), 741 MT7988_PIN(81, "UART1_TXD"), 742 MT7988_PIN(82, "UART1_CTS"), 743 MT7988_PIN(83, "UART1_RTS"), 744}; 745 746/* jtag */ 747static const int mt7988_tops_jtag0_0_pins[] = { 0, 1, 2, 3, 4 }; 748static int mt7988_tops_jtag0_0_funcs[] = { 2, 2, 2, 2, 2 }; 749 750static const int mt7988_wo0_jtag_pins[] = { 50, 51, 52, 53, 54 }; 751static int mt7988_wo0_jtag_funcs[] = { 3, 3, 3, 3, 3 }; 752 753static const int mt7988_wo1_jtag_pins[] = { 50, 51, 52, 53, 54 }; 754static int mt7988_wo1_jtag_funcs[] = { 4, 4, 4, 4, 4 }; 755 756static const int mt7988_wo2_jtag_pins[] = { 50, 51, 52, 53, 54 }; 757static int mt7988_wo2_jtag_funcs[] = { 5, 5, 5, 5, 5 }; 758 759static const int mt7988_jtag_pins[] = { 58, 59, 60, 61, 62 }; 760static int mt7988_jtag_funcs[] = { 1, 1, 1, 1, 1 }; 761 762static const int mt7988_tops_jtag0_1_pins[] = { 58, 59, 60, 61, 62 }; 763static int mt7988_tops_jtag0_1_funcs[] = { 4, 4, 4, 4, 4 }; 764 765/* int_usxgmii */ 766static const int mt7988_int_usxgmii_pins[] = { 2, 3 }; 767static int mt7988_int_usxgmii_funcs[] = { 3, 3 }; 768 769/* pwm */ 770static const int mt7988_pwm0_pins[] = { 57 }; 771static int mt7988_pwm0_funcs[] = { 1 }; 772 773static const int mt7988_pwm1_pins[] = { 21 }; 774static int mt7988_pwm1_funcs[] = { 1 }; 775 776static const int mt7988_pwm2_pins[] = { 80 }; 777static int mt7988_pwm2_funcs[] = { 2 }; 778 779static const int mt7988_pwm2_0_pins[] = { 58 }; 780static int mt7988_pwm2_0_funcs[] = { 5 }; 781 782static const int mt7988_pwm3_pins[] = { 81 }; 783static int mt7988_pwm3_funcs[] = { 2 }; 784 785static const int mt7988_pwm3_0_pins[] = { 59 }; 786static int mt7988_pwm3_0_funcs[] = { 5 }; 787 788static const int mt7988_pwm4_pins[] = { 82 }; 789static int mt7988_pwm4_funcs[] = { 2 }; 790 791static const int mt7988_pwm4_0_pins[] = { 60 }; 792static int mt7988_pwm4_0_funcs[] = { 5 }; 793 794static const int mt7988_pwm5_pins[] = { 83 }; 795static int mt7988_pwm5_funcs[] = { 2 }; 796 797static const int mt7988_pwm5_0_pins[] = { 61 }; 798static int mt7988_pwm5_0_funcs[] = { 5 }; 799 800static const int mt7988_pwm6_pins[] = { 69 }; 801static int mt7988_pwm6_funcs[] = { 3 }; 802 803static const int mt7988_pwm6_0_pins[] = { 62 }; 804static int mt7988_pwm6_0_funcs[] = { 5 }; 805 806static const int mt7988_pwm7_pins[] = { 70 }; 807static int mt7988_pwm7_funcs[] = { 3 }; 808 809static const int mt7988_pwm7_0_pins[] = { 4 }; 810static int mt7988_pwm7_0_funcs[] = { 3 }; 811 812/* dfd */ 813static const int mt7988_dfd_pins[] = { 0, 1, 2, 3, 4 }; 814static int mt7988_dfd_funcs[] = { 4, 4, 4, 4, 4 }; 815 816/* i2c */ 817static const int mt7988_xfi_phy0_i2c0_pins[] = { 0, 1 }; 818static int mt7988_xfi_phy0_i2c0_funcs[] = { 5, 5 }; 819 820static const int mt7988_xfi_phy1_i2c0_pins[] = { 0, 1 }; 821static int mt7988_xfi_phy1_i2c0_funcs[] = { 6, 6 }; 822 823static const int mt7988_xfi_phy_pll_i2c0_pins[] = { 3, 4 }; 824static int mt7988_xfi_phy_pll_i2c0_funcs[] = { 5, 5 }; 825 826static const int mt7988_xfi_phy_pll_i2c1_pins[] = { 3, 4 }; 827static int mt7988_xfi_phy_pll_i2c1_funcs[] = { 6, 6 }; 828 829static const int mt7988_i2c0_0_pins[] = { 5, 6 }; 830static int mt7988_i2c0_0_funcs[] = { 2, 2 }; 831 832static const int mt7988_i2c1_sfp_pins[] = { 5, 6 }; 833static int mt7988_i2c1_sfp_funcs[] = { 4, 4 }; 834 835static const int mt7988_xfi_pextp_phy0_i2c_pins[] = { 5, 6 }; 836static int mt7988_xfi_pextp_phy0_i2c_funcs[] = { 5, 5 }; 837 838static const int mt7988_xfi_pextp_phy1_i2c_pins[] = { 5, 6 }; 839static int mt7988_xfi_pextp_phy1_i2c_funcs[] = { 6, 6 }; 840 841static const int mt7988_i2c0_1_pins[] = { 15, 16 }; 842static int mt7988_i2c0_1_funcs[] = { 1, 1 }; 843 844static const int mt7988_u30_phy_i2c0_pins[] = { 15, 16 }; 845static int mt7988_u30_phy_i2c0_funcs[] = { 2, 2 }; 846 847static const int mt7988_u32_phy_i2c0_pins[] = { 15, 16 }; 848static int mt7988_u32_phy_i2c0_funcs[] = { 3, 3 }; 849 850static const int mt7988_xfi_phy0_i2c1_pins[] = { 15, 16 }; 851static int mt7988_xfi_phy0_i2c1_funcs[] = { 5, 5 }; 852 853static const int mt7988_xfi_phy1_i2c1_pins[] = { 15, 16 }; 854static int mt7988_xfi_phy1_i2c1_funcs[] = { 6, 6 }; 855 856static const int mt7988_xfi_phy_pll_i2c2_pins[] = { 15, 16 }; 857static int mt7988_xfi_phy_pll_i2c2_funcs[] = { 7, 7 }; 858 859static const int mt7988_i2c1_0_pins[] = { 17, 18 }; 860static int mt7988_i2c1_0_funcs[] = { 1, 1 }; 861 862static const int mt7988_u30_phy_i2c1_pins[] = { 17, 18 }; 863static int mt7988_u30_phy_i2c1_funcs[] = { 2, 2 }; 864 865static const int mt7988_u32_phy_i2c1_pins[] = { 17, 18 }; 866static int mt7988_u32_phy_i2c1_funcs[] = { 3, 3 }; 867 868static const int mt7988_xfi_phy_pll_i2c3_pins[] = { 17, 18 }; 869static int mt7988_xfi_phy_pll_i2c3_funcs[] = { 4, 4 }; 870 871static const int mt7988_sgmii0_i2c_pins[] = { 17, 18 }; 872static int mt7988_sgmii0_i2c_funcs[] = { 5, 5 }; 873 874static const int mt7988_sgmii1_i2c_pins[] = { 17, 18 }; 875static int mt7988_sgmii1_i2c_funcs[] = { 6, 6 }; 876 877static const int mt7988_i2c1_2_pins[] = { 69, 70 }; 878static int mt7988_i2c1_2_funcs[] = { 2, 2 }; 879 880static const int mt7988_i2c2_0_pins[] = { 69, 70 }; 881static int mt7988_i2c2_0_funcs[] = { 4, 4 }; 882 883static const int mt7988_i2c2_1_pins[] = { 71, 72 }; 884static int mt7988_i2c2_1_funcs[] = { 1, 1 }; 885 886/* eth */ 887static const int mt7988_mdc_mdio0_pins[] = { 5, 6 }; 888static int mt7988_mdc_mdio0_funcs[] = { 1, 1 }; 889 890static const int mt7988_2p5g_ext_mdio_pins[] = { 28, 29 }; 891static int mt7988_2p5g_ext_mdio_funcs[] = { 6, 6 }; 892 893static const int mt7988_gbe_ext_mdio_pins[] = { 30, 31 }; 894static int mt7988_gbe_ext_mdio_funcs[] = { 6, 6 }; 895 896static const int mt7988_mdc_mdio1_pins[] = { 69, 70 }; 897static int mt7988_mdc_mdio1_funcs[] = { 1, 1 }; 898 899/* pcie */ 900static const int mt7988_pcie_wake_n0_0_pins[] = { 7 }; 901static int mt7988_pcie_wake_n0_0_funcs[] = { 1 }; 902 903static const int mt7988_pcie_clk_req_n0_0_pins[] = { 8 }; 904static int mt7988_pcie_clk_req_n0_0_funcs[] = { 1 }; 905 906static const int mt7988_pcie_wake_n3_0_pins[] = { 9 }; 907static int mt7988_pcie_wake_n3_0_funcs[] = { 1 }; 908 909static const int mt7988_pcie_clk_req_n3_pins[] = { 10 }; 910static int mt7988_pcie_clk_req_n3_funcs[] = { 1 }; 911 912static const int mt7988_pcie_clk_req_n0_1_pins[] = { 10 }; 913static int mt7988_pcie_clk_req_n0_1_funcs[] = { 2 }; 914 915static const int mt7988_pcie_p0_phy_i2c_pins[] = { 7, 8 }; 916static int mt7988_pcie_p0_phy_i2c_funcs[] = { 3, 3 }; 917 918static const int mt7988_pcie_p1_phy_i2c_pins[] = { 7, 8 }; 919static int mt7988_pcie_p1_phy_i2c_funcs[] = { 4, 4 }; 920 921static const int mt7988_pcie_p3_phy_i2c_pins[] = { 9, 10 }; 922static int mt7988_pcie_p3_phy_i2c_funcs[] = { 4, 4 }; 923 924static const int mt7988_pcie_p2_phy_i2c_pins[] = { 7, 8 }; 925static int mt7988_pcie_p2_phy_i2c_funcs[] = { 5, 5 }; 926 927static const int mt7988_ckm_phy_i2c_pins[] = { 9, 10 }; 928static int mt7988_ckm_phy_i2c_funcs[] = { 5, 5 }; 929 930static const int mt7988_pcie_wake_n0_1_pins[] = { 13 }; 931static int mt7988_pcie_wake_n0_1_funcs[] = { 2 }; 932 933static const int mt7988_pcie_wake_n3_1_pins[] = { 14 }; 934static int mt7988_pcie_wake_n3_1_funcs[] = { 2 }; 935 936static const int mt7988_pcie_2l_0_pereset_pins[] = { 19 }; 937static int mt7988_pcie_2l_0_pereset_funcs[] = { 1 }; 938 939static const int mt7988_pcie_1l_1_pereset_pins[] = { 20 }; 940static int mt7988_pcie_1l_1_pereset_funcs[] = { 1 }; 941 942static const int mt7988_pcie_clk_req_n2_1_pins[] = { 63 }; 943static int mt7988_pcie_clk_req_n2_1_funcs[] = { 2 }; 944 945static const int mt7988_pcie_2l_1_pereset_pins[] = { 73 }; 946static int mt7988_pcie_2l_1_pereset_funcs[] = { 1 }; 947 948static const int mt7988_pcie_1l_0_pereset_pins[] = { 74 }; 949static int mt7988_pcie_1l_0_pereset_funcs[] = { 1 }; 950 951static const int mt7988_pcie_wake_n1_0_pins[] = { 75 }; 952static int mt7988_pcie_wake_n1_0_funcs[] = { 1 }; 953 954static const int mt7988_pcie_clk_req_n1_pins[] = { 76 }; 955static int mt7988_pcie_clk_req_n1_funcs[] = { 1 }; 956 957static const int mt7988_pcie_wake_n2_0_pins[] = { 77 }; 958static int mt7988_pcie_wake_n2_0_funcs[] = { 1 }; 959 960static const int mt7988_pcie_clk_req_n2_0_pins[] = { 78 }; 961static int mt7988_pcie_clk_req_n2_0_funcs[] = { 1 }; 962 963static const int mt7988_pcie_wake_n2_1_pins[] = { 79 }; 964static int mt7988_pcie_wake_n2_1_funcs[] = { 2 }; 965 966/* pmic */ 967static const int mt7988_pmic_pins[] = { 11 }; 968static int mt7988_pmic_funcs[] = { 1 }; 969 970/* watchdog */ 971static const int mt7988_watchdog_pins[] = { 12 }; 972static int mt7988_watchdog_funcs[] = { 1 }; 973 974/* spi */ 975static const int mt7988_spi0_wp_hold_pins[] = { 22, 23 }; 976static int mt7988_spi0_wp_hold_funcs[] = { 1, 1 }; 977 978static const int mt7988_spi0_pins[] = { 24, 25, 26, 27 }; 979static int mt7988_spi0_funcs[] = { 1, 1, 1, 1 }; 980 981static const int mt7988_spi1_pins[] = { 28, 29, 30, 31 }; 982static int mt7988_spi1_funcs[] = { 1, 1, 1, 1 }; 983 984static const int mt7988_spi2_pins[] = { 32, 33, 34, 35 }; 985static int mt7988_spi2_funcs[] = { 1, 1, 1, 1 }; 986 987static const int mt7988_spi2_wp_hold_pins[] = { 36, 37 }; 988static int mt7988_spi2_wp_hold_funcs[] = { 1, 1 }; 989 990/* flash */ 991static const int mt7988_snfi_pins[] = { 22, 23, 24, 25, 26, 27 }; 992static int mt7988_snfi_funcs[] = { 2, 2, 2, 2, 2, 2 }; 993 994static const int mt7988_emmc_45_pins[] = { 995 21, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37 996}; 997static int mt7988_emmc_45_funcs[] = { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5 }; 998 999static const int mt7988_sdcard_pins[] = { 32, 33, 34, 35, 36, 37 }; 1000static int mt7988_sdcard_funcs[] = { 5, 5, 5, 5, 5, 5 }; 1001 1002static const int mt7988_emmc_51_pins[] = { 38, 39, 40, 41, 42, 43, 1003 44, 45, 46, 47, 48, 49 }; 1004static int mt7988_emmc_51_funcs[] = { 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 }; 1005 1006/* uart */ 1007static const int mt7988_uart2_pins[] = { 0, 1, 2, 3 }; 1008static int mt7988_uart2_funcs[] = { 1, 1, 1, 1 }; 1009 1010static const int mt7988_tops_uart0_0_pins[] = { 22, 23 }; 1011static int mt7988_tops_uart0_0_funcs[] = { 3, 3 }; 1012 1013static const int mt7988_uart2_0_pins[] = { 28, 29, 30, 31 }; 1014static int mt7988_uart2_0_funcs[] = { 2, 2, 2, 2 }; 1015 1016static const int mt7988_uart1_0_pins[] = { 32, 33, 34, 35 }; 1017static int mt7988_uart1_0_funcs[] = { 2, 2, 2, 2 }; 1018 1019static const int mt7988_uart2_1_pins[] = { 32, 33, 34, 35 }; 1020static int mt7988_uart2_1_funcs[] = { 3, 3, 3, 3 }; 1021 1022static const int mt7988_net_wo0_uart_txd_0_pins[] = { 28 }; 1023static int mt7988_net_wo0_uart_txd_0_funcs[] = { 3 }; 1024 1025static const int mt7988_net_wo1_uart_txd_0_pins[] = { 29 }; 1026static int mt7988_net_wo1_uart_txd_0_funcs[] = { 3 }; 1027 1028static const int mt7988_net_wo2_uart_txd_0_pins[] = { 30 }; 1029static int mt7988_net_wo2_uart_txd_0_funcs[] = { 3 }; 1030 1031static const int mt7988_tops_uart1_0_pins[] = { 28, 29 }; 1032static int mt7988_tops_uart1_0_funcs[] = { 4, 4 }; 1033 1034static const int mt7988_tops_uart0_1_pins[] = { 30, 31 }; 1035static int mt7988_tops_uart0_1_funcs[] = { 4, 4 }; 1036 1037static const int mt7988_tops_uart1_1_pins[] = { 36, 37 }; 1038static int mt7988_tops_uart1_1_funcs[] = { 3, 3 }; 1039 1040static const int mt7988_uart0_pins[] = { 55, 56 }; 1041static int mt7988_uart0_funcs[] = { 1, 1 }; 1042 1043static const int mt7988_tops_uart0_2_pins[] = { 55, 56 }; 1044static int mt7988_tops_uart0_2_funcs[] = { 2, 2 }; 1045 1046static const int mt7988_uart2_2_pins[] = { 50, 51, 52, 53 }; 1047static int mt7988_uart2_2_funcs[] = { 2, 2, 2, 2 }; 1048 1049static const int mt7988_uart1_1_pins[] = { 58, 59, 60, 61 }; 1050static int mt7988_uart1_1_funcs[] = { 2, 2, 2, 2 }; 1051 1052static const int mt7988_uart2_3_pins[] = { 58, 59, 60, 61 }; 1053static int mt7988_uart2_3_funcs[] = { 3, 3, 3, 3 }; 1054 1055static const int mt7988_uart1_2_pins[] = { 80, 81, 82, 83 }; 1056static int mt7988_uart1_2_funcs[] = { 1, 1, 1, 1 }; 1057 1058static const int mt7988_uart1_2_lite_pins[] = { 80, 81 }; 1059static int mt7988_uart1_2_lite_funcs[] = { 1, 1 }; 1060 1061static const int mt7988_tops_uart1_2_pins[] = { 80, 81 }; 1062static int mt7988_tops_uart1_2_funcs[] = { 4, 4, }; 1063 1064static const int mt7988_net_wo0_uart_txd_1_pins[] = { 80 }; 1065static int mt7988_net_wo0_uart_txd_1_funcs[] = { 3 }; 1066 1067static const int mt7988_net_wo1_uart_txd_1_pins[] = { 81 }; 1068static int mt7988_net_wo1_uart_txd_1_funcs[] = { 3 }; 1069 1070static const int mt7988_net_wo2_uart_txd_1_pins[] = { 82 }; 1071static int mt7988_net_wo2_uart_txd_1_funcs[] = { 3 }; 1072 1073/* udi */ 1074static const int mt7988_udi_pins[] = { 32, 33, 34, 35, 36 }; 1075static int mt7988_udi_funcs[] = { 4, 4, 4, 4, 4 }; 1076 1077/* i2s */ 1078static const int mt7988_i2s_pins[] = { 50, 51, 52, 53, 54 }; 1079static int mt7988_i2s_funcs[] = { 1, 1, 1, 1, 1 }; 1080 1081/* pcm */ 1082static const int mt7988_pcm_pins[] = { 50, 51, 52, 53 }; 1083static int mt7988_pcm_funcs[] = { 1, 1, 1, 1 }; 1084 1085/* led */ 1086static const int mt7988_gbe0_led1_pins[] = { 58 }; 1087static int mt7988_gbe0_led1_funcs[] = { 6 }; 1088static const int mt7988_gbe1_led1_pins[] = { 59 }; 1089static int mt7988_gbe1_led1_funcs[] = { 6 }; 1090static const int mt7988_gbe2_led1_pins[] = { 60 }; 1091static int mt7988_gbe2_led1_funcs[] = { 6 }; 1092static const int mt7988_gbe3_led1_pins[] = { 61 }; 1093static int mt7988_gbe3_led1_funcs[] = { 6 }; 1094 1095static const int mt7988_2p5gbe_led1_pins[] = { 62 }; 1096static int mt7988_2p5gbe_led1_funcs[] = { 6 }; 1097 1098static const int mt7988_gbe0_led0_pins[] = { 64 }; 1099static int mt7988_gbe0_led0_funcs[] = { 1 }; 1100static const int mt7988_gbe1_led0_pins[] = { 65 }; 1101static int mt7988_gbe1_led0_funcs[] = { 1 }; 1102static const int mt7988_gbe2_led0_pins[] = { 66 }; 1103static int mt7988_gbe2_led0_funcs[] = { 1 }; 1104static const int mt7988_gbe3_led0_pins[] = { 67 }; 1105static int mt7988_gbe3_led0_funcs[] = { 1 }; 1106 1107static const int mt7988_2p5gbe_led0_pins[] = { 68 }; 1108static int mt7988_2p5gbe_led0_funcs[] = { 1 }; 1109 1110/* usb */ 1111static const int mt7988_drv_vbus_p1_pins[] = { 63 }; 1112static int mt7988_drv_vbus_p1_funcs[] = { 1 }; 1113 1114static const int mt7988_drv_vbus_pins[] = { 79 }; 1115static int mt7988_drv_vbus_funcs[] = { 1 }; 1116 1117static const struct group_desc mt7988_groups[] = { 1118 /* @GPIO(0,1,2,3): uart2 */ 1119 PINCTRL_PIN_GROUP("uart2", mt7988_uart2), 1120 /* @GPIO(0,1,2,3,4): tops_jtag0_0 */ 1121 PINCTRL_PIN_GROUP("tops_jtag0_0", mt7988_tops_jtag0_0), 1122 /* @GPIO(2,3): int_usxgmii */ 1123 PINCTRL_PIN_GROUP("int_usxgmii", mt7988_int_usxgmii), 1124 /* @GPIO(0,1,2,3,4): dfd */ 1125 PINCTRL_PIN_GROUP("dfd", mt7988_dfd), 1126 /* @GPIO(0,1): xfi_phy0_i2c0 */ 1127 PINCTRL_PIN_GROUP("xfi_phy0_i2c0", mt7988_xfi_phy0_i2c0), 1128 /* @GPIO(0,1): xfi_phy1_i2c0 */ 1129 PINCTRL_PIN_GROUP("xfi_phy1_i2c0", mt7988_xfi_phy1_i2c0), 1130 /* @GPIO(3,4): xfi_phy_pll_i2c0 */ 1131 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c0", mt7988_xfi_phy_pll_i2c0), 1132 /* @GPIO(3,4): xfi_phy_pll_i2c1 */ 1133 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c1", mt7988_xfi_phy_pll_i2c1), 1134 /* @GPIO(4): pwm7 */ 1135 PINCTRL_PIN_GROUP("pwm7_0", mt7988_pwm7_0), 1136 /* @GPIO(5,6) i2c0_0 */ 1137 PINCTRL_PIN_GROUP("i2c0_0", mt7988_i2c0_0), 1138 /* @GPIO(5,6) i2c1_sfp */ 1139 PINCTRL_PIN_GROUP("i2c1_sfp", mt7988_i2c1_sfp), 1140 /* @GPIO(5,6) xfi_pextp_phy0_i2c */ 1141 PINCTRL_PIN_GROUP("xfi_pextp_phy0_i2c", mt7988_xfi_pextp_phy0_i2c), 1142 /* @GPIO(5,6) xfi_pextp_phy1_i2c */ 1143 PINCTRL_PIN_GROUP("xfi_pextp_phy1_i2c", mt7988_xfi_pextp_phy1_i2c), 1144 /* @GPIO(5,6) mdc_mdio0 */ 1145 PINCTRL_PIN_GROUP("mdc_mdio0", mt7988_mdc_mdio0), 1146 /* @GPIO(7): pcie_wake_n0_0 */ 1147 PINCTRL_PIN_GROUP("pcie_wake_n0_0", mt7988_pcie_wake_n0_0), 1148 /* @GPIO(8): pcie_clk_req_n0_0 */ 1149 PINCTRL_PIN_GROUP("pcie_clk_req_n0_0", mt7988_pcie_clk_req_n0_0), 1150 /* @GPIO(9): pcie_wake_n3_0 */ 1151 PINCTRL_PIN_GROUP("pcie_wake_n3_0", mt7988_pcie_wake_n3_0), 1152 /* @GPIO(10): pcie_clk_req_n3 */ 1153 PINCTRL_PIN_GROUP("pcie_clk_req_n3", mt7988_pcie_clk_req_n3), 1154 /* @GPIO(10): pcie_clk_req_n0_1 */ 1155 PINCTRL_PIN_GROUP("pcie_clk_req_n0_1", mt7988_pcie_clk_req_n0_1), 1156 /* @GPIO(7,8) pcie_p0_phy_i2c */ 1157 PINCTRL_PIN_GROUP("pcie_p0_phy_i2c", mt7988_pcie_p0_phy_i2c), 1158 /* @GPIO(7,8) pcie_p1_phy_i2c */ 1159 PINCTRL_PIN_GROUP("pcie_p1_phy_i2c", mt7988_pcie_p1_phy_i2c), 1160 /* @GPIO(7,8) pcie_p2_phy_i2c */ 1161 PINCTRL_PIN_GROUP("pcie_p2_phy_i2c", mt7988_pcie_p2_phy_i2c), 1162 /* @GPIO(9,10) pcie_p3_phy_i2c */ 1163 PINCTRL_PIN_GROUP("pcie_p3_phy_i2c", mt7988_pcie_p3_phy_i2c), 1164 /* @GPIO(9,10) ckm_phy_i2c */ 1165 PINCTRL_PIN_GROUP("ckm_phy_i2c", mt7988_ckm_phy_i2c), 1166 /* @GPIO(11): pmic */ 1167 PINCTRL_PIN_GROUP("pcie_pmic", mt7988_pmic), 1168 /* @GPIO(12): watchdog */ 1169 PINCTRL_PIN_GROUP("watchdog", mt7988_watchdog), 1170 /* @GPIO(13): pcie_wake_n0_1 */ 1171 PINCTRL_PIN_GROUP("pcie_wake_n0_1", mt7988_pcie_wake_n0_1), 1172 /* @GPIO(14): pcie_wake_n3_1 */ 1173 PINCTRL_PIN_GROUP("pcie_wake_n3_1", mt7988_pcie_wake_n3_1), 1174 /* @GPIO(15,16) i2c0_1 */ 1175 PINCTRL_PIN_GROUP("i2c0_1", mt7988_i2c0_1), 1176 /* @GPIO(15,16) u30_phy_i2c0 */ 1177 PINCTRL_PIN_GROUP("u30_phy_i2c0", mt7988_u30_phy_i2c0), 1178 /* @GPIO(15,16) u32_phy_i2c0 */ 1179 PINCTRL_PIN_GROUP("u32_phy_i2c0", mt7988_u32_phy_i2c0), 1180 /* @GPIO(15,16) xfi_phy0_i2c1 */ 1181 PINCTRL_PIN_GROUP("xfi_phy0_i2c1", mt7988_xfi_phy0_i2c1), 1182 /* @GPIO(15,16) xfi_phy1_i2c1 */ 1183 PINCTRL_PIN_GROUP("xfi_phy1_i2c1", mt7988_xfi_phy1_i2c1), 1184 /* @GPIO(15,16) xfi_phy_pll_i2c2 */ 1185 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c2", mt7988_xfi_phy_pll_i2c2), 1186 /* @GPIO(17,18) i2c1_0 */ 1187 PINCTRL_PIN_GROUP("i2c1_0", mt7988_i2c1_0), 1188 /* @GPIO(17,18) u30_phy_i2c1 */ 1189 PINCTRL_PIN_GROUP("u30_phy_i2c1", mt7988_u30_phy_i2c1), 1190 /* @GPIO(17,18) u32_phy_i2c1 */ 1191 PINCTRL_PIN_GROUP("u32_phy_i2c1", mt7988_u32_phy_i2c1), 1192 /* @GPIO(17,18) xfi_phy_pll_i2c3 */ 1193 PINCTRL_PIN_GROUP("xfi_phy_pll_i2c3", mt7988_xfi_phy_pll_i2c3), 1194 /* @GPIO(17,18) sgmii0_i2c */ 1195 PINCTRL_PIN_GROUP("sgmii0_i2c", mt7988_sgmii0_i2c), 1196 /* @GPIO(17,18) sgmii1_i2c */ 1197 PINCTRL_PIN_GROUP("sgmii1_i2c", mt7988_sgmii1_i2c), 1198 /* @GPIO(19): pcie_2l_0_pereset */ 1199 PINCTRL_PIN_GROUP("pcie_2l_0_pereset", mt7988_pcie_2l_0_pereset), 1200 /* @GPIO(20): pcie_1l_1_pereset */ 1201 PINCTRL_PIN_GROUP("pcie_1l_1_pereset", mt7988_pcie_1l_1_pereset), 1202 /* @GPIO(21): pwm1 */ 1203 PINCTRL_PIN_GROUP("pwm1", mt7988_pwm1), 1204 /* @GPIO(22,23) spi0_wp_hold */ 1205 PINCTRL_PIN_GROUP("spi0_wp_hold", mt7988_spi0_wp_hold), 1206 /* @GPIO(24,25,26,27) spi0 */ 1207 PINCTRL_PIN_GROUP("spi0", mt7988_spi0), 1208 /* @GPIO(28,29,30,31) spi1 */ 1209 PINCTRL_PIN_GROUP("spi1", mt7988_spi1), 1210 /* @GPIO(32,33,34,35) spi2 */ 1211 PINCTRL_PIN_GROUP("spi2", mt7988_spi2), 1212 /* @GPIO(36,37) spi2_wp_hold */ 1213 PINCTRL_PIN_GROUP("spi2_wp_hold", mt7988_spi2_wp_hold), 1214 /* @GPIO(22,23,24,25,26,27) snfi */ 1215 PINCTRL_PIN_GROUP("snfi", mt7988_snfi), 1216 /* @GPIO(22,23) tops_uart0_0 */ 1217 PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart0_0), 1218 /* @GPIO(28,29,30,31) uart2_0 */ 1219 PINCTRL_PIN_GROUP("uart2_0", mt7988_uart2_0), 1220 /* @GPIO(32,33,34,35) uart1_0 */ 1221 PINCTRL_PIN_GROUP("uart1_0", mt7988_uart1_0), 1222 /* @GPIO(32,33,34,35) uart2_1 */ 1223 PINCTRL_PIN_GROUP("uart2_1", mt7988_uart2_1), 1224 /* @GPIO(28) net_wo0_uart_txd_0 */ 1225 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), 1226 /* @GPIO(29) net_wo1_uart_txd_0 */ 1227 PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), 1228 /* @GPIO(30) net_wo2_uart_txd_0 */ 1229 PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), 1230 /* @GPIO(28,29) tops_uart1_0 */ 1231 PINCTRL_PIN_GROUP("tops_uart0_0", mt7988_tops_uart1_0), 1232 /* @GPIO(30,31) tops_uart0_1 */ 1233 PINCTRL_PIN_GROUP("tops_uart0_1", mt7988_tops_uart0_1), 1234 /* @GPIO(36,37) tops_uart1_1 */ 1235 PINCTRL_PIN_GROUP("tops_uart1_1", mt7988_tops_uart1_1), 1236 /* @GPIO(32,33,34,35,36) udi */ 1237 PINCTRL_PIN_GROUP("udi", mt7988_udi), 1238 /* @GPIO(21,28,29,30,31,32,33,34,35,36,37) emmc_45 */ 1239 PINCTRL_PIN_GROUP("emmc_45", mt7988_emmc_45), 1240 /* @GPIO(32,33,34,35,36,37) sdcard */ 1241 PINCTRL_PIN_GROUP("sdcard", mt7988_sdcard), 1242 /* @GPIO(38,39,40,41,42,43,44,45,46,47,48,49) emmc_51 */ 1243 PINCTRL_PIN_GROUP("emmc_51", mt7988_emmc_51), 1244 /* @GPIO(28,29) 2p5g_ext_mdio */ 1245 PINCTRL_PIN_GROUP("2p5g_ext_mdio", mt7988_2p5g_ext_mdio), 1246 /* @GPIO(30,31) gbe_ext_mdio */ 1247 PINCTRL_PIN_GROUP("gbe_ext_mdio", mt7988_gbe_ext_mdio), 1248 /* @GPIO(50,51,52,53,54) i2s */ 1249 PINCTRL_PIN_GROUP("i2s", mt7988_i2s), 1250 /* @GPIO(50,51,52,53) pcm */ 1251 PINCTRL_PIN_GROUP("pcm", mt7988_pcm), 1252 /* @GPIO(55,56) uart0 */ 1253 PINCTRL_PIN_GROUP("uart0", mt7988_uart0), 1254 /* @GPIO(55,56) tops_uart0_2 */ 1255 PINCTRL_PIN_GROUP("tops_uart0_2", mt7988_tops_uart0_2), 1256 /* @GPIO(50,51,52,53) uart2_2 */ 1257 PINCTRL_PIN_GROUP("uart2_2", mt7988_uart2_2), 1258 /* @GPIO(50,51,52,53,54) wo0_jtag */ 1259 PINCTRL_PIN_GROUP("wo0_jtag", mt7988_wo0_jtag), 1260 /* @GPIO(50,51,52,53,54) wo1-wo1_jtag */ 1261 PINCTRL_PIN_GROUP("wo1_jtag", mt7988_wo1_jtag), 1262 /* @GPIO(50,51,52,53,54) wo2_jtag */ 1263 PINCTRL_PIN_GROUP("wo2_jtag", mt7988_wo2_jtag), 1264 /* @GPIO(57) pwm0 */ 1265 PINCTRL_PIN_GROUP("pwm0", mt7988_pwm0), 1266 /* @GPIO(58) pwm2_0 */ 1267 PINCTRL_PIN_GROUP("pwm2_0", mt7988_pwm2_0), 1268 /* @GPIO(59) pwm3_0 */ 1269 PINCTRL_PIN_GROUP("pwm3_0", mt7988_pwm3_0), 1270 /* @GPIO(60) pwm4_0 */ 1271 PINCTRL_PIN_GROUP("pwm4_0", mt7988_pwm4_0), 1272 /* @GPIO(61) pwm5_0 */ 1273 PINCTRL_PIN_GROUP("pwm5_0", mt7988_pwm5_0), 1274 /* @GPIO(58,59,60,61,62) jtag */ 1275 PINCTRL_PIN_GROUP("jtag", mt7988_jtag), 1276 /* @GPIO(58,59,60,61,62) tops_jtag0_1 */ 1277 PINCTRL_PIN_GROUP("tops_jtag0_1", mt7988_tops_jtag0_1), 1278 /* @GPIO(58,59,60,61) uart2_3 */ 1279 PINCTRL_PIN_GROUP("uart2_3", mt7988_uart2_3), 1280 /* @GPIO(58,59,60,61) uart1_1 */ 1281 PINCTRL_PIN_GROUP("uart1_1", mt7988_uart1_1), 1282 /* @GPIO(58,59,60,61) gbe_led1 */ 1283 PINCTRL_PIN_GROUP("gbe0_led1", mt7988_gbe0_led1), 1284 PINCTRL_PIN_GROUP("gbe1_led1", mt7988_gbe1_led1), 1285 PINCTRL_PIN_GROUP("gbe2_led1", mt7988_gbe2_led1), 1286 PINCTRL_PIN_GROUP("gbe3_led1", mt7988_gbe3_led1), 1287 /* @GPIO(62) pwm6_0 */ 1288 PINCTRL_PIN_GROUP("pwm6_0", mt7988_pwm6_0), 1289 /* @GPIO(62) 2p5gbe_led1 */ 1290 PINCTRL_PIN_GROUP("2p5gbe_led1", mt7988_2p5gbe_led1), 1291 /* @GPIO(64,65,66,67) gbe_led0 */ 1292 PINCTRL_PIN_GROUP("gbe0_led0", mt7988_gbe0_led0), 1293 PINCTRL_PIN_GROUP("gbe1_led0", mt7988_gbe1_led0), 1294 PINCTRL_PIN_GROUP("gbe2_led0", mt7988_gbe2_led0), 1295 PINCTRL_PIN_GROUP("gbe3_led0", mt7988_gbe3_led0), 1296 /* @GPIO(68) 2p5gbe_led0 */ 1297 PINCTRL_PIN_GROUP("2p5gbe_led0", mt7988_2p5gbe_led0), 1298 /* @GPIO(63) drv_vbus_p1 */ 1299 PINCTRL_PIN_GROUP("drv_vbus_p1", mt7988_drv_vbus_p1), 1300 /* @GPIO(63) pcie_clk_req_n2_1 */ 1301 PINCTRL_PIN_GROUP("pcie_clk_req_n2_1", mt7988_pcie_clk_req_n2_1), 1302 /* @GPIO(69, 70) mdc_mdio1 */ 1303 PINCTRL_PIN_GROUP("mdc_mdio1", mt7988_mdc_mdio1), 1304 /* @GPIO(69, 70) i2c1_2 */ 1305 PINCTRL_PIN_GROUP("i2c1_2", mt7988_i2c1_2), 1306 /* @GPIO(69) pwm6 */ 1307 PINCTRL_PIN_GROUP("pwm6", mt7988_pwm6), 1308 /* @GPIO(70) pwm7 */ 1309 PINCTRL_PIN_GROUP("pwm7", mt7988_pwm7), 1310 /* @GPIO(69,70) i2c2_0 */ 1311 PINCTRL_PIN_GROUP("i2c2_0", mt7988_i2c2_0), 1312 /* @GPIO(71,72) i2c2_1 */ 1313 PINCTRL_PIN_GROUP("i2c2_1", mt7988_i2c2_1), 1314 /* @GPIO(73) pcie_2l_1_pereset */ 1315 PINCTRL_PIN_GROUP("pcie_2l_1_pereset", mt7988_pcie_2l_1_pereset), 1316 /* @GPIO(74) pcie_1l_0_pereset */ 1317 PINCTRL_PIN_GROUP("pcie_1l_0_pereset", mt7988_pcie_1l_0_pereset), 1318 /* @GPIO(75) pcie_wake_n1_0 */ 1319 PINCTRL_PIN_GROUP("pcie_wake_n1_0", mt7988_pcie_wake_n1_0), 1320 /* @GPIO(76) pcie_clk_req_n1 */ 1321 PINCTRL_PIN_GROUP("pcie_clk_req_n1", mt7988_pcie_clk_req_n1), 1322 /* @GPIO(77) pcie_wake_n2_0 */ 1323 PINCTRL_PIN_GROUP("pcie_wake_n2_0", mt7988_pcie_wake_n2_0), 1324 /* @GPIO(78) pcie_clk_req_n2_0 */ 1325 PINCTRL_PIN_GROUP("pcie_clk_req_n2_0", mt7988_pcie_clk_req_n2_0), 1326 /* @GPIO(79) drv_vbus */ 1327 PINCTRL_PIN_GROUP("drv_vbus", mt7988_drv_vbus), 1328 /* @GPIO(79) pcie_wake_n2_1 */ 1329 PINCTRL_PIN_GROUP("pcie_wake_n2_1", mt7988_pcie_wake_n2_1), 1330 /* @GPIO(80,81,82,83) uart1_2 */ 1331 PINCTRL_PIN_GROUP("uart1_2", mt7988_uart1_2), 1332 /* @GPIO(80,81) uart1_2_lite */ 1333 PINCTRL_PIN_GROUP("uart1_2_lite", mt7988_uart1_2_lite), 1334 /* @GPIO(80) pwm2 */ 1335 PINCTRL_PIN_GROUP("pwm2", mt7988_pwm2), 1336 /* @GPIO(81) pwm3 */ 1337 PINCTRL_PIN_GROUP("pwm3", mt7988_pwm3), 1338 /* @GPIO(82) pwm4 */ 1339 PINCTRL_PIN_GROUP("pwm4", mt7988_pwm4), 1340 /* @GPIO(83) pwm5 */ 1341 PINCTRL_PIN_GROUP("pwm5", mt7988_pwm5), 1342 /* @GPIO(80) net_wo0_uart_txd_0 */ 1343 PINCTRL_PIN_GROUP("net_wo0_uart_txd_0", mt7988_net_wo0_uart_txd_0), 1344 /* @GPIO(81) net_wo1_uart_txd_0 */ 1345 PINCTRL_PIN_GROUP("net_wo1_uart_txd_0", mt7988_net_wo1_uart_txd_0), 1346 /* @GPIO(82) net_wo2_uart_txd_0 */ 1347 PINCTRL_PIN_GROUP("net_wo2_uart_txd_0", mt7988_net_wo2_uart_txd_0), 1348 /* @GPIO(80,81) tops_uart1_2 */ 1349 PINCTRL_PIN_GROUP("tops_uart1_2", mt7988_tops_uart1_2), 1350 /* @GPIO(80) net_wo0_uart_txd_1 */ 1351 PINCTRL_PIN_GROUP("net_wo0_uart_txd_1", mt7988_net_wo0_uart_txd_1), 1352 /* @GPIO(81) net_wo1_uart_txd_1 */ 1353 PINCTRL_PIN_GROUP("net_wo1_uart_txd_1", mt7988_net_wo1_uart_txd_1), 1354 /* @GPIO(82) net_wo2_uart_txd_1 */ 1355 PINCTRL_PIN_GROUP("net_wo2_uart_txd_1", mt7988_net_wo2_uart_txd_1), 1356}; 1357 1358/* Joint those groups owning the same capability in user point of view which 1359 * allows that people tend to use through the device tree. 1360 */ 1361static const char * const mt7988_jtag_groups[] = { 1362 "tops_jtag0_0", "wo0_jtag", "wo1_jtag", 1363 "wo2_jtag", "jtag", "tops_jtag0_1", 1364}; 1365static const char * const mt7988_int_usxgmii_groups[] = { 1366 "int_usxgmii", 1367}; 1368static const char * const mt7988_pwm_groups[] = { 1369 "pwm0", "pwm1", "pwm2", "pwm2_0", "pwm3", "pwm3_0", "pwm4", "pwm4_0", 1370 "pwm5", "pwm5_0", "pwm6", "pwm6_0", "pwm7", "pwm7_0", 1371 1372}; 1373static const char * const mt7988_dfd_groups[] = { 1374 "dfd", 1375}; 1376static const char * const mt7988_i2c_groups[] = { 1377 "xfi_phy0_i2c0", 1378 "xfi_phy1_i2c0", 1379 "xfi_phy_pll_i2c0", 1380 "xfi_phy_pll_i2c1", 1381 "i2c0_0", 1382 "i2c1_sfp", 1383 "xfi_pextp_phy0_i2c", 1384 "xfi_pextp_phy1_i2c", 1385 "i2c0_1", 1386 "u30_phy_i2c0", 1387 "u32_phy_i2c0", 1388 "xfi_phy0_i2c1", 1389 "xfi_phy1_i2c1", 1390 "xfi_phy_pll_i2c2", 1391 "i2c1_0", 1392 "u30_phy_i2c1", 1393 "u32_phy_i2c1", 1394 "xfi_phy_pll_i2c3", 1395 "sgmii0_i2c", 1396 "sgmii1_i2c", 1397 "i2c1_2", 1398 "i2c2_0", 1399 "i2c2_1", 1400}; 1401static const char * const mt7988_ethernet_groups[] = { 1402 "mdc_mdio0", 1403 "2p5g_ext_mdio", 1404 "gbe_ext_mdio", 1405 "mdc_mdio1", 1406}; 1407static const char * const mt7988_pcie_groups[] = { 1408 "pcie_wake_n0_0", "pcie_clk_req_n0_0", "pcie_wake_n3_0", 1409 "pcie_clk_req_n3", "pcie_p0_phy_i2c", "pcie_p1_phy_i2c", 1410 "pcie_p3_phy_i2c", "pcie_p2_phy_i2c", "ckm_phy_i2c", 1411 "pcie_wake_n0_1", "pcie_wake_n3_1", "pcie_2l_0_pereset", 1412 "pcie_1l_1_pereset", "pcie_clk_req_n2_1", "pcie_2l_1_pereset", 1413 "pcie_1l_0_pereset", "pcie_wake_n1_0", "pcie_clk_req_n1", 1414 "pcie_wake_n2_0", "pcie_clk_req_n2_0", "pcie_wake_n2_1", 1415 "pcie_clk_req_n0_1" 1416}; 1417static const char * const mt7988_pmic_groups[] = { 1418 "pmic", 1419}; 1420static const char * const mt7988_wdt_groups[] = { 1421 "watchdog", 1422}; 1423static const char * const mt7988_spi_groups[] = { 1424 "spi0", "spi0_wp_hold", "spi1", "spi2", "spi2_wp_hold", 1425}; 1426static const char * const mt7988_flash_groups[] = { "emmc_45", "sdcard", "snfi", 1427 "emmc_51" }; 1428static const char * const mt7988_uart_groups[] = { 1429 "uart2", 1430 "tops_uart0_0", 1431 "uart2_0", 1432 "uart1_0", 1433 "uart2_1", 1434 "net_wo0_uart_txd_0", 1435 "net_wo1_uart_txd_0", 1436 "net_wo2_uart_txd_0", 1437 "tops_uart1_0", 1438 "ops_uart0_1", 1439 "ops_uart1_1", 1440 "uart0", 1441 "tops_uart0_2", 1442 "uart1_1", 1443 "uart2_3", 1444 "uart1_2", 1445 "uart1_2_lite", 1446 "tops_uart1_2", 1447 "net_wo0_uart_txd_1", 1448 "net_wo1_uart_txd_1", 1449 "net_wo2_uart_txd_1", 1450}; 1451static const char * const mt7988_udi_groups[] = { 1452 "udi", 1453}; 1454static const char * const mt7988_audio_groups[] = { 1455 "i2s", "pcm", 1456}; 1457static const char * const mt7988_led_groups[] = { 1458 "gbe0_led1", "gbe1_led1", "gbe2_led1", "gbe3_led1", "2p5gbe_led1", 1459 "gbe0_led0", "gbe1_led0", "gbe2_led0", "gbe3_led0", "2p5gbe_led0", 1460 "wf5g_led0", "wf5g_led1", 1461}; 1462static const char * const mt7988_usb_groups[] = { 1463 "drv_vbus", 1464 "drv_vbus_p1", 1465}; 1466 1467static const struct pinfunction mt7988_functions[] = { 1468 PINCTRL_PIN_FUNCTION("audio", mt7988_audio), 1469 PINCTRL_PIN_FUNCTION("jtag", mt7988_jtag), 1470 PINCTRL_PIN_FUNCTION("int_usxgmii", mt7988_int_usxgmii), 1471 PINCTRL_PIN_FUNCTION("pwm", mt7988_pwm), 1472 PINCTRL_PIN_FUNCTION("dfd", mt7988_dfd), 1473 PINCTRL_PIN_FUNCTION("i2c", mt7988_i2c), 1474 PINCTRL_PIN_FUNCTION("eth", mt7988_ethernet), 1475 PINCTRL_PIN_FUNCTION("pcie", mt7988_pcie), 1476 PINCTRL_PIN_FUNCTION("pmic", mt7988_pmic), 1477 PINCTRL_PIN_FUNCTION("watchdog", mt7988_wdt), 1478 PINCTRL_PIN_FUNCTION("spi", mt7988_spi), 1479 PINCTRL_PIN_FUNCTION("flash", mt7988_flash), 1480 PINCTRL_PIN_FUNCTION("uart", mt7988_uart), 1481 PINCTRL_PIN_FUNCTION("udi", mt7988_udi), 1482 PINCTRL_PIN_FUNCTION("usb", mt7988_usb), 1483 PINCTRL_PIN_FUNCTION("led", mt7988_led), 1484}; 1485 1486static const struct mtk_eint_hw mt7988_eint_hw = { 1487 .port_mask = 7, 1488 .ports = 7, 1489 .ap_num = ARRAY_SIZE(mt7988_pins), 1490 .db_cnt = 16, 1491}; 1492 1493static const char * const mt7988_pinctrl_register_base_names[] = { 1494 "gpio", "iocfg_tr", "iocfg_br", 1495 "iocfg_rb", "iocfg_lb", "iocfg_tl", 1496}; 1497 1498static const struct mtk_pin_soc mt7988_data = { 1499 .reg_cal = mt7988_reg_cals, 1500 .pins = mt7988_pins, 1501 .npins = ARRAY_SIZE(mt7988_pins), 1502 .grps = mt7988_groups, 1503 .ngrps = ARRAY_SIZE(mt7988_groups), 1504 .funcs = mt7988_functions, 1505 .nfuncs = ARRAY_SIZE(mt7988_functions), 1506 .eint_hw = &mt7988_eint_hw, 1507 .gpio_m = 0, 1508 .ies_present = false, 1509 .base_names = mt7988_pinctrl_register_base_names, 1510 .nbase_names = ARRAY_SIZE(mt7988_pinctrl_register_base_names), 1511 .bias_disable_set = mtk_pinconf_bias_disable_set, 1512 .bias_disable_get = mtk_pinconf_bias_disable_get, 1513 .bias_set = mtk_pinconf_bias_set, 1514 .bias_get = mtk_pinconf_bias_get, 1515 .pull_type = mt7988_pull_type, 1516 .bias_set_combo = mtk_pinconf_bias_set_combo, 1517 .bias_get_combo = mtk_pinconf_bias_get_combo, 1518 .drive_set = mtk_pinconf_drive_set_rev1, 1519 .drive_get = mtk_pinconf_drive_get_rev1, 1520 .adv_pull_get = mtk_pinconf_adv_pull_get, 1521 .adv_pull_set = mtk_pinconf_adv_pull_set, 1522}; 1523 1524static const struct of_device_id mt7988_pinctrl_of_match[] = { 1525 { .compatible = "mediatek,mt7988-pinctrl" }, 1526 {} 1527}; 1528 1529static int mt7988_pinctrl_probe(struct platform_device *pdev) 1530{ 1531 return mtk_moore_pinctrl_probe(pdev, &mt7988_data); 1532} 1533 1534static struct platform_driver mt7988_pinctrl_driver = { 1535 .driver = { 1536 .name = "mt7988-pinctrl", 1537 .of_match_table = mt7988_pinctrl_of_match, 1538 }, 1539 .probe = mt7988_pinctrl_probe, 1540}; 1541 1542static int __init mt7988_pinctrl_init(void) 1543{ 1544 return platform_driver_register(&mt7988_pinctrl_driver); 1545} 1546arch_initcall(mt7988_pinctrl_init);
~/
Read-only file preview.