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pinctrl-airoha.c
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linux-6.19.14/drivers/pinctrl/mediatek/pinctrl-airoha.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Author: Lorenzo Bianconi <lorenzo@kernel.org> 4 * Author: Benjamin Larsson <benjamin.larsson@genexis.eu> 5 * Author: Markus Gothe <markus.gothe@genexis.eu> 6 */ 7 8#include <dt-bindings/pinctrl/mt65xx.h> 9#include <linux/bitfield.h> 10#include <linux/bits.h> 11#include <linux/cleanup.h> 12#include <linux/gpio/driver.h> 13#include <linux/interrupt.h> 14#include <linux/io.h> 15#include <linux/irq.h> 16#include <linux/irqdomain.h> 17#include <linux/mfd/syscon.h> 18#include <linux/of.h> 19#include <linux/of_irq.h> 20#include <linux/of_platform.h> 21#include <linux/pinctrl/consumer.h> 22#include <linux/pinctrl/pinctrl.h> 23#include <linux/pinctrl/pinconf.h> 24#include <linux/pinctrl/pinconf-generic.h> 25#include <linux/pinctrl/pinmux.h> 26#include <linux/platform_device.h> 27#include <linux/regmap.h> 28 29#include "../core.h" 30#include "../pinconf.h" 31#include "../pinmux.h" 32 33#define PINCTRL_PIN_GROUP(id, table) \ 34 PINCTRL_PINGROUP(id, table##_pins, ARRAY_SIZE(table##_pins)) 35 36#define PINCTRL_FUNC_DESC(id, table) \ 37 { \ 38 .desc = PINCTRL_PINFUNCTION(id, table##_groups, \ 39 ARRAY_SIZE(table##_groups)),\ 40 .groups = table##_func_group, \ 41 .group_size = ARRAY_SIZE(table##_func_group), \ 42 } 43 44#define PINCTRL_CONF_DESC(p, offset, mask) \ 45 { \ 46 .pin = p, \ 47 .reg = { offset, mask }, \ 48 } 49 50/* MUX */ 51#define REG_GPIO_2ND_I2C_MODE 0x0214 52#define GPIO_MDC_IO_MASTER_MODE_MODE BIT(14) 53#define GPIO_I2C_MASTER_MODE_MODE BIT(13) 54#define GPIO_I2S_MODE_MASK BIT(12) 55#define GPIO_I2C_SLAVE_MODE_MODE BIT(11) 56#define GPIO_LAN3_LED1_MODE_MASK BIT(10) 57#define GPIO_LAN3_LED0_MODE_MASK BIT(9) 58#define GPIO_LAN2_LED1_MODE_MASK BIT(8) 59#define GPIO_LAN2_LED0_MODE_MASK BIT(7) 60#define GPIO_LAN1_LED1_MODE_MASK BIT(6) 61#define GPIO_LAN1_LED0_MODE_MASK BIT(5) 62#define GPIO_LAN0_LED1_MODE_MASK BIT(4) 63#define GPIO_LAN0_LED0_MODE_MASK BIT(3) 64#define PON_TOD_1PPS_MODE_MASK BIT(2) 65#define GSW_TOD_1PPS_MODE_MASK BIT(1) 66#define GPIO_2ND_I2C_MODE_MASK BIT(0) 67 68#define REG_GPIO_SPI_CS1_MODE 0x0218 69#define GPIO_PCM_SPI_CS4_MODE_MASK BIT(21) 70#define GPIO_PCM_SPI_CS3_MODE_MASK BIT(20) 71#define GPIO_PCM_SPI_CS2_MODE_P156_MASK BIT(19) 72#define GPIO_PCM_SPI_CS2_MODE_P128_MASK BIT(18) 73#define AN7583_GPIO_PCM_SPI_CS2_MODE_MASK BIT(18) 74#define GPIO_PCM_SPI_CS1_MODE_MASK BIT(17) 75#define GPIO_PCM_SPI_MODE_MASK BIT(16) 76#define GPIO_PCM2_MODE_MASK BIT(13) 77#define GPIO_PCM1_MODE_MASK BIT(12) 78#define GPIO_PCM_INT_MODE_MASK BIT(9) 79#define GPIO_PCM_RESET_MODE_MASK BIT(8) 80#define GPIO_SPI_QUAD_MODE_MASK BIT(4) 81#define GPIO_SPI_CS4_MODE_MASK BIT(3) 82#define GPIO_SPI_CS3_MODE_MASK BIT(2) 83#define GPIO_SPI_CS2_MODE_MASK BIT(1) 84#define GPIO_SPI_CS1_MODE_MASK BIT(0) 85 86#define REG_GPIO_PON_MODE 0x021c 87#define GPIO_PARALLEL_NAND_MODE_MASK BIT(14) 88#define GPIO_SGMII_MDIO_MODE_MASK BIT(13) 89#define GPIO_PCIE_RESET2_MASK BIT(12) 90#define SIPO_RCLK_MODE_MASK BIT(11) 91#define GPIO_PCIE_RESET1_MASK BIT(10) 92#define GPIO_PCIE_RESET0_MASK BIT(9) 93#define GPIO_UART5_MODE_MASK BIT(8) 94#define GPIO_UART4_MODE_MASK BIT(7) 95#define GPIO_HSUART_CTS_RTS_MODE_MASK BIT(6) 96#define GPIO_HSUART_MODE_MASK BIT(5) 97#define GPIO_UART2_CTS_RTS_MODE_MASK BIT(4) 98#define GPIO_UART2_MODE_MASK BIT(3) 99#define GPIO_SIPO_MODE_MASK BIT(2) 100#define GPIO_EMMC_MODE_MASK BIT(1) 101#define GPIO_PON_MODE_MASK BIT(0) 102 103#define REG_NPU_UART_EN 0x0224 104#define JTAG_UDI_EN_MASK BIT(4) 105#define JTAG_DFD_EN_MASK BIT(3) 106 107#define REG_FORCE_GPIO_EN 0x0228 108#define FORCE_GPIO_EN(n) BIT(n) 109 110/* LED MAP */ 111#define REG_LAN_LED0_MAPPING 0x027c 112#define REG_LAN_LED1_MAPPING 0x0280 113 114#define LAN4_LED_MAPPING_MASK GENMASK(18, 16) 115#define LAN4_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN4_LED_MAPPING_MASK, (_n)) 116 117#define LAN3_LED_MAPPING_MASK GENMASK(14, 12) 118#define LAN3_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN3_LED_MAPPING_MASK, (_n)) 119 120#define LAN2_LED_MAPPING_MASK GENMASK(10, 8) 121#define LAN2_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN2_LED_MAPPING_MASK, (_n)) 122 123#define LAN1_LED_MAPPING_MASK GENMASK(6, 4) 124#define LAN1_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN1_LED_MAPPING_MASK, (_n)) 125 126#define LAN0_LED_MAPPING_MASK GENMASK(2, 0) 127#define LAN0_PHY_LED_MAP(_n) FIELD_PREP_CONST(LAN0_LED_MAPPING_MASK, (_n)) 128 129/* CONF */ 130#define REG_I2C_SDA_E2 0x001c 131#define AN7583_I2C1_SCL_E2_MASK BIT(16) 132#define AN7583_I2C1_SDA_E2_MASK BIT(15) 133#define SPI_MISO_E2_MASK BIT(14) 134#define SPI_MOSI_E2_MASK BIT(13) 135#define SPI_CLK_E2_MASK BIT(12) 136#define SPI_CS0_E2_MASK BIT(11) 137#define PCIE2_RESET_E2_MASK BIT(10) 138#define PCIE1_RESET_E2_MASK BIT(9) 139#define PCIE0_RESET_E2_MASK BIT(8) 140#define AN7583_MDIO_0_E2_MASK BIT(5) 141#define AN7583_MDC_0_E2_MASK BIT(4) 142#define UART1_RXD_E2_MASK BIT(3) 143#define UART1_TXD_E2_MASK BIT(2) 144#define I2C_SCL_E2_MASK BIT(1) 145#define I2C_SDA_E2_MASK BIT(0) 146 147#define REG_I2C_SDA_E4 0x0020 148#define AN7583_I2C1_SCL_E4_MASK BIT(16) 149#define AN7583_I2C1_SDA_E4_MASK BIT(15) 150#define SPI_MISO_E4_MASK BIT(14) 151#define SPI_MOSI_E4_MASK BIT(13) 152#define SPI_CLK_E4_MASK BIT(12) 153#define SPI_CS0_E4_MASK BIT(11) 154#define PCIE2_RESET_E4_MASK BIT(10) 155#define PCIE1_RESET_E4_MASK BIT(9) 156#define PCIE0_RESET_E4_MASK BIT(8) 157#define AN7583_MDIO_0_E4_MASK BIT(5) 158#define AN7583_MDC_0_E4_MASK BIT(4) 159#define UART1_RXD_E4_MASK BIT(3) 160#define UART1_TXD_E4_MASK BIT(2) 161#define I2C_SCL_E4_MASK BIT(1) 162#define I2C_SDA_E4_MASK BIT(0) 163 164#define REG_GPIO_L_E2 0x0024 165#define REG_GPIO_L_E4 0x0028 166#define REG_GPIO_H_E2 0x002c 167#define REG_GPIO_H_E4 0x0030 168 169#define REG_I2C_SDA_PU 0x0044 170#define AN7583_I2C1_SCL_PU_MASK BIT(16) 171#define AN7583_I2C1_SDA_PU_MASK BIT(15) 172#define SPI_MISO_PU_MASK BIT(14) 173#define SPI_MOSI_PU_MASK BIT(13) 174#define SPI_CLK_PU_MASK BIT(12) 175#define SPI_CS0_PU_MASK BIT(11) 176#define PCIE2_RESET_PU_MASK BIT(10) 177#define PCIE1_RESET_PU_MASK BIT(9) 178#define PCIE0_RESET_PU_MASK BIT(8) 179#define AN7583_MDIO_0_PU_MASK BIT(5) 180#define AN7583_MDC_0_PU_MASK BIT(4) 181#define UART1_RXD_PU_MASK BIT(3) 182#define UART1_TXD_PU_MASK BIT(2) 183#define I2C_SCL_PU_MASK BIT(1) 184#define I2C_SDA_PU_MASK BIT(0) 185 186#define REG_I2C_SDA_PD 0x0048 187#define AN7583_I2C1_SDA_PD_MASK BIT(16) 188#define AN7583_I2C1_SCL_PD_MASK BIT(15) 189#define SPI_MISO_PD_MASK BIT(14) 190#define SPI_MOSI_PD_MASK BIT(13) 191#define SPI_CLK_PD_MASK BIT(12) 192#define SPI_CS0_PD_MASK BIT(11) 193#define PCIE2_RESET_PD_MASK BIT(10) 194#define PCIE1_RESET_PD_MASK BIT(9) 195#define PCIE0_RESET_PD_MASK BIT(8) 196#define AN7583_MDIO_0_PD_MASK BIT(5) 197#define AN7583_MDC_0_PD_MASK BIT(4) 198#define UART1_RXD_PD_MASK BIT(3) 199#define UART1_TXD_PD_MASK BIT(2) 200#define I2C_SCL_PD_MASK BIT(1) 201#define I2C_SDA_PD_MASK BIT(0) 202 203#define REG_GPIO_L_PU 0x004c 204#define REG_GPIO_L_PD 0x0050 205#define REG_GPIO_H_PU 0x0054 206#define REG_GPIO_H_PD 0x0058 207 208#define REG_PCIE_RESET_OD 0x018c 209#define PCIE2_RESET_OD_MASK BIT(2) 210#define PCIE1_RESET_OD_MASK BIT(1) 211#define PCIE0_RESET_OD_MASK BIT(0) 212 213/* GPIOs */ 214#define REG_GPIO_CTRL 0x0000 215#define REG_GPIO_DATA 0x0004 216#define REG_GPIO_INT 0x0008 217#define REG_GPIO_INT_EDGE 0x000c 218#define REG_GPIO_INT_LEVEL 0x0010 219#define REG_GPIO_OE 0x0014 220#define REG_GPIO_CTRL1 0x0020 221 222/* PWM MODE CONF */ 223#define REG_GPIO_FLASH_MODE_CFG 0x0034 224#define GPIO15_FLASH_MODE_CFG BIT(15) 225#define GPIO14_FLASH_MODE_CFG BIT(14) 226#define GPIO13_FLASH_MODE_CFG BIT(13) 227#define GPIO12_FLASH_MODE_CFG BIT(12) 228#define GPIO11_FLASH_MODE_CFG BIT(11) 229#define GPIO10_FLASH_MODE_CFG BIT(10) 230#define GPIO9_FLASH_MODE_CFG BIT(9) 231#define GPIO8_FLASH_MODE_CFG BIT(8) 232#define GPIO7_FLASH_MODE_CFG BIT(7) 233#define GPIO6_FLASH_MODE_CFG BIT(6) 234#define GPIO5_FLASH_MODE_CFG BIT(5) 235#define GPIO4_FLASH_MODE_CFG BIT(4) 236#define GPIO3_FLASH_MODE_CFG BIT(3) 237#define GPIO2_FLASH_MODE_CFG BIT(2) 238#define GPIO1_FLASH_MODE_CFG BIT(1) 239#define GPIO0_FLASH_MODE_CFG BIT(0) 240 241#define REG_GPIO_CTRL2 0x0060 242#define REG_GPIO_CTRL3 0x0064 243 244/* PWM MODE CONF EXT */ 245#define REG_GPIO_FLASH_MODE_CFG_EXT 0x0068 246#define GPIO51_FLASH_MODE_CFG BIT(31) 247#define GPIO50_FLASH_MODE_CFG BIT(30) 248#define GPIO49_FLASH_MODE_CFG BIT(29) 249#define GPIO48_FLASH_MODE_CFG BIT(28) 250#define GPIO47_FLASH_MODE_CFG BIT(27) 251#define GPIO46_FLASH_MODE_CFG BIT(26) 252#define GPIO45_FLASH_MODE_CFG BIT(25) 253#define GPIO44_FLASH_MODE_CFG BIT(24) 254#define GPIO43_FLASH_MODE_CFG BIT(23) 255#define GPIO42_FLASH_MODE_CFG BIT(22) 256#define GPIO41_FLASH_MODE_CFG BIT(21) 257#define GPIO40_FLASH_MODE_CFG BIT(20) 258#define GPIO39_FLASH_MODE_CFG BIT(19) 259#define GPIO38_FLASH_MODE_CFG BIT(18) 260#define GPIO37_FLASH_MODE_CFG BIT(17) 261#define GPIO36_FLASH_MODE_CFG BIT(16) 262#define GPIO31_FLASH_MODE_CFG BIT(15) 263#define GPIO30_FLASH_MODE_CFG BIT(14) 264#define GPIO29_FLASH_MODE_CFG BIT(13) 265#define GPIO28_FLASH_MODE_CFG BIT(12) 266#define GPIO27_FLASH_MODE_CFG BIT(11) 267#define GPIO26_FLASH_MODE_CFG BIT(10) 268#define GPIO25_FLASH_MODE_CFG BIT(9) 269#define GPIO24_FLASH_MODE_CFG BIT(8) 270#define GPIO23_FLASH_MODE_CFG BIT(7) 271#define GPIO22_FLASH_MODE_CFG BIT(6) 272#define GPIO21_FLASH_MODE_CFG BIT(5) 273#define GPIO20_FLASH_MODE_CFG BIT(4) 274#define GPIO19_FLASH_MODE_CFG BIT(3) 275#define GPIO18_FLASH_MODE_CFG BIT(2) 276#define GPIO17_FLASH_MODE_CFG BIT(1) 277#define GPIO16_FLASH_MODE_CFG BIT(0) 278 279#define REG_GPIO_DATA1 0x0070 280#define REG_GPIO_OE1 0x0078 281#define REG_GPIO_INT1 0x007c 282#define REG_GPIO_INT_EDGE1 0x0080 283#define REG_GPIO_INT_EDGE2 0x0084 284#define REG_GPIO_INT_EDGE3 0x0088 285#define REG_GPIO_INT_LEVEL1 0x008c 286#define REG_GPIO_INT_LEVEL2 0x0090 287#define REG_GPIO_INT_LEVEL3 0x0094 288 289#define AIROHA_NUM_PINS 64 290#define AIROHA_PIN_BANK_SIZE (AIROHA_NUM_PINS / 2) 291#define AIROHA_REG_GPIOCTRL_NUM_PIN (AIROHA_NUM_PINS / 4) 292 293static const u32 gpio_data_regs[] = { 294 REG_GPIO_DATA, 295 REG_GPIO_DATA1 296}; 297 298static const u32 gpio_out_regs[] = { 299 REG_GPIO_OE, 300 REG_GPIO_OE1 301}; 302 303static const u32 gpio_dir_regs[] = { 304 REG_GPIO_CTRL, 305 REG_GPIO_CTRL1, 306 REG_GPIO_CTRL2, 307 REG_GPIO_CTRL3 308}; 309 310static const u32 irq_status_regs[] = { 311 REG_GPIO_INT, 312 REG_GPIO_INT1 313}; 314 315static const u32 irq_level_regs[] = { 316 REG_GPIO_INT_LEVEL, 317 REG_GPIO_INT_LEVEL1, 318 REG_GPIO_INT_LEVEL2, 319 REG_GPIO_INT_LEVEL3 320}; 321 322static const u32 irq_edge_regs[] = { 323 REG_GPIO_INT_EDGE, 324 REG_GPIO_INT_EDGE1, 325 REG_GPIO_INT_EDGE2, 326 REG_GPIO_INT_EDGE3 327}; 328 329struct airoha_pinctrl_reg { 330 u32 offset; 331 u32 mask; 332}; 333 334enum airoha_pinctrl_mux_func { 335 AIROHA_FUNC_MUX, 336 AIROHA_FUNC_PWM_MUX, 337 AIROHA_FUNC_PWM_EXT_MUX, 338}; 339 340struct airoha_pinctrl_func_group { 341 const char *name; 342 struct { 343 enum airoha_pinctrl_mux_func mux; 344 u32 offset; 345 u32 mask; 346 u32 val; 347 } regmap[2]; 348 int regmap_size; 349}; 350 351struct airoha_pinctrl_func { 352 const struct pinfunction desc; 353 const struct airoha_pinctrl_func_group *groups; 354 u8 group_size; 355}; 356 357struct airoha_pinctrl_conf { 358 u32 pin; 359 struct airoha_pinctrl_reg reg; 360}; 361 362struct airoha_pinctrl_gpiochip { 363 struct gpio_chip chip; 364 365 /* gpio */ 366 const u32 *data; 367 const u32 *dir; 368 const u32 *out; 369 /* irq */ 370 const u32 *status; 371 const u32 *level; 372 const u32 *edge; 373 374 u32 irq_type[AIROHA_NUM_PINS]; 375}; 376 377struct airoha_pinctrl_confs_info { 378 const struct airoha_pinctrl_conf *confs; 379 unsigned int num_confs; 380}; 381 382enum airoha_pinctrl_confs_type { 383 AIROHA_PINCTRL_CONFS_PULLUP, 384 AIROHA_PINCTRL_CONFS_PULLDOWN, 385 AIROHA_PINCTRL_CONFS_DRIVE_E2, 386 AIROHA_PINCTRL_CONFS_DRIVE_E4, 387 AIROHA_PINCTRL_CONFS_PCIE_RST_OD, 388 389 AIROHA_PINCTRL_CONFS_MAX, 390}; 391 392struct airoha_pinctrl { 393 struct pinctrl_dev *ctrl; 394 395 struct pinctrl_desc desc; 396 const struct pingroup *grps; 397 const struct airoha_pinctrl_func *funcs; 398 const struct airoha_pinctrl_confs_info *confs_info; 399 400 struct regmap *chip_scu; 401 struct regmap *regmap; 402 403 struct airoha_pinctrl_gpiochip gpiochip; 404}; 405 406struct airoha_pinctrl_match_data { 407 const struct pinctrl_pin_desc *pins; 408 const unsigned int num_pins; 409 const struct pingroup *grps; 410 const unsigned int num_grps; 411 const struct airoha_pinctrl_func *funcs; 412 const unsigned int num_funcs; 413 const struct airoha_pinctrl_confs_info confs_info[AIROHA_PINCTRL_CONFS_MAX]; 414}; 415 416static struct pinctrl_pin_desc en7581_pinctrl_pins[] = { 417 PINCTRL_PIN(0, "uart1_txd"), 418 PINCTRL_PIN(1, "uart1_rxd"), 419 PINCTRL_PIN(2, "i2c_scl"), 420 PINCTRL_PIN(3, "i2c_sda"), 421 PINCTRL_PIN(4, "spi_cs0"), 422 PINCTRL_PIN(5, "spi_clk"), 423 PINCTRL_PIN(6, "spi_mosi"), 424 PINCTRL_PIN(7, "spi_miso"), 425 PINCTRL_PIN(13, "gpio0"), 426 PINCTRL_PIN(14, "gpio1"), 427 PINCTRL_PIN(15, "gpio2"), 428 PINCTRL_PIN(16, "gpio3"), 429 PINCTRL_PIN(17, "gpio4"), 430 PINCTRL_PIN(18, "gpio5"), 431 PINCTRL_PIN(19, "gpio6"), 432 PINCTRL_PIN(20, "gpio7"), 433 PINCTRL_PIN(21, "gpio8"), 434 PINCTRL_PIN(22, "gpio9"), 435 PINCTRL_PIN(23, "gpio10"), 436 PINCTRL_PIN(24, "gpio11"), 437 PINCTRL_PIN(25, "gpio12"), 438 PINCTRL_PIN(26, "gpio13"), 439 PINCTRL_PIN(27, "gpio14"), 440 PINCTRL_PIN(28, "gpio15"), 441 PINCTRL_PIN(29, "gpio16"), 442 PINCTRL_PIN(30, "gpio17"), 443 PINCTRL_PIN(31, "gpio18"), 444 PINCTRL_PIN(32, "gpio19"), 445 PINCTRL_PIN(33, "gpio20"), 446 PINCTRL_PIN(34, "gpio21"), 447 PINCTRL_PIN(35, "gpio22"), 448 PINCTRL_PIN(36, "gpio23"), 449 PINCTRL_PIN(37, "gpio24"), 450 PINCTRL_PIN(38, "gpio25"), 451 PINCTRL_PIN(39, "gpio26"), 452 PINCTRL_PIN(40, "gpio27"), 453 PINCTRL_PIN(41, "gpio28"), 454 PINCTRL_PIN(42, "gpio29"), 455 PINCTRL_PIN(43, "gpio30"), 456 PINCTRL_PIN(44, "gpio31"), 457 PINCTRL_PIN(45, "gpio32"), 458 PINCTRL_PIN(46, "gpio33"), 459 PINCTRL_PIN(47, "gpio34"), 460 PINCTRL_PIN(48, "gpio35"), 461 PINCTRL_PIN(49, "gpio36"), 462 PINCTRL_PIN(50, "gpio37"), 463 PINCTRL_PIN(51, "gpio38"), 464 PINCTRL_PIN(52, "gpio39"), 465 PINCTRL_PIN(53, "gpio40"), 466 PINCTRL_PIN(54, "gpio41"), 467 PINCTRL_PIN(55, "gpio42"), 468 PINCTRL_PIN(56, "gpio43"), 469 PINCTRL_PIN(57, "gpio44"), 470 PINCTRL_PIN(58, "gpio45"), 471 PINCTRL_PIN(59, "gpio46"), 472 PINCTRL_PIN(61, "pcie_reset0"), 473 PINCTRL_PIN(62, "pcie_reset1"), 474 PINCTRL_PIN(63, "pcie_reset2"), 475}; 476 477static const int en7581_pon_pins[] = { 49, 50, 51, 52, 53, 54 }; 478static const int en7581_pon_tod_1pps_pins[] = { 46 }; 479static const int en7581_gsw_tod_1pps_pins[] = { 46 }; 480static const int en7581_sipo_pins[] = { 16, 17 }; 481static const int en7581_sipo_rclk_pins[] = { 16, 17, 43 }; 482static const int en7581_mdio_pins[] = { 14, 15 }; 483static const int en7581_uart2_pins[] = { 48, 55 }; 484static const int en7581_uart2_cts_rts_pins[] = { 46, 47 }; 485static const int en7581_hsuart_pins[] = { 28, 29 }; 486static const int en7581_hsuart_cts_rts_pins[] = { 26, 27 }; 487static const int en7581_uart4_pins[] = { 38, 39 }; 488static const int en7581_uart5_pins[] = { 18, 19 }; 489static const int en7581_i2c0_pins[] = { 2, 3 }; 490static const int en7581_i2c1_pins[] = { 14, 15 }; 491static const int en7581_jtag_udi_pins[] = { 16, 17, 18, 19, 20 }; 492static const int en7581_jtag_dfd_pins[] = { 16, 17, 18, 19, 20 }; 493static const int en7581_i2s_pins[] = { 26, 27, 28, 29 }; 494static const int en7581_pcm1_pins[] = { 22, 23, 24, 25 }; 495static const int en7581_pcm2_pins[] = { 18, 19, 20, 21 }; 496static const int en7581_spi_quad_pins[] = { 32, 33 }; 497static const int en7581_spi_pins[] = { 4, 5, 6, 7 }; 498static const int en7581_spi_cs1_pins[] = { 34 }; 499static const int en7581_pcm_spi_pins[] = { 18, 19, 20, 21, 22, 23, 24, 25 }; 500static const int en7581_pcm_spi_int_pins[] = { 14 }; 501static const int en7581_pcm_spi_rst_pins[] = { 15 }; 502static const int en7581_pcm_spi_cs1_pins[] = { 43 }; 503static const int en7581_pcm_spi_cs2_pins[] = { 40 }; 504static const int en7581_pcm_spi_cs2_p128_pins[] = { 40 }; 505static const int en7581_pcm_spi_cs2_p156_pins[] = { 40 }; 506static const int en7581_pcm_spi_cs3_pins[] = { 41 }; 507static const int en7581_pcm_spi_cs4_pins[] = { 42 }; 508static const int en7581_emmc_pins[] = { 4, 5, 6, 30, 31, 32, 33, 34, 35, 36, 37 }; 509static const int en7581_pnand_pins[] = { 4, 5, 6, 7, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42 }; 510static const int en7581_gpio0_pins[] = { 13 }; 511static const int en7581_gpio1_pins[] = { 14 }; 512static const int en7581_gpio2_pins[] = { 15 }; 513static const int en7581_gpio3_pins[] = { 16 }; 514static const int en7581_gpio4_pins[] = { 17 }; 515static const int en7581_gpio5_pins[] = { 18 }; 516static const int en7581_gpio6_pins[] = { 19 }; 517static const int en7581_gpio7_pins[] = { 20 }; 518static const int en7581_gpio8_pins[] = { 21 }; 519static const int en7581_gpio9_pins[] = { 22 }; 520static const int en7581_gpio10_pins[] = { 23 }; 521static const int en7581_gpio11_pins[] = { 24 }; 522static const int en7581_gpio12_pins[] = { 25 }; 523static const int en7581_gpio13_pins[] = { 26 }; 524static const int en7581_gpio14_pins[] = { 27 }; 525static const int en7581_gpio15_pins[] = { 28 }; 526static const int en7581_gpio16_pins[] = { 29 }; 527static const int en7581_gpio17_pins[] = { 30 }; 528static const int en7581_gpio18_pins[] = { 31 }; 529static const int en7581_gpio19_pins[] = { 32 }; 530static const int en7581_gpio20_pins[] = { 33 }; 531static const int en7581_gpio21_pins[] = { 34 }; 532static const int en7581_gpio22_pins[] = { 35 }; 533static const int en7581_gpio23_pins[] = { 36 }; 534static const int en7581_gpio24_pins[] = { 37 }; 535static const int en7581_gpio25_pins[] = { 38 }; 536static const int en7581_gpio26_pins[] = { 39 }; 537static const int en7581_gpio27_pins[] = { 40 }; 538static const int en7581_gpio28_pins[] = { 41 }; 539static const int en7581_gpio29_pins[] = { 42 }; 540static const int en7581_gpio30_pins[] = { 43 }; 541static const int en7581_gpio31_pins[] = { 44 }; 542static const int en7581_gpio33_pins[] = { 46 }; 543static const int en7581_gpio34_pins[] = { 47 }; 544static const int en7581_gpio35_pins[] = { 48 }; 545static const int en7581_gpio36_pins[] = { 49 }; 546static const int en7581_gpio37_pins[] = { 50 }; 547static const int en7581_gpio38_pins[] = { 51 }; 548static const int en7581_gpio39_pins[] = { 52 }; 549static const int en7581_gpio40_pins[] = { 53 }; 550static const int en7581_gpio41_pins[] = { 54 }; 551static const int en7581_gpio42_pins[] = { 55 }; 552static const int en7581_gpio43_pins[] = { 56 }; 553static const int en7581_gpio44_pins[] = { 57 }; 554static const int en7581_gpio45_pins[] = { 58 }; 555static const int en7581_gpio46_pins[] = { 59 }; 556static const int en7581_pcie_reset0_pins[] = { 61 }; 557static const int en7581_pcie_reset1_pins[] = { 62 }; 558static const int en7581_pcie_reset2_pins[] = { 63 }; 559 560static const struct pingroup en7581_pinctrl_groups[] = { 561 PINCTRL_PIN_GROUP("pon", en7581_pon), 562 PINCTRL_PIN_GROUP("pon_tod_1pps", en7581_pon_tod_1pps), 563 PINCTRL_PIN_GROUP("gsw_tod_1pps", en7581_gsw_tod_1pps), 564 PINCTRL_PIN_GROUP("sipo", en7581_sipo), 565 PINCTRL_PIN_GROUP("sipo_rclk", en7581_sipo_rclk), 566 PINCTRL_PIN_GROUP("mdio", en7581_mdio), 567 PINCTRL_PIN_GROUP("uart2", en7581_uart2), 568 PINCTRL_PIN_GROUP("uart2_cts_rts", en7581_uart2_cts_rts), 569 PINCTRL_PIN_GROUP("hsuart", en7581_hsuart), 570 PINCTRL_PIN_GROUP("hsuart_cts_rts", en7581_hsuart_cts_rts), 571 PINCTRL_PIN_GROUP("uart4", en7581_uart4), 572 PINCTRL_PIN_GROUP("uart5", en7581_uart5), 573 PINCTRL_PIN_GROUP("i2c0", en7581_i2c0), 574 PINCTRL_PIN_GROUP("i2c1", en7581_i2c1), 575 PINCTRL_PIN_GROUP("jtag_udi", en7581_jtag_udi), 576 PINCTRL_PIN_GROUP("jtag_dfd", en7581_jtag_dfd), 577 PINCTRL_PIN_GROUP("i2s", en7581_i2s), 578 PINCTRL_PIN_GROUP("pcm1", en7581_pcm1), 579 PINCTRL_PIN_GROUP("pcm2", en7581_pcm2), 580 PINCTRL_PIN_GROUP("spi", en7581_spi), 581 PINCTRL_PIN_GROUP("spi_quad", en7581_spi_quad), 582 PINCTRL_PIN_GROUP("spi_cs1", en7581_spi_cs1), 583 PINCTRL_PIN_GROUP("pcm_spi", en7581_pcm_spi), 584 PINCTRL_PIN_GROUP("pcm_spi_int", en7581_pcm_spi_int), 585 PINCTRL_PIN_GROUP("pcm_spi_rst", en7581_pcm_spi_rst), 586 PINCTRL_PIN_GROUP("pcm_spi_cs1", en7581_pcm_spi_cs1), 587 PINCTRL_PIN_GROUP("pcm_spi_cs2_p128", en7581_pcm_spi_cs2_p128), 588 PINCTRL_PIN_GROUP("pcm_spi_cs2_p156", en7581_pcm_spi_cs2_p156), 589 PINCTRL_PIN_GROUP("pcm_spi_cs2", en7581_pcm_spi_cs2), 590 PINCTRL_PIN_GROUP("pcm_spi_cs3", en7581_pcm_spi_cs3), 591 PINCTRL_PIN_GROUP("pcm_spi_cs4", en7581_pcm_spi_cs4), 592 PINCTRL_PIN_GROUP("emmc", en7581_emmc), 593 PINCTRL_PIN_GROUP("pnand", en7581_pnand), 594 PINCTRL_PIN_GROUP("gpio0", en7581_gpio0), 595 PINCTRL_PIN_GROUP("gpio1", en7581_gpio1), 596 PINCTRL_PIN_GROUP("gpio2", en7581_gpio2), 597 PINCTRL_PIN_GROUP("gpio3", en7581_gpio3), 598 PINCTRL_PIN_GROUP("gpio4", en7581_gpio4), 599 PINCTRL_PIN_GROUP("gpio5", en7581_gpio5), 600 PINCTRL_PIN_GROUP("gpio6", en7581_gpio6), 601 PINCTRL_PIN_GROUP("gpio7", en7581_gpio7), 602 PINCTRL_PIN_GROUP("gpio8", en7581_gpio8), 603 PINCTRL_PIN_GROUP("gpio9", en7581_gpio9), 604 PINCTRL_PIN_GROUP("gpio10", en7581_gpio10), 605 PINCTRL_PIN_GROUP("gpio11", en7581_gpio11), 606 PINCTRL_PIN_GROUP("gpio12", en7581_gpio12), 607 PINCTRL_PIN_GROUP("gpio13", en7581_gpio13), 608 PINCTRL_PIN_GROUP("gpio14", en7581_gpio14), 609 PINCTRL_PIN_GROUP("gpio15", en7581_gpio15), 610 PINCTRL_PIN_GROUP("gpio16", en7581_gpio16), 611 PINCTRL_PIN_GROUP("gpio17", en7581_gpio17), 612 PINCTRL_PIN_GROUP("gpio18", en7581_gpio18), 613 PINCTRL_PIN_GROUP("gpio19", en7581_gpio19), 614 PINCTRL_PIN_GROUP("gpio20", en7581_gpio20), 615 PINCTRL_PIN_GROUP("gpio21", en7581_gpio21), 616 PINCTRL_PIN_GROUP("gpio22", en7581_gpio22), 617 PINCTRL_PIN_GROUP("gpio23", en7581_gpio23), 618 PINCTRL_PIN_GROUP("gpio24", en7581_gpio24), 619 PINCTRL_PIN_GROUP("gpio25", en7581_gpio25), 620 PINCTRL_PIN_GROUP("gpio26", en7581_gpio26), 621 PINCTRL_PIN_GROUP("gpio27", en7581_gpio27), 622 PINCTRL_PIN_GROUP("gpio28", en7581_gpio28), 623 PINCTRL_PIN_GROUP("gpio29", en7581_gpio29), 624 PINCTRL_PIN_GROUP("gpio30", en7581_gpio30), 625 PINCTRL_PIN_GROUP("gpio31", en7581_gpio31), 626 PINCTRL_PIN_GROUP("gpio33", en7581_gpio33), 627 PINCTRL_PIN_GROUP("gpio34", en7581_gpio34), 628 PINCTRL_PIN_GROUP("gpio35", en7581_gpio35), 629 PINCTRL_PIN_GROUP("gpio36", en7581_gpio36), 630 PINCTRL_PIN_GROUP("gpio37", en7581_gpio37), 631 PINCTRL_PIN_GROUP("gpio38", en7581_gpio38), 632 PINCTRL_PIN_GROUP("gpio39", en7581_gpio39), 633 PINCTRL_PIN_GROUP("gpio40", en7581_gpio40), 634 PINCTRL_PIN_GROUP("gpio41", en7581_gpio41), 635 PINCTRL_PIN_GROUP("gpio42", en7581_gpio42), 636 PINCTRL_PIN_GROUP("gpio43", en7581_gpio43), 637 PINCTRL_PIN_GROUP("gpio44", en7581_gpio44), 638 PINCTRL_PIN_GROUP("gpio45", en7581_gpio45), 639 PINCTRL_PIN_GROUP("gpio46", en7581_gpio46), 640 PINCTRL_PIN_GROUP("pcie_reset0", en7581_pcie_reset0), 641 PINCTRL_PIN_GROUP("pcie_reset1", en7581_pcie_reset1), 642 PINCTRL_PIN_GROUP("pcie_reset2", en7581_pcie_reset2), 643}; 644 645static struct pinctrl_pin_desc an7583_pinctrl_pins[] = { 646 PINCTRL_PIN(2, "gpio0"), 647 PINCTRL_PIN(3, "gpio1"), 648 PINCTRL_PIN(4, "gpio2"), 649 PINCTRL_PIN(5, "gpio3"), 650 PINCTRL_PIN(6, "gpio4"), 651 PINCTRL_PIN(7, "gpio5"), 652 PINCTRL_PIN(8, "gpio6"), 653 PINCTRL_PIN(9, "gpio7"), 654 PINCTRL_PIN(10, "gpio8"), 655 PINCTRL_PIN(11, "gpio9"), 656 PINCTRL_PIN(12, "gpio10"), 657 PINCTRL_PIN(13, "gpio11"), 658 PINCTRL_PIN(14, "gpio12"), 659 PINCTRL_PIN(15, "gpio13"), 660 PINCTRL_PIN(16, "gpio14"), 661 PINCTRL_PIN(17, "gpio15"), 662 PINCTRL_PIN(18, "gpio16"), 663 PINCTRL_PIN(19, "gpio17"), 664 PINCTRL_PIN(20, "gpio18"), 665 PINCTRL_PIN(21, "gpio19"), 666 PINCTRL_PIN(22, "gpio20"), 667 PINCTRL_PIN(23, "gpio21"), 668 PINCTRL_PIN(24, "gpio22"), 669 PINCTRL_PIN(25, "gpio23"), 670 PINCTRL_PIN(26, "gpio24"), 671 PINCTRL_PIN(27, "gpio25"), 672 PINCTRL_PIN(28, "gpio26"), 673 PINCTRL_PIN(29, "gpio27"), 674 PINCTRL_PIN(30, "gpio28"), 675 PINCTRL_PIN(31, "gpio29"), 676 PINCTRL_PIN(32, "gpio30"), 677 PINCTRL_PIN(33, "gpio31"), 678 PINCTRL_PIN(34, "gpio32"), 679 PINCTRL_PIN(35, "gpio33"), 680 PINCTRL_PIN(36, "gpio34"), 681 PINCTRL_PIN(37, "gpio35"), 682 PINCTRL_PIN(38, "gpio36"), 683 PINCTRL_PIN(39, "gpio37"), 684 PINCTRL_PIN(40, "gpio38"), 685 PINCTRL_PIN(41, "i2c0_scl"), 686 PINCTRL_PIN(42, "i2c0_sda"), 687 PINCTRL_PIN(43, "i2c1_scl"), 688 PINCTRL_PIN(44, "i2c1_sda"), 689 PINCTRL_PIN(45, "spi_clk"), 690 PINCTRL_PIN(46, "spi_cs"), 691 PINCTRL_PIN(47, "spi_mosi"), 692 PINCTRL_PIN(48, "spi_miso"), 693 PINCTRL_PIN(49, "uart_txd"), 694 PINCTRL_PIN(50, "uart_rxd"), 695 PINCTRL_PIN(51, "pcie_reset0"), 696 PINCTRL_PIN(52, "pcie_reset1"), 697 PINCTRL_PIN(53, "mdc_0"), 698 PINCTRL_PIN(54, "mdio_0"), 699}; 700 701static const int an7583_pon_pins[] = { 15, 16, 17, 18, 19, 20 }; 702static const int an7583_pon_tod_1pps_pins[] = { 32 }; 703static const int an7583_gsw_tod_1pps_pins[] = { 32 }; 704static const int an7583_sipo_pins[] = { 34, 35 }; 705static const int an7583_sipo_rclk_pins[] = { 34, 35, 33 }; 706static const int an7583_mdio_pins[] = { 43, 44 }; 707static const int an7583_uart2_pins[] = { 34, 35 }; 708static const int an7583_uart2_cts_rts_pins[] = { 32, 33 }; 709static const int an7583_hsuart_pins[] = { 30, 31 }; 710static const int an7583_hsuart_cts_rts_pins[] = { 28, 29 }; 711static const int an7583_npu_uart_pins[] = { 7, 8 }; 712static const int an7583_uart4_pins[] = { 7, 8 }; 713static const int an7583_uart5_pins[] = { 23, 24 }; 714static const int an7583_i2c0_pins[] = { 41, 42 }; 715static const int an7583_i2c1_pins[] = { 43, 44 }; 716static const int an7583_jtag_udi_pins[] = { 23, 24, 22, 25, 26 }; 717static const int an7583_jtag_dfd_pins[] = { 23, 24, 22, 25, 26 }; 718static const int an7583_pcm1_pins[] = { 10, 11, 12, 13, 14 }; 719static const int an7583_pcm2_pins[] = { 28, 29, 30, 31, 24 }; 720static const int an7583_spi_pins[] = { 28, 29, 30, 31 }; 721static const int an7583_spi_quad_pins[] = { 25, 26 }; 722static const int an7583_spi_cs1_pins[] = { 27 }; 723static const int an7583_pcm_spi_pins[] = { 28, 29, 30, 31, 10, 11, 12, 13 }; 724static const int an7583_pcm_spi_rst_pins[] = { 14 }; 725static const int an7583_pcm_spi_cs1_pins[] = { 24 }; 726static const int an7583_emmc_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 45, 46, 47 }; 727static const int an7583_pnand_pins[] = { 7, 8, 9, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 45, 46, 47, 48 }; 728static const int an7583_gpio0_pins[] = { 2 }; 729static const int an7583_gpio1_pins[] = { 3 }; 730static const int an7583_gpio2_pins[] = { 4 }; 731static const int an7583_gpio3_pins[] = { 5 }; 732static const int an7583_gpio4_pins[] = { 6 }; 733static const int an7583_gpio5_pins[] = { 7 }; 734static const int an7583_gpio6_pins[] = { 8 }; 735static const int an7583_gpio7_pins[] = { 9 }; 736static const int an7583_gpio8_pins[] = { 10 }; 737static const int an7583_gpio9_pins[] = { 11 }; 738static const int an7583_gpio10_pins[] = { 12 }; 739static const int an7583_gpio11_pins[] = { 13 }; 740static const int an7583_gpio12_pins[] = { 14 }; 741static const int an7583_gpio13_pins[] = { 15 }; 742static const int an7583_gpio14_pins[] = { 16 }; 743static const int an7583_gpio15_pins[] = { 17 }; 744static const int an7583_gpio16_pins[] = { 18 }; 745static const int an7583_gpio17_pins[] = { 19 }; 746static const int an7583_gpio18_pins[] = { 20 }; 747static const int an7583_gpio19_pins[] = { 21 }; 748static const int an7583_gpio20_pins[] = { 22 }; 749static const int an7583_gpio21_pins[] = { 24 }; 750static const int an7583_gpio23_pins[] = { 25 }; 751static const int an7583_gpio24_pins[] = { 26 }; 752static const int an7583_gpio25_pins[] = { 27 }; 753static const int an7583_gpio26_pins[] = { 28 }; 754static const int an7583_gpio27_pins[] = { 29 }; 755static const int an7583_gpio28_pins[] = { 30 }; 756static const int an7583_gpio29_pins[] = { 31 }; 757static const int an7583_gpio30_pins[] = { 32 }; 758static const int an7583_gpio31_pins[] = { 33 }; 759static const int an7583_gpio33_pins[] = { 35 }; 760static const int an7583_gpio34_pins[] = { 36 }; 761static const int an7583_gpio35_pins[] = { 37 }; 762static const int an7583_gpio36_pins[] = { 38 }; 763static const int an7583_gpio37_pins[] = { 39 }; 764static const int an7583_gpio38_pins[] = { 40 }; 765static const int an7583_gpio39_pins[] = { 41 }; 766static const int an7583_gpio40_pins[] = { 42 }; 767static const int an7583_gpio41_pins[] = { 43 }; 768static const int an7583_gpio42_pins[] = { 44 }; 769static const int an7583_gpio43_pins[] = { 45 }; 770static const int an7583_gpio44_pins[] = { 46 }; 771static const int an7583_gpio45_pins[] = { 47 }; 772static const int an7583_gpio46_pins[] = { 48 }; 773static const int an7583_gpio47_pins[] = { 49 }; 774static const int an7583_gpio48_pins[] = { 50 }; 775static const int an7583_pcie_reset0_pins[] = { 51 }; 776static const int an7583_pcie_reset1_pins[] = { 52 }; 777 778static const struct pingroup an7583_pinctrl_groups[] = { 779 PINCTRL_PIN_GROUP("pon", an7583_pon), 780 PINCTRL_PIN_GROUP("pon_tod_1pps", an7583_pon_tod_1pps), 781 PINCTRL_PIN_GROUP("gsw_tod_1pps", an7583_gsw_tod_1pps), 782 PINCTRL_PIN_GROUP("sipo", an7583_sipo), 783 PINCTRL_PIN_GROUP("sipo_rclk", an7583_sipo_rclk), 784 PINCTRL_PIN_GROUP("mdio", an7583_mdio), 785 PINCTRL_PIN_GROUP("uart2", an7583_uart2), 786 PINCTRL_PIN_GROUP("uart2_cts_rts", an7583_uart2_cts_rts), 787 PINCTRL_PIN_GROUP("hsuart", an7583_hsuart), 788 PINCTRL_PIN_GROUP("hsuart_cts_rts", an7583_hsuart_cts_rts), 789 PINCTRL_PIN_GROUP("npu_uart", an7583_npu_uart), 790 PINCTRL_PIN_GROUP("uart4", an7583_uart4), 791 PINCTRL_PIN_GROUP("uart5", an7583_uart5), 792 PINCTRL_PIN_GROUP("i2c0", an7583_i2c0), 793 PINCTRL_PIN_GROUP("i2c1", an7583_i2c1), 794 PINCTRL_PIN_GROUP("jtag_udi", an7583_jtag_udi), 795 PINCTRL_PIN_GROUP("jtag_dfd", an7583_jtag_dfd), 796 PINCTRL_PIN_GROUP("pcm1", an7583_pcm1), 797 PINCTRL_PIN_GROUP("pcm2", an7583_pcm2), 798 PINCTRL_PIN_GROUP("spi", an7583_spi), 799 PINCTRL_PIN_GROUP("spi_quad", an7583_spi_quad), 800 PINCTRL_PIN_GROUP("spi_cs1", an7583_spi_cs1), 801 PINCTRL_PIN_GROUP("pcm_spi", an7583_pcm_spi), 802 PINCTRL_PIN_GROUP("pcm_spi_rst", an7583_pcm_spi_rst), 803 PINCTRL_PIN_GROUP("pcm_spi_cs1", an7583_pcm_spi_cs1), 804 PINCTRL_PIN_GROUP("emmc", an7583_emmc), 805 PINCTRL_PIN_GROUP("pnand", an7583_pnand), 806 PINCTRL_PIN_GROUP("gpio0", an7583_gpio0), 807 PINCTRL_PIN_GROUP("gpio1", an7583_gpio1), 808 PINCTRL_PIN_GROUP("gpio2", an7583_gpio2), 809 PINCTRL_PIN_GROUP("gpio3", an7583_gpio3), 810 PINCTRL_PIN_GROUP("gpio4", an7583_gpio4), 811 PINCTRL_PIN_GROUP("gpio5", an7583_gpio5), 812 PINCTRL_PIN_GROUP("gpio6", an7583_gpio6), 813 PINCTRL_PIN_GROUP("gpio7", an7583_gpio7), 814 PINCTRL_PIN_GROUP("gpio8", an7583_gpio8), 815 PINCTRL_PIN_GROUP("gpio9", an7583_gpio9), 816 PINCTRL_PIN_GROUP("gpio10", an7583_gpio10), 817 PINCTRL_PIN_GROUP("gpio11", an7583_gpio11), 818 PINCTRL_PIN_GROUP("gpio12", an7583_gpio12), 819 PINCTRL_PIN_GROUP("gpio13", an7583_gpio13), 820 PINCTRL_PIN_GROUP("gpio14", an7583_gpio14), 821 PINCTRL_PIN_GROUP("gpio15", an7583_gpio15), 822 PINCTRL_PIN_GROUP("gpio16", an7583_gpio16), 823 PINCTRL_PIN_GROUP("gpio17", an7583_gpio17), 824 PINCTRL_PIN_GROUP("gpio18", an7583_gpio18), 825 PINCTRL_PIN_GROUP("gpio19", an7583_gpio19), 826 PINCTRL_PIN_GROUP("gpio20", an7583_gpio20), 827 PINCTRL_PIN_GROUP("gpio21", an7583_gpio21), 828 PINCTRL_PIN_GROUP("gpio23", an7583_gpio23), 829 PINCTRL_PIN_GROUP("gpio24", an7583_gpio24), 830 PINCTRL_PIN_GROUP("gpio25", an7583_gpio25), 831 PINCTRL_PIN_GROUP("gpio26", an7583_gpio26), 832 PINCTRL_PIN_GROUP("gpio27", an7583_gpio27), 833 PINCTRL_PIN_GROUP("gpio28", an7583_gpio28), 834 PINCTRL_PIN_GROUP("gpio29", an7583_gpio29), 835 PINCTRL_PIN_GROUP("gpio30", an7583_gpio30), 836 PINCTRL_PIN_GROUP("gpio31", an7583_gpio31), 837 PINCTRL_PIN_GROUP("gpio33", an7583_gpio33), 838 PINCTRL_PIN_GROUP("gpio34", an7583_gpio34), 839 PINCTRL_PIN_GROUP("gpio35", an7583_gpio35), 840 PINCTRL_PIN_GROUP("gpio36", an7583_gpio36), 841 PINCTRL_PIN_GROUP("gpio37", an7583_gpio37), 842 PINCTRL_PIN_GROUP("gpio38", an7583_gpio38), 843 PINCTRL_PIN_GROUP("gpio39", an7583_gpio39), 844 PINCTRL_PIN_GROUP("gpio40", an7583_gpio40), 845 PINCTRL_PIN_GROUP("gpio41", an7583_gpio41), 846 PINCTRL_PIN_GROUP("gpio42", an7583_gpio42), 847 PINCTRL_PIN_GROUP("gpio43", an7583_gpio43), 848 PINCTRL_PIN_GROUP("gpio44", an7583_gpio44), 849 PINCTRL_PIN_GROUP("gpio45", an7583_gpio45), 850 PINCTRL_PIN_GROUP("gpio46", an7583_gpio46), 851 PINCTRL_PIN_GROUP("gpio47", an7583_gpio47), 852 PINCTRL_PIN_GROUP("gpio48", an7583_gpio48), 853 PINCTRL_PIN_GROUP("pcie_reset0", an7583_pcie_reset0), 854 PINCTRL_PIN_GROUP("pcie_reset1", an7583_pcie_reset1), 855}; 856 857static const char *const pon_groups[] = { "pon" }; 858static const char *const tod_1pps_groups[] = { "pon_tod_1pps", "gsw_tod_1pps" }; 859static const char *const sipo_groups[] = { "sipo", "sipo_rclk" }; 860static const char *const mdio_groups[] = { "mdio" }; 861static const char *const an7583_mdio_groups[] = { "mdio" }; 862static const char *const uart_groups[] = { "uart2", "uart2_cts_rts", "hsuart", 863 "hsuart_cts_rts", "uart4", 864 "uart5" }; 865static const char *const i2c_groups[] = { "i2c1" }; 866static const char *const jtag_groups[] = { "jtag_udi", "jtag_dfd" }; 867static const char *const pcm_groups[] = { "pcm1", "pcm2" }; 868static const char *const spi_groups[] = { "spi_quad", "spi_cs1" }; 869static const char *const pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", 870 "pcm_spi_rst", "pcm_spi_cs1", 871 "pcm_spi_cs2_p156", 872 "pcm_spi_cs2_p128", 873 "pcm_spi_cs3", "pcm_spi_cs4" }; 874static const char *const an7583_pcm_spi_groups[] = { "pcm_spi", "pcm_spi_int", 875 "pcm_spi_rst", "pcm_spi_cs1", 876 "pcm_spi_cs2", "pcm_spi_cs3", 877 "pcm_spi_cs4" }; 878static const char *const i2s_groups[] = { "i2s" }; 879static const char *const emmc_groups[] = { "emmc" }; 880static const char *const pnand_groups[] = { "pnand" }; 881static const char *const pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1", 882 "pcie_reset2" }; 883static const char *const an7583_pcie_reset_groups[] = { "pcie_reset0", "pcie_reset1" }; 884static const char *const pwm_groups[] = { "gpio0", "gpio1", 885 "gpio2", "gpio3", 886 "gpio4", "gpio5", 887 "gpio6", "gpio7", 888 "gpio8", "gpio9", 889 "gpio10", "gpio11", 890 "gpio12", "gpio13", 891 "gpio14", "gpio15", 892 "gpio16", "gpio17", 893 "gpio18", "gpio19", 894 "gpio20", "gpio21", 895 "gpio22", "gpio23", 896 "gpio24", "gpio25", 897 "gpio26", "gpio27", 898 "gpio28", "gpio29", 899 "gpio30", "gpio31", 900 "gpio36", "gpio37", 901 "gpio38", "gpio39", 902 "gpio40", "gpio41", 903 "gpio42", "gpio43", 904 "gpio44", "gpio45", 905 "gpio46", "gpio47" }; 906static const char *const phy1_led0_groups[] = { "gpio33", "gpio34", 907 "gpio35", "gpio42" }; 908static const char *const phy2_led0_groups[] = { "gpio33", "gpio34", 909 "gpio35", "gpio42" }; 910static const char *const phy3_led0_groups[] = { "gpio33", "gpio34", 911 "gpio35", "gpio42" }; 912static const char *const phy4_led0_groups[] = { "gpio33", "gpio34", 913 "gpio35", "gpio42" }; 914static const char *const phy1_led1_groups[] = { "gpio43", "gpio44", 915 "gpio45", "gpio46" }; 916static const char *const phy2_led1_groups[] = { "gpio43", "gpio44", 917 "gpio45", "gpio46" }; 918static const char *const phy3_led1_groups[] = { "gpio43", "gpio44", 919 "gpio45", "gpio46" }; 920static const char *const phy4_led1_groups[] = { "gpio43", "gpio44", 921 "gpio45", "gpio46" }; 922static const char *const an7583_phy1_led0_groups[] = { "gpio1", "gpio2", 923 "gpio3", "gpio4" }; 924static const char *const an7583_phy2_led0_groups[] = { "gpio1", "gpio2", 925 "gpio3", "gpio4" }; 926static const char *const an7583_phy3_led0_groups[] = { "gpio1", "gpio2", 927 "gpio3", "gpio4" }; 928static const char *const an7583_phy4_led0_groups[] = { "gpio1", "gpio2", 929 "gpio3", "gpio4" }; 930static const char *const an7583_phy1_led1_groups[] = { "gpio8", "gpio9", 931 "gpio10", "gpio11" }; 932static const char *const an7583_phy2_led1_groups[] = { "gpio8", "gpio9", 933 "gpio10", "gpio11" }; 934static const char *const an7583_phy3_led1_groups[] = { "gpio8", "gpio9", 935 "gpio10", "gpio11" }; 936static const char *const an7583_phy4_led1_groups[] = { "gpio8", "gpio9", 937 "gpio10", "gpio11" }; 938 939static const struct airoha_pinctrl_func_group pon_func_group[] = { 940 { 941 .name = "pon", 942 .regmap[0] = { 943 AIROHA_FUNC_MUX, 944 REG_GPIO_PON_MODE, 945 GPIO_PON_MODE_MASK, 946 GPIO_PON_MODE_MASK 947 }, 948 .regmap_size = 1, 949 }, 950}; 951 952static const struct airoha_pinctrl_func_group tod_1pps_func_group[] = { 953 { 954 .name = "pon_tod_1pps", 955 .regmap[0] = { 956 AIROHA_FUNC_MUX, 957 REG_GPIO_2ND_I2C_MODE, 958 PON_TOD_1PPS_MODE_MASK, 959 PON_TOD_1PPS_MODE_MASK 960 }, 961 .regmap_size = 1, 962 }, { 963 .name = "gsw_tod_1pps", 964 .regmap[0] = { 965 AIROHA_FUNC_MUX, 966 REG_GPIO_2ND_I2C_MODE, 967 GSW_TOD_1PPS_MODE_MASK, 968 GSW_TOD_1PPS_MODE_MASK 969 }, 970 .regmap_size = 1, 971 }, 972}; 973 974static const struct airoha_pinctrl_func_group sipo_func_group[] = { 975 { 976 .name = "sipo", 977 .regmap[0] = { 978 AIROHA_FUNC_MUX, 979 REG_GPIO_PON_MODE, 980 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 981 GPIO_SIPO_MODE_MASK 982 }, 983 .regmap_size = 1, 984 }, { 985 .name = "sipo_rclk", 986 .regmap[0] = { 987 AIROHA_FUNC_MUX, 988 REG_GPIO_PON_MODE, 989 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK, 990 GPIO_SIPO_MODE_MASK | SIPO_RCLK_MODE_MASK 991 }, 992 .regmap_size = 1, 993 }, 994}; 995 996static const struct airoha_pinctrl_func_group mdio_func_group[] = { 997 { 998 .name = "mdio", 999 .regmap[0] = { 1000 AIROHA_FUNC_MUX, 1001 REG_GPIO_2ND_I2C_MODE, 1002 GPIO_MDC_IO_MASTER_MODE_MODE, 1003 GPIO_MDC_IO_MASTER_MODE_MODE 1004 }, 1005 .regmap[1] = { 1006 AIROHA_FUNC_MUX, 1007 REG_FORCE_GPIO_EN, 1008 FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2), 1009 FORCE_GPIO_EN(1) | FORCE_GPIO_EN(2) 1010 }, 1011 .regmap_size = 2, 1012 }, 1013}; 1014 1015static const struct airoha_pinctrl_func_group an7583_mdio_func_group[] = { 1016 { 1017 .name = "mdio", 1018 .regmap[0] = { 1019 AIROHA_FUNC_MUX, 1020 REG_GPIO_PON_MODE, 1021 GPIO_SGMII_MDIO_MODE_MASK, 1022 GPIO_SGMII_MDIO_MODE_MASK 1023 }, 1024 .regmap[1] = { 1025 AIROHA_FUNC_MUX, 1026 REG_GPIO_SPI_CS1_MODE, 1027 GPIO_MDC_IO_MASTER_MODE_MODE, 1028 GPIO_MDC_IO_MASTER_MODE_MODE 1029 }, 1030 .regmap_size = 2, 1031 }, 1032}; 1033 1034static const struct airoha_pinctrl_func_group uart_func_group[] = { 1035 { 1036 .name = "uart2", 1037 .regmap[0] = { 1038 AIROHA_FUNC_MUX, 1039 REG_GPIO_PON_MODE, 1040 GPIO_UART2_MODE_MASK, 1041 GPIO_UART2_MODE_MASK 1042 }, 1043 .regmap_size = 1, 1044 }, { 1045 .name = "uart2_cts_rts", 1046 .regmap[0] = { 1047 AIROHA_FUNC_MUX, 1048 REG_GPIO_PON_MODE, 1049 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK, 1050 GPIO_UART2_MODE_MASK | GPIO_UART2_CTS_RTS_MODE_MASK 1051 }, 1052 .regmap_size = 1, 1053 }, { 1054 .name = "hsuart", 1055 .regmap[0] = { 1056 AIROHA_FUNC_MUX, 1057 REG_GPIO_PON_MODE, 1058 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 1059 GPIO_HSUART_MODE_MASK 1060 }, 1061 .regmap_size = 1, 1062 }, 1063 { 1064 .name = "hsuart_cts_rts", 1065 .regmap[0] = { 1066 AIROHA_FUNC_MUX, 1067 REG_GPIO_PON_MODE, 1068 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK, 1069 GPIO_HSUART_MODE_MASK | GPIO_HSUART_CTS_RTS_MODE_MASK 1070 }, 1071 .regmap_size = 1, 1072 }, { 1073 .name = "uart4", 1074 .regmap[0] = { 1075 AIROHA_FUNC_MUX, 1076 REG_GPIO_PON_MODE, 1077 GPIO_UART4_MODE_MASK, 1078 GPIO_UART4_MODE_MASK 1079 }, 1080 .regmap_size = 1, 1081 }, { 1082 .name = "uart5", 1083 .regmap[0] = { 1084 AIROHA_FUNC_MUX, 1085 REG_GPIO_PON_MODE, 1086 GPIO_UART5_MODE_MASK, 1087 GPIO_UART5_MODE_MASK 1088 }, 1089 .regmap_size = 1, 1090 }, 1091}; 1092 1093static const struct airoha_pinctrl_func_group i2c_func_group[] = { 1094 { 1095 .name = "i2c1", 1096 .regmap[0] = { 1097 AIROHA_FUNC_MUX, 1098 REG_GPIO_2ND_I2C_MODE, 1099 GPIO_2ND_I2C_MODE_MASK, 1100 GPIO_2ND_I2C_MODE_MASK 1101 }, 1102 .regmap_size = 1, 1103 }, 1104}; 1105 1106static const struct airoha_pinctrl_func_group jtag_func_group[] = { 1107 { 1108 .name = "jtag_udi", 1109 .regmap[0] = { 1110 AIROHA_FUNC_MUX, 1111 REG_NPU_UART_EN, 1112 JTAG_UDI_EN_MASK, 1113 JTAG_UDI_EN_MASK 1114 }, 1115 .regmap_size = 1, 1116 }, { 1117 .name = "jtag_dfd", 1118 .regmap[0] = { 1119 AIROHA_FUNC_MUX, 1120 REG_NPU_UART_EN, 1121 JTAG_DFD_EN_MASK, 1122 JTAG_DFD_EN_MASK 1123 }, 1124 .regmap_size = 1, 1125 }, 1126}; 1127 1128static const struct airoha_pinctrl_func_group pcm_func_group[] = { 1129 { 1130 .name = "pcm1", 1131 .regmap[0] = { 1132 AIROHA_FUNC_MUX, 1133 REG_GPIO_SPI_CS1_MODE, 1134 GPIO_PCM1_MODE_MASK, 1135 GPIO_PCM1_MODE_MASK 1136 }, 1137 .regmap_size = 1, 1138 }, { 1139 .name = "pcm2", 1140 .regmap[0] = { 1141 AIROHA_FUNC_MUX, 1142 REG_GPIO_SPI_CS1_MODE, 1143 GPIO_PCM2_MODE_MASK, 1144 GPIO_PCM2_MODE_MASK 1145 }, 1146 .regmap_size = 1, 1147 }, 1148}; 1149 1150static const struct airoha_pinctrl_func_group spi_func_group[] = { 1151 { 1152 .name = "spi_quad", 1153 .regmap[0] = { 1154 AIROHA_FUNC_MUX, 1155 REG_GPIO_SPI_CS1_MODE, 1156 GPIO_SPI_QUAD_MODE_MASK, 1157 GPIO_SPI_QUAD_MODE_MASK 1158 }, 1159 .regmap_size = 1, 1160 }, { 1161 .name = "spi_cs1", 1162 .regmap[0] = { 1163 AIROHA_FUNC_MUX, 1164 REG_GPIO_SPI_CS1_MODE, 1165 GPIO_SPI_CS1_MODE_MASK, 1166 GPIO_SPI_CS1_MODE_MASK 1167 }, 1168 .regmap_size = 1, 1169 }, { 1170 .name = "spi_cs2", 1171 .regmap[0] = { 1172 AIROHA_FUNC_MUX, 1173 REG_GPIO_SPI_CS1_MODE, 1174 GPIO_SPI_CS2_MODE_MASK, 1175 GPIO_SPI_CS2_MODE_MASK 1176 }, 1177 .regmap_size = 1, 1178 }, { 1179 .name = "spi_cs3", 1180 .regmap[0] = { 1181 AIROHA_FUNC_MUX, 1182 REG_GPIO_SPI_CS1_MODE, 1183 GPIO_SPI_CS3_MODE_MASK, 1184 GPIO_SPI_CS3_MODE_MASK 1185 }, 1186 .regmap_size = 1, 1187 }, { 1188 .name = "spi_cs4", 1189 .regmap[0] = { 1190 AIROHA_FUNC_MUX, 1191 REG_GPIO_SPI_CS1_MODE, 1192 GPIO_SPI_CS4_MODE_MASK, 1193 GPIO_SPI_CS4_MODE_MASK 1194 }, 1195 .regmap_size = 1, 1196 }, 1197}; 1198 1199static const struct airoha_pinctrl_func_group pcm_spi_func_group[] = { 1200 { 1201 .name = "pcm_spi", 1202 .regmap[0] = { 1203 AIROHA_FUNC_MUX, 1204 REG_GPIO_SPI_CS1_MODE, 1205 GPIO_PCM_SPI_MODE_MASK, 1206 GPIO_PCM_SPI_MODE_MASK 1207 }, 1208 .regmap_size = 1, 1209 }, { 1210 .name = "pcm_spi_int", 1211 .regmap[0] = { 1212 AIROHA_FUNC_MUX, 1213 REG_GPIO_SPI_CS1_MODE, 1214 GPIO_PCM_INT_MODE_MASK, 1215 GPIO_PCM_INT_MODE_MASK 1216 }, 1217 .regmap_size = 1, 1218 }, { 1219 .name = "pcm_spi_rst", 1220 .regmap[0] = { 1221 AIROHA_FUNC_MUX, 1222 REG_GPIO_SPI_CS1_MODE, 1223 GPIO_PCM_RESET_MODE_MASK, 1224 GPIO_PCM_RESET_MODE_MASK 1225 }, 1226 .regmap_size = 1, 1227 }, { 1228 .name = "pcm_spi_cs1", 1229 .regmap[0] = { 1230 AIROHA_FUNC_MUX, 1231 REG_GPIO_SPI_CS1_MODE, 1232 GPIO_PCM_SPI_CS1_MODE_MASK, 1233 GPIO_PCM_SPI_CS1_MODE_MASK 1234 }, 1235 .regmap_size = 1, 1236 }, { 1237 .name = "pcm_spi_cs2_p128", 1238 .regmap[0] = { 1239 AIROHA_FUNC_MUX, 1240 REG_GPIO_SPI_CS1_MODE, 1241 GPIO_PCM_SPI_CS2_MODE_P128_MASK, 1242 GPIO_PCM_SPI_CS2_MODE_P128_MASK 1243 }, 1244 .regmap_size = 1, 1245 }, { 1246 .name = "pcm_spi_cs2_p156", 1247 .regmap[0] = { 1248 AIROHA_FUNC_MUX, 1249 REG_GPIO_SPI_CS1_MODE, 1250 GPIO_PCM_SPI_CS2_MODE_P156_MASK, 1251 GPIO_PCM_SPI_CS2_MODE_P156_MASK 1252 }, 1253 .regmap_size = 1, 1254 }, { 1255 .name = "pcm_spi_cs3", 1256 .regmap[0] = { 1257 AIROHA_FUNC_MUX, 1258 REG_GPIO_SPI_CS1_MODE, 1259 GPIO_PCM_SPI_CS3_MODE_MASK, 1260 GPIO_PCM_SPI_CS3_MODE_MASK 1261 }, 1262 .regmap_size = 1, 1263 }, { 1264 .name = "pcm_spi_cs4", 1265 .regmap[0] = { 1266 AIROHA_FUNC_MUX, 1267 REG_GPIO_SPI_CS1_MODE, 1268 GPIO_PCM_SPI_CS4_MODE_MASK, 1269 GPIO_PCM_SPI_CS4_MODE_MASK 1270 }, 1271 .regmap_size = 1, 1272 }, 1273}; 1274 1275static const struct airoha_pinctrl_func_group an7583_pcm_spi_func_group[] = { 1276 { 1277 .name = "pcm_spi", 1278 .regmap[0] = { 1279 AIROHA_FUNC_MUX, 1280 REG_GPIO_SPI_CS1_MODE, 1281 GPIO_PCM_SPI_MODE_MASK, 1282 GPIO_PCM_SPI_MODE_MASK 1283 }, 1284 .regmap_size = 1, 1285 }, { 1286 .name = "pcm_spi_int", 1287 .regmap[0] = { 1288 AIROHA_FUNC_MUX, 1289 REG_GPIO_SPI_CS1_MODE, 1290 GPIO_PCM_INT_MODE_MASK, 1291 GPIO_PCM_INT_MODE_MASK 1292 }, 1293 .regmap_size = 1, 1294 }, { 1295 .name = "pcm_spi_rst", 1296 .regmap[0] = { 1297 AIROHA_FUNC_MUX, 1298 REG_GPIO_SPI_CS1_MODE, 1299 GPIO_PCM_RESET_MODE_MASK, 1300 GPIO_PCM_RESET_MODE_MASK 1301 }, 1302 .regmap_size = 1, 1303 }, { 1304 .name = "pcm_spi_cs1", 1305 .regmap[0] = { 1306 AIROHA_FUNC_MUX, 1307 REG_GPIO_SPI_CS1_MODE, 1308 GPIO_PCM_SPI_CS1_MODE_MASK, 1309 GPIO_PCM_SPI_CS1_MODE_MASK 1310 }, 1311 .regmap_size = 1, 1312 }, { 1313 .name = "pcm_spi_cs2", 1314 .regmap[0] = { 1315 AIROHA_FUNC_MUX, 1316 REG_GPIO_SPI_CS1_MODE, 1317 AN7583_GPIO_PCM_SPI_CS2_MODE_MASK, 1318 AN7583_GPIO_PCM_SPI_CS2_MODE_MASK 1319 }, 1320 .regmap_size = 1, 1321 }, { 1322 .name = "pcm_spi_cs3", 1323 .regmap[0] = { 1324 AIROHA_FUNC_MUX, 1325 REG_GPIO_SPI_CS1_MODE, 1326 GPIO_PCM_SPI_CS3_MODE_MASK, 1327 GPIO_PCM_SPI_CS3_MODE_MASK 1328 }, 1329 .regmap_size = 1, 1330 }, { 1331 .name = "pcm_spi_cs4", 1332 .regmap[0] = { 1333 AIROHA_FUNC_MUX, 1334 REG_GPIO_SPI_CS1_MODE, 1335 GPIO_PCM_SPI_CS4_MODE_MASK, 1336 GPIO_PCM_SPI_CS4_MODE_MASK 1337 }, 1338 .regmap_size = 1, 1339 }, 1340}; 1341 1342static const struct airoha_pinctrl_func_group i2s_func_group[] = { 1343 { 1344 .name = "i2s", 1345 .regmap[0] = { 1346 AIROHA_FUNC_MUX, 1347 REG_GPIO_2ND_I2C_MODE, 1348 GPIO_I2S_MODE_MASK, 1349 GPIO_I2S_MODE_MASK 1350 }, 1351 .regmap_size = 1, 1352 }, 1353}; 1354 1355static const struct airoha_pinctrl_func_group emmc_func_group[] = { 1356 { 1357 .name = "emmc", 1358 .regmap[0] = { 1359 AIROHA_FUNC_MUX, 1360 REG_GPIO_PON_MODE, 1361 GPIO_EMMC_MODE_MASK, 1362 GPIO_EMMC_MODE_MASK 1363 }, 1364 .regmap_size = 1, 1365 }, 1366}; 1367 1368static const struct airoha_pinctrl_func_group pnand_func_group[] = { 1369 { 1370 .name = "pnand", 1371 .regmap[0] = { 1372 AIROHA_FUNC_MUX, 1373 REG_GPIO_PON_MODE, 1374 GPIO_PARALLEL_NAND_MODE_MASK, 1375 GPIO_PARALLEL_NAND_MODE_MASK 1376 }, 1377 .regmap_size = 1, 1378 }, 1379}; 1380 1381static const struct airoha_pinctrl_func_group pcie_reset_func_group[] = { 1382 { 1383 .name = "pcie_reset0", 1384 .regmap[0] = { 1385 AIROHA_FUNC_MUX, 1386 REG_GPIO_PON_MODE, 1387 GPIO_PCIE_RESET0_MASK, 1388 GPIO_PCIE_RESET0_MASK 1389 }, 1390 .regmap_size = 1, 1391 }, { 1392 .name = "pcie_reset1", 1393 .regmap[0] = { 1394 AIROHA_FUNC_MUX, 1395 REG_GPIO_PON_MODE, 1396 GPIO_PCIE_RESET1_MASK, 1397 GPIO_PCIE_RESET1_MASK 1398 }, 1399 .regmap_size = 1, 1400 }, { 1401 .name = "pcie_reset2", 1402 .regmap[0] = { 1403 AIROHA_FUNC_MUX, 1404 REG_GPIO_PON_MODE, 1405 GPIO_PCIE_RESET2_MASK, 1406 GPIO_PCIE_RESET2_MASK 1407 }, 1408 .regmap_size = 1, 1409 }, 1410}; 1411 1412static const struct airoha_pinctrl_func_group an7583_pcie_reset_func_group[] = { 1413 { 1414 .name = "pcie_reset0", 1415 .regmap[0] = { 1416 AIROHA_FUNC_MUX, 1417 REG_GPIO_PON_MODE, 1418 GPIO_PCIE_RESET0_MASK, 1419 GPIO_PCIE_RESET0_MASK 1420 }, 1421 .regmap_size = 1, 1422 }, { 1423 .name = "pcie_reset1", 1424 .regmap[0] = { 1425 AIROHA_FUNC_MUX, 1426 REG_GPIO_PON_MODE, 1427 GPIO_PCIE_RESET1_MASK, 1428 GPIO_PCIE_RESET1_MASK 1429 }, 1430 .regmap_size = 1, 1431 }, 1432}; 1433 1434/* PWM */ 1435#define AIROHA_PINCTRL_PWM(gpio, mux_val) \ 1436 { \ 1437 .name = (gpio), \ 1438 .regmap[0] = { \ 1439 AIROHA_FUNC_PWM_MUX, \ 1440 REG_GPIO_FLASH_MODE_CFG, \ 1441 (mux_val), \ 1442 (mux_val) \ 1443 }, \ 1444 .regmap_size = 1, \ 1445 } \ 1446 1447#define AIROHA_PINCTRL_PWM_EXT(gpio, mux_val) \ 1448 { \ 1449 .name = (gpio), \ 1450 .regmap[0] = { \ 1451 AIROHA_FUNC_PWM_EXT_MUX, \ 1452 REG_GPIO_FLASH_MODE_CFG_EXT, \ 1453 (mux_val), \ 1454 (mux_val) \ 1455 }, \ 1456 .regmap_size = 1, \ 1457 } \ 1458 1459static const struct airoha_pinctrl_func_group pwm_func_group[] = { 1460 AIROHA_PINCTRL_PWM("gpio0", GPIO0_FLASH_MODE_CFG), 1461 AIROHA_PINCTRL_PWM("gpio1", GPIO1_FLASH_MODE_CFG), 1462 AIROHA_PINCTRL_PWM("gpio2", GPIO2_FLASH_MODE_CFG), 1463 AIROHA_PINCTRL_PWM("gpio3", GPIO3_FLASH_MODE_CFG), 1464 AIROHA_PINCTRL_PWM("gpio4", GPIO4_FLASH_MODE_CFG), 1465 AIROHA_PINCTRL_PWM("gpio5", GPIO5_FLASH_MODE_CFG), 1466 AIROHA_PINCTRL_PWM("gpio6", GPIO6_FLASH_MODE_CFG), 1467 AIROHA_PINCTRL_PWM("gpio7", GPIO7_FLASH_MODE_CFG), 1468 AIROHA_PINCTRL_PWM("gpio8", GPIO8_FLASH_MODE_CFG), 1469 AIROHA_PINCTRL_PWM("gpio9", GPIO9_FLASH_MODE_CFG), 1470 AIROHA_PINCTRL_PWM("gpio10", GPIO10_FLASH_MODE_CFG), 1471 AIROHA_PINCTRL_PWM("gpio11", GPIO11_FLASH_MODE_CFG), 1472 AIROHA_PINCTRL_PWM("gpio12", GPIO12_FLASH_MODE_CFG), 1473 AIROHA_PINCTRL_PWM("gpio13", GPIO13_FLASH_MODE_CFG), 1474 AIROHA_PINCTRL_PWM("gpio14", GPIO14_FLASH_MODE_CFG), 1475 AIROHA_PINCTRL_PWM("gpio15", GPIO15_FLASH_MODE_CFG), 1476 AIROHA_PINCTRL_PWM_EXT("gpio16", GPIO16_FLASH_MODE_CFG), 1477 AIROHA_PINCTRL_PWM_EXT("gpio17", GPIO17_FLASH_MODE_CFG), 1478 AIROHA_PINCTRL_PWM_EXT("gpio18", GPIO18_FLASH_MODE_CFG), 1479 AIROHA_PINCTRL_PWM_EXT("gpio19", GPIO19_FLASH_MODE_CFG), 1480 AIROHA_PINCTRL_PWM_EXT("gpio20", GPIO20_FLASH_MODE_CFG), 1481 AIROHA_PINCTRL_PWM_EXT("gpio21", GPIO21_FLASH_MODE_CFG), 1482 AIROHA_PINCTRL_PWM_EXT("gpio22", GPIO22_FLASH_MODE_CFG), 1483 AIROHA_PINCTRL_PWM_EXT("gpio23", GPIO23_FLASH_MODE_CFG), 1484 AIROHA_PINCTRL_PWM_EXT("gpio24", GPIO24_FLASH_MODE_CFG), 1485 AIROHA_PINCTRL_PWM_EXT("gpio25", GPIO25_FLASH_MODE_CFG), 1486 AIROHA_PINCTRL_PWM_EXT("gpio26", GPIO26_FLASH_MODE_CFG), 1487 AIROHA_PINCTRL_PWM_EXT("gpio27", GPIO27_FLASH_MODE_CFG), 1488 AIROHA_PINCTRL_PWM_EXT("gpio28", GPIO28_FLASH_MODE_CFG), 1489 AIROHA_PINCTRL_PWM_EXT("gpio29", GPIO29_FLASH_MODE_CFG), 1490 AIROHA_PINCTRL_PWM_EXT("gpio30", GPIO30_FLASH_MODE_CFG), 1491 AIROHA_PINCTRL_PWM_EXT("gpio31", GPIO31_FLASH_MODE_CFG), 1492 AIROHA_PINCTRL_PWM_EXT("gpio36", GPIO36_FLASH_MODE_CFG), 1493 AIROHA_PINCTRL_PWM_EXT("gpio37", GPIO37_FLASH_MODE_CFG), 1494 AIROHA_PINCTRL_PWM_EXT("gpio38", GPIO38_FLASH_MODE_CFG), 1495 AIROHA_PINCTRL_PWM_EXT("gpio39", GPIO39_FLASH_MODE_CFG), 1496 AIROHA_PINCTRL_PWM_EXT("gpio40", GPIO40_FLASH_MODE_CFG), 1497 AIROHA_PINCTRL_PWM_EXT("gpio41", GPIO41_FLASH_MODE_CFG), 1498 AIROHA_PINCTRL_PWM_EXT("gpio42", GPIO42_FLASH_MODE_CFG), 1499 AIROHA_PINCTRL_PWM_EXT("gpio43", GPIO43_FLASH_MODE_CFG), 1500 AIROHA_PINCTRL_PWM_EXT("gpio44", GPIO44_FLASH_MODE_CFG), 1501 AIROHA_PINCTRL_PWM_EXT("gpio45", GPIO45_FLASH_MODE_CFG), 1502 AIROHA_PINCTRL_PWM_EXT("gpio46", GPIO46_FLASH_MODE_CFG), 1503 AIROHA_PINCTRL_PWM_EXT("gpio47", GPIO47_FLASH_MODE_CFG), 1504}; 1505 1506#define AIROHA_PINCTRL_PHY_LED0(gpio, mux_val, map_mask, map_val) \ 1507 { \ 1508 .name = (gpio), \ 1509 .regmap[0] = { \ 1510 AIROHA_FUNC_MUX, \ 1511 REG_GPIO_2ND_I2C_MODE, \ 1512 (mux_val), \ 1513 (mux_val), \ 1514 }, \ 1515 .regmap[1] = { \ 1516 AIROHA_FUNC_MUX, \ 1517 REG_LAN_LED0_MAPPING, \ 1518 (map_mask), \ 1519 (map_val), \ 1520 }, \ 1521 .regmap_size = 2, \ 1522 } 1523 1524#define AIROHA_PINCTRL_PHY_LED1(gpio, mux_val, map_mask, map_val) \ 1525 { \ 1526 .name = (gpio), \ 1527 .regmap[0] = { \ 1528 AIROHA_FUNC_MUX, \ 1529 REG_GPIO_2ND_I2C_MODE, \ 1530 (mux_val), \ 1531 (mux_val), \ 1532 }, \ 1533 .regmap[1] = { \ 1534 AIROHA_FUNC_MUX, \ 1535 REG_LAN_LED1_MAPPING, \ 1536 (map_mask), \ 1537 (map_val), \ 1538 }, \ 1539 .regmap_size = 2, \ 1540 } 1541 1542static const struct airoha_pinctrl_func_group phy1_led0_func_group[] = { 1543 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1544 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1545 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1546 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1547 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1548 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1549 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1550 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1551}; 1552 1553static const struct airoha_pinctrl_func_group phy2_led0_func_group[] = { 1554 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1555 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1556 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1557 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1558 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1559 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1560 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1561 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1562}; 1563 1564static const struct airoha_pinctrl_func_group phy3_led0_func_group[] = { 1565 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1566 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1567 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1568 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1569 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1570 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1571 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1572 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1573}; 1574 1575static const struct airoha_pinctrl_func_group phy4_led0_func_group[] = { 1576 AIROHA_PINCTRL_PHY_LED0("gpio33", GPIO_LAN0_LED0_MODE_MASK, 1577 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 1578 AIROHA_PINCTRL_PHY_LED0("gpio34", GPIO_LAN1_LED0_MODE_MASK, 1579 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 1580 AIROHA_PINCTRL_PHY_LED0("gpio35", GPIO_LAN2_LED0_MODE_MASK, 1581 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 1582 AIROHA_PINCTRL_PHY_LED0("gpio42", GPIO_LAN3_LED0_MODE_MASK, 1583 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 1584}; 1585 1586static const struct airoha_pinctrl_func_group phy1_led1_func_group[] = { 1587 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1588 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1589 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1590 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1591 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1592 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1593 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1594 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1595}; 1596 1597static const struct airoha_pinctrl_func_group phy2_led1_func_group[] = { 1598 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1599 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1600 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1601 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1602 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1603 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1604 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1605 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1606}; 1607 1608static const struct airoha_pinctrl_func_group phy3_led1_func_group[] = { 1609 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1610 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1611 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1612 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1613 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1614 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1615 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1616 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1617}; 1618 1619static const struct airoha_pinctrl_func_group phy4_led1_func_group[] = { 1620 AIROHA_PINCTRL_PHY_LED1("gpio43", GPIO_LAN0_LED1_MODE_MASK, 1621 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1622 AIROHA_PINCTRL_PHY_LED1("gpio44", GPIO_LAN1_LED1_MODE_MASK, 1623 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1624 AIROHA_PINCTRL_PHY_LED1("gpio45", GPIO_LAN2_LED1_MODE_MASK, 1625 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1626 AIROHA_PINCTRL_PHY_LED1("gpio46", GPIO_LAN3_LED1_MODE_MASK, 1627 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1628}; 1629 1630static const struct airoha_pinctrl_func_group an7583_phy1_led0_func_group[] = { 1631 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1632 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1633 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1634 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1635 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1636 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1637 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1638 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1639}; 1640 1641static const struct airoha_pinctrl_func_group an7583_phy2_led0_func_group[] = { 1642 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1643 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1644 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1645 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1646 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1647 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1648 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1649 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1650}; 1651 1652static const struct airoha_pinctrl_func_group an7583_phy3_led0_func_group[] = { 1653 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1654 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1655 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1656 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1657 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1658 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1659 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1660 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1661}; 1662 1663static const struct airoha_pinctrl_func_group an7583_phy4_led0_func_group[] = { 1664 AIROHA_PINCTRL_PHY_LED0("gpio1", GPIO_LAN0_LED0_MODE_MASK, 1665 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(3)), 1666 AIROHA_PINCTRL_PHY_LED0("gpio2", GPIO_LAN1_LED0_MODE_MASK, 1667 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(3)), 1668 AIROHA_PINCTRL_PHY_LED0("gpio3", GPIO_LAN2_LED0_MODE_MASK, 1669 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(3)), 1670 AIROHA_PINCTRL_PHY_LED0("gpio4", GPIO_LAN3_LED0_MODE_MASK, 1671 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(3)), 1672}; 1673 1674static const struct airoha_pinctrl_func_group an7583_phy1_led1_func_group[] = { 1675 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1676 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(0)), 1677 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1678 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(0)), 1679 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1680 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(0)), 1681 AIROHA_PINCTRL_PHY_LED1("gpio1", GPIO_LAN3_LED1_MODE_MASK, 1682 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(0)), 1683}; 1684 1685static const struct airoha_pinctrl_func_group an7583_phy2_led1_func_group[] = { 1686 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1687 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(1)), 1688 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1689 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(1)), 1690 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1691 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(1)), 1692 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1693 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(1)), 1694}; 1695 1696static const struct airoha_pinctrl_func_group an7583_phy3_led1_func_group[] = { 1697 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1698 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1699 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1700 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1701 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1702 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1703 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1704 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1705}; 1706 1707static const struct airoha_pinctrl_func_group an7583_phy4_led1_func_group[] = { 1708 AIROHA_PINCTRL_PHY_LED1("gpio8", GPIO_LAN0_LED1_MODE_MASK, 1709 LAN0_LED_MAPPING_MASK, LAN0_PHY_LED_MAP(2)), 1710 AIROHA_PINCTRL_PHY_LED1("gpio9", GPIO_LAN1_LED1_MODE_MASK, 1711 LAN1_LED_MAPPING_MASK, LAN1_PHY_LED_MAP(2)), 1712 AIROHA_PINCTRL_PHY_LED1("gpio10", GPIO_LAN2_LED1_MODE_MASK, 1713 LAN2_LED_MAPPING_MASK, LAN2_PHY_LED_MAP(2)), 1714 AIROHA_PINCTRL_PHY_LED1("gpio11", GPIO_LAN3_LED1_MODE_MASK, 1715 LAN3_LED_MAPPING_MASK, LAN3_PHY_LED_MAP(2)), 1716}; 1717 1718static const struct airoha_pinctrl_func en7581_pinctrl_funcs[] = { 1719 PINCTRL_FUNC_DESC("pon", pon), 1720 PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), 1721 PINCTRL_FUNC_DESC("sipo", sipo), 1722 PINCTRL_FUNC_DESC("mdio", mdio), 1723 PINCTRL_FUNC_DESC("uart", uart), 1724 PINCTRL_FUNC_DESC("i2c", i2c), 1725 PINCTRL_FUNC_DESC("jtag", jtag), 1726 PINCTRL_FUNC_DESC("pcm", pcm), 1727 PINCTRL_FUNC_DESC("spi", spi), 1728 PINCTRL_FUNC_DESC("pcm_spi", pcm_spi), 1729 PINCTRL_FUNC_DESC("i2s", i2s), 1730 PINCTRL_FUNC_DESC("emmc", emmc), 1731 PINCTRL_FUNC_DESC("pnand", pnand), 1732 PINCTRL_FUNC_DESC("pcie_reset", pcie_reset), 1733 PINCTRL_FUNC_DESC("pwm", pwm), 1734 PINCTRL_FUNC_DESC("phy1_led0", phy1_led0), 1735 PINCTRL_FUNC_DESC("phy2_led0", phy2_led0), 1736 PINCTRL_FUNC_DESC("phy3_led0", phy3_led0), 1737 PINCTRL_FUNC_DESC("phy4_led0", phy4_led0), 1738 PINCTRL_FUNC_DESC("phy1_led1", phy1_led1), 1739 PINCTRL_FUNC_DESC("phy2_led1", phy2_led1), 1740 PINCTRL_FUNC_DESC("phy3_led1", phy3_led1), 1741 PINCTRL_FUNC_DESC("phy4_led1", phy4_led1), 1742}; 1743 1744static const struct airoha_pinctrl_func an7583_pinctrl_funcs[] = { 1745 PINCTRL_FUNC_DESC("pon", pon), 1746 PINCTRL_FUNC_DESC("tod_1pps", tod_1pps), 1747 PINCTRL_FUNC_DESC("sipo", sipo), 1748 PINCTRL_FUNC_DESC("mdio", an7583_mdio), 1749 PINCTRL_FUNC_DESC("uart", uart), 1750 PINCTRL_FUNC_DESC("i2c", i2c), 1751 PINCTRL_FUNC_DESC("jtag", jtag), 1752 PINCTRL_FUNC_DESC("pcm", pcm), 1753 PINCTRL_FUNC_DESC("spi", spi), 1754 PINCTRL_FUNC_DESC("pcm_spi", an7583_pcm_spi), 1755 PINCTRL_FUNC_DESC("emmc", emmc), 1756 PINCTRL_FUNC_DESC("pnand", pnand), 1757 PINCTRL_FUNC_DESC("pcie_reset", an7583_pcie_reset), 1758 PINCTRL_FUNC_DESC("pwm", pwm), 1759 PINCTRL_FUNC_DESC("phy1_led0", an7583_phy1_led0), 1760 PINCTRL_FUNC_DESC("phy2_led0", an7583_phy2_led0), 1761 PINCTRL_FUNC_DESC("phy3_led0", an7583_phy3_led0), 1762 PINCTRL_FUNC_DESC("phy4_led0", an7583_phy4_led0), 1763 PINCTRL_FUNC_DESC("phy1_led1", an7583_phy1_led1), 1764 PINCTRL_FUNC_DESC("phy2_led1", an7583_phy2_led1), 1765 PINCTRL_FUNC_DESC("phy3_led1", an7583_phy3_led1), 1766 PINCTRL_FUNC_DESC("phy4_led1", an7583_phy4_led1), 1767}; 1768 1769static const struct airoha_pinctrl_conf en7581_pinctrl_pullup_conf[] = { 1770 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), 1771 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), 1772 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), 1773 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), 1774 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), 1775 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), 1776 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), 1777 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), 1778 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(0)), 1779 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(1)), 1780 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(2)), 1781 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(3)), 1782 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(4)), 1783 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(5)), 1784 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(6)), 1785 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(7)), 1786 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(8)), 1787 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(9)), 1788 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(10)), 1789 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(11)), 1790 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(12)), 1791 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(13)), 1792 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(14)), 1793 PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(15)), 1794 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(16)), 1795 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(17)), 1796 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(18)), 1797 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(18)), 1798 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(20)), 1799 PINCTRL_CONF_DESC(34, REG_GPIO_L_PU, BIT(21)), 1800 PINCTRL_CONF_DESC(35, REG_GPIO_L_PU, BIT(22)), 1801 PINCTRL_CONF_DESC(36, REG_GPIO_L_PU, BIT(23)), 1802 PINCTRL_CONF_DESC(37, REG_GPIO_L_PU, BIT(24)), 1803 PINCTRL_CONF_DESC(38, REG_GPIO_L_PU, BIT(25)), 1804 PINCTRL_CONF_DESC(39, REG_GPIO_L_PU, BIT(26)), 1805 PINCTRL_CONF_DESC(40, REG_GPIO_L_PU, BIT(27)), 1806 PINCTRL_CONF_DESC(41, REG_GPIO_L_PU, BIT(28)), 1807 PINCTRL_CONF_DESC(42, REG_GPIO_L_PU, BIT(29)), 1808 PINCTRL_CONF_DESC(43, REG_GPIO_L_PU, BIT(30)), 1809 PINCTRL_CONF_DESC(44, REG_GPIO_L_PU, BIT(31)), 1810 PINCTRL_CONF_DESC(45, REG_GPIO_H_PU, BIT(0)), 1811 PINCTRL_CONF_DESC(46, REG_GPIO_H_PU, BIT(1)), 1812 PINCTRL_CONF_DESC(47, REG_GPIO_H_PU, BIT(2)), 1813 PINCTRL_CONF_DESC(48, REG_GPIO_H_PU, BIT(3)), 1814 PINCTRL_CONF_DESC(49, REG_GPIO_H_PU, BIT(4)), 1815 PINCTRL_CONF_DESC(50, REG_GPIO_H_PU, BIT(5)), 1816 PINCTRL_CONF_DESC(51, REG_GPIO_H_PU, BIT(6)), 1817 PINCTRL_CONF_DESC(52, REG_GPIO_H_PU, BIT(7)), 1818 PINCTRL_CONF_DESC(53, REG_GPIO_H_PU, BIT(8)), 1819 PINCTRL_CONF_DESC(54, REG_GPIO_H_PU, BIT(9)), 1820 PINCTRL_CONF_DESC(55, REG_GPIO_H_PU, BIT(10)), 1821 PINCTRL_CONF_DESC(56, REG_GPIO_H_PU, BIT(11)), 1822 PINCTRL_CONF_DESC(57, REG_GPIO_H_PU, BIT(12)), 1823 PINCTRL_CONF_DESC(58, REG_GPIO_H_PU, BIT(13)), 1824 PINCTRL_CONF_DESC(59, REG_GPIO_H_PU, BIT(14)), 1825 PINCTRL_CONF_DESC(61, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), 1826 PINCTRL_CONF_DESC(62, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), 1827 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PU, PCIE2_RESET_PU_MASK), 1828}; 1829 1830static const struct airoha_pinctrl_conf an7583_pinctrl_pullup_conf[] = { 1831 PINCTRL_CONF_DESC(2, REG_GPIO_L_PU, BIT(0)), 1832 PINCTRL_CONF_DESC(3, REG_GPIO_L_PU, BIT(1)), 1833 PINCTRL_CONF_DESC(4, REG_GPIO_L_PU, BIT(2)), 1834 PINCTRL_CONF_DESC(5, REG_GPIO_L_PU, BIT(3)), 1835 PINCTRL_CONF_DESC(6, REG_GPIO_L_PU, BIT(4)), 1836 PINCTRL_CONF_DESC(7, REG_GPIO_L_PU, BIT(5)), 1837 PINCTRL_CONF_DESC(8, REG_GPIO_L_PU, BIT(6)), 1838 PINCTRL_CONF_DESC(9, REG_GPIO_L_PU, BIT(7)), 1839 PINCTRL_CONF_DESC(10, REG_GPIO_L_PU, BIT(8)), 1840 PINCTRL_CONF_DESC(11, REG_GPIO_L_PU, BIT(9)), 1841 PINCTRL_CONF_DESC(12, REG_GPIO_L_PU, BIT(10)), 1842 PINCTRL_CONF_DESC(13, REG_GPIO_L_PU, BIT(11)), 1843 PINCTRL_CONF_DESC(14, REG_GPIO_L_PU, BIT(12)), 1844 PINCTRL_CONF_DESC(15, REG_GPIO_L_PU, BIT(13)), 1845 PINCTRL_CONF_DESC(16, REG_GPIO_L_PU, BIT(14)), 1846 PINCTRL_CONF_DESC(17, REG_GPIO_L_PU, BIT(15)), 1847 PINCTRL_CONF_DESC(18, REG_GPIO_L_PU, BIT(16)), 1848 PINCTRL_CONF_DESC(19, REG_GPIO_L_PU, BIT(17)), 1849 PINCTRL_CONF_DESC(20, REG_GPIO_L_PU, BIT(18)), 1850 PINCTRL_CONF_DESC(21, REG_GPIO_L_PU, BIT(18)), 1851 PINCTRL_CONF_DESC(22, REG_GPIO_L_PU, BIT(20)), 1852 PINCTRL_CONF_DESC(23, REG_GPIO_L_PU, BIT(21)), 1853 PINCTRL_CONF_DESC(24, REG_GPIO_L_PU, BIT(22)), 1854 PINCTRL_CONF_DESC(25, REG_GPIO_L_PU, BIT(23)), 1855 PINCTRL_CONF_DESC(26, REG_GPIO_L_PU, BIT(24)), 1856 PINCTRL_CONF_DESC(27, REG_GPIO_L_PU, BIT(25)), 1857 PINCTRL_CONF_DESC(28, REG_GPIO_L_PU, BIT(26)), 1858 PINCTRL_CONF_DESC(29, REG_GPIO_L_PU, BIT(27)), 1859 PINCTRL_CONF_DESC(30, REG_GPIO_L_PU, BIT(28)), 1860 PINCTRL_CONF_DESC(31, REG_GPIO_L_PU, BIT(29)), 1861 PINCTRL_CONF_DESC(32, REG_GPIO_L_PU, BIT(30)), 1862 PINCTRL_CONF_DESC(33, REG_GPIO_L_PU, BIT(31)), 1863 PINCTRL_CONF_DESC(34, REG_GPIO_H_PU, BIT(0)), 1864 PINCTRL_CONF_DESC(35, REG_GPIO_H_PU, BIT(1)), 1865 PINCTRL_CONF_DESC(36, REG_GPIO_H_PU, BIT(2)), 1866 PINCTRL_CONF_DESC(37, REG_GPIO_H_PU, BIT(3)), 1867 PINCTRL_CONF_DESC(38, REG_GPIO_H_PU, BIT(4)), 1868 PINCTRL_CONF_DESC(39, REG_GPIO_H_PU, BIT(5)), 1869 PINCTRL_CONF_DESC(40, REG_GPIO_H_PU, BIT(6)), 1870 PINCTRL_CONF_DESC(41, REG_I2C_SDA_PU, I2C_SCL_PU_MASK), 1871 PINCTRL_CONF_DESC(42, REG_I2C_SDA_PU, I2C_SDA_PU_MASK), 1872 PINCTRL_CONF_DESC(43, REG_I2C_SDA_PU, AN7583_I2C1_SCL_PU_MASK), 1873 PINCTRL_CONF_DESC(44, REG_I2C_SDA_PU, AN7583_I2C1_SDA_PU_MASK), 1874 PINCTRL_CONF_DESC(45, REG_I2C_SDA_PU, SPI_CLK_PU_MASK), 1875 PINCTRL_CONF_DESC(46, REG_I2C_SDA_PU, SPI_CS0_PU_MASK), 1876 PINCTRL_CONF_DESC(47, REG_I2C_SDA_PU, SPI_MOSI_PU_MASK), 1877 PINCTRL_CONF_DESC(48, REG_I2C_SDA_PU, SPI_MISO_PU_MASK), 1878 PINCTRL_CONF_DESC(49, REG_I2C_SDA_PU, UART1_TXD_PU_MASK), 1879 PINCTRL_CONF_DESC(50, REG_I2C_SDA_PU, UART1_RXD_PU_MASK), 1880 PINCTRL_CONF_DESC(51, REG_I2C_SDA_PU, PCIE0_RESET_PU_MASK), 1881 PINCTRL_CONF_DESC(52, REG_I2C_SDA_PU, PCIE1_RESET_PU_MASK), 1882 PINCTRL_CONF_DESC(53, REG_I2C_SDA_PU, AN7583_MDC_0_PU_MASK), 1883 PINCTRL_CONF_DESC(54, REG_I2C_SDA_PU, AN7583_MDIO_0_PU_MASK), 1884}; 1885 1886static const struct airoha_pinctrl_conf en7581_pinctrl_pulldown_conf[] = { 1887 PINCTRL_CONF_DESC(0, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), 1888 PINCTRL_CONF_DESC(1, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), 1889 PINCTRL_CONF_DESC(2, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), 1890 PINCTRL_CONF_DESC(3, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), 1891 PINCTRL_CONF_DESC(4, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), 1892 PINCTRL_CONF_DESC(5, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), 1893 PINCTRL_CONF_DESC(6, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), 1894 PINCTRL_CONF_DESC(7, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), 1895 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(0)), 1896 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(1)), 1897 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(2)), 1898 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(3)), 1899 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(4)), 1900 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(5)), 1901 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(6)), 1902 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(7)), 1903 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(8)), 1904 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(9)), 1905 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(10)), 1906 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(11)), 1907 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(12)), 1908 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(13)), 1909 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(14)), 1910 PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(15)), 1911 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(16)), 1912 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(17)), 1913 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(18)), 1914 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(18)), 1915 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(20)), 1916 PINCTRL_CONF_DESC(34, REG_GPIO_L_PD, BIT(21)), 1917 PINCTRL_CONF_DESC(35, REG_GPIO_L_PD, BIT(22)), 1918 PINCTRL_CONF_DESC(36, REG_GPIO_L_PD, BIT(23)), 1919 PINCTRL_CONF_DESC(37, REG_GPIO_L_PD, BIT(24)), 1920 PINCTRL_CONF_DESC(38, REG_GPIO_L_PD, BIT(25)), 1921 PINCTRL_CONF_DESC(39, REG_GPIO_L_PD, BIT(26)), 1922 PINCTRL_CONF_DESC(40, REG_GPIO_L_PD, BIT(27)), 1923 PINCTRL_CONF_DESC(41, REG_GPIO_L_PD, BIT(28)), 1924 PINCTRL_CONF_DESC(42, REG_GPIO_L_PD, BIT(29)), 1925 PINCTRL_CONF_DESC(43, REG_GPIO_L_PD, BIT(30)), 1926 PINCTRL_CONF_DESC(44, REG_GPIO_L_PD, BIT(31)), 1927 PINCTRL_CONF_DESC(45, REG_GPIO_H_PD, BIT(0)), 1928 PINCTRL_CONF_DESC(46, REG_GPIO_H_PD, BIT(1)), 1929 PINCTRL_CONF_DESC(47, REG_GPIO_H_PD, BIT(2)), 1930 PINCTRL_CONF_DESC(48, REG_GPIO_H_PD, BIT(3)), 1931 PINCTRL_CONF_DESC(49, REG_GPIO_H_PD, BIT(4)), 1932 PINCTRL_CONF_DESC(50, REG_GPIO_H_PD, BIT(5)), 1933 PINCTRL_CONF_DESC(51, REG_GPIO_H_PD, BIT(6)), 1934 PINCTRL_CONF_DESC(52, REG_GPIO_H_PD, BIT(7)), 1935 PINCTRL_CONF_DESC(53, REG_GPIO_H_PD, BIT(8)), 1936 PINCTRL_CONF_DESC(54, REG_GPIO_H_PD, BIT(9)), 1937 PINCTRL_CONF_DESC(55, REG_GPIO_H_PD, BIT(10)), 1938 PINCTRL_CONF_DESC(56, REG_GPIO_H_PD, BIT(11)), 1939 PINCTRL_CONF_DESC(57, REG_GPIO_H_PD, BIT(12)), 1940 PINCTRL_CONF_DESC(58, REG_GPIO_H_PD, BIT(13)), 1941 PINCTRL_CONF_DESC(59, REG_GPIO_H_PD, BIT(14)), 1942 PINCTRL_CONF_DESC(61, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), 1943 PINCTRL_CONF_DESC(62, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), 1944 PINCTRL_CONF_DESC(63, REG_I2C_SDA_PD, PCIE2_RESET_PD_MASK), 1945}; 1946 1947static const struct airoha_pinctrl_conf an7583_pinctrl_pulldown_conf[] = { 1948 PINCTRL_CONF_DESC(2, REG_GPIO_L_PD, BIT(0)), 1949 PINCTRL_CONF_DESC(3, REG_GPIO_L_PD, BIT(1)), 1950 PINCTRL_CONF_DESC(4, REG_GPIO_L_PD, BIT(2)), 1951 PINCTRL_CONF_DESC(5, REG_GPIO_L_PD, BIT(3)), 1952 PINCTRL_CONF_DESC(6, REG_GPIO_L_PD, BIT(4)), 1953 PINCTRL_CONF_DESC(7, REG_GPIO_L_PD, BIT(5)), 1954 PINCTRL_CONF_DESC(8, REG_GPIO_L_PD, BIT(6)), 1955 PINCTRL_CONF_DESC(9, REG_GPIO_L_PD, BIT(7)), 1956 PINCTRL_CONF_DESC(10, REG_GPIO_L_PD, BIT(8)), 1957 PINCTRL_CONF_DESC(11, REG_GPIO_L_PD, BIT(9)), 1958 PINCTRL_CONF_DESC(12, REG_GPIO_L_PD, BIT(10)), 1959 PINCTRL_CONF_DESC(13, REG_GPIO_L_PD, BIT(11)), 1960 PINCTRL_CONF_DESC(14, REG_GPIO_L_PD, BIT(12)), 1961 PINCTRL_CONF_DESC(15, REG_GPIO_L_PD, BIT(13)), 1962 PINCTRL_CONF_DESC(16, REG_GPIO_L_PD, BIT(14)), 1963 PINCTRL_CONF_DESC(17, REG_GPIO_L_PD, BIT(15)), 1964 PINCTRL_CONF_DESC(18, REG_GPIO_L_PD, BIT(16)), 1965 PINCTRL_CONF_DESC(19, REG_GPIO_L_PD, BIT(17)), 1966 PINCTRL_CONF_DESC(20, REG_GPIO_L_PD, BIT(18)), 1967 PINCTRL_CONF_DESC(21, REG_GPIO_L_PD, BIT(18)), 1968 PINCTRL_CONF_DESC(22, REG_GPIO_L_PD, BIT(20)), 1969 PINCTRL_CONF_DESC(23, REG_GPIO_L_PD, BIT(21)), 1970 PINCTRL_CONF_DESC(24, REG_GPIO_L_PD, BIT(22)), 1971 PINCTRL_CONF_DESC(25, REG_GPIO_L_PD, BIT(23)), 1972 PINCTRL_CONF_DESC(26, REG_GPIO_L_PD, BIT(24)), 1973 PINCTRL_CONF_DESC(27, REG_GPIO_L_PD, BIT(25)), 1974 PINCTRL_CONF_DESC(28, REG_GPIO_L_PD, BIT(26)), 1975 PINCTRL_CONF_DESC(29, REG_GPIO_L_PD, BIT(27)), 1976 PINCTRL_CONF_DESC(30, REG_GPIO_L_PD, BIT(28)), 1977 PINCTRL_CONF_DESC(31, REG_GPIO_L_PD, BIT(29)), 1978 PINCTRL_CONF_DESC(32, REG_GPIO_L_PD, BIT(30)), 1979 PINCTRL_CONF_DESC(33, REG_GPIO_L_PD, BIT(31)), 1980 PINCTRL_CONF_DESC(34, REG_GPIO_H_PD, BIT(0)), 1981 PINCTRL_CONF_DESC(35, REG_GPIO_H_PD, BIT(1)), 1982 PINCTRL_CONF_DESC(36, REG_GPIO_H_PD, BIT(2)), 1983 PINCTRL_CONF_DESC(37, REG_GPIO_H_PD, BIT(3)), 1984 PINCTRL_CONF_DESC(38, REG_GPIO_H_PD, BIT(4)), 1985 PINCTRL_CONF_DESC(39, REG_GPIO_H_PD, BIT(5)), 1986 PINCTRL_CONF_DESC(40, REG_GPIO_H_PD, BIT(6)), 1987 PINCTRL_CONF_DESC(41, REG_I2C_SDA_PD, I2C_SCL_PD_MASK), 1988 PINCTRL_CONF_DESC(42, REG_I2C_SDA_PD, I2C_SDA_PD_MASK), 1989 PINCTRL_CONF_DESC(43, REG_I2C_SDA_PD, AN7583_I2C1_SCL_PD_MASK), 1990 PINCTRL_CONF_DESC(44, REG_I2C_SDA_PD, AN7583_I2C1_SDA_PD_MASK), 1991 PINCTRL_CONF_DESC(45, REG_I2C_SDA_PD, SPI_CLK_PD_MASK), 1992 PINCTRL_CONF_DESC(46, REG_I2C_SDA_PD, SPI_CS0_PD_MASK), 1993 PINCTRL_CONF_DESC(47, REG_I2C_SDA_PD, SPI_MOSI_PD_MASK), 1994 PINCTRL_CONF_DESC(48, REG_I2C_SDA_PD, SPI_MISO_PD_MASK), 1995 PINCTRL_CONF_DESC(49, REG_I2C_SDA_PD, UART1_TXD_PD_MASK), 1996 PINCTRL_CONF_DESC(50, REG_I2C_SDA_PD, UART1_RXD_PD_MASK), 1997 PINCTRL_CONF_DESC(51, REG_I2C_SDA_PD, PCIE0_RESET_PD_MASK), 1998 PINCTRL_CONF_DESC(52, REG_I2C_SDA_PD, PCIE1_RESET_PD_MASK), 1999 PINCTRL_CONF_DESC(53, REG_I2C_SDA_PD, AN7583_MDC_0_PD_MASK), 2000 PINCTRL_CONF_DESC(54, REG_I2C_SDA_PD, AN7583_MDIO_0_PD_MASK), 2001}; 2002 2003static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e2_conf[] = { 2004 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), 2005 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), 2006 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), 2007 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), 2008 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), 2009 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), 2010 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), 2011 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), 2012 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(0)), 2013 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(1)), 2014 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(2)), 2015 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(3)), 2016 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(4)), 2017 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(5)), 2018 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(6)), 2019 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(7)), 2020 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(8)), 2021 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(9)), 2022 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(10)), 2023 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(11)), 2024 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(12)), 2025 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(13)), 2026 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(14)), 2027 PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(15)), 2028 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(16)), 2029 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(17)), 2030 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(18)), 2031 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(18)), 2032 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(20)), 2033 PINCTRL_CONF_DESC(34, REG_GPIO_L_E2, BIT(21)), 2034 PINCTRL_CONF_DESC(35, REG_GPIO_L_E2, BIT(22)), 2035 PINCTRL_CONF_DESC(36, REG_GPIO_L_E2, BIT(23)), 2036 PINCTRL_CONF_DESC(37, REG_GPIO_L_E2, BIT(24)), 2037 PINCTRL_CONF_DESC(38, REG_GPIO_L_E2, BIT(25)), 2038 PINCTRL_CONF_DESC(39, REG_GPIO_L_E2, BIT(26)), 2039 PINCTRL_CONF_DESC(40, REG_GPIO_L_E2, BIT(27)), 2040 PINCTRL_CONF_DESC(41, REG_GPIO_L_E2, BIT(28)), 2041 PINCTRL_CONF_DESC(42, REG_GPIO_L_E2, BIT(29)), 2042 PINCTRL_CONF_DESC(43, REG_GPIO_L_E2, BIT(30)), 2043 PINCTRL_CONF_DESC(44, REG_GPIO_L_E2, BIT(31)), 2044 PINCTRL_CONF_DESC(45, REG_GPIO_H_E2, BIT(0)), 2045 PINCTRL_CONF_DESC(46, REG_GPIO_H_E2, BIT(1)), 2046 PINCTRL_CONF_DESC(47, REG_GPIO_H_E2, BIT(2)), 2047 PINCTRL_CONF_DESC(48, REG_GPIO_H_E2, BIT(3)), 2048 PINCTRL_CONF_DESC(49, REG_GPIO_H_E2, BIT(4)), 2049 PINCTRL_CONF_DESC(50, REG_GPIO_H_E2, BIT(5)), 2050 PINCTRL_CONF_DESC(51, REG_GPIO_H_E2, BIT(6)), 2051 PINCTRL_CONF_DESC(52, REG_GPIO_H_E2, BIT(7)), 2052 PINCTRL_CONF_DESC(53, REG_GPIO_H_E2, BIT(8)), 2053 PINCTRL_CONF_DESC(54, REG_GPIO_H_E2, BIT(9)), 2054 PINCTRL_CONF_DESC(55, REG_GPIO_H_E2, BIT(10)), 2055 PINCTRL_CONF_DESC(56, REG_GPIO_H_E2, BIT(11)), 2056 PINCTRL_CONF_DESC(57, REG_GPIO_H_E2, BIT(12)), 2057 PINCTRL_CONF_DESC(58, REG_GPIO_H_E2, BIT(13)), 2058 PINCTRL_CONF_DESC(59, REG_GPIO_H_E2, BIT(14)), 2059 PINCTRL_CONF_DESC(61, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), 2060 PINCTRL_CONF_DESC(62, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), 2061 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E2, PCIE2_RESET_E2_MASK), 2062}; 2063 2064static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { 2065 PINCTRL_CONF_DESC(2, REG_GPIO_L_E2, BIT(0)), 2066 PINCTRL_CONF_DESC(3, REG_GPIO_L_E2, BIT(1)), 2067 PINCTRL_CONF_DESC(4, REG_GPIO_L_E2, BIT(2)), 2068 PINCTRL_CONF_DESC(5, REG_GPIO_L_E2, BIT(3)), 2069 PINCTRL_CONF_DESC(6, REG_GPIO_L_E2, BIT(4)), 2070 PINCTRL_CONF_DESC(7, REG_GPIO_L_E2, BIT(5)), 2071 PINCTRL_CONF_DESC(8, REG_GPIO_L_E2, BIT(6)), 2072 PINCTRL_CONF_DESC(9, REG_GPIO_L_E2, BIT(7)), 2073 PINCTRL_CONF_DESC(10, REG_GPIO_L_E2, BIT(8)), 2074 PINCTRL_CONF_DESC(11, REG_GPIO_L_E2, BIT(9)), 2075 PINCTRL_CONF_DESC(12, REG_GPIO_L_E2, BIT(10)), 2076 PINCTRL_CONF_DESC(13, REG_GPIO_L_E2, BIT(11)), 2077 PINCTRL_CONF_DESC(14, REG_GPIO_L_E2, BIT(12)), 2078 PINCTRL_CONF_DESC(15, REG_GPIO_L_E2, BIT(13)), 2079 PINCTRL_CONF_DESC(16, REG_GPIO_L_E2, BIT(14)), 2080 PINCTRL_CONF_DESC(17, REG_GPIO_L_E2, BIT(15)), 2081 PINCTRL_CONF_DESC(18, REG_GPIO_L_E2, BIT(16)), 2082 PINCTRL_CONF_DESC(19, REG_GPIO_L_E2, BIT(17)), 2083 PINCTRL_CONF_DESC(20, REG_GPIO_L_E2, BIT(18)), 2084 PINCTRL_CONF_DESC(21, REG_GPIO_L_E2, BIT(18)), 2085 PINCTRL_CONF_DESC(22, REG_GPIO_L_E2, BIT(20)), 2086 PINCTRL_CONF_DESC(23, REG_GPIO_L_E2, BIT(21)), 2087 PINCTRL_CONF_DESC(24, REG_GPIO_L_E2, BIT(22)), 2088 PINCTRL_CONF_DESC(25, REG_GPIO_L_E2, BIT(23)), 2089 PINCTRL_CONF_DESC(26, REG_GPIO_L_E2, BIT(24)), 2090 PINCTRL_CONF_DESC(27, REG_GPIO_L_E2, BIT(25)), 2091 PINCTRL_CONF_DESC(28, REG_GPIO_L_E2, BIT(26)), 2092 PINCTRL_CONF_DESC(29, REG_GPIO_L_E2, BIT(27)), 2093 PINCTRL_CONF_DESC(30, REG_GPIO_L_E2, BIT(28)), 2094 PINCTRL_CONF_DESC(31, REG_GPIO_L_E2, BIT(29)), 2095 PINCTRL_CONF_DESC(32, REG_GPIO_L_E2, BIT(30)), 2096 PINCTRL_CONF_DESC(33, REG_GPIO_L_E2, BIT(31)), 2097 PINCTRL_CONF_DESC(34, REG_GPIO_H_E2, BIT(0)), 2098 PINCTRL_CONF_DESC(35, REG_GPIO_H_E2, BIT(1)), 2099 PINCTRL_CONF_DESC(36, REG_GPIO_H_E2, BIT(2)), 2100 PINCTRL_CONF_DESC(37, REG_GPIO_H_E2, BIT(3)), 2101 PINCTRL_CONF_DESC(38, REG_GPIO_H_E2, BIT(4)), 2102 PINCTRL_CONF_DESC(39, REG_GPIO_H_E2, BIT(5)), 2103 PINCTRL_CONF_DESC(40, REG_GPIO_H_E2, BIT(6)), 2104 PINCTRL_CONF_DESC(41, REG_I2C_SDA_E2, I2C_SCL_E2_MASK), 2105 PINCTRL_CONF_DESC(42, REG_I2C_SDA_E2, I2C_SDA_E2_MASK), 2106 PINCTRL_CONF_DESC(43, REG_I2C_SDA_E2, AN7583_I2C1_SCL_E2_MASK), 2107 PINCTRL_CONF_DESC(44, REG_I2C_SDA_E2, AN7583_I2C1_SDA_E2_MASK), 2108 PINCTRL_CONF_DESC(45, REG_I2C_SDA_E2, SPI_CLK_E2_MASK), 2109 PINCTRL_CONF_DESC(46, REG_I2C_SDA_E2, SPI_CS0_E2_MASK), 2110 PINCTRL_CONF_DESC(47, REG_I2C_SDA_E2, SPI_MOSI_E2_MASK), 2111 PINCTRL_CONF_DESC(48, REG_I2C_SDA_E2, SPI_MISO_E2_MASK), 2112 PINCTRL_CONF_DESC(49, REG_I2C_SDA_E2, UART1_TXD_E2_MASK), 2113 PINCTRL_CONF_DESC(50, REG_I2C_SDA_E2, UART1_RXD_E2_MASK), 2114 PINCTRL_CONF_DESC(51, REG_I2C_SDA_E2, PCIE0_RESET_E2_MASK), 2115 PINCTRL_CONF_DESC(52, REG_I2C_SDA_E2, PCIE1_RESET_E2_MASK), 2116 PINCTRL_CONF_DESC(53, REG_I2C_SDA_E2, AN7583_MDC_0_E2_MASK), 2117 PINCTRL_CONF_DESC(54, REG_I2C_SDA_E2, AN7583_MDIO_0_E2_MASK), 2118}; 2119 2120static const struct airoha_pinctrl_conf en7581_pinctrl_drive_e4_conf[] = { 2121 PINCTRL_CONF_DESC(0, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), 2122 PINCTRL_CONF_DESC(1, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), 2123 PINCTRL_CONF_DESC(2, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), 2124 PINCTRL_CONF_DESC(3, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), 2125 PINCTRL_CONF_DESC(4, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), 2126 PINCTRL_CONF_DESC(5, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), 2127 PINCTRL_CONF_DESC(6, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), 2128 PINCTRL_CONF_DESC(7, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), 2129 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(0)), 2130 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(1)), 2131 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(2)), 2132 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(3)), 2133 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(4)), 2134 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(5)), 2135 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(6)), 2136 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(7)), 2137 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(8)), 2138 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(9)), 2139 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(10)), 2140 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(11)), 2141 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(12)), 2142 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(13)), 2143 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(14)), 2144 PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(15)), 2145 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(16)), 2146 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(17)), 2147 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(18)), 2148 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(18)), 2149 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(20)), 2150 PINCTRL_CONF_DESC(34, REG_GPIO_L_E4, BIT(21)), 2151 PINCTRL_CONF_DESC(35, REG_GPIO_L_E4, BIT(22)), 2152 PINCTRL_CONF_DESC(36, REG_GPIO_L_E4, BIT(23)), 2153 PINCTRL_CONF_DESC(37, REG_GPIO_L_E4, BIT(24)), 2154 PINCTRL_CONF_DESC(38, REG_GPIO_L_E4, BIT(25)), 2155 PINCTRL_CONF_DESC(39, REG_GPIO_L_E4, BIT(26)), 2156 PINCTRL_CONF_DESC(40, REG_GPIO_L_E4, BIT(27)), 2157 PINCTRL_CONF_DESC(41, REG_GPIO_L_E4, BIT(28)), 2158 PINCTRL_CONF_DESC(42, REG_GPIO_L_E4, BIT(29)), 2159 PINCTRL_CONF_DESC(43, REG_GPIO_L_E4, BIT(30)), 2160 PINCTRL_CONF_DESC(44, REG_GPIO_L_E4, BIT(31)), 2161 PINCTRL_CONF_DESC(45, REG_GPIO_H_E4, BIT(0)), 2162 PINCTRL_CONF_DESC(46, REG_GPIO_H_E4, BIT(1)), 2163 PINCTRL_CONF_DESC(47, REG_GPIO_H_E4, BIT(2)), 2164 PINCTRL_CONF_DESC(48, REG_GPIO_H_E4, BIT(3)), 2165 PINCTRL_CONF_DESC(49, REG_GPIO_H_E4, BIT(4)), 2166 PINCTRL_CONF_DESC(50, REG_GPIO_H_E4, BIT(5)), 2167 PINCTRL_CONF_DESC(51, REG_GPIO_H_E4, BIT(6)), 2168 PINCTRL_CONF_DESC(52, REG_GPIO_H_E4, BIT(7)), 2169 PINCTRL_CONF_DESC(53, REG_GPIO_H_E4, BIT(8)), 2170 PINCTRL_CONF_DESC(54, REG_GPIO_H_E4, BIT(9)), 2171 PINCTRL_CONF_DESC(55, REG_GPIO_H_E4, BIT(10)), 2172 PINCTRL_CONF_DESC(56, REG_GPIO_H_E4, BIT(11)), 2173 PINCTRL_CONF_DESC(57, REG_GPIO_H_E4, BIT(12)), 2174 PINCTRL_CONF_DESC(58, REG_GPIO_H_E4, BIT(13)), 2175 PINCTRL_CONF_DESC(59, REG_GPIO_H_E4, BIT(14)), 2176 PINCTRL_CONF_DESC(61, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), 2177 PINCTRL_CONF_DESC(62, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), 2178 PINCTRL_CONF_DESC(63, REG_I2C_SDA_E4, PCIE2_RESET_E4_MASK), 2179}; 2180 2181static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e4_conf[] = { 2182 PINCTRL_CONF_DESC(2, REG_GPIO_L_E4, BIT(0)), 2183 PINCTRL_CONF_DESC(3, REG_GPIO_L_E4, BIT(1)), 2184 PINCTRL_CONF_DESC(4, REG_GPIO_L_E4, BIT(2)), 2185 PINCTRL_CONF_DESC(5, REG_GPIO_L_E4, BIT(3)), 2186 PINCTRL_CONF_DESC(6, REG_GPIO_L_E4, BIT(4)), 2187 PINCTRL_CONF_DESC(7, REG_GPIO_L_E4, BIT(5)), 2188 PINCTRL_CONF_DESC(8, REG_GPIO_L_E4, BIT(6)), 2189 PINCTRL_CONF_DESC(9, REG_GPIO_L_E4, BIT(7)), 2190 PINCTRL_CONF_DESC(10, REG_GPIO_L_E4, BIT(8)), 2191 PINCTRL_CONF_DESC(11, REG_GPIO_L_E4, BIT(9)), 2192 PINCTRL_CONF_DESC(12, REG_GPIO_L_E4, BIT(10)), 2193 PINCTRL_CONF_DESC(13, REG_GPIO_L_E4, BIT(11)), 2194 PINCTRL_CONF_DESC(14, REG_GPIO_L_E4, BIT(12)), 2195 PINCTRL_CONF_DESC(15, REG_GPIO_L_E4, BIT(13)), 2196 PINCTRL_CONF_DESC(16, REG_GPIO_L_E4, BIT(14)), 2197 PINCTRL_CONF_DESC(17, REG_GPIO_L_E4, BIT(15)), 2198 PINCTRL_CONF_DESC(18, REG_GPIO_L_E4, BIT(16)), 2199 PINCTRL_CONF_DESC(19, REG_GPIO_L_E4, BIT(17)), 2200 PINCTRL_CONF_DESC(20, REG_GPIO_L_E4, BIT(18)), 2201 PINCTRL_CONF_DESC(21, REG_GPIO_L_E4, BIT(18)), 2202 PINCTRL_CONF_DESC(22, REG_GPIO_L_E4, BIT(20)), 2203 PINCTRL_CONF_DESC(23, REG_GPIO_L_E4, BIT(21)), 2204 PINCTRL_CONF_DESC(24, REG_GPIO_L_E4, BIT(22)), 2205 PINCTRL_CONF_DESC(25, REG_GPIO_L_E4, BIT(23)), 2206 PINCTRL_CONF_DESC(26, REG_GPIO_L_E4, BIT(24)), 2207 PINCTRL_CONF_DESC(27, REG_GPIO_L_E4, BIT(25)), 2208 PINCTRL_CONF_DESC(28, REG_GPIO_L_E4, BIT(26)), 2209 PINCTRL_CONF_DESC(29, REG_GPIO_L_E4, BIT(27)), 2210 PINCTRL_CONF_DESC(30, REG_GPIO_L_E4, BIT(28)), 2211 PINCTRL_CONF_DESC(31, REG_GPIO_L_E4, BIT(29)), 2212 PINCTRL_CONF_DESC(32, REG_GPIO_L_E4, BIT(30)), 2213 PINCTRL_CONF_DESC(33, REG_GPIO_L_E4, BIT(31)), 2214 PINCTRL_CONF_DESC(34, REG_GPIO_H_E4, BIT(0)), 2215 PINCTRL_CONF_DESC(35, REG_GPIO_H_E4, BIT(1)), 2216 PINCTRL_CONF_DESC(36, REG_GPIO_H_E4, BIT(2)), 2217 PINCTRL_CONF_DESC(37, REG_GPIO_H_E4, BIT(3)), 2218 PINCTRL_CONF_DESC(38, REG_GPIO_H_E4, BIT(4)), 2219 PINCTRL_CONF_DESC(39, REG_GPIO_H_E4, BIT(5)), 2220 PINCTRL_CONF_DESC(40, REG_GPIO_H_E4, BIT(6)), 2221 PINCTRL_CONF_DESC(41, REG_I2C_SDA_E4, I2C_SCL_E4_MASK), 2222 PINCTRL_CONF_DESC(42, REG_I2C_SDA_E4, I2C_SDA_E4_MASK), 2223 PINCTRL_CONF_DESC(43, REG_I2C_SDA_E4, AN7583_I2C1_SCL_E4_MASK), 2224 PINCTRL_CONF_DESC(44, REG_I2C_SDA_E4, AN7583_I2C1_SDA_E4_MASK), 2225 PINCTRL_CONF_DESC(45, REG_I2C_SDA_E4, SPI_CLK_E4_MASK), 2226 PINCTRL_CONF_DESC(46, REG_I2C_SDA_E4, SPI_CS0_E4_MASK), 2227 PINCTRL_CONF_DESC(47, REG_I2C_SDA_E4, SPI_MOSI_E4_MASK), 2228 PINCTRL_CONF_DESC(48, REG_I2C_SDA_E4, SPI_MISO_E4_MASK), 2229 PINCTRL_CONF_DESC(49, REG_I2C_SDA_E4, UART1_TXD_E4_MASK), 2230 PINCTRL_CONF_DESC(50, REG_I2C_SDA_E4, UART1_RXD_E4_MASK), 2231 PINCTRL_CONF_DESC(51, REG_I2C_SDA_E4, PCIE0_RESET_E4_MASK), 2232 PINCTRL_CONF_DESC(52, REG_I2C_SDA_E4, PCIE1_RESET_E4_MASK), 2233 PINCTRL_CONF_DESC(53, REG_I2C_SDA_E4, AN7583_MDC_0_E4_MASK), 2234 PINCTRL_CONF_DESC(54, REG_I2C_SDA_E4, AN7583_MDIO_0_E4_MASK), 2235}; 2236 2237static const struct airoha_pinctrl_conf en7581_pinctrl_pcie_rst_od_conf[] = { 2238 PINCTRL_CONF_DESC(61, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), 2239 PINCTRL_CONF_DESC(62, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), 2240 PINCTRL_CONF_DESC(63, REG_PCIE_RESET_OD, PCIE2_RESET_OD_MASK), 2241}; 2242 2243static const struct airoha_pinctrl_conf an7583_pinctrl_pcie_rst_od_conf[] = { 2244 PINCTRL_CONF_DESC(51, REG_PCIE_RESET_OD, PCIE0_RESET_OD_MASK), 2245 PINCTRL_CONF_DESC(52, REG_PCIE_RESET_OD, PCIE1_RESET_OD_MASK), 2246}; 2247 2248static int airoha_convert_pin_to_reg_offset(struct pinctrl_dev *pctrl_dev, 2249 struct pinctrl_gpio_range *range, 2250 int pin) 2251{ 2252 if (!range) 2253 range = pinctrl_find_gpio_range_from_pin_nolock(pctrl_dev, 2254 pin); 2255 if (!range) 2256 return -EINVAL; 2257 2258 return pin - range->pin_base; 2259} 2260 2261/* gpio callbacks */ 2262static int airoha_gpio_set(struct gpio_chip *chip, unsigned int gpio, 2263 int value) 2264{ 2265 struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); 2266 u32 offset = gpio % AIROHA_PIN_BANK_SIZE; 2267 u8 index = gpio / AIROHA_PIN_BANK_SIZE; 2268 2269 return regmap_update_bits(pinctrl->regmap, 2270 pinctrl->gpiochip.data[index], 2271 BIT(offset), value ? BIT(offset) : 0); 2272} 2273 2274static int airoha_gpio_get(struct gpio_chip *chip, unsigned int gpio) 2275{ 2276 struct airoha_pinctrl *pinctrl = gpiochip_get_data(chip); 2277 u32 val, pin = gpio % AIROHA_PIN_BANK_SIZE; 2278 u8 index = gpio / AIROHA_PIN_BANK_SIZE; 2279 int err; 2280 2281 err = regmap_read(pinctrl->regmap, 2282 pinctrl->gpiochip.data[index], &val); 2283 2284 return err ? err : !!(val & BIT(pin)); 2285} 2286 2287static int airoha_gpio_direction_output(struct gpio_chip *chip, 2288 unsigned int gpio, int value) 2289{ 2290 int err; 2291 2292 err = pinctrl_gpio_direction_output(chip, gpio); 2293 if (err) 2294 return err; 2295 2296 return airoha_gpio_set(chip, gpio, value); 2297} 2298 2299/* irq callbacks */ 2300static void airoha_irq_unmask(struct irq_data *data) 2301{ 2302 u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; 2303 u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; 2304 u32 mask = GENMASK(2 * offset + 1, 2 * offset); 2305 struct airoha_pinctrl_gpiochip *gpiochip; 2306 struct airoha_pinctrl *pinctrl; 2307 u32 val = BIT(2 * offset); 2308 2309 gpiochip = irq_data_get_irq_chip_data(data); 2310 if (WARN_ON_ONCE(data->hwirq >= ARRAY_SIZE(gpiochip->irq_type))) 2311 return; 2312 2313 pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); 2314 switch (gpiochip->irq_type[data->hwirq]) { 2315 case IRQ_TYPE_LEVEL_LOW: 2316 val = val << 1; 2317 fallthrough; 2318 case IRQ_TYPE_LEVEL_HIGH: 2319 regmap_update_bits(pinctrl->regmap, gpiochip->level[index], 2320 mask, val); 2321 break; 2322 case IRQ_TYPE_EDGE_FALLING: 2323 val = val << 1; 2324 fallthrough; 2325 case IRQ_TYPE_EDGE_RISING: 2326 regmap_update_bits(pinctrl->regmap, gpiochip->edge[index], 2327 mask, val); 2328 break; 2329 case IRQ_TYPE_EDGE_BOTH: 2330 regmap_set_bits(pinctrl->regmap, gpiochip->edge[index], mask); 2331 break; 2332 default: 2333 break; 2334 } 2335} 2336 2337static void airoha_irq_mask(struct irq_data *data) 2338{ 2339 u8 offset = data->hwirq % AIROHA_REG_GPIOCTRL_NUM_PIN; 2340 u8 index = data->hwirq / AIROHA_REG_GPIOCTRL_NUM_PIN; 2341 u32 mask = GENMASK(2 * offset + 1, 2 * offset); 2342 struct airoha_pinctrl_gpiochip *gpiochip; 2343 struct airoha_pinctrl *pinctrl; 2344 2345 gpiochip = irq_data_get_irq_chip_data(data); 2346 pinctrl = container_of(gpiochip, struct airoha_pinctrl, gpiochip); 2347 2348 regmap_clear_bits(pinctrl->regmap, gpiochip->level[index], mask); 2349 regmap_clear_bits(pinctrl->regmap, gpiochip->edge[index], mask); 2350} 2351 2352static int airoha_irq_type(struct irq_data *data, unsigned int type) 2353{ 2354 struct airoha_pinctrl_gpiochip *gpiochip; 2355 2356 gpiochip = irq_data_get_irq_chip_data(data); 2357 if (data->hwirq >= ARRAY_SIZE(gpiochip->irq_type)) 2358 return -EINVAL; 2359 2360 if (type == IRQ_TYPE_PROBE) { 2361 if (gpiochip->irq_type[data->hwirq]) 2362 return 0; 2363 2364 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 2365 } 2366 gpiochip->irq_type[data->hwirq] = type & IRQ_TYPE_SENSE_MASK; 2367 2368 return 0; 2369} 2370 2371static irqreturn_t airoha_irq_handler(int irq, void *data) 2372{ 2373 struct airoha_pinctrl *pinctrl = data; 2374 bool handled = false; 2375 int i; 2376 2377 for (i = 0; i < ARRAY_SIZE(irq_status_regs); i++) { 2378 struct gpio_irq_chip *girq = &pinctrl->gpiochip.chip.irq; 2379 u32 regmap; 2380 unsigned long status; 2381 int irq; 2382 2383 if (regmap_read(pinctrl->regmap, pinctrl->gpiochip.status[i], 2384 ®map)) 2385 continue; 2386 2387 status = regmap; 2388 for_each_set_bit(irq, &status, AIROHA_PIN_BANK_SIZE) { 2389 u32 offset = irq + i * AIROHA_PIN_BANK_SIZE; 2390 2391 generic_handle_irq(irq_find_mapping(girq->domain, 2392 offset)); 2393 regmap_write(pinctrl->regmap, 2394 pinctrl->gpiochip.status[i], BIT(irq)); 2395 } 2396 handled |= !!status; 2397 } 2398 2399 return handled ? IRQ_HANDLED : IRQ_NONE; 2400} 2401 2402static const struct irq_chip airoha_gpio_irq_chip = { 2403 .name = "airoha-gpio-irq", 2404 .irq_unmask = airoha_irq_unmask, 2405 .irq_mask = airoha_irq_mask, 2406 .irq_mask_ack = airoha_irq_mask, 2407 .irq_set_type = airoha_irq_type, 2408 .flags = IRQCHIP_SET_TYPE_MASKED | IRQCHIP_IMMUTABLE, 2409}; 2410 2411static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl, 2412 struct platform_device *pdev) 2413{ 2414 struct airoha_pinctrl_gpiochip *chip = &pinctrl->gpiochip; 2415 struct gpio_chip *gc = &chip->chip; 2416 struct gpio_irq_chip *girq = &gc->irq; 2417 struct device *dev = &pdev->dev; 2418 int irq, err; 2419 2420 chip->data = gpio_data_regs; 2421 chip->dir = gpio_dir_regs; 2422 chip->out = gpio_out_regs; 2423 chip->status = irq_status_regs; 2424 chip->level = irq_level_regs; 2425 chip->edge = irq_edge_regs; 2426 2427 gc->parent = dev; 2428 gc->label = dev_name(dev); 2429 gc->request = gpiochip_generic_request; 2430 gc->free = gpiochip_generic_free; 2431 gc->direction_input = pinctrl_gpio_direction_input; 2432 gc->direction_output = airoha_gpio_direction_output; 2433 gc->set = airoha_gpio_set; 2434 gc->get = airoha_gpio_get; 2435 gc->base = -1; 2436 gc->ngpio = AIROHA_NUM_PINS; 2437 2438 girq->default_type = IRQ_TYPE_NONE; 2439 girq->handler = handle_simple_irq; 2440 gpio_irq_chip_set_chip(girq, &airoha_gpio_irq_chip); 2441 2442 irq = platform_get_irq(pdev, 0); 2443 if (irq < 0) 2444 return irq; 2445 2446 err = devm_request_irq(dev, irq, airoha_irq_handler, IRQF_SHARED, 2447 dev_name(dev), pinctrl); 2448 if (err) { 2449 dev_err(dev, "error requesting irq %d: %d\n", irq, err); 2450 return err; 2451 } 2452 2453 return devm_gpiochip_add_data(dev, gc, pinctrl); 2454} 2455 2456/* pinmux callbacks */ 2457static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev, 2458 unsigned int selector, 2459 unsigned int group) 2460{ 2461 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2462 const struct airoha_pinctrl_func *func; 2463 const struct function_desc *desc; 2464 struct group_desc *grp; 2465 int i; 2466 2467 desc = pinmux_generic_get_function(pctrl_dev, selector); 2468 if (!desc) 2469 return -EINVAL; 2470 2471 grp = pinctrl_generic_get_group(pctrl_dev, group); 2472 if (!grp) 2473 return -EINVAL; 2474 2475 dev_dbg(pctrl_dev->dev, "enable function %s group %s\n", 2476 desc->func->name, grp->grp.name); 2477 2478 func = desc->data; 2479 for (i = 0; i < func->group_size; i++) { 2480 const struct airoha_pinctrl_func_group *group; 2481 int j; 2482 2483 group = &func->groups[i]; 2484 if (strcmp(group->name, grp->grp.name)) 2485 continue; 2486 2487 for (j = 0; j < group->regmap_size; j++) { 2488 switch (group->regmap[j].mux) { 2489 case AIROHA_FUNC_PWM_EXT_MUX: 2490 case AIROHA_FUNC_PWM_MUX: 2491 regmap_update_bits(pinctrl->regmap, 2492 group->regmap[j].offset, 2493 group->regmap[j].mask, 2494 group->regmap[j].val); 2495 break; 2496 default: 2497 regmap_update_bits(pinctrl->chip_scu, 2498 group->regmap[j].offset, 2499 group->regmap[j].mask, 2500 group->regmap[j].val); 2501 break; 2502 } 2503 } 2504 return 0; 2505 } 2506 2507 return -EINVAL; 2508} 2509 2510static int airoha_pinmux_set_direction(struct pinctrl_dev *pctrl_dev, 2511 struct pinctrl_gpio_range *range, 2512 unsigned int p, bool input) 2513{ 2514 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2515 u32 mask, index; 2516 int err, pin; 2517 2518 pin = airoha_convert_pin_to_reg_offset(pctrl_dev, range, p); 2519 if (pin < 0) 2520 return pin; 2521 2522 /* set output enable */ 2523 mask = BIT(pin % AIROHA_PIN_BANK_SIZE); 2524 index = pin / AIROHA_PIN_BANK_SIZE; 2525 err = regmap_update_bits(pinctrl->regmap, pinctrl->gpiochip.out[index], 2526 mask, !input ? mask : 0); 2527 if (err) 2528 return err; 2529 2530 /* set direction */ 2531 mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); 2532 index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; 2533 return regmap_update_bits(pinctrl->regmap, 2534 pinctrl->gpiochip.dir[index], mask, 2535 !input ? mask : 0); 2536} 2537 2538static const struct pinmux_ops airoha_pmxops = { 2539 .get_functions_count = pinmux_generic_get_function_count, 2540 .get_function_name = pinmux_generic_get_function_name, 2541 .get_function_groups = pinmux_generic_get_function_groups, 2542 .gpio_set_direction = airoha_pinmux_set_direction, 2543 .set_mux = airoha_pinmux_set_mux, 2544 .strict = true, 2545}; 2546 2547/* pinconf callbacks */ 2548static const struct airoha_pinctrl_reg * 2549airoha_pinctrl_get_conf_reg(const struct airoha_pinctrl_conf *conf, 2550 int conf_size, int pin) 2551{ 2552 int i; 2553 2554 for (i = 0; i < conf_size; i++) { 2555 if (conf[i].pin == pin) 2556 return &conf[i].reg; 2557 } 2558 2559 return NULL; 2560} 2561 2562static int airoha_pinctrl_get_conf(struct airoha_pinctrl *pinctrl, 2563 enum airoha_pinctrl_confs_type conf_type, 2564 int pin, u32 *val) 2565{ 2566 const struct airoha_pinctrl_confs_info *confs_info; 2567 const struct airoha_pinctrl_reg *reg; 2568 2569 confs_info = &pinctrl->confs_info[conf_type]; 2570 2571 reg = airoha_pinctrl_get_conf_reg(confs_info->confs, 2572 confs_info->num_confs, 2573 pin); 2574 if (!reg) 2575 return -EINVAL; 2576 2577 if (regmap_read(pinctrl->chip_scu, reg->offset, val)) 2578 return -EINVAL; 2579 2580 *val = (*val & reg->mask) >> __ffs(reg->mask); 2581 2582 return 0; 2583} 2584 2585static int airoha_pinctrl_set_conf(struct airoha_pinctrl *pinctrl, 2586 enum airoha_pinctrl_confs_type conf_type, 2587 int pin, u32 val) 2588{ 2589 const struct airoha_pinctrl_confs_info *confs_info; 2590 const struct airoha_pinctrl_reg *reg = NULL; 2591 2592 confs_info = &pinctrl->confs_info[conf_type]; 2593 2594 reg = airoha_pinctrl_get_conf_reg(confs_info->confs, 2595 confs_info->num_confs, 2596 pin); 2597 if (!reg) 2598 return -EINVAL; 2599 2600 2601 if (regmap_update_bits(pinctrl->chip_scu, reg->offset, reg->mask, 2602 val << __ffs(reg->mask))) 2603 return -EINVAL; 2604 2605 return 0; 2606} 2607 2608#define airoha_pinctrl_get_pullup_conf(pinctrl, pin, val) \ 2609 airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ 2610 (pin), (val)) 2611#define airoha_pinctrl_get_pulldown_conf(pinctrl, pin, val) \ 2612 airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ 2613 (pin), (val)) 2614#define airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, val) \ 2615 airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ 2616 (pin), (val)) 2617#define airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, val) \ 2618 airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ 2619 (pin), (val)) 2620#define airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, val) \ 2621 airoha_pinctrl_get_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ 2622 (pin), (val)) 2623#define airoha_pinctrl_set_pullup_conf(pinctrl, pin, val) \ 2624 airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLUP, \ 2625 (pin), (val)) 2626#define airoha_pinctrl_set_pulldown_conf(pinctrl, pin, val) \ 2627 airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PULLDOWN, \ 2628 (pin), (val)) 2629#define airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, val) \ 2630 airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E2, \ 2631 (pin), (val)) 2632#define airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, val) \ 2633 airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_DRIVE_E4, \ 2634 (pin), (val)) 2635#define airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, val) \ 2636 airoha_pinctrl_set_conf((pinctrl), AIROHA_PINCTRL_CONFS_PCIE_RST_OD, \ 2637 (pin), (val)) 2638 2639static int airoha_pinconf_get_direction(struct pinctrl_dev *pctrl_dev, u32 p) 2640{ 2641 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2642 u32 val, mask; 2643 int err, pin; 2644 u8 index; 2645 2646 pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); 2647 if (pin < 0) 2648 return pin; 2649 2650 index = pin / AIROHA_REG_GPIOCTRL_NUM_PIN; 2651 err = regmap_read(pinctrl->regmap, pinctrl->gpiochip.dir[index], &val); 2652 if (err) 2653 return err; 2654 2655 mask = BIT(2 * (pin % AIROHA_REG_GPIOCTRL_NUM_PIN)); 2656 return val & mask ? PIN_CONFIG_OUTPUT_ENABLE : PIN_CONFIG_INPUT_ENABLE; 2657} 2658 2659static int airoha_pinconf_get(struct pinctrl_dev *pctrl_dev, 2660 unsigned int pin, unsigned long *config) 2661{ 2662 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2663 enum pin_config_param param = pinconf_to_config_param(*config); 2664 u32 arg; 2665 2666 switch (param) { 2667 case PIN_CONFIG_BIAS_PULL_DOWN: 2668 case PIN_CONFIG_BIAS_DISABLE: 2669 case PIN_CONFIG_BIAS_PULL_UP: { 2670 u32 pull_up, pull_down; 2671 2672 if (airoha_pinctrl_get_pullup_conf(pinctrl, pin, &pull_up) || 2673 airoha_pinctrl_get_pulldown_conf(pinctrl, pin, &pull_down)) 2674 return -EINVAL; 2675 2676 if (param == PIN_CONFIG_BIAS_PULL_UP && 2677 !(pull_up && !pull_down)) 2678 return -EINVAL; 2679 else if (param == PIN_CONFIG_BIAS_PULL_DOWN && 2680 !(pull_down && !pull_up)) 2681 return -EINVAL; 2682 else if (pull_up || pull_down) 2683 return -EINVAL; 2684 2685 arg = 1; 2686 break; 2687 } 2688 case PIN_CONFIG_DRIVE_STRENGTH: { 2689 u32 e2, e4; 2690 2691 if (airoha_pinctrl_get_drive_e2_conf(pinctrl, pin, &e2) || 2692 airoha_pinctrl_get_drive_e4_conf(pinctrl, pin, &e4)) 2693 return -EINVAL; 2694 2695 arg = e4 << 1 | e2; 2696 break; 2697 } 2698 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2699 if (airoha_pinctrl_get_pcie_rst_od_conf(pinctrl, pin, &arg)) 2700 return -EINVAL; 2701 break; 2702 case PIN_CONFIG_OUTPUT_ENABLE: 2703 case PIN_CONFIG_INPUT_ENABLE: 2704 arg = airoha_pinconf_get_direction(pctrl_dev, pin); 2705 if (arg != param) 2706 return -EINVAL; 2707 2708 arg = 1; 2709 break; 2710 default: 2711 return -ENOTSUPP; 2712 } 2713 2714 *config = pinconf_to_config_packed(param, arg); 2715 2716 return 0; 2717} 2718 2719static int airoha_pinconf_set_pin_value(struct pinctrl_dev *pctrl_dev, 2720 unsigned int p, bool value) 2721{ 2722 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2723 int pin; 2724 2725 pin = airoha_convert_pin_to_reg_offset(pctrl_dev, NULL, p); 2726 if (pin < 0) 2727 return pin; 2728 2729 return airoha_gpio_set(&pinctrl->gpiochip.chip, pin, value); 2730} 2731 2732static int airoha_pinconf_set(struct pinctrl_dev *pctrl_dev, 2733 unsigned int pin, unsigned long *configs, 2734 unsigned int num_configs) 2735{ 2736 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2737 int i; 2738 2739 for (i = 0; i < num_configs; i++) { 2740 u32 param = pinconf_to_config_param(configs[i]); 2741 u32 arg = pinconf_to_config_argument(configs[i]); 2742 2743 switch (param) { 2744 case PIN_CONFIG_BIAS_DISABLE: 2745 airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); 2746 airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); 2747 break; 2748 case PIN_CONFIG_BIAS_PULL_UP: 2749 airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 0); 2750 airoha_pinctrl_set_pullup_conf(pinctrl, pin, 1); 2751 break; 2752 case PIN_CONFIG_BIAS_PULL_DOWN: 2753 airoha_pinctrl_set_pulldown_conf(pinctrl, pin, 1); 2754 airoha_pinctrl_set_pullup_conf(pinctrl, pin, 0); 2755 break; 2756 case PIN_CONFIG_DRIVE_STRENGTH: { 2757 u32 e2 = 0, e4 = 0; 2758 2759 switch (arg) { 2760 case MTK_DRIVE_2mA: 2761 break; 2762 case MTK_DRIVE_4mA: 2763 e2 = 1; 2764 break; 2765 case MTK_DRIVE_6mA: 2766 e4 = 1; 2767 break; 2768 case MTK_DRIVE_8mA: 2769 e2 = 1; 2770 e4 = 1; 2771 break; 2772 default: 2773 return -EINVAL; 2774 } 2775 2776 airoha_pinctrl_set_drive_e2_conf(pinctrl, pin, e2); 2777 airoha_pinctrl_set_drive_e4_conf(pinctrl, pin, e4); 2778 break; 2779 } 2780 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 2781 airoha_pinctrl_set_pcie_rst_od_conf(pinctrl, pin, !!arg); 2782 break; 2783 case PIN_CONFIG_OUTPUT_ENABLE: 2784 case PIN_CONFIG_INPUT_ENABLE: 2785 case PIN_CONFIG_LEVEL: { 2786 bool input = param == PIN_CONFIG_INPUT_ENABLE; 2787 int err; 2788 2789 err = airoha_pinmux_set_direction(pctrl_dev, NULL, pin, 2790 input); 2791 if (err) 2792 return err; 2793 2794 if (param == PIN_CONFIG_LEVEL) { 2795 err = airoha_pinconf_set_pin_value(pctrl_dev, 2796 pin, !!arg); 2797 if (err) 2798 return err; 2799 } 2800 break; 2801 } 2802 default: 2803 return -ENOTSUPP; 2804 } 2805 } 2806 2807 return 0; 2808} 2809 2810static int airoha_pinconf_group_get(struct pinctrl_dev *pctrl_dev, 2811 unsigned int group, unsigned long *config) 2812{ 2813 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2814 u32 cur_config = 0; 2815 int i; 2816 2817 for (i = 0; i < pinctrl->grps[group].npins; i++) { 2818 if (airoha_pinconf_get(pctrl_dev, 2819 pinctrl->grps[group].pins[i], 2820 config)) 2821 return -ENOTSUPP; 2822 2823 if (i && cur_config != *config) 2824 return -ENOTSUPP; 2825 2826 cur_config = *config; 2827 } 2828 2829 return 0; 2830} 2831 2832static int airoha_pinconf_group_set(struct pinctrl_dev *pctrl_dev, 2833 unsigned int group, unsigned long *configs, 2834 unsigned int num_configs) 2835{ 2836 struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev); 2837 int i; 2838 2839 for (i = 0; i < pinctrl->grps[group].npins; i++) { 2840 int err; 2841 2842 err = airoha_pinconf_set(pctrl_dev, 2843 pinctrl->grps[group].pins[i], 2844 configs, num_configs); 2845 if (err) 2846 return err; 2847 } 2848 2849 return 0; 2850} 2851 2852static const struct pinconf_ops airoha_confops = { 2853 .is_generic = true, 2854 .pin_config_get = airoha_pinconf_get, 2855 .pin_config_set = airoha_pinconf_set, 2856 .pin_config_group_get = airoha_pinconf_group_get, 2857 .pin_config_group_set = airoha_pinconf_group_set, 2858 .pin_config_config_dbg_show = pinconf_generic_dump_config, 2859}; 2860 2861static const struct pinctrl_ops airoha_pctlops = { 2862 .get_groups_count = pinctrl_generic_get_group_count, 2863 .get_group_name = pinctrl_generic_get_group_name, 2864 .get_group_pins = pinctrl_generic_get_group_pins, 2865 .dt_node_to_map = pinconf_generic_dt_node_to_map_all, 2866 .dt_free_map = pinconf_generic_dt_free_map, 2867}; 2868 2869static int airoha_pinctrl_probe(struct platform_device *pdev) 2870{ 2871 const struct airoha_pinctrl_match_data *data; 2872 struct device *dev = &pdev->dev; 2873 struct airoha_pinctrl *pinctrl; 2874 struct regmap *map; 2875 int err, i; 2876 2877 data = device_get_match_data(dev); 2878 2879 pinctrl = devm_kzalloc(dev, sizeof(*pinctrl), GFP_KERNEL); 2880 if (!pinctrl) 2881 return -ENOMEM; 2882 2883 pinctrl->regmap = device_node_to_regmap(dev->parent->of_node); 2884 if (IS_ERR(pinctrl->regmap)) 2885 return PTR_ERR(pinctrl->regmap); 2886 2887 map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu"); 2888 if (IS_ERR(map)) 2889 return PTR_ERR(map); 2890 2891 pinctrl->chip_scu = map; 2892 2893 /* Init pinctrl desc struct */ 2894 pinctrl->desc.name = KBUILD_MODNAME; 2895 pinctrl->desc.owner = THIS_MODULE; 2896 pinctrl->desc.pctlops = &airoha_pctlops; 2897 pinctrl->desc.pmxops = &airoha_pmxops; 2898 pinctrl->desc.confops = &airoha_confops; 2899 pinctrl->desc.pins = data->pins; 2900 pinctrl->desc.npins = data->num_pins; 2901 2902 err = devm_pinctrl_register_and_init(dev, &pinctrl->desc, 2903 pinctrl, &pinctrl->ctrl); 2904 if (err) 2905 return err; 2906 2907 /* build pin groups */ 2908 for (i = 0; i < data->num_grps; i++) { 2909 const struct pingroup *grp = &data->grps[i]; 2910 2911 err = pinctrl_generic_add_group(pinctrl->ctrl, grp->name, 2912 grp->pins, grp->npins, 2913 (void *)grp); 2914 if (err < 0) { 2915 dev_err(&pdev->dev, "Failed to register group %s\n", 2916 grp->name); 2917 return err; 2918 } 2919 } 2920 2921 /* build functions */ 2922 for (i = 0; i < data->num_funcs; i++) { 2923 const struct airoha_pinctrl_func *func; 2924 2925 func = &data->funcs[i]; 2926 err = pinmux_generic_add_pinfunction(pinctrl->ctrl, 2927 &func->desc, 2928 (void *)func); 2929 if (err < 0) { 2930 dev_err(dev, "Failed to register function %s\n", 2931 func->desc.name); 2932 return err; 2933 } 2934 } 2935 2936 pinctrl->grps = data->grps; 2937 pinctrl->funcs = data->funcs; 2938 pinctrl->confs_info = data->confs_info; 2939 2940 err = pinctrl_enable(pinctrl->ctrl); 2941 if (err) 2942 return err; 2943 2944 /* build gpio-chip */ 2945 return airoha_pinctrl_add_gpiochip(pinctrl, pdev); 2946} 2947 2948static const struct airoha_pinctrl_match_data en7581_pinctrl_match_data = { 2949 .pins = en7581_pinctrl_pins, 2950 .num_pins = ARRAY_SIZE(en7581_pinctrl_pins), 2951 .grps = en7581_pinctrl_groups, 2952 .num_grps = ARRAY_SIZE(en7581_pinctrl_groups), 2953 .funcs = en7581_pinctrl_funcs, 2954 .num_funcs = ARRAY_SIZE(en7581_pinctrl_funcs), 2955 .confs_info = { 2956 [AIROHA_PINCTRL_CONFS_PULLUP] = { 2957 .confs = en7581_pinctrl_pullup_conf, 2958 .num_confs = ARRAY_SIZE(en7581_pinctrl_pullup_conf), 2959 }, 2960 [AIROHA_PINCTRL_CONFS_PULLDOWN] = { 2961 .confs = en7581_pinctrl_pulldown_conf, 2962 .num_confs = ARRAY_SIZE(en7581_pinctrl_pulldown_conf), 2963 }, 2964 [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { 2965 .confs = en7581_pinctrl_drive_e2_conf, 2966 .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e2_conf), 2967 }, 2968 [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { 2969 .confs = en7581_pinctrl_drive_e4_conf, 2970 .num_confs = ARRAY_SIZE(en7581_pinctrl_drive_e4_conf), 2971 }, 2972 [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { 2973 .confs = en7581_pinctrl_pcie_rst_od_conf, 2974 .num_confs = ARRAY_SIZE(en7581_pinctrl_pcie_rst_od_conf), 2975 }, 2976 }, 2977}; 2978 2979static const struct airoha_pinctrl_match_data an7583_pinctrl_match_data = { 2980 .pins = an7583_pinctrl_pins, 2981 .num_pins = ARRAY_SIZE(an7583_pinctrl_pins), 2982 .grps = an7583_pinctrl_groups, 2983 .num_grps = ARRAY_SIZE(an7583_pinctrl_groups), 2984 .funcs = an7583_pinctrl_funcs, 2985 .num_funcs = ARRAY_SIZE(an7583_pinctrl_funcs), 2986 .confs_info = { 2987 [AIROHA_PINCTRL_CONFS_PULLUP] = { 2988 .confs = an7583_pinctrl_pullup_conf, 2989 .num_confs = ARRAY_SIZE(an7583_pinctrl_pullup_conf), 2990 }, 2991 [AIROHA_PINCTRL_CONFS_PULLDOWN] = { 2992 .confs = an7583_pinctrl_pulldown_conf, 2993 .num_confs = ARRAY_SIZE(an7583_pinctrl_pulldown_conf), 2994 }, 2995 [AIROHA_PINCTRL_CONFS_DRIVE_E2] = { 2996 .confs = an7583_pinctrl_drive_e2_conf, 2997 .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e2_conf), 2998 }, 2999 [AIROHA_PINCTRL_CONFS_DRIVE_E4] = { 3000 .confs = an7583_pinctrl_drive_e4_conf, 3001 .num_confs = ARRAY_SIZE(an7583_pinctrl_drive_e4_conf), 3002 }, 3003 [AIROHA_PINCTRL_CONFS_PCIE_RST_OD] = { 3004 .confs = an7583_pinctrl_pcie_rst_od_conf, 3005 .num_confs = ARRAY_SIZE(an7583_pinctrl_pcie_rst_od_conf), 3006 }, 3007 }, 3008}; 3009 3010static const struct of_device_id airoha_pinctrl_of_match[] = { 3011 { .compatible = "airoha,en7581-pinctrl", .data = &en7581_pinctrl_match_data }, 3012 { .compatible = "airoha,an7583-pinctrl", .data = &an7583_pinctrl_match_data }, 3013 { /* sentinel */ } 3014}; 3015MODULE_DEVICE_TABLE(of, airoha_pinctrl_of_match); 3016 3017static struct platform_driver airoha_pinctrl_driver = { 3018 .probe = airoha_pinctrl_probe, 3019 .driver = { 3020 .name = "pinctrl-airoha", 3021 .of_match_table = airoha_pinctrl_of_match, 3022 }, 3023}; 3024module_platform_driver(airoha_pinctrl_driver); 3025 3026MODULE_LICENSE("GPL"); 3027MODULE_AUTHOR("Lorenzo Bianconi <lorenzo@kernel.org>"); 3028MODULE_AUTHOR("Benjamin Larsson <benjamin.larsson@genexis.eu>"); 3029MODULE_AUTHOR("Markus Gothe <markus.gothe@genexis.eu>"); 3030MODULE_DESCRIPTION("Pinctrl driver for Airoha SoC");
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