pinctrl-meteorlake.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Intel Meteor Lake PCH pinctrl/GPIO driver
  4 *
  5 * Copyright (C) 2022, Intel Corporation
  6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  7 */
  8
  9#include <linux/mod_devicetable.h>
 10#include <linux/module.h>
 11#include <linux/platform_device.h>
 12#include <linux/pm.h>
 13
 14#include <linux/pinctrl/pinctrl.h>
 15
 16#include "pinctrl-intel.h"
 17
 18#define MTL_P_PAD_OWN		0x0b0
 19#define MTL_P_PADCFGLOCK	0x110
 20#define MTL_P_HOSTSW_OWN	0x140
 21#define MTL_P_GPI_IS		0x200
 22#define MTL_P_GPI_IE		0x210
 23
 24#define MTL_S_PAD_OWN		0x0b0
 25#define MTL_S_PADCFGLOCK	0x0f0
 26#define MTL_S_HOSTSW_OWN	0x110
 27#define MTL_S_GPI_IS		0x200
 28#define MTL_S_GPI_IE		0x210
 29
 30#define MTL_P_COMMUNITY(b, s, e, g)			\
 31	INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
 32
 33#define MTL_S_COMMUNITY(b, s, e, g)			\
 34	INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_S)
 35
 36/* Meteor Lake-P */
 37static const struct pinctrl_pin_desc mtlp_pins[] = {
 38	/* CPU */
 39	PINCTRL_PIN(0, "PECI"),
 40	PINCTRL_PIN(1, "UFS_RESET_B"),
 41	PINCTRL_PIN(2, "VIDSOUT"),
 42	PINCTRL_PIN(3, "VIDSCK"),
 43	PINCTRL_PIN(4, "VIDALERT_B"),
 44	/* GPP_V */
 45	PINCTRL_PIN(5, "BATLOW_B"),
 46	PINCTRL_PIN(6, "AC_PRESENT"),
 47	PINCTRL_PIN(7, "SOC_WAKE_B"),
 48	PINCTRL_PIN(8, "PWRBTN_B"),
 49	PINCTRL_PIN(9, "SLP_S3_B"),
 50	PINCTRL_PIN(10, "SLP_S4_B"),
 51	PINCTRL_PIN(11, "SLP_A_B"),
 52	PINCTRL_PIN(12, "GPP_V_7"),
 53	PINCTRL_PIN(13, "SUSCLK"),
 54	PINCTRL_PIN(14, "SLP_WLAN_B"),
 55	PINCTRL_PIN(15, "SLP_S5_B"),
 56	PINCTRL_PIN(16, "LANPHYPC"),
 57	PINCTRL_PIN(17, "SLP_LAN_B"),
 58	PINCTRL_PIN(18, "GPP_V_13"),
 59	PINCTRL_PIN(19, "WAKE_B"),
 60	PINCTRL_PIN(20, "GPP_V_15"),
 61	PINCTRL_PIN(21, "GPP_V_16"),
 62	PINCTRL_PIN(22, "GPP_V_17"),
 63	PINCTRL_PIN(23, "GPP_V_18"),
 64	PINCTRL_PIN(24, "CATERR_B"),
 65	PINCTRL_PIN(25, "PROCHOT_B"),
 66	PINCTRL_PIN(26, "THERMTRIP_B"),
 67	PINCTRL_PIN(27, "DSI_DE_TE_2_GENLOCK_REF"),
 68	PINCTRL_PIN(28, "DSI_DE_TE_1_DISP_UTILS"),
 69	/* GPP_C */
 70	PINCTRL_PIN(29, "SMBCLK"),
 71	PINCTRL_PIN(30, "SMBDATA"),
 72	PINCTRL_PIN(31, "SMBALERT_B"),
 73	PINCTRL_PIN(32, "SML0CLK"),
 74	PINCTRL_PIN(33, "SML0DATA"),
 75	PINCTRL_PIN(34, "GPP_C_5"),
 76	PINCTRL_PIN(35, "GPP_C_6"),
 77	PINCTRL_PIN(36, "GPP_C_7"),
 78	PINCTRL_PIN(37, "GPP_C_8"),
 79	PINCTRL_PIN(38, "GPP_C_9"),
 80	PINCTRL_PIN(39, "GPP_C_10"),
 81	PINCTRL_PIN(40, "GPP_C_11"),
 82	PINCTRL_PIN(41, "GPP_C_12"),
 83	PINCTRL_PIN(42, "GPP_C_13"),
 84	PINCTRL_PIN(43, "GPP_C_14"),
 85	PINCTRL_PIN(44, "GPP_C_15"),
 86	PINCTRL_PIN(45, "GPP_C_16"),
 87	PINCTRL_PIN(46, "GPP_C_17"),
 88	PINCTRL_PIN(47, "GPP_C_18"),
 89	PINCTRL_PIN(48, "GPP_C_19"),
 90	PINCTRL_PIN(49, "GPP_C_20"),
 91	PINCTRL_PIN(50, "GPP_C_21"),
 92	PINCTRL_PIN(51, "GPP_C_22"),
 93	PINCTRL_PIN(52, "GPP_C_23"),
 94	/* GPP_A */
 95	PINCTRL_PIN(53, "ESPI_IO_0"),
 96	PINCTRL_PIN(54, "ESPI_IO_1"),
 97	PINCTRL_PIN(55, "ESPI_IO_2"),
 98	PINCTRL_PIN(56, "ESPI_IO_3"),
 99	PINCTRL_PIN(57, "ESPI_CS0_B"),
100	PINCTRL_PIN(58, "ESPI_CLK"),
101	PINCTRL_PIN(59, "ESPI_RESET_B"),
102	PINCTRL_PIN(60, "GPP_A_7"),
103	PINCTRL_PIN(61, "GPP_A_8"),
104	PINCTRL_PIN(62, "GPP_A_9"),
105	PINCTRL_PIN(63, "GPP_A_10"),
106	PINCTRL_PIN(64, "GPP_A_11"),
107	PINCTRL_PIN(65, "GPP_A_12"),
108	PINCTRL_PIN(66, "ESPI_CS1_B"),
109	PINCTRL_PIN(67, "ESPI_CS2_B"),
110	PINCTRL_PIN(68, "ESPI_CS3_B"),
111	PINCTRL_PIN(69, "ESPI_ALERT0_B"),
112	PINCTRL_PIN(70, "ESPI_ALERT1_B"),
113	PINCTRL_PIN(71, "ESPI_ALERT2_B"),
114	PINCTRL_PIN(72, "ESPI_ALERT3_B"),
115	PINCTRL_PIN(73, "GPP_A_20"),
116	PINCTRL_PIN(74, "GPP_A_21"),
117	PINCTRL_PIN(75, "GPP_A_22"),
118	PINCTRL_PIN(76, "GPP_A_23"),
119	PINCTRL_PIN(77, "ESPI_CLK_LOOPBK"),
120	/* GPP_E */
121	PINCTRL_PIN(78, "GPP_E_0"),
122	PINCTRL_PIN(79, "GPP_E_1"),
123	PINCTRL_PIN(80, "GPP_E_2"),
124	PINCTRL_PIN(81, "GPP_E_3"),
125	PINCTRL_PIN(82, "GPP_E_4"),
126	PINCTRL_PIN(83, "GPP_E_5"),
127	PINCTRL_PIN(84, "GPP_E_6"),
128	PINCTRL_PIN(85, "GPP_E_7"),
129	PINCTRL_PIN(86, "GPP_E_8"),
130	PINCTRL_PIN(87, "GPP_E_9"),
131	PINCTRL_PIN(88, "GPP_E_10"),
132	PINCTRL_PIN(89, "GPP_E_11"),
133	PINCTRL_PIN(90, "GPP_E_12"),
134	PINCTRL_PIN(91, "GPP_E_13"),
135	PINCTRL_PIN(92, "GPP_E_14"),
136	PINCTRL_PIN(93, "SLP_DRAM_B"),
137	PINCTRL_PIN(94, "GPP_E_16"),
138	PINCTRL_PIN(95, "GPP_E_17"),
139	PINCTRL_PIN(96, "GPP_E_18"),
140	PINCTRL_PIN(97, "GPP_E_19"),
141	PINCTRL_PIN(98, "GPP_E_20"),
142	PINCTRL_PIN(99, "GPP_E_21"),
143	PINCTRL_PIN(100, "DNX_FORCE_RELOAD"),
144	PINCTRL_PIN(101, "GPP_E_23"),
145	PINCTRL_PIN(102, "THC0_GSPI0_CLK_LOOPBK"),
146	/* GPP_H */
147	PINCTRL_PIN(103, "GPP_H_0"),
148	PINCTRL_PIN(104, "GPP_H_1"),
149	PINCTRL_PIN(105, "GPP_H_2"),
150	PINCTRL_PIN(106, "GPP_H_3"),
151	PINCTRL_PIN(107, "GPP_H_4"),
152	PINCTRL_PIN(108, "GPP_H_5"),
153	PINCTRL_PIN(109, "GPP_H_6"),
154	PINCTRL_PIN(110, "GPP_H_7"),
155	PINCTRL_PIN(111, "GPP_H_8"),
156	PINCTRL_PIN(112, "GPP_H_9"),
157	PINCTRL_PIN(113, "GPP_H_10"),
158	PINCTRL_PIN(114, "GPP_H_11"),
159	PINCTRL_PIN(115, "GPP_H_12"),
160	PINCTRL_PIN(116, "CPU_C10_GATE_B"),
161	PINCTRL_PIN(117, "GPP_H_14"),
162	PINCTRL_PIN(118, "GPP_H_15"),
163	PINCTRL_PIN(119, "GPP_H_16"),
164	PINCTRL_PIN(120, "GPP_H_17"),
165	PINCTRL_PIN(121, "GPP_H_18"),
166	PINCTRL_PIN(122, "GPP_H_19"),
167	PINCTRL_PIN(123, "GPP_H_20"),
168	PINCTRL_PIN(124, "GPP_H_21"),
169	PINCTRL_PIN(125, "GPP_H_22"),
170	PINCTRL_PIN(126, "GPP_H_23"),
171	PINCTRL_PIN(127, "LPI3C1_CLK_LOOPBK"),
172	PINCTRL_PIN(128, "I3C0_CLK_LOOPBK"),
173	/* GPP_F */
174	PINCTRL_PIN(129, "CNV_BRI_DT"),
175	PINCTRL_PIN(130, "CNV_BRI_RSP"),
176	PINCTRL_PIN(131, "CNV_RGI_DT"),
177	PINCTRL_PIN(132, "CNV_RGI_RSP"),
178	PINCTRL_PIN(133, "CNV_RF_RESET_B"),
179	PINCTRL_PIN(134, "CRF_CLKREQ"),
180	PINCTRL_PIN(135, "GPP_F_6"),
181	PINCTRL_PIN(136, "FUSA_DIAGTEST_EN"),
182	PINCTRL_PIN(137, "FUSA_DIAGTEST_MODE"),
183	PINCTRL_PIN(138, "BOOTMPC"),
184	PINCTRL_PIN(139, "GPP_F_10"),
185	PINCTRL_PIN(140, "GPP_F_11"),
186	PINCTRL_PIN(141, "GSXDOUT"),
187	PINCTRL_PIN(142, "GSXSLOAD"),
188	PINCTRL_PIN(143, "GSXDIN"),
189	PINCTRL_PIN(144, "GSXSRESETB"),
190	PINCTRL_PIN(145, "GSXCLK"),
191	PINCTRL_PIN(146, "GMII_MDC_0"),
192	PINCTRL_PIN(147, "GMII_MDIO_0"),
193	PINCTRL_PIN(148, "GPP_F_19"),
194	PINCTRL_PIN(149, "GPP_F_20"),
195	PINCTRL_PIN(150, "GPP_F_21"),
196	PINCTRL_PIN(151, "GPP_F_22"),
197	PINCTRL_PIN(152, "GPP_F_23"),
198	PINCTRL_PIN(153, "THC1_GSPI1_CLK_LOOPBK"),
199	PINCTRL_PIN(154, "GSPI0A_CLK_LOOPBK"),
200	/* SPI0 */
201	PINCTRL_PIN(155, "SPI0_IO_2"),
202	PINCTRL_PIN(156, "SPI0_IO_3"),
203	PINCTRL_PIN(157, "SPI0_MOSI_IO_0"),
204	PINCTRL_PIN(158, "SPI0_MISO_IO_1"),
205	PINCTRL_PIN(159, "SPI0_TPM_CS_B"),
206	PINCTRL_PIN(160, "SPI0_FLASH_0_CS_B"),
207	PINCTRL_PIN(161, "SPI0_FLASH_1_CS_B"),
208	PINCTRL_PIN(162, "SPI0_CLK"),
209	PINCTRL_PIN(163, "L_BKLTEN"),
210	PINCTRL_PIN(164, "L_BKLTCTL"),
211	PINCTRL_PIN(165, "L_VDDEN"),
212	PINCTRL_PIN(166, "SYS_PWROK"),
213	PINCTRL_PIN(167, "SYS_RESET_B"),
214	PINCTRL_PIN(168, "MLK_RST_B"),
215	PINCTRL_PIN(169, "SPI0_CLK_LOOPBK"),
216	/* vGPIO_3 */
217	PINCTRL_PIN(170, "ESPI_USB_OCB_0"),
218	PINCTRL_PIN(171, "ESPI_USB_OCB_1"),
219	PINCTRL_PIN(172, "ESPI_USB_OCB_2"),
220	PINCTRL_PIN(173, "ESPI_USB_OCB_3"),
221	PINCTRL_PIN(174, "USB_CPU_OCB_0"),
222	PINCTRL_PIN(175, "USB_CPU_OCB_1"),
223	PINCTRL_PIN(176, "USB_CPU_OCB_2"),
224	PINCTRL_PIN(177, "USB_CPU_OCB_3"),
225	PINCTRL_PIN(178, "TS0_IN_INT"),
226	PINCTRL_PIN(179, "TS1_IN_INT"),
227	PINCTRL_PIN(180, "THC0_WOT_INT"),
228	PINCTRL_PIN(181, "THC1_WOT_INT"),
229	PINCTRL_PIN(182, "THC0_WHC_INT"),
230	PINCTRL_PIN(183, "THC1_WHC_INT"),
231	/* GPP_S */
232	PINCTRL_PIN(184, "GPP_S_0"),
233	PINCTRL_PIN(185, "GPP_S_1"),
234	PINCTRL_PIN(186, "GPP_S_2"),
235	PINCTRL_PIN(187, "GPP_S_3"),
236	PINCTRL_PIN(188, "GPP_S_4"),
237	PINCTRL_PIN(189, "GPP_S_5"),
238	PINCTRL_PIN(190, "GPP_S_6"),
239	PINCTRL_PIN(191, "GPP_S_7"),
240	/* JTAG */
241	PINCTRL_PIN(192, "JTAG_MBPB0"),
242	PINCTRL_PIN(193, "JTAG_MBPB1"),
243	PINCTRL_PIN(194, "JTAG_MBPB2"),
244	PINCTRL_PIN(195, "JTAG_MBPB3"),
245	PINCTRL_PIN(196, "JTAG_TDO"),
246	PINCTRL_PIN(197, "PRDY_B"),
247	PINCTRL_PIN(198, "PREQ_B"),
248	PINCTRL_PIN(199, "JTAG_TDI"),
249	PINCTRL_PIN(200, "JTAG_TMS"),
250	PINCTRL_PIN(201, "JTAG_TCK"),
251	PINCTRL_PIN(202, "DBG_PMODE"),
252	PINCTRL_PIN(203, "JTAG_TRST_B"),
253	/* GPP_B */
254	PINCTRL_PIN(204, "ADM_VID_0"),
255	PINCTRL_PIN(205, "ADM_VID_1"),
256	PINCTRL_PIN(206, "GPP_B_2"),
257	PINCTRL_PIN(207, "GPP_B_3"),
258	PINCTRL_PIN(208, "GPP_B_4"),
259	PINCTRL_PIN(209, "GPP_B_5"),
260	PINCTRL_PIN(210, "GPP_B_6"),
261	PINCTRL_PIN(211, "GPP_B_7"),
262	PINCTRL_PIN(212, "GPP_B_8"),
263	PINCTRL_PIN(213, "GPP_B_9"),
264	PINCTRL_PIN(214, "GPP_B_10"),
265	PINCTRL_PIN(215, "GPP_B_11"),
266	PINCTRL_PIN(216, "SLP_S0_B"),
267	PINCTRL_PIN(217, "PLTRST_B"),
268	PINCTRL_PIN(218, "GPP_B_14"),
269	PINCTRL_PIN(219, "GPP_B_15"),
270	PINCTRL_PIN(220, "GPP_B_16"),
271	PINCTRL_PIN(221, "GPP_B_17"),
272	PINCTRL_PIN(222, "GPP_B_18"),
273	PINCTRL_PIN(223, "GPP_B_19"),
274	PINCTRL_PIN(224, "GPP_B_20"),
275	PINCTRL_PIN(225, "GPP_B_21"),
276	PINCTRL_PIN(226, "GPP_B_22"),
277	PINCTRL_PIN(227, "GPP_B_23"),
278	PINCTRL_PIN(228, "ISH_I3C0_CLK_LOOPBK"),
279	/* GPP_D */
280	PINCTRL_PIN(229, "GPP_D_0"),
281	PINCTRL_PIN(230, "GPP_D_1"),
282	PINCTRL_PIN(231, "GPP_D_2"),
283	PINCTRL_PIN(232, "GPP_D_3"),
284	PINCTRL_PIN(233, "GPP_D_4"),
285	PINCTRL_PIN(234, "GPP_D_5"),
286	PINCTRL_PIN(235, "GPP_D_6"),
287	PINCTRL_PIN(236, "GPP_D_7"),
288	PINCTRL_PIN(237, "GPP_D_8"),
289	PINCTRL_PIN(238, "GPP_D_9"),
290	PINCTRL_PIN(239, "HDA_BCLK"),
291	PINCTRL_PIN(240, "HDA_SYNC"),
292	PINCTRL_PIN(241, "HDA_SDO"),
293	PINCTRL_PIN(242, "HDA_SDI_0"),
294	PINCTRL_PIN(243, "GPP_D_14"),
295	PINCTRL_PIN(244, "GPP_D_15"),
296	PINCTRL_PIN(245, "GPP_D_16"),
297	PINCTRL_PIN(246, "HDA_RST_B"),
298	PINCTRL_PIN(247, "GPP_D_18"),
299	PINCTRL_PIN(248, "GPP_D_19"),
300	PINCTRL_PIN(249, "GPP_D_20"),
301	PINCTRL_PIN(250, "UFS_REFCLK"),
302	PINCTRL_PIN(251, "BPKI3C_SDA"),
303	PINCTRL_PIN(252, "BPKI3C_SCL"),
304	PINCTRL_PIN(253, "BOOTHALT_B"),
305	/* vGPIO */
306	PINCTRL_PIN(254, "CNV_BTEN"),
307	PINCTRL_PIN(255, "CNV_BT_HOST_WAKEB"),
308	PINCTRL_PIN(256, "CNV_BT_IF_SELECT"),
309	PINCTRL_PIN(257, "vCNV_BT_UART_TXD"),
310	PINCTRL_PIN(258, "vCNV_BT_UART_RXD"),
311	PINCTRL_PIN(259, "vCNV_BT_UART_CTS_B"),
312	PINCTRL_PIN(260, "vCNV_BT_UART_RTS_B"),
313	PINCTRL_PIN(261, "vCNV_MFUART1_TXD"),
314	PINCTRL_PIN(262, "vCNV_MFUART1_RXD"),
315	PINCTRL_PIN(263, "vCNV_MFUART1_CTS_B"),
316	PINCTRL_PIN(264, "vCNV_MFUART1_RTS_B"),
317	PINCTRL_PIN(265, "vUART0_TXD"),
318	PINCTRL_PIN(266, "vUART0_RXD"),
319	PINCTRL_PIN(267, "vUART0_CTS_B"),
320	PINCTRL_PIN(268, "vUART0_RTS_B"),
321	PINCTRL_PIN(269, "vISH_UART0_TXD"),
322	PINCTRL_PIN(270, "vISH_UART0_RXD"),
323	PINCTRL_PIN(271, "vISH_UART0_CTS_B"),
324	PINCTRL_PIN(272, "vISH_UART0_RTS_B"),
325	PINCTRL_PIN(273, "vCNV_BT_I2S_BCLK"),
326	PINCTRL_PIN(274, "vCNV_BT_I2S_WS_SYNC"),
327	PINCTRL_PIN(275, "vCNV_BT_I2S_SDO"),
328	PINCTRL_PIN(276, "vCNV_BT_I2S_SDI"),
329	PINCTRL_PIN(277, "vI2S2_SCLK"),
330	PINCTRL_PIN(278, "vI2S2_SFRM"),
331	PINCTRL_PIN(279, "vI2S2_TXD"),
332	PINCTRL_PIN(280, "vI2S2_RXD"),
333	PINCTRL_PIN(281, "vCNV_BT_I2S_BCLK_2"),
334	PINCTRL_PIN(282, "vCNV_BT_I2S_WS_SYNC_2"),
335	PINCTRL_PIN(283, "vCNV_BT_I2S_SDO_2"),
336	PINCTRL_PIN(284, "vCNV_BT_I2S_SDI_2"),
337	PINCTRL_PIN(285, "vI2S2_SCLK_2"),
338	PINCTRL_PIN(286, "vI2S2_SFRM_2"),
339	PINCTRL_PIN(287, "vI2S2_TXD_2"),
340	PINCTRL_PIN(288, "vI2S2_RXD_2"),
341};
342
343static const struct intel_padgroup mtlp_community0_gpps[] = {
344	INTEL_GPP(0, 0, 4, 0),		/* CPU */
345	INTEL_GPP(1, 5, 28, 32),	/* GPP_V */
346	INTEL_GPP(2, 29, 52, 64),	/* GPP_C */
347};
348
349static const struct intel_padgroup mtlp_community1_gpps[] = {
350	INTEL_GPP(0, 53, 77, 96),	/* GPP_A */
351	INTEL_GPP(1, 78, 102, 128),	/* GPP_E */
352};
353
354static const struct intel_padgroup mtlp_community3_gpps[] = {
355	INTEL_GPP(0, 103, 128, 160),	/* GPP_H */
356	INTEL_GPP(1, 129, 154, 192),	/* GPP_F */
357	INTEL_GPP(2, 155, 169, 224),	/* SPI0 */
358	INTEL_GPP(3, 170, 183, 256),	/* vGPIO_3 */
359};
360
361static const struct intel_padgroup mtlp_community4_gpps[] = {
362	INTEL_GPP(0, 184, 191, 288),	/* GPP_S */
363	INTEL_GPP(1, 192, 203, 320),	/* JTAG */
364};
365
366static const struct intel_padgroup mtlp_community5_gpps[] = {
367	INTEL_GPP(0, 204, 228, 352),	/* GPP_B */
368	INTEL_GPP(1, 229, 253, 384),	/* GPP_D */
369	INTEL_GPP(2, 254, 285, 416),	/* vGPIO_0 */
370	INTEL_GPP(3, 286, 288, 448),	/* vGPIO_1 */
371};
372
373static const struct intel_community mtlp_communities[] = {
374	MTL_P_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
375	MTL_P_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
376	MTL_P_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
377	MTL_P_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
378	MTL_P_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
379};
380
381static const struct intel_pinctrl_soc_data mtlp_soc_data = {
382	.pins = mtlp_pins,
383	.npins = ARRAY_SIZE(mtlp_pins),
384	.communities = mtlp_communities,
385	.ncommunities = ARRAY_SIZE(mtlp_communities),
386};
387
388/* Meteor Lake-S */
389static const struct pinctrl_pin_desc mtls_pins[] = {
390	/* GPP_A */
391	PINCTRL_PIN(0, "DIR_ESPI_IO_0"),
392	PINCTRL_PIN(1, "DIR_ESPI_IO_1"),
393	PINCTRL_PIN(2, "DIR_ESPI_IO_2"),
394	PINCTRL_PIN(3, "DIR_ESPI_IO_3"),
395	PINCTRL_PIN(4, "DIR_ESPI_CS0_B"),
396	PINCTRL_PIN(5, "DIR_ESPI_CLK"),
397	PINCTRL_PIN(6, "DIR_ESPI_RCLK"),
398	PINCTRL_PIN(7, "DIR_ESPI_RESET_B"),
399	PINCTRL_PIN(8, "SLP_S0_B"),
400	PINCTRL_PIN(9, "DMI_PERSTB"),
401	PINCTRL_PIN(10, "CATERR_B"),
402	PINCTRL_PIN(11, "THERMTRIP_B"),
403	PINCTRL_PIN(12, "CPU_C10_GATE_B"),
404	PINCTRL_PIN(13, "PS_ONB"),
405	PINCTRL_PIN(14, "GPP_SA_14"),
406	PINCTRL_PIN(15, "GPP_SA_15"),
407	PINCTRL_PIN(16, "GPP_SA_16"),
408	PINCTRL_PIN(17, "GPP_SA_17"),
409	PINCTRL_PIN(18, "GPP_SA_18"),
410	PINCTRL_PIN(19, "GPP_SA_19"),
411	PINCTRL_PIN(20, "GPP_SA_20"),
412	PINCTRL_PIN(21, "GPP_SA_21"),
413	PINCTRL_PIN(22, "FUSA_DIAGTEST_EN"),
414	PINCTRL_PIN(23, "FUSA_DIAGTEST_MODE"),
415	PINCTRL_PIN(24, "RTCCLKIN"),
416	PINCTRL_PIN(25, "RESET_SYNC_B"),
417	PINCTRL_PIN(26, "PCH_PWROK"),
418	PINCTRL_PIN(27, "DIR_ESPI_CLK_LOOPBACK"),
419	/* vGPIO_0 */
420	PINCTRL_PIN(28, "LPC_ME_FTPM_ENABLE"),
421	PINCTRL_PIN(29, "LPC_DTFUS_CORE_SPITPM_DIS"),
422	PINCTRL_PIN(30, "LPC_SPI_STRAP_TOS"),
423	PINCTRL_PIN(31, "ITSS_KU1_SHTDWN"),
424	PINCTRL_PIN(32, "LPC_PRR_TS_OVR"),
425	PINCTRL_PIN(33, "ESPI_PMC_EC_SCI"),
426	PINCTRL_PIN(34, "ESPI_PMC_EC_SCI1"),
427	PINCTRL_PIN(35, "vGPIO_SPARE0"),
428	PINCTRL_PIN(36, "vGPIO_SPARE1"),
429	PINCTRL_PIN(37, "vGPIO_SPARE2"),
430	PINCTRL_PIN(38, "vGPIO_SPARE3"),
431	PINCTRL_PIN(39, "vGPIO_SPARE8"),
432	PINCTRL_PIN(40, "vGPIO_SPARE9"),
433	PINCTRL_PIN(41, "vGPIO_SPARE10"),
434	PINCTRL_PIN(42, "vGPIO_SPARE11"),
435	PINCTRL_PIN(43, "vGPIO_SPARE12"),
436	PINCTRL_PIN(44, "vGPIO_SPARE13"),
437	PINCTRL_PIN(45, "vGPIO_SPARE14"),
438	PINCTRL_PIN(46, "vGPIO_SPARE15"),
439	/* GPP_C */
440	PINCTRL_PIN(47, "GPP_SC_0"),
441	PINCTRL_PIN(48, "GPP_SC_1"),
442	PINCTRL_PIN(49, "GPP_SC_2"),
443	PINCTRL_PIN(50, "GPP_SC_3"),
444	PINCTRL_PIN(51, "GPP_SC_4"),
445	PINCTRL_PIN(52, "GPP_SC_5"),
446	PINCTRL_PIN(53, "GPP_SC_6"),
447	PINCTRL_PIN(54, "GPP_SC_7"),
448	PINCTRL_PIN(55, "GPP_SC_8"),
449	PINCTRL_PIN(56, "GPP_SC_9"),
450	PINCTRL_PIN(57, "GPP_SC_10"),
451	PINCTRL_PIN(58, "GPP_SC_11"),
452	PINCTRL_PIN(59, "GPP_SC_12"),
453	PINCTRL_PIN(60, "GPP_SC_13"),
454	PINCTRL_PIN(61, "GPP_SC_14"),
455	PINCTRL_PIN(62, "GPP_SC_15"),
456	PINCTRL_PIN(63, "GPP_SC_16"),
457	PINCTRL_PIN(64, "GPP_SC_17"),
458	PINCTRL_PIN(65, "GPP_SC_18"),
459	PINCTRL_PIN(66, "GPP_SC_19"),
460	PINCTRL_PIN(67, "GPP_SC_20"),
461	PINCTRL_PIN(68, "GPP_SC_21"),
462	PINCTRL_PIN(69, "GPP_SC_22"),
463	PINCTRL_PIN(70, "GPP_SC_23"),
464	PINCTRL_PIN(71, "GPP_SC_24"),
465	PINCTRL_PIN(72, "GPP_SC_25"),
466	PINCTRL_PIN(73, "GPP_SC_26"),
467	/* GPP_B */
468	PINCTRL_PIN(74, "GPP_SB_0"),
469	PINCTRL_PIN(75, "GPP_SB_1"),
470	PINCTRL_PIN(76, "GPP_SB_2"),
471	PINCTRL_PIN(77, "GPP_SB_3"),
472	PINCTRL_PIN(78, "GPP_SB_4"),
473	PINCTRL_PIN(79, "GPP_SB_5"),
474	PINCTRL_PIN(80, "GPP_SB_6"),
475	PINCTRL_PIN(81, "GPP_SB_7"),
476	PINCTRL_PIN(82, "GPP_SB_8"),
477	PINCTRL_PIN(83, "GPP_SB_9"),
478	PINCTRL_PIN(84, "GPP_SB_10"),
479	PINCTRL_PIN(85, "GPP_SB_11"),
480	PINCTRL_PIN(86, "GPP_SB_12"),
481	PINCTRL_PIN(87, "GPP_SB_13"),
482	PINCTRL_PIN(88, "GPP_SB_14"),
483	PINCTRL_PIN(89, "GPP_SB_15"),
484	PINCTRL_PIN(90, "GPP_SB_16"),
485	PINCTRL_PIN(91, "PROCHOT_B"),
486	PINCTRL_PIN(92, "BPKI3C_SDA"),
487	PINCTRL_PIN(93, "BPKI3C_SCL"),
488	/* vGPIO_3 */
489	PINCTRL_PIN(94, "TS0_IN_INT"),
490	PINCTRL_PIN(95, "TS1_IN_INT"),
491	/* GPP_D */
492	PINCTRL_PIN(96, "TIME_SYNC_0"),
493	PINCTRL_PIN(97, "TIME_SYNC_1"),
494	PINCTRL_PIN(98, "DSI_DE_TE_2_GENLOCK_REF"),
495	PINCTRL_PIN(99, "DSI_DE_TE_1_DISP_UTILS"),
496	PINCTRL_PIN(100, "DSI_GENLOCK_2"),
497	PINCTRL_PIN(101, "DSI_GENLOCK_3"),
498	PINCTRL_PIN(102, "SRCCLKREQ2_B"),
499	PINCTRL_PIN(103, "SRCCLKREQ3_B"),
500	PINCTRL_PIN(104, "GPP_SD_8"),
501	PINCTRL_PIN(105, "GPP_SD_9"),
502	PINCTRL_PIN(106, "GPP_SD_10"),
503	PINCTRL_PIN(107, "GPP_SD_11"),
504	PINCTRL_PIN(108, "GPP_SD_12"),
505	PINCTRL_PIN(109, "GPP_SD_13"),
506	PINCTRL_PIN(110, "GPP_SD_14"),
507	PINCTRL_PIN(111, "GPP_SD_15"),
508	PINCTRL_PIN(112, "GPP_SD_16"),
509	PINCTRL_PIN(113, "GPP_SD_17"),
510	PINCTRL_PIN(114, "BOOTHALT_B"),
511	PINCTRL_PIN(115, "GPP_SD_19"),
512	PINCTRL_PIN(116, "GPP_SD_20"),
513	PINCTRL_PIN(117, "AUDCLK"),
514	PINCTRL_PIN(118, "AUDIN"),
515	PINCTRL_PIN(119, "AUDOUT"),
516	/* JTAG_CPU */
517	PINCTRL_PIN(120, "PECI"),
518	PINCTRL_PIN(121, "VIDSOUT"),
519	PINCTRL_PIN(122, "VIDSCK"),
520	PINCTRL_PIN(123, "VIDALERT_B"),
521	PINCTRL_PIN(124, "JTAG_MBPB0"),
522	PINCTRL_PIN(125, "JTAG_MBPB1"),
523	PINCTRL_PIN(126, "JTAG_MBPB2"),
524	PINCTRL_PIN(127, "JTAG_MBPB3"),
525	PINCTRL_PIN(128, "JTAG_TDO"),
526	PINCTRL_PIN(129, "PRDY_B"),
527	PINCTRL_PIN(130, "PREQ_B"),
528	PINCTRL_PIN(131, "JTAG_TDI"),
529	PINCTRL_PIN(132, "JTAG_TMS"),
530	PINCTRL_PIN(133, "JTAG_TCK"),
531	PINCTRL_PIN(134, "DBG_PMODE"),
532	PINCTRL_PIN(135, "JTAG_TRST_B"),
533	/* vGPIO_4 */
534	PINCTRL_PIN(136, "ISCLK_ESPI_XTAL_CLKREQ"),
535	PINCTRL_PIN(137, "ESPI_ISCLK_XTAL_CLKACK"),
536	PINCTRL_PIN(138, "vGPIO_SPARE4"),
537	PINCTRL_PIN(139, "vGPIO_SPARE5"),
538	PINCTRL_PIN(140, "vGPIO_SPARE6"),
539	PINCTRL_PIN(141, "vGPIO_SPARE7"),
540	PINCTRL_PIN(142, "vGPIO_SPARE16"),
541	PINCTRL_PIN(143, "vGPIO_SPARE17"),
542	PINCTRL_PIN(144, "vGPIO_SPARE18"),
543	PINCTRL_PIN(145, "vGPIO_SPARE19"),
544	PINCTRL_PIN(146, "vGPIO_SPARE20"),
545	PINCTRL_PIN(147, "vGPIO_SPARE21"),
546};
547
548static const struct intel_padgroup mtls_community0_gpps[] = {
549	INTEL_GPP(0, 0, 27, 0),		/* GPP_A */
550	INTEL_GPP(1, 28, 46, 32),	/* vGPIO_0 */
551	INTEL_GPP(2, 47, 73, 64),	/* GPP_C */
552};
553
554static const struct intel_padgroup mtls_community1_gpps[] = {
555	INTEL_GPP(0, 74, 93, 96),	/* GPP_B */
556	INTEL_GPP(1, 94, 95, 128),	/* vGPIO_3 */
557	INTEL_GPP(2, 96, 119, 160),	/* GPP_D */
558};
559
560static const struct intel_padgroup mtls_community3_gpps[] = {
561	INTEL_GPP(0, 120, 135, 192),	/* JTAG_CPU */
562	INTEL_GPP(1, 136, 147, 224),	/* vGPIO_4 */
563};
564
565static const struct intel_community mtls_communities[] = {
566	MTL_S_COMMUNITY(0, 0, 73, mtls_community0_gpps),
567	MTL_S_COMMUNITY(1, 74, 119, mtls_community1_gpps),
568	MTL_S_COMMUNITY(2, 120, 147, mtls_community3_gpps),
569};
570
571static const struct intel_pinctrl_soc_data mtls_soc_data = {
572	.pins = mtls_pins,
573	.npins = ARRAY_SIZE(mtls_pins),
574	.communities = mtls_communities,
575	.ncommunities = ARRAY_SIZE(mtls_communities),
576};
577
578static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
579	{ "INTC105E", (kernel_ulong_t)&mtlp_soc_data },
580	{ "INTC1083", (kernel_ulong_t)&mtlp_soc_data },
581	{ "INTC1082", (kernel_ulong_t)&mtls_soc_data },
582	{ }
583};
584MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);
585
586static struct platform_driver mtl_pinctrl_driver = {
587	.probe = intel_pinctrl_probe_by_hid,
588	.driver = {
589		.name = "meteorlake-pinctrl",
590		.acpi_match_table = mtl_pinctrl_acpi_match,
591		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
592	},
593};
594module_platform_driver(mtl_pinctrl_driver);
595
596MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
597MODULE_DESCRIPTION("Intel Meteor Lake PCH pinctrl/GPIO driver");
598MODULE_LICENSE("GPL v2");
599MODULE_IMPORT_NS("PINCTRL_INTEL");