pinctrl-lynxpoint.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Intel Lynxpoint PCH pinctrl/GPIO driver
  4 *
  5 * Copyright (c) 2012, 2019, Intel Corporation
  6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
  7 *          Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  8 */
  9
 10#include <linux/acpi.h>
 11#include <linux/array_size.h>
 12#include <linux/bitops.h>
 13#include <linux/cleanup.h>
 14#include <linux/gpio/driver.h>
 15#include <linux/interrupt.h>
 16#include <linux/io.h>
 17#include <linux/module.h>
 18#include <linux/platform_device.h>
 19#include <linux/pm.h>
 20#include <linux/seq_file.h>
 21#include <linux/slab.h>
 22#include <linux/types.h>
 23
 24#include <linux/pinctrl/consumer.h>
 25#include <linux/pinctrl/pinconf-generic.h>
 26#include <linux/pinctrl/pinconf.h>
 27#include <linux/pinctrl/pinctrl.h>
 28#include <linux/pinctrl/pinmux.h>
 29
 30#include "pinctrl-intel.h"
 31
 32#define COMMUNITY(p, n)			\
 33	{				\
 34		.pin_base	= (p),	\
 35		.npins		= (n),	\
 36	}
 37
 38static const struct pinctrl_pin_desc lptlp_pins[] = {
 39	PINCTRL_PIN(0, "GP0_UART1_RXD"),
 40	PINCTRL_PIN(1, "GP1_UART1_TXD"),
 41	PINCTRL_PIN(2, "GP2_UART1_RTSB"),
 42	PINCTRL_PIN(3, "GP3_UART1_CTSB"),
 43	PINCTRL_PIN(4, "GP4_I2C0_SDA"),
 44	PINCTRL_PIN(5, "GP5_I2C0_SCL"),
 45	PINCTRL_PIN(6, "GP6_I2C1_SDA"),
 46	PINCTRL_PIN(7, "GP7_I2C1_SCL"),
 47	PINCTRL_PIN(8, "GP8"),
 48	PINCTRL_PIN(9, "GP9"),
 49	PINCTRL_PIN(10, "GP10"),
 50	PINCTRL_PIN(11, "GP11_SMBALERTB"),
 51	PINCTRL_PIN(12, "GP12_LANPHYPC"),
 52	PINCTRL_PIN(13, "GP13"),
 53	PINCTRL_PIN(14, "GP14"),
 54	PINCTRL_PIN(15, "GP15"),
 55	PINCTRL_PIN(16, "GP16_MGPIO9"),
 56	PINCTRL_PIN(17, "GP17_MGPIO10"),
 57	PINCTRL_PIN(18, "GP18_SRC0CLKRQB"),
 58	PINCTRL_PIN(19, "GP19_SRC1CLKRQB"),
 59	PINCTRL_PIN(20, "GP20_SRC2CLKRQB"),
 60	PINCTRL_PIN(21, "GP21_SRC3CLKRQB"),
 61	PINCTRL_PIN(22, "GP22_SRC4CLKRQB_TRST2"),
 62	PINCTRL_PIN(23, "GP23_SRC5CLKRQB_TDI2"),
 63	PINCTRL_PIN(24, "GP24_MGPIO0"),
 64	PINCTRL_PIN(25, "GP25_USBWAKEOUTB"),
 65	PINCTRL_PIN(26, "GP26_MGPIO5"),
 66	PINCTRL_PIN(27, "GP27_MGPIO6"),
 67	PINCTRL_PIN(28, "GP28_MGPIO7"),
 68	PINCTRL_PIN(29, "GP29_SLP_WLANB_MGPIO3"),
 69	PINCTRL_PIN(30, "GP30_SUSWARNB_SUSPWRDNACK_MGPIO1"),
 70	PINCTRL_PIN(31, "GP31_ACPRESENT_MGPIO2"),
 71	PINCTRL_PIN(32, "GP32_CLKRUNB"),
 72	PINCTRL_PIN(33, "GP33_DEVSLP0"),
 73	PINCTRL_PIN(34, "GP34_SATA0XPCIE6L3B_SATA0GP"),
 74	PINCTRL_PIN(35, "GP35_SATA1XPCIE6L2B_SATA1GP"),
 75	PINCTRL_PIN(36, "GP36_SATA2XPCIE6L1B_SATA2GP"),
 76	PINCTRL_PIN(37, "GP37_SATA3XPCIE6L0B_SATA3GP"),
 77	PINCTRL_PIN(38, "GP38_DEVSLP1"),
 78	PINCTRL_PIN(39, "GP39_DEVSLP2"),
 79	PINCTRL_PIN(40, "GP40_OC0B"),
 80	PINCTRL_PIN(41, "GP41_OC1B"),
 81	PINCTRL_PIN(42, "GP42_OC2B"),
 82	PINCTRL_PIN(43, "GP43_OC3B"),
 83	PINCTRL_PIN(44, "GP44"),
 84	PINCTRL_PIN(45, "GP45_TMS2"),
 85	PINCTRL_PIN(46, "GP46_TDO2"),
 86	PINCTRL_PIN(47, "GP47"),
 87	PINCTRL_PIN(48, "GP48"),
 88	PINCTRL_PIN(49, "GP49"),
 89	PINCTRL_PIN(50, "GP50"),
 90	PINCTRL_PIN(51, "GP51_GSXDOUT"),
 91	PINCTRL_PIN(52, "GP52_GSXSLOAD"),
 92	PINCTRL_PIN(53, "GP53_GSXDIN"),
 93	PINCTRL_PIN(54, "GP54_GSXSRESETB"),
 94	PINCTRL_PIN(55, "GP55_GSXCLK"),
 95	PINCTRL_PIN(56, "GP56"),
 96	PINCTRL_PIN(57, "GP57"),
 97	PINCTRL_PIN(58, "GP58"),
 98	PINCTRL_PIN(59, "GP59"),
 99	PINCTRL_PIN(60, "GP60_SML0ALERTB_MGPIO4"),
100	PINCTRL_PIN(61, "GP61_SUS_STATB"),
101	PINCTRL_PIN(62, "GP62_SUSCLK"),
102	PINCTRL_PIN(63, "GP63_SLP_S5B"),
103	PINCTRL_PIN(64, "GP64_SDIO_CLK"),
104	PINCTRL_PIN(65, "GP65_SDIO_CMD"),
105	PINCTRL_PIN(66, "GP66_SDIO_D0"),
106	PINCTRL_PIN(67, "GP67_SDIO_D1"),
107	PINCTRL_PIN(68, "GP68_SDIO_D2"),
108	PINCTRL_PIN(69, "GP69_SDIO_D3"),
109	PINCTRL_PIN(70, "GP70_SDIO_POWER_EN"),
110	PINCTRL_PIN(71, "GP71_MPHYPC"),
111	PINCTRL_PIN(72, "GP72_BATLOWB"),
112	PINCTRL_PIN(73, "GP73_SML1ALERTB_PCHHOTB_MGPIO8"),
113	PINCTRL_PIN(74, "GP74_SML1DATA_MGPIO12"),
114	PINCTRL_PIN(75, "GP75_SML1CLK_MGPIO11"),
115	PINCTRL_PIN(76, "GP76_BMBUSYB"),
116	PINCTRL_PIN(77, "GP77_PIRQAB"),
117	PINCTRL_PIN(78, "GP78_PIRQBB"),
118	PINCTRL_PIN(79, "GP79_PIRQCB"),
119	PINCTRL_PIN(80, "GP80_PIRQDB"),
120	PINCTRL_PIN(81, "GP81_SPKR"),
121	PINCTRL_PIN(82, "GP82_RCINB"),
122	PINCTRL_PIN(83, "GP83_GSPI0_CSB"),
123	PINCTRL_PIN(84, "GP84_GSPI0_CLK"),
124	PINCTRL_PIN(85, "GP85_GSPI0_MISO"),
125	PINCTRL_PIN(86, "GP86_GSPI0_MOSI"),
126	PINCTRL_PIN(87, "GP87_GSPI1_CSB"),
127	PINCTRL_PIN(88, "GP88_GSPI1_CLK"),
128	PINCTRL_PIN(89, "GP89_GSPI1_MISO"),
129	PINCTRL_PIN(90, "GP90_GSPI1_MOSI"),
130	PINCTRL_PIN(91, "GP91_UART0_RXD"),
131	PINCTRL_PIN(92, "GP92_UART0_TXD"),
132	PINCTRL_PIN(93, "GP93_UART0_RTSB"),
133	PINCTRL_PIN(94, "GP94_UART0_CTSB"),
134};
135
136static const struct intel_community lptlp_communities[] = {
137	COMMUNITY(0, 95),
138};
139
140static const struct intel_pinctrl_soc_data lptlp_soc_data = {
141	.pins		= lptlp_pins,
142	.npins		= ARRAY_SIZE(lptlp_pins),
143	.communities	= lptlp_communities,
144	.ncommunities	= ARRAY_SIZE(lptlp_communities),
145};
146
147/* LynxPoint chipset has support for 95 GPIO pins */
148
149#define LP_NUM_GPIO	95
150
151/* Bitmapped register offsets */
152#define LP_ACPI_OWNED	0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
153#define LP_IRQ2IOXAPIC	0x10 /* Bitmap, set by bios, 1: pin routed to IOxAPIC */
154#define LP_GC		0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
155#define LP_INT_STAT	0x80
156#define LP_INT_ENABLE	0x90
157
158/* Each pin has two 32 bit config registers, starting at 0x100 */
159#define LP_CONFIG1	0x100
160#define LP_CONFIG2	0x104
161
162/* LP_CONFIG1 reg bits */
163#define OUT_LVL_BIT	BIT(31)
164#define IN_LVL_BIT	BIT(30)
165#define TRIG_SEL_BIT	BIT(4) /* 0: Edge, 1: Level */
166#define INT_INV_BIT	BIT(3) /* Invert interrupt triggering */
167#define DIR_BIT		BIT(2) /* 0: Output, 1: Input */
168#define USE_SEL_MASK	GENMASK(1, 0)	/* 0: Native, 1: GPIO, ... */
169#define USE_SEL_NATIVE	(0 << 0)
170#define USE_SEL_GPIO	(1 << 0)
171
172/* LP_CONFIG2 reg bits */
173#define GPINDIS_BIT	BIT(2) /* disable input sensing */
174#define GPIWP_MASK	GENMASK(1, 0)	/* weak pull options */
175#define GPIWP_NONE	0		/* none */
176#define GPIWP_DOWN	1		/* weak pull down */
177#define GPIWP_UP	2		/* weak pull up */
178
179/*
180 * Lynxpoint gpios are controlled through both bitmapped registers and
181 * per gpio specific registers. The bitmapped registers are in chunks of
182 * 3 x 32bit registers to cover all 95 GPIOs
183 *
184 * per gpio specific registers consist of two 32bit registers per gpio
185 * (LP_CONFIG1 and LP_CONFIG2), with 95 GPIOs there's a total of
186 * 190 config registers.
187 *
188 * A simplified view of the register layout look like this:
189 *
190 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31  (bitmapped registers)
191 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
192 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
193 * ...
194 * LP_INT_ENABLE[31:0] ...
195 * LP_INT_ENABLE[63:32] ...
196 * LP_INT_ENABLE[94:64] ...
197 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
198 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
199 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
200 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
201 * LP2_CONFIG1 (gpio 2) ...
202 * LP2_CONFIG2 (gpio 2) ...
203 * ...
204 * LP94_CONFIG1 (gpio 94) ...
205 * LP94_CONFIG2 (gpio 94) ...
206 *
207 * IOxAPIC redirection map applies only for gpio 8-10, 13-14, 45-55.
208 */
209
210static void __iomem *lp_gpio_reg(struct gpio_chip *chip, unsigned int offset,
211				 int reg)
212{
213	struct intel_pinctrl *lg = gpiochip_get_data(chip);
214	const struct intel_community *comm;
215	int reg_offset;
216
217	comm = intel_get_community(lg, offset);
218	if (!comm)
219		return NULL;
220
221	offset -= comm->pin_base;
222
223	if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
224		/* per gpio specific config registers */
225		reg_offset = offset * 8;
226	else
227		/* bitmapped registers */
228		reg_offset = (offset / 32) * 4;
229
230	return comm->regs + reg_offset + reg;
231}
232
233static bool lp_gpio_acpi_use(struct intel_pinctrl *lg, unsigned int pin)
234{
235	void __iomem *acpi_use;
236
237	acpi_use = lp_gpio_reg(&lg->chip, pin, LP_ACPI_OWNED);
238	if (!acpi_use)
239		return true;
240
241	return !(ioread32(acpi_use) & BIT(pin % 32));
242}
243
244static bool lp_gpio_ioxapic_use(struct gpio_chip *chip, unsigned int offset)
245{
246	void __iomem *ioxapic_use = lp_gpio_reg(chip, offset, LP_IRQ2IOXAPIC);
247	u32 value;
248
249	value = ioread32(ioxapic_use);
250
251	if (offset >= 8 && offset <= 10)
252		return !!(value & BIT(offset -  8 + 0));
253	if (offset >= 13 && offset <= 14)
254		return !!(value & BIT(offset - 13 + 3));
255	if (offset >= 45 && offset <= 55)
256		return !!(value & BIT(offset - 45 + 5));
257
258	return false;
259}
260
261static void lp_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
262			    unsigned int pin)
263{
264	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
265	void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
266	void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
267	u32 value, mode;
268
269	value = ioread32(reg);
270
271	mode = value & USE_SEL_MASK;
272	if (mode == USE_SEL_GPIO)
273		seq_puts(s, "GPIO ");
274	else
275		seq_printf(s, "mode %d ", mode);
276
277	seq_printf(s, "0x%08x 0x%08x", value, ioread32(conf2));
278
279	if (lp_gpio_acpi_use(lg, pin))
280		seq_puts(s, " [ACPI]");
281}
282
283static const struct pinctrl_ops lptlp_pinctrl_ops = {
284	.get_groups_count	= intel_get_groups_count,
285	.get_group_name		= intel_get_group_name,
286	.get_group_pins		= intel_get_group_pins,
287	.pin_dbg_show		= lp_pin_dbg_show,
288};
289
290static int lp_pinmux_set_mux(struct pinctrl_dev *pctldev,
291			     unsigned int function, unsigned int group)
292{
293	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
294	const struct intel_pingroup *grp = &lg->soc->groups[group];
295	int i;
296
297	guard(raw_spinlock_irqsave)(&lg->lock);
298
299	/* Now enable the mux setting for each pin in the group */
300	for (i = 0; i < grp->grp.npins; i++) {
301		void __iomem *reg = lp_gpio_reg(&lg->chip, grp->grp.pins[i], LP_CONFIG1);
302		u32 value;
303
304		value = ioread32(reg);
305
306		value &= ~USE_SEL_MASK;
307		if (grp->modes)
308			value |= grp->modes[i];
309		else
310			value |= grp->mode;
311
312		iowrite32(value, reg);
313	}
314
315	return 0;
316}
317
318static void lp_gpio_enable_input(void __iomem *reg)
319{
320	iowrite32(ioread32(reg) & ~GPINDIS_BIT, reg);
321}
322
323static void lp_gpio_disable_input(void __iomem *reg)
324{
325	iowrite32(ioread32(reg) | GPINDIS_BIT, reg);
326}
327
328static int lp_gpio_request_enable(struct pinctrl_dev *pctldev,
329				  struct pinctrl_gpio_range *range,
330				  unsigned int pin)
331{
332	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
333	void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
334	void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
335	u32 value;
336
337	guard(raw_spinlock_irqsave)(&lg->lock);
338
339	/*
340	 * Reconfigure pin to GPIO mode if needed and issue a warning,
341	 * since we expect firmware to configure it properly.
342	 */
343	value = ioread32(reg);
344	if ((value & USE_SEL_MASK) != USE_SEL_GPIO) {
345		iowrite32((value & USE_SEL_MASK) | USE_SEL_GPIO, reg);
346		dev_warn(lg->dev, FW_BUG "pin %u forcibly reconfigured as GPIO\n", pin);
347	}
348
349	/* Enable input sensing */
350	lp_gpio_enable_input(conf2);
351
352	return 0;
353}
354
355static void lp_gpio_disable_free(struct pinctrl_dev *pctldev,
356				 struct pinctrl_gpio_range *range,
357				 unsigned int pin)
358{
359	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
360	void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
361
362	guard(raw_spinlock_irqsave)(&lg->lock);
363
364	/* Disable input sensing */
365	lp_gpio_disable_input(conf2);
366}
367
368static int lp_gpio_set_direction(struct pinctrl_dev *pctldev,
369				 struct pinctrl_gpio_range *range,
370				 unsigned int pin, bool input)
371{
372	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
373	void __iomem *reg = lp_gpio_reg(&lg->chip, pin, LP_CONFIG1);
374	u32 value;
375
376	guard(raw_spinlock_irqsave)(&lg->lock);
377
378	value = ioread32(reg);
379	value &= ~DIR_BIT;
380	if (input) {
381		value |= DIR_BIT;
382	} else {
383		/*
384		 * Before making any direction modifications, do a check if GPIO
385		 * is set for direct IRQ. On Lynxpoint, setting GPIO to output
386		 * does not make sense, so let's at least warn the caller before
387		 * they shoot themselves in the foot.
388		 */
389		WARN(lp_gpio_ioxapic_use(&lg->chip, pin),
390		     "Potential Error: Setting GPIO to output with IOxAPIC redirection");
391	}
392	iowrite32(value, reg);
393
394	return 0;
395}
396
397static const struct pinmux_ops lptlp_pinmux_ops = {
398	.get_functions_count	= intel_get_functions_count,
399	.get_function_name	= intel_get_function_name,
400	.get_function_groups	= intel_get_function_groups,
401	.set_mux		= lp_pinmux_set_mux,
402	.gpio_request_enable	= lp_gpio_request_enable,
403	.gpio_disable_free	= lp_gpio_disable_free,
404	.gpio_set_direction	= lp_gpio_set_direction,
405};
406
407static int lp_pin_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
408			     unsigned long *config)
409{
410	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
411	void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
412	enum pin_config_param param = pinconf_to_config_param(*config);
413	u32 value, pull;
414	u16 arg;
415
416	scoped_guard(raw_spinlock_irqsave, &lg->lock)
417		value = ioread32(conf2);
418
419	pull = value & GPIWP_MASK;
420
421	switch (param) {
422	case PIN_CONFIG_BIAS_DISABLE:
423		if (pull != GPIWP_NONE)
424			return -EINVAL;
425		arg = 0;
426		break;
427	case PIN_CONFIG_BIAS_PULL_DOWN:
428		if (pull != GPIWP_DOWN)
429			return -EINVAL;
430
431		arg = 1;
432		break;
433	case PIN_CONFIG_BIAS_PULL_UP:
434		if (pull != GPIWP_UP)
435			return -EINVAL;
436
437		arg = 1;
438		break;
439	default:
440		return -ENOTSUPP;
441	}
442
443	*config = pinconf_to_config_packed(param, arg);
444
445	return 0;
446}
447
448static int lp_pin_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
449			     unsigned long *configs, unsigned int num_configs)
450{
451	struct intel_pinctrl *lg = pinctrl_dev_get_drvdata(pctldev);
452	void __iomem *conf2 = lp_gpio_reg(&lg->chip, pin, LP_CONFIG2);
453	enum pin_config_param param;
454	unsigned int i;
455	u32 value;
456
457	guard(raw_spinlock_irqsave)(&lg->lock);
458
459	value = ioread32(conf2);
460
461	for (i = 0; i < num_configs; i++) {
462		param = pinconf_to_config_param(configs[i]);
463
464		switch (param) {
465		case PIN_CONFIG_BIAS_DISABLE:
466			value &= ~GPIWP_MASK;
467			value |= GPIWP_NONE;
468			break;
469		case PIN_CONFIG_BIAS_PULL_DOWN:
470			value &= ~GPIWP_MASK;
471			value |= GPIWP_DOWN;
472			break;
473		case PIN_CONFIG_BIAS_PULL_UP:
474			value &= ~GPIWP_MASK;
475			value |= GPIWP_UP;
476			break;
477		default:
478			return -ENOTSUPP;
479		}
480	}
481
482	iowrite32(value, conf2);
483
484	return 0;
485}
486
487static const struct pinconf_ops lptlp_pinconf_ops = {
488	.is_generic	= true,
489	.pin_config_get	= lp_pin_config_get,
490	.pin_config_set	= lp_pin_config_set,
491};
492
493static const struct pinctrl_desc lptlp_pinctrl_desc = {
494	.pctlops	= &lptlp_pinctrl_ops,
495	.pmxops		= &lptlp_pinmux_ops,
496	.confops	= &lptlp_pinconf_ops,
497	.owner		= THIS_MODULE,
498};
499
500static int lp_gpio_get(struct gpio_chip *chip, unsigned int offset)
501{
502	void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
503	return !!(ioread32(reg) & IN_LVL_BIT);
504}
505
506static int lp_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
507{
508	struct intel_pinctrl *lg = gpiochip_get_data(chip);
509	void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
510
511	guard(raw_spinlock_irqsave)(&lg->lock);
512
513	if (value)
514		iowrite32(ioread32(reg) | OUT_LVL_BIT, reg);
515	else
516		iowrite32(ioread32(reg) & ~OUT_LVL_BIT, reg);
517
518	return 0;
519}
520
521static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
522{
523	return pinctrl_gpio_direction_input(chip, offset);
524}
525
526static int lp_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
527				    int value)
528{
529	lp_gpio_set(chip, offset, value);
530
531	return pinctrl_gpio_direction_output(chip,  offset);
532}
533
534static int lp_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
535{
536	void __iomem *reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
537
538	if (ioread32(reg) & DIR_BIT)
539		return GPIO_LINE_DIRECTION_IN;
540
541	return GPIO_LINE_DIRECTION_OUT;
542}
543
544static void lp_gpio_irq_handler(struct irq_desc *desc)
545{
546	struct irq_data *data = irq_desc_get_irq_data(desc);
547	struct gpio_chip *gc = irq_desc_get_handler_data(desc);
548	struct intel_pinctrl *lg = gpiochip_get_data(gc);
549	struct irq_chip *chip = irq_data_get_irq_chip(data);
550	void __iomem *reg, *ena;
551	unsigned long pending;
552	u32 base, pin;
553
554	chained_irq_enter(chip, desc);
555
556	/* check from GPIO controller which pin triggered the interrupt */
557	for (base = 0; base < lg->chip.ngpio; base += 32) {
558		reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
559		ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
560
561		/* Only interrupts that are enabled */
562		pending = ioread32(reg) & ioread32(ena);
563
564		for_each_set_bit(pin, &pending, 32)
565			generic_handle_domain_irq(lg->chip.irq.domain, base + pin);
566	}
567
568	chained_irq_exit(chip, desc);
569}
570
571static void lp_irq_ack(struct irq_data *d)
572{
573	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
574	struct intel_pinctrl *lg = gpiochip_get_data(gc);
575	irq_hw_number_t hwirq = irqd_to_hwirq(d);
576	void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_STAT);
577
578	guard(raw_spinlock_irqsave)(&lg->lock);
579
580	iowrite32(BIT(hwirq % 32), reg);
581}
582
583static void lp_irq_unmask(struct irq_data *d)
584{
585}
586
587static void lp_irq_mask(struct irq_data *d)
588{
589}
590
591static void lp_irq_enable(struct irq_data *d)
592{
593	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
594	struct intel_pinctrl *lg = gpiochip_get_data(gc);
595	irq_hw_number_t hwirq = irqd_to_hwirq(d);
596	void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
597
598	gpiochip_enable_irq(gc, hwirq);
599
600	scoped_guard(raw_spinlock_irqsave, &lg->lock)
601		iowrite32(ioread32(reg) | BIT(hwirq % 32), reg);
602}
603
604static void lp_irq_disable(struct irq_data *d)
605{
606	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
607	struct intel_pinctrl *lg = gpiochip_get_data(gc);
608	irq_hw_number_t hwirq = irqd_to_hwirq(d);
609	void __iomem *reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
610
611	scoped_guard(raw_spinlock_irqsave, &lg->lock)
612		iowrite32(ioread32(reg) & ~BIT(hwirq % 32), reg);
613
614	gpiochip_disable_irq(gc, hwirq);
615}
616
617static int lp_irq_set_type(struct irq_data *d, unsigned int type)
618{
619	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
620	struct intel_pinctrl *lg = gpiochip_get_data(gc);
621	irq_hw_number_t hwirq = irqd_to_hwirq(d);
622	void __iomem *reg;
623	u32 value;
624
625	reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
626	if (!reg)
627		return -EINVAL;
628
629	/* Fail if BIOS reserved pin for ACPI use */
630	if (lp_gpio_acpi_use(lg, hwirq)) {
631		dev_err(lg->dev, "pin %lu can't be used as IRQ\n", hwirq);
632		return -EBUSY;
633	}
634
635	guard(raw_spinlock_irqsave)(&lg->lock);
636
637	value = ioread32(reg);
638
639	/* set both TRIG_SEL and INV bits to 0 for rising edge */
640	if (type & IRQ_TYPE_EDGE_RISING)
641		value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
642
643	/* TRIG_SEL bit 0, INV bit 1 for falling edge */
644	if (type & IRQ_TYPE_EDGE_FALLING)
645		value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
646
647	/* TRIG_SEL bit 1, INV bit 0 for level low */
648	if (type & IRQ_TYPE_LEVEL_LOW)
649		value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
650
651	/* TRIG_SEL bit 1, INV bit 1 for level high */
652	if (type & IRQ_TYPE_LEVEL_HIGH)
653		value |= TRIG_SEL_BIT | INT_INV_BIT;
654
655	iowrite32(value, reg);
656
657	if (type & IRQ_TYPE_EDGE_BOTH)
658		irq_set_handler_locked(d, handle_edge_irq);
659	else if (type & IRQ_TYPE_LEVEL_MASK)
660		irq_set_handler_locked(d, handle_level_irq);
661
662	return 0;
663}
664
665static const struct irq_chip lp_irqchip = {
666	.name = "LP-GPIO",
667	.irq_ack = lp_irq_ack,
668	.irq_mask = lp_irq_mask,
669	.irq_unmask = lp_irq_unmask,
670	.irq_enable = lp_irq_enable,
671	.irq_disable = lp_irq_disable,
672	.irq_set_type = lp_irq_set_type,
673	.flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE,
674	GPIOCHIP_IRQ_RESOURCE_HELPERS,
675};
676
677static int lp_gpio_irq_init_hw(struct gpio_chip *chip)
678{
679	struct intel_pinctrl *lg = gpiochip_get_data(chip);
680	void __iomem *reg;
681	unsigned int base;
682
683	for (base = 0; base < lg->chip.ngpio; base += 32) {
684		/* disable gpio pin interrupts */
685		reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
686		iowrite32(0, reg);
687		/* Clear interrupt status register */
688		reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
689		iowrite32(0xffffffff, reg);
690	}
691
692	return 0;
693}
694
695static int lp_gpio_add_pin_ranges(struct gpio_chip *chip)
696{
697	struct intel_pinctrl *lg = gpiochip_get_data(chip);
698	struct device *dev = lg->dev;
699	int ret;
700
701	ret = gpiochip_add_pin_range(chip, dev_name(dev), 0, 0, lg->soc->npins);
702	if (ret)
703		return dev_err_probe(dev, ret, "failed to add GPIO pin range\n");
704
705	return 0;
706}
707
708static int lp_gpio_probe(struct platform_device *pdev)
709{
710	const struct intel_pinctrl_soc_data *soc;
711	struct intel_pinctrl *lg;
712	struct gpio_chip *gc;
713	struct device *dev = &pdev->dev;
714	struct resource *io_rc;
715	void __iomem *regs;
716	unsigned int i;
717	int irq, ret;
718
719	soc = (const struct intel_pinctrl_soc_data *)device_get_match_data(dev);
720	if (!soc)
721		return -ENODEV;
722
723	lg = devm_kzalloc(dev, sizeof(*lg), GFP_KERNEL);
724	if (!lg)
725		return -ENOMEM;
726
727	lg->dev = dev;
728	lg->soc = soc;
729
730	lg->ncommunities = lg->soc->ncommunities;
731	lg->communities = devm_kcalloc(dev, lg->ncommunities,
732				       sizeof(*lg->communities), GFP_KERNEL);
733	if (!lg->communities)
734		return -ENOMEM;
735
736	lg->pctldesc           = lptlp_pinctrl_desc;
737	lg->pctldesc.name      = dev_name(dev);
738	lg->pctldesc.pins      = lg->soc->pins;
739	lg->pctldesc.npins     = lg->soc->npins;
740
741	lg->pctldev = devm_pinctrl_register(dev, &lg->pctldesc, lg);
742	if (IS_ERR(lg->pctldev))
743		return dev_err_probe(dev, PTR_ERR(lg->pctldev), "failed to register pinctrl\n");
744
745	platform_set_drvdata(pdev, lg);
746
747	io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
748	if (!io_rc)
749		return dev_err_probe(dev, -EINVAL, "missing IO resources\n");
750
751	regs = devm_ioport_map(dev, io_rc->start, resource_size(io_rc));
752	if (!regs)
753		return dev_err_probe(dev, -EBUSY, "failed mapping IO region %pR\n", &io_rc);
754
755	for (i = 0; i < lg->soc->ncommunities; i++) {
756		struct intel_community *comm = &lg->communities[i];
757
758		*comm = lg->soc->communities[i];
759
760		comm->regs = regs;
761		comm->pad_regs = regs + 0x100;
762	}
763
764	raw_spin_lock_init(&lg->lock);
765
766	gc = &lg->chip;
767	gc->label = dev_name(dev);
768	gc->owner = THIS_MODULE;
769	gc->request = gpiochip_generic_request;
770	gc->free = gpiochip_generic_free;
771	gc->direction_input = lp_gpio_direction_input;
772	gc->direction_output = lp_gpio_direction_output;
773	gc->get = lp_gpio_get;
774	gc->set = lp_gpio_set;
775	gc->set_config = gpiochip_generic_config;
776	gc->get_direction = lp_gpio_get_direction;
777	gc->base = -1;
778	gc->ngpio = LP_NUM_GPIO;
779	gc->can_sleep = false;
780	gc->add_pin_ranges = lp_gpio_add_pin_ranges;
781	gc->parent = dev;
782
783	/* set up interrupts  */
784	irq = platform_get_irq_optional(pdev, 0);
785	if (irq > 0) {
786		struct gpio_irq_chip *girq;
787
788		girq = &gc->irq;
789		gpio_irq_chip_set_chip(girq, &lp_irqchip);
790		girq->init_hw = lp_gpio_irq_init_hw;
791		girq->parent_handler = lp_gpio_irq_handler;
792		girq->num_parents = 1;
793		girq->parents = devm_kcalloc(dev, girq->num_parents,
794					     sizeof(*girq->parents),
795					     GFP_KERNEL);
796		if (!girq->parents)
797			return -ENOMEM;
798		girq->parents[0] = irq;
799		girq->default_type = IRQ_TYPE_NONE;
800		girq->handler = handle_bad_irq;
801	}
802
803	ret = devm_gpiochip_add_data(dev, gc, lg);
804	if (ret)
805		return dev_err_probe(dev, ret, "failed to register gpiochip\n");
806
807	return 0;
808}
809
810static int lp_gpio_resume(struct device *dev)
811{
812	struct intel_pinctrl *lg = dev_get_drvdata(dev);
813	struct gpio_chip *chip = &lg->chip;
814	const char *dummy;
815	int i;
816
817	/* on some hardware suspend clears input sensing, re-enable it here */
818	for_each_requested_gpio(chip, i, dummy)
819		lp_gpio_enable_input(lp_gpio_reg(chip, i, LP_CONFIG2));
820
821	return 0;
822}
823
824static DEFINE_SIMPLE_DEV_PM_OPS(lp_gpio_pm_ops, NULL, lp_gpio_resume);
825
826static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
827	{ "INT33C7", (kernel_ulong_t)&lptlp_soc_data },
828	{ "INT3437", (kernel_ulong_t)&lptlp_soc_data },
829	{ }
830};
831MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
832
833static struct platform_driver lp_gpio_driver = {
834	.probe          = lp_gpio_probe,
835	.driver         = {
836		.name   = "lp_gpio",
837		.pm	= pm_sleep_ptr(&lp_gpio_pm_ops),
838		.acpi_match_table = lynxpoint_gpio_acpi_match,
839	},
840};
841
842static int __init lp_gpio_init(void)
843{
844	return platform_driver_register(&lp_gpio_driver);
845}
846subsys_initcall(lp_gpio_init);
847
848static void __exit lp_gpio_exit(void)
849{
850	platform_driver_unregister(&lp_gpio_driver);
851}
852module_exit(lp_gpio_exit);
853
854MODULE_AUTHOR("Mathias Nyman (Intel)");
855MODULE_AUTHOR("Andy Shevchenko (Intel)");
856MODULE_DESCRIPTION("Intel Lynxpoint pinctrl driver");
857MODULE_LICENSE("GPL v2");
858MODULE_ALIAS("platform:lp_gpio");
859MODULE_IMPORT_NS("PINCTRL_INTEL");