pinctrl-intel.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/*
  3 * Core pinctrl/GPIO driver for Intel GPIO controllers
  4 *
  5 * Copyright (C) 2015, Intel Corporation
  6 * Authors: Mathias Nyman <mathias.nyman@linux.intel.com>
  7 *          Mika Westerberg <mika.westerberg@linux.intel.com>
  8 */
  9
 10#ifndef PINCTRL_INTEL_H
 11#define PINCTRL_INTEL_H
 12
 13#include <linux/array_size.h>
 14#include <linux/bits.h>
 15#include <linux/compiler_types.h>
 16#include <linux/gpio/driver.h>
 17#include <linux/irq.h>
 18#include <linux/pm.h>
 19#include <linux/pinctrl/pinctrl.h>
 20#include <linux/spinlock_types.h>
 21
 22struct platform_device;
 23struct device;
 24
 25/**
 26 * struct intel_pingroup - Description about group of pins
 27 * @grp: Generic data of the pin group (name and pins)
 28 * @mode: Native mode in which the group is muxed out @pins. Used if @modes is %NULL.
 29 * @modes: If not %NULL this will hold mode for each pin in @pins
 30 */
 31struct intel_pingroup {
 32	struct pingroup grp;
 33	unsigned short mode;
 34	const unsigned int *modes;
 35};
 36
 37/**
 38 * struct intel_function - Description about a function
 39 * @func: Generic data of the pin function (name and groups of pins)
 40 */
 41struct intel_function {
 42	struct pinfunction func;
 43};
 44
 45#define INTEL_PINCTRL_MAX_GPP_SIZE	32
 46
 47/**
 48 * struct intel_padgroup - Hardware pad group information
 49 * @reg_num: GPI_IS register number
 50 * @base: Starting pin of this group
 51 * @size: Size of this group (maximum is %INTEL_PINCTRL_MAX_GPP_SIZE).
 52 * @gpio_base: Starting GPIO base of this group
 53 * @padown_num: PAD_OWN register number (assigned by the core driver)
 54 *
 55 * If pad groups of a community are not the same size, use this structure
 56 * to specify them.
 57 */
 58struct intel_padgroup {
 59	unsigned int reg_num;
 60	unsigned int base;
 61	unsigned int size;
 62	int gpio_base;
 63	unsigned int padown_num;
 64};
 65
 66/**
 67 * enum - Special treatment for GPIO base in pad group
 68 *
 69 * @INTEL_GPIO_BASE_ZERO:	force GPIO base to be 0
 70 * @INTEL_GPIO_BASE_NOMAP:	no GPIO mapping should be created
 71 * @INTEL_GPIO_BASE_MATCH:	matches with starting pin number
 72 */
 73enum {
 74	INTEL_GPIO_BASE_ZERO	= -2,
 75	INTEL_GPIO_BASE_NOMAP	= -1,
 76	INTEL_GPIO_BASE_MATCH	= 0,
 77};
 78
 79/* Initialise struct intel_padgroup */
 80#define INTEL_GPP(r, s, e, g)				\
 81	{						\
 82		.reg_num = (r),				\
 83		.base = (s),				\
 84		.size = ((e) - (s) + 1),		\
 85		.gpio_base = (g),			\
 86	}
 87
 88/**
 89 * struct intel_community - Intel pin community description
 90 * @barno: MMIO BAR number where registers for this community reside
 91 * @padown_offset: Register offset of PAD_OWN register from @regs. If %0
 92 *                 then there is no support for owner.
 93 * @padcfglock_offset: Register offset of PADCFGLOCK from @regs. If %0 then
 94 *                     locking is not supported.
 95 * @hostown_offset: Register offset of HOSTSW_OWN from @regs. If %0 then it
 96 *                  is assumed that the host owns the pin (rather than
 97 *                  ACPI).
 98 * @is_offset: Register offset of GPI_IS from @regs.
 99 * @ie_offset: Register offset of GPI_IE from @regs.
100 * @features: Additional features supported by the hardware
101 * @pin_base: Starting pin of pins in this community
102 * @npins: Number of pins in this community
103 * @gpp_size: Maximum number of pads in each group, such as PADCFGLOCK,
104 *            HOSTSW_OWN, GPI_IS, GPI_IE. Used when @gpps is %NULL.
105 * @gpp_num_padown_regs: Number of pad registers each pad group consumes at
106 *			 minimum. Used when @gpps is %NULL.
107 * @gpps: Pad groups if the controller has variable size pad groups
108 * @ngpps: Number of pad groups in this community
109 * @pad_map: Optional non-linear mapping of the pads
110 * @nirqs: Optional total number of IRQs this community can generate
111 * @acpi_space_id: Optional address space ID for ACPI OpRegion handler
112 * @regs: Community specific common registers (reserved for core driver)
113 * @pad_regs: Community specific pad registers (reserved for core driver)
114 *
115 * In older Intel GPIO host controllers, this driver supports, each pad group
116 * is of equal size (except the last one). In that case the driver can just
117 * fill in @gpp_size and @gpp_num_padown_regs fields and let the core driver
118 * to handle the rest.
119 *
120 * In newer Intel GPIO host controllers each pad group is of variable size,
121 * so the client driver can pass custom @gpps and @ngpps instead.
122 */
123struct intel_community {
124	unsigned int barno;
125	unsigned int padown_offset;
126	unsigned int padcfglock_offset;
127	unsigned int hostown_offset;
128	unsigned int is_offset;
129	unsigned int ie_offset;
130	unsigned int features;
131	unsigned int pin_base;
132	size_t npins;
133	unsigned int gpp_size;
134	unsigned int gpp_num_padown_regs;
135	const struct intel_padgroup *gpps;
136	size_t ngpps;
137	const unsigned int *pad_map;
138	unsigned short nirqs;
139	unsigned short acpi_space_id;
140
141	/* Reserved for the core driver */
142	void __iomem *regs;
143	void __iomem *pad_regs;
144};
145
146/* Additional features supported by the hardware */
147#define PINCTRL_FEATURE_DEBOUNCE	BIT(0)
148#define PINCTRL_FEATURE_1K_PD		BIT(1)
149#define PINCTRL_FEATURE_GPIO_HW_INFO	BIT(2)
150#define PINCTRL_FEATURE_PWM		BIT(3)
151#define PINCTRL_FEATURE_BLINK		BIT(4)
152#define PINCTRL_FEATURE_EXP		BIT(5)
153
154#define __INTEL_COMMUNITY(b, s, e, g, n, gs, gn, soc)		\
155	{							\
156		.barno = (b),					\
157		.padown_offset = soc ## _PAD_OWN,		\
158		.padcfglock_offset = soc ## _PADCFGLOCK,	\
159		.hostown_offset = soc ## _HOSTSW_OWN,		\
160		.is_offset = soc ## _GPI_IS,			\
161		.ie_offset = soc ## _GPI_IE,			\
162		.gpp_size = (gs),				\
163		.gpp_num_padown_regs = (gn),			\
164		.pin_base = (s),				\
165		.npins = ((e) - (s) + 1),			\
166		.gpps = (g),					\
167		.ngpps = (n),					\
168	}
169
170#define INTEL_COMMUNITY_GPPS(b, s, e, g, soc)			\
171	__INTEL_COMMUNITY(b, s, e, g, ARRAY_SIZE(g), 0, 0, soc)
172
173#define INTEL_COMMUNITY_SIZE(b, s, e, gs, gn, soc)		\
174	__INTEL_COMMUNITY(b, s, e, NULL, 0, gs, gn, soc)
175
176/**
177 * PIN_GROUP - Declare a pin group
178 * @n: Name of the group
179 * @p: An array of pins this group consists
180 * @m: Mode which the pins are put when this group is active. Can be either
181 *     a single integer or an array of integers in which case mode is per
182 *     pin.
183 */
184#define PIN_GROUP(n, p, m)								\
185	{										\
186		.grp = PINCTRL_PINGROUP((n), (p), ARRAY_SIZE((p))),			\
187		.mode = __builtin_choose_expr(__builtin_constant_p((m)), (m), 0),	\
188		.modes = __builtin_choose_expr(__builtin_constant_p((m)), NULL, (m)),	\
189	}
190
191#define PIN_GROUP_GPIO(n, p, m)						\
192	 PIN_GROUP(n, p, m),						\
193	 PIN_GROUP(n "_gpio", p, 0)
194
195#define FUNCTION(n, g)							\
196	{								\
197		.func = PINCTRL_PINFUNCTION((n), (g), ARRAY_SIZE(g)),	\
198	}
199
200/**
201 * struct intel_pinctrl_soc_data - Intel pin controller per-SoC configuration
202 * @uid: ACPI _UID for the probe driver use if needed
203 * @pins: Array if pins this pinctrl controls
204 * @npins: Number of pins in the array
205 * @groups: Array of pin groups
206 * @ngroups: Number of groups in the array
207 * @functions: Array of functions
208 * @nfunctions: Number of functions in the array
209 * @communities: Array of communities this pinctrl handles
210 * @ncommunities: Number of communities in the array
211 *
212 * The @communities is used as a template by the core driver. It will make
213 * copy of all communities and fill in rest of the information.
214 */
215struct intel_pinctrl_soc_data {
216	const char *uid;
217	const struct pinctrl_pin_desc *pins;
218	size_t npins;
219	const struct intel_pingroup *groups;
220	size_t ngroups;
221	const struct intel_function *functions;
222	size_t nfunctions;
223	const struct intel_community *communities;
224	size_t ncommunities;
225};
226
227const struct intel_pinctrl_soc_data *intel_pinctrl_get_soc_data(struct platform_device *pdev);
228
229struct intel_pad_context;
230struct intel_community_context;
231
232/**
233 * struct intel_pinctrl_context - context to be saved during suspend-resume
234 * @pads: Opaque context per pad (driver dependent)
235 * @communities: Opaque context per community (driver dependent)
236 */
237struct intel_pinctrl_context {
238	struct intel_pad_context *pads;
239	struct intel_community_context *communities;
240};
241
242/**
243 * struct intel_pinctrl - Intel pinctrl private structure
244 * @dev: Pointer to the device structure
245 * @lock: Lock to serialize register access
246 * @pctldesc: Pin controller description
247 * @pctldev: Pointer to the pin controller device
248 * @chip: GPIO chip in this pin controller
249 * @soc: SoC/PCH specific pin configuration data
250 * @communities: All communities in this pin controller
251 * @ncommunities: Number of communities in this pin controller
252 * @context: Configuration saved over system sleep
253 * @irq: pinctrl/GPIO chip irq number
254 */
255struct intel_pinctrl {
256	struct device *dev;
257	raw_spinlock_t lock;
258	struct pinctrl_desc pctldesc;
259	struct pinctrl_dev *pctldev;
260	struct gpio_chip chip;
261	const struct intel_pinctrl_soc_data *soc;
262	struct intel_community *communities;
263	size_t ncommunities;
264	struct intel_pinctrl_context context;
265	int irq;
266};
267
268int intel_pinctrl_probe(struct platform_device *pdev,
269			const struct intel_pinctrl_soc_data *soc_data);
270
271int intel_pinctrl_probe_by_hid(struct platform_device *pdev);
272int intel_pinctrl_probe_by_uid(struct platform_device *pdev);
273
274extern const struct dev_pm_ops intel_pinctrl_pm_ops;
275
276const struct intel_community *intel_get_community(const struct intel_pinctrl *pctrl,
277						  unsigned int pin);
278
279int intel_gpio_add_pin_ranges(struct gpio_chip *gc);
280
281int intel_get_groups_count(struct pinctrl_dev *pctldev);
282const char *intel_get_group_name(struct pinctrl_dev *pctldev, unsigned int group);
283int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
284			 const unsigned int **pins, unsigned int *npins);
285
286int intel_get_functions_count(struct pinctrl_dev *pctldev);
287const char *intel_get_function_name(struct pinctrl_dev *pctldev, unsigned int function);
288int intel_get_function_groups(struct pinctrl_dev *pctldev, unsigned int function,
289			      const char * const **groups, unsigned int * const ngroups);
290
291#endif /* PINCTRL_INTEL_H */