pinctrl-elkhartlake.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Intel Elkhart Lake PCH pinctrl/GPIO driver
  4 *
  5 * Copyright (C) 2019, Intel Corporation
  6 * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
  7 */
  8
  9#include <linux/mod_devicetable.h>
 10#include <linux/module.h>
 11#include <linux/platform_device.h>
 12#include <linux/pm.h>
 13
 14#include <linux/pinctrl/pinctrl.h>
 15
 16#include "pinctrl-intel.h"
 17
 18#define EHL_PAD_OWN	0x020
 19#define EHL_PADCFGLOCK	0x080
 20#define EHL_HOSTSW_OWN	0x0b0
 21#define EHL_GPI_IS	0x100
 22#define EHL_GPI_IE	0x120
 23
 24#define EHL_COMMUNITY(b, s, e, g)			\
 25	INTEL_COMMUNITY_GPPS(b, s, e, g, EHL)
 26
 27/* Elkhart Lake */
 28static const struct pinctrl_pin_desc ehl_community0_pins[] = {
 29	/* GPP_B */
 30	PINCTRL_PIN(0, "CORE_VID_0"),
 31	PINCTRL_PIN(1, "CORE_VID_1"),
 32	PINCTRL_PIN(2, "VRALERTB"),
 33	PINCTRL_PIN(3, "CPU_GP_2"),
 34	PINCTRL_PIN(4, "CPU_GP_3"),
 35	PINCTRL_PIN(5, "OSE_I2C0_SCLK"),
 36	PINCTRL_PIN(6, "OSE_I2C0_SDAT"),
 37	PINCTRL_PIN(7, "OSE_I2C1_SCLK"),
 38	PINCTRL_PIN(8, "OSE_I2C1_SDAT"),
 39	PINCTRL_PIN(9, "I2C5_SDA"),
 40	PINCTRL_PIN(10, "I2C5_SCL"),
 41	PINCTRL_PIN(11, "PMCALERTB"),
 42	PINCTRL_PIN(12, "SLP_S0B"),
 43	PINCTRL_PIN(13, "PLTRSTB"),
 44	PINCTRL_PIN(14, "SPKR"),
 45	PINCTRL_PIN(15, "GSPI0_CS0B"),
 46	PINCTRL_PIN(16, "GSPI0_CLK"),
 47	PINCTRL_PIN(17, "GSPI0_MISO"),
 48	PINCTRL_PIN(18, "GSPI0_MOSI"),
 49	PINCTRL_PIN(19, "GSPI1_CS0B"),
 50	PINCTRL_PIN(20, "GSPI1_CLK"),
 51	PINCTRL_PIN(21, "GSPI1_MISO"),
 52	PINCTRL_PIN(22, "GSPI1_MOSI"),
 53	PINCTRL_PIN(23, "GPPC_B_23"),
 54	PINCTRL_PIN(24, "GSPI0_CLK_LOOPBK"),
 55	PINCTRL_PIN(25, "GSPI1_CLK_LOOPBK"),
 56	/* GPP_T */
 57	PINCTRL_PIN(26, "OSE_QEPA_2"),
 58	PINCTRL_PIN(27, "OSE_QEPB_2"),
 59	PINCTRL_PIN(28, "OSE_QEPI_2"),
 60	PINCTRL_PIN(29, "GPPC_T_3"),
 61	PINCTRL_PIN(30, "RGMII0_INT"),
 62	PINCTRL_PIN(31, "RGMII0_RESETB"),
 63	PINCTRL_PIN(32, "RGMII0_AUXTS"),
 64	PINCTRL_PIN(33, "RGMII0_PPS"),
 65	PINCTRL_PIN(34, "USB2_OCB_2"),
 66	PINCTRL_PIN(35, "OSE_HSUART2_EN"),
 67	PINCTRL_PIN(36, "OSE_HSUART2_RE"),
 68	PINCTRL_PIN(37, "USB2_OCB_3"),
 69	PINCTRL_PIN(38, "OSE_UART2_RXD"),
 70	PINCTRL_PIN(39, "OSE_UART2_TXD"),
 71	PINCTRL_PIN(40, "OSE_UART2_RTSB"),
 72	PINCTRL_PIN(41, "OSE_UART2_CTSB"),
 73	/* GPP_G */
 74	PINCTRL_PIN(42, "SD3_CMD"),
 75	PINCTRL_PIN(43, "SD3_D0"),
 76	PINCTRL_PIN(44, "SD3_D1"),
 77	PINCTRL_PIN(45, "SD3_D2"),
 78	PINCTRL_PIN(46, "SD3_D3"),
 79	PINCTRL_PIN(47, "SD3_CDB"),
 80	PINCTRL_PIN(48, "SD3_CLK"),
 81	PINCTRL_PIN(49, "I2S2_SCLK"),
 82	PINCTRL_PIN(50, "I2S2_SFRM"),
 83	PINCTRL_PIN(51, "I2S2_TXD"),
 84	PINCTRL_PIN(52, "I2S2_RXD"),
 85	PINCTRL_PIN(53, "I2S3_SCLK"),
 86	PINCTRL_PIN(54, "I2S3_SFRM"),
 87	PINCTRL_PIN(55, "I2S3_TXD"),
 88	PINCTRL_PIN(56, "I2S3_RXD"),
 89	PINCTRL_PIN(57, "ESPI_IO_0"),
 90	PINCTRL_PIN(58, "ESPI_IO_1"),
 91	PINCTRL_PIN(59, "ESPI_IO_2"),
 92	PINCTRL_PIN(60, "ESPI_IO_3"),
 93	PINCTRL_PIN(61, "I2S1_SCLK"),
 94	PINCTRL_PIN(62, "ESPI_CSB"),
 95	PINCTRL_PIN(63, "ESPI_CLK"),
 96	PINCTRL_PIN(64, "ESPI_RESETB"),
 97	PINCTRL_PIN(65, "SD3_WP"),
 98	PINCTRL_PIN(66, "ESPI_CLK_LOOPBK"),
 99};
100
101static const struct intel_padgroup ehl_community0_gpps[] = {
102	INTEL_GPP(0, 0, 25, 0),		/* GPP_B */
103	INTEL_GPP(1, 26, 41, 26),	/* GPP_T */
104	INTEL_GPP(2, 42, 66, 42),	/* GPP_G */
105};
106
107static const struct intel_community ehl_community0[] = {
108	EHL_COMMUNITY(0, 0, 66, ehl_community0_gpps),
109};
110
111static const struct intel_pinctrl_soc_data ehl_community0_soc_data = {
112	.uid = "0",
113	.pins = ehl_community0_pins,
114	.npins = ARRAY_SIZE(ehl_community0_pins),
115	.communities = ehl_community0,
116	.ncommunities = ARRAY_SIZE(ehl_community0),
117};
118
119static const struct pinctrl_pin_desc ehl_community1_pins[] = {
120	/* GPP_V */
121	PINCTRL_PIN(0, "EMMC_CMD"),
122	PINCTRL_PIN(1, "EMMC_DATA0"),
123	PINCTRL_PIN(2, "EMMC_DATA1"),
124	PINCTRL_PIN(3, "EMMC_DATA2"),
125	PINCTRL_PIN(4, "EMMC_DATA3"),
126	PINCTRL_PIN(5, "EMMC_DATA4"),
127	PINCTRL_PIN(6, "EMMC_DATA5"),
128	PINCTRL_PIN(7, "EMMC_DATA6"),
129	PINCTRL_PIN(8, "EMMC_DATA7"),
130	PINCTRL_PIN(9, "EMMC_RCLK"),
131	PINCTRL_PIN(10, "EMMC_CLK"),
132	PINCTRL_PIN(11, "EMMC_RESETB"),
133	PINCTRL_PIN(12, "OSE_TGPIO0"),
134	PINCTRL_PIN(13, "OSE_TGPIO1"),
135	PINCTRL_PIN(14, "OSE_TGPIO2"),
136	PINCTRL_PIN(15, "OSE_TGPIO3"),
137	/* GPP_H */
138	PINCTRL_PIN(16, "RGMII1_INT"),
139	PINCTRL_PIN(17, "RGMII1_RESETB"),
140	PINCTRL_PIN(18, "RGMII1_AUXTS"),
141	PINCTRL_PIN(19, "RGMII1_PPS"),
142	PINCTRL_PIN(20, "I2C2_SDA"),
143	PINCTRL_PIN(21, "I2C2_SCL"),
144	PINCTRL_PIN(22, "I2C3_SDA"),
145	PINCTRL_PIN(23, "I2C3_SCL"),
146	PINCTRL_PIN(24, "I2C4_SDA"),
147	PINCTRL_PIN(25, "I2C4_SCL"),
148	PINCTRL_PIN(26, "SRCCLKREQB_4"),
149	PINCTRL_PIN(27, "SRCCLKREQB_5"),
150	PINCTRL_PIN(28, "OSE_UART1_RXD"),
151	PINCTRL_PIN(29, "OSE_UART1_TXD"),
152	PINCTRL_PIN(30, "GPPC_H_14"),
153	PINCTRL_PIN(31, "OSE_UART1_CTSB"),
154	PINCTRL_PIN(32, "PCIE_LNK_DOWN"),
155	PINCTRL_PIN(33, "SD_PWR_EN_B"),
156	PINCTRL_PIN(34, "CPU_C10_GATEB"),
157	PINCTRL_PIN(35, "GPPC_H_19"),
158	PINCTRL_PIN(36, "OSE_PWM7"),
159	PINCTRL_PIN(37, "OSE_HSUART1_DE"),
160	PINCTRL_PIN(38, "OSE_HSUART1_RE"),
161	PINCTRL_PIN(39, "OSE_HSUART1_EN"),
162	/* GPP_D */
163	PINCTRL_PIN(40, "OSE_QEPA_0"),
164	PINCTRL_PIN(41, "OSE_QEPB_0"),
165	PINCTRL_PIN(42, "OSE_QEPI_0"),
166	PINCTRL_PIN(43, "OSE_PWM6"),
167	PINCTRL_PIN(44, "OSE_PWM2"),
168	PINCTRL_PIN(45, "SRCCLKREQB_0"),
169	PINCTRL_PIN(46, "SRCCLKREQB_1"),
170	PINCTRL_PIN(47, "SRCCLKREQB_2"),
171	PINCTRL_PIN(48, "SRCCLKREQB_3"),
172	PINCTRL_PIN(49, "OSE_SPI0_CSB"),
173	PINCTRL_PIN(50, "OSE_SPI0_SCLK"),
174	PINCTRL_PIN(51, "OSE_SPI0_MISO"),
175	PINCTRL_PIN(52, "OSE_SPI0_MOSI"),
176	PINCTRL_PIN(53, "OSE_QEPA_1"),
177	PINCTRL_PIN(54, "OSE_QEPB_1"),
178	PINCTRL_PIN(55, "OSE_PWM3"),
179	PINCTRL_PIN(56, "OSE_QEPI_1"),
180	PINCTRL_PIN(57, "OSE_PWM4"),
181	PINCTRL_PIN(58, "OSE_PWM5"),
182	PINCTRL_PIN(59, "I2S_MCLK1_OUT"),
183	PINCTRL_PIN(60, "GSPI2_CLK_LOOPBK"),
184	/* GPP_U */
185	PINCTRL_PIN(61, "RGMII2_INT"),
186	PINCTRL_PIN(62, "RGMII2_RESETB"),
187	PINCTRL_PIN(63, "RGMII2_PPS"),
188	PINCTRL_PIN(64, "RGMII2_AUXTS"),
189	PINCTRL_PIN(65, "ISI_SPIM_CS"),
190	PINCTRL_PIN(66, "ISI_SPIM_SCLK"),
191	PINCTRL_PIN(67, "ISI_SPIM_MISO"),
192	PINCTRL_PIN(68, "OSE_QEPA_3"),
193	PINCTRL_PIN(69, "ISI_SPIS_CS"),
194	PINCTRL_PIN(70, "ISI_SPIS_SCLK"),
195	PINCTRL_PIN(71, "ISI_SPIS_MISO"),
196	PINCTRL_PIN(72, "OSE_QEPB_3"),
197	PINCTRL_PIN(73, "ISI_CHX_OKNOK_0"),
198	PINCTRL_PIN(74, "ISI_CHX_OKNOK_1"),
199	PINCTRL_PIN(75, "ISI_CHX_RLY_SWTCH"),
200	PINCTRL_PIN(76, "ISI_CHX_PMIC_EN"),
201	PINCTRL_PIN(77, "ISI_OKNOK_0"),
202	PINCTRL_PIN(78, "ISI_OKNOK_1"),
203	PINCTRL_PIN(79, "ISI_ALERT"),
204	PINCTRL_PIN(80, "OSE_QEPI_3"),
205	PINCTRL_PIN(81, "GSPI3_CLK_LOOPBK"),
206	PINCTRL_PIN(82, "GSPI4_CLK_LOOPBK"),
207	PINCTRL_PIN(83, "GSPI5_CLK_LOOPBK"),
208	PINCTRL_PIN(84, "GSPI6_CLK_LOOPBK"),
209	/* vGPIO */
210	PINCTRL_PIN(85, "CNV_BTEN"),
211	PINCTRL_PIN(86, "CNV_BT_HOST_WAKEB"),
212	PINCTRL_PIN(87, "CNV_BT_IF_SELECT"),
213	PINCTRL_PIN(88, "vCNV_BT_UART_TXD"),
214	PINCTRL_PIN(89, "vCNV_BT_UART_RXD"),
215	PINCTRL_PIN(90, "vCNV_BT_UART_CTS_B"),
216	PINCTRL_PIN(91, "vCNV_BT_UART_RTS_B"),
217	PINCTRL_PIN(92, "vCNV_MFUART1_TXD"),
218	PINCTRL_PIN(93, "vCNV_MFUART1_RXD"),
219	PINCTRL_PIN(94, "vCNV_MFUART1_CTS_B"),
220	PINCTRL_PIN(95, "vCNV_MFUART1_RTS_B"),
221	PINCTRL_PIN(96, "vUART0_TXD"),
222	PINCTRL_PIN(97, "vUART0_RXD"),
223	PINCTRL_PIN(98, "vUART0_CTS_B"),
224	PINCTRL_PIN(99, "vUART0_RTS_B"),
225	PINCTRL_PIN(100, "vOSE_UART0_TXD"),
226	PINCTRL_PIN(101, "vOSE_UART0_RXD"),
227	PINCTRL_PIN(102, "vOSE_UART0_CTS_B"),
228	PINCTRL_PIN(103, "vOSE_UART0_RTS_B"),
229	PINCTRL_PIN(104, "vCNV_BT_I2S_BCLK"),
230	PINCTRL_PIN(105, "vCNV_BT_I2S_WS_SYNC"),
231	PINCTRL_PIN(106, "vCNV_BT_I2S_SDO"),
232	PINCTRL_PIN(107, "vCNV_BT_I2S_SDI"),
233	PINCTRL_PIN(108, "vI2S2_SCLK"),
234	PINCTRL_PIN(109, "vI2S2_SFRM"),
235	PINCTRL_PIN(110, "vI2S2_TXD"),
236	PINCTRL_PIN(111, "vI2S2_RXD"),
237	PINCTRL_PIN(112, "vSD3_CD_B"),
238};
239
240static const struct intel_padgroup ehl_community1_gpps[] = {
241	INTEL_GPP(0, 0, 15, 0),		/* GPP_V */
242	INTEL_GPP(1, 16, 39, 16),	/* GPP_H */
243	INTEL_GPP(2, 40, 60, 40),	/* GPP_D */
244	INTEL_GPP(3, 61, 84, 61),	/* GPP_U */
245	INTEL_GPP(4, 85, 112, 85),	/* vGPIO */
246};
247
248static const struct intel_community ehl_community1[] = {
249	EHL_COMMUNITY(0, 0, 112, ehl_community1_gpps),
250};
251
252static const struct intel_pinctrl_soc_data ehl_community1_soc_data = {
253	.uid = "1",
254	.pins = ehl_community1_pins,
255	.npins = ARRAY_SIZE(ehl_community1_pins),
256	.communities = ehl_community1,
257	.ncommunities = ARRAY_SIZE(ehl_community1),
258};
259
260static const struct pinctrl_pin_desc ehl_community2_pins[] = {
261	/* DSW */
262	PINCTRL_PIN(0, "BATLOWB"),
263	PINCTRL_PIN(1, "ACPRESENT"),
264	PINCTRL_PIN(2, "LAN_WAKEB"),
265	PINCTRL_PIN(3, "PWRBTNB"),
266	PINCTRL_PIN(4, "SLP_S3B"),
267	PINCTRL_PIN(5, "SLP_S4B"),
268	PINCTRL_PIN(6, "SLP_AB"),
269	PINCTRL_PIN(7, "GPD_7"),
270	PINCTRL_PIN(8, "SUSCLK"),
271	PINCTRL_PIN(9, "SLP_WLANB"),
272	PINCTRL_PIN(10, "SLP_S5B"),
273	PINCTRL_PIN(11, "LANPHYPC"),
274	PINCTRL_PIN(12, "INPUT3VSEL"),
275	PINCTRL_PIN(13, "SLP_LANB"),
276	PINCTRL_PIN(14, "SLP_SUSB"),
277	PINCTRL_PIN(15, "WAKEB"),
278	PINCTRL_PIN(16, "DRAM_RESETB"),
279};
280
281static const struct intel_padgroup ehl_community2_gpps[] = {
282	INTEL_GPP(0, 0, 16, 0),		/* DSW */
283};
284
285static const struct intel_community ehl_community2[] = {
286	EHL_COMMUNITY(0, 0, 16, ehl_community2_gpps),
287};
288
289static const struct intel_pinctrl_soc_data ehl_community2_soc_data = {
290	.uid = "2",
291	.pins = ehl_community2_pins,
292	.npins = ARRAY_SIZE(ehl_community2_pins),
293	.communities = ehl_community2,
294	.ncommunities = ARRAY_SIZE(ehl_community2),
295};
296
297static const struct pinctrl_pin_desc ehl_community3_pins[] = {
298	/* CPU */
299	PINCTRL_PIN(0, "HDACPU_SDI"),
300	PINCTRL_PIN(1, "HDACPU_SDO"),
301	PINCTRL_PIN(2, "HDACPU_BCLK"),
302	PINCTRL_PIN(3, "PM_SYNC"),
303	PINCTRL_PIN(4, "PECI"),
304	PINCTRL_PIN(5, "CPUPWRGD"),
305	PINCTRL_PIN(6, "THRMTRIPB"),
306	PINCTRL_PIN(7, "PLTRST_CPUB"),
307	PINCTRL_PIN(8, "PM_DOWN"),
308	PINCTRL_PIN(9, "TRIGGER_IN"),
309	PINCTRL_PIN(10, "TRIGGER_OUT"),
310	PINCTRL_PIN(11, "UFS_RESETB"),
311	PINCTRL_PIN(12, "CLKOUT_CPURTC"),
312	PINCTRL_PIN(13, "VCCST_OVERRIDE"),
313	PINCTRL_PIN(14, "C10_WAKE"),
314	PINCTRL_PIN(15, "PROCHOTB"),
315	PINCTRL_PIN(16, "CATERRB"),
316	/* GPP_S */
317	PINCTRL_PIN(17, "UFS_REF_CLK_0"),
318	PINCTRL_PIN(18, "UFS_REF_CLK_1"),
319	/* GPP_A */
320	PINCTRL_PIN(19, "RGMII0_TXDATA_3"),
321	PINCTRL_PIN(20, "RGMII0_TXDATA_2"),
322	PINCTRL_PIN(21, "RGMII0_TXDATA_1"),
323	PINCTRL_PIN(22, "RGMII0_TXDATA_0"),
324	PINCTRL_PIN(23, "RGMII0_TXCLK"),
325	PINCTRL_PIN(24, "RGMII0_TXCTL"),
326	PINCTRL_PIN(25, "RGMII0_RXCLK"),
327	PINCTRL_PIN(26, "RGMII0_RXDATA_3"),
328	PINCTRL_PIN(27, "RGMII0_RXDATA_2"),
329	PINCTRL_PIN(28, "RGMII0_RXDATA_1"),
330	PINCTRL_PIN(29, "RGMII0_RXDATA_0"),
331	PINCTRL_PIN(30, "RGMII1_TXDATA_3"),
332	PINCTRL_PIN(31, "RGMII1_TXDATA_2"),
333	PINCTRL_PIN(32, "RGMII1_TXDATA_1"),
334	PINCTRL_PIN(33, "RGMII1_TXDATA_0"),
335	PINCTRL_PIN(34, "RGMII1_TXCLK"),
336	PINCTRL_PIN(35, "RGMII1_TXCTL"),
337	PINCTRL_PIN(36, "RGMII1_RXCLK"),
338	PINCTRL_PIN(37, "RGMII1_RXCTL"),
339	PINCTRL_PIN(38, "RGMII1_RXDATA_3"),
340	PINCTRL_PIN(39, "RGMII1_RXDATA_2"),
341	PINCTRL_PIN(40, "RGMII1_RXDATA_1"),
342	PINCTRL_PIN(41, "RGMII1_RXDATA_0"),
343	PINCTRL_PIN(42, "RGMII0_RXCTL"),
344	/* vGPIO_3 */
345	PINCTRL_PIN(43, "ESPI_USB_OCB_0"),
346	PINCTRL_PIN(44, "ESPI_USB_OCB_1"),
347	PINCTRL_PIN(45, "ESPI_USB_OCB_2"),
348	PINCTRL_PIN(46, "ESPI_USB_OCB_3"),
349};
350
351static const struct intel_padgroup ehl_community3_gpps[] = {
352	INTEL_GPP(0, 0, 16,  0),	/* CPU */
353	INTEL_GPP(1, 17, 18, 17),	/* GPP_S */
354	INTEL_GPP(2, 19, 42, 19),	/* GPP_A */
355	INTEL_GPP(3, 43, 46, 43),	/* vGPIO_3 */
356};
357
358static const struct intel_community ehl_community3[] = {
359	EHL_COMMUNITY(0, 0, 46, ehl_community3_gpps),
360};
361
362static const struct intel_pinctrl_soc_data ehl_community3_soc_data = {
363	.uid = "3",
364	.pins = ehl_community3_pins,
365	.npins = ARRAY_SIZE(ehl_community3_pins),
366	.communities = ehl_community3,
367	.ncommunities = ARRAY_SIZE(ehl_community3),
368};
369
370static const struct pinctrl_pin_desc ehl_community4_pins[] = {
371	/* GPP_C */
372	PINCTRL_PIN(0, "SMBCLK"),
373	PINCTRL_PIN(1, "SMBDATA"),
374	PINCTRL_PIN(2, "OSE_PWM0"),
375	PINCTRL_PIN(3, "RGMII0_MDC"),
376	PINCTRL_PIN(4, "RGMII0_MDIO"),
377	PINCTRL_PIN(5, "OSE_PWM1"),
378	PINCTRL_PIN(6, "RGMII1_MDC"),
379	PINCTRL_PIN(7, "RGMII1_MDIO"),
380	PINCTRL_PIN(8, "OSE_TGPIO4"),
381	PINCTRL_PIN(9, "OSE_HSUART0_EN"),
382	PINCTRL_PIN(10, "OSE_TGPIO5"),
383	PINCTRL_PIN(11, "OSE_HSUART0_RE"),
384	PINCTRL_PIN(12, "OSE_UART0_RXD"),
385	PINCTRL_PIN(13, "OSE_UART0_TXD"),
386	PINCTRL_PIN(14, "OSE_UART0_RTSB"),
387	PINCTRL_PIN(15, "OSE_UART0_CTSB"),
388	PINCTRL_PIN(16, "RGMII2_MDIO"),
389	PINCTRL_PIN(17, "RGMII2_MDC"),
390	PINCTRL_PIN(18, "OSE_I2C4_SDAT"),
391	PINCTRL_PIN(19, "OSE_I2C4_SCLK"),
392	PINCTRL_PIN(20, "OSE_UART4_RXD"),
393	PINCTRL_PIN(21, "OSE_UART4_TXD"),
394	PINCTRL_PIN(22, "OSE_UART4_RTSB"),
395	PINCTRL_PIN(23, "OSE_UART4_CTSB"),
396	/* GPP_F */
397	PINCTRL_PIN(24, "CNV_BRI_DT"),
398	PINCTRL_PIN(25, "CNV_BRI_RSP"),
399	PINCTRL_PIN(26, "CNV_RGI_DT"),
400	PINCTRL_PIN(27, "CNV_RGI_RSP"),
401	PINCTRL_PIN(28, "CNV_RF_RESET_B"),
402	PINCTRL_PIN(29, "EMMC_HIP_MON"),
403	PINCTRL_PIN(30, "CNV_PA_BLANKING"),
404	PINCTRL_PIN(31, "OSE_I2S1_SCLK"),
405	PINCTRL_PIN(32, "I2S_MCLK2_INOUT"),
406	PINCTRL_PIN(33, "BOOTMPC"),
407	PINCTRL_PIN(34, "OSE_I2S1_SFRM"),
408	PINCTRL_PIN(35, "GPPC_F_11"),
409	PINCTRL_PIN(36, "GSXDOUT"),
410	PINCTRL_PIN(37, "GSXSLOAD"),
411	PINCTRL_PIN(38, "GSXDIN"),
412	PINCTRL_PIN(39, "GSXSRESETB"),
413	PINCTRL_PIN(40, "GSXCLK"),
414	PINCTRL_PIN(41, "GPPC_F_17"),
415	PINCTRL_PIN(42, "OSE_I2S1_TXD"),
416	PINCTRL_PIN(43, "OSE_I2S1_RXD"),
417	PINCTRL_PIN(44, "EXT_PWR_GATEB"),
418	PINCTRL_PIN(45, "EXT_PWR_GATE2B"),
419	PINCTRL_PIN(46, "VNN_CTRL"),
420	PINCTRL_PIN(47, "V1P05_CTRL"),
421	PINCTRL_PIN(48, "GPPF_CLK_LOOPBACK"),
422	/* HVCMOS */
423	PINCTRL_PIN(49, "L_BKLTEN"),
424	PINCTRL_PIN(50, "L_BKLTCTL"),
425	PINCTRL_PIN(51, "L_VDDEN"),
426	PINCTRL_PIN(52, "SYS_PWROK"),
427	PINCTRL_PIN(53, "SYS_RESETB"),
428	PINCTRL_PIN(54, "MLK_RSTB"),
429	/* GPP_E */
430	PINCTRL_PIN(55, "SATA_LEDB"),
431	PINCTRL_PIN(56, "GPPC_E_1"),
432	PINCTRL_PIN(57, "GPPC_E_2"),
433	PINCTRL_PIN(58, "DDSP_HPD_B"),
434	PINCTRL_PIN(59, "SATA_DEVSLP_0"),
435	PINCTRL_PIN(60, "DDPB_CTRLDATA"),
436	PINCTRL_PIN(61, "GPPC_E_6"),
437	PINCTRL_PIN(62, "DDPB_CTRLCLK"),
438	PINCTRL_PIN(63, "GPPC_E_8"),
439	PINCTRL_PIN(64, "USB2_OCB_0"),
440	PINCTRL_PIN(65, "GPPC_E_10"),
441	PINCTRL_PIN(66, "GPPC_E_11"),
442	PINCTRL_PIN(67, "GPPC_E_12"),
443	PINCTRL_PIN(68, "GPPC_E_13"),
444	PINCTRL_PIN(69, "DDSP_HPD_A"),
445	PINCTRL_PIN(70, "OSE_I2S0_RXD"),
446	PINCTRL_PIN(71, "OSE_I2S0_TXD"),
447	PINCTRL_PIN(72, "DDSP_HPD_C"),
448	PINCTRL_PIN(73, "DDPA_CTRLDATA"),
449	PINCTRL_PIN(74, "DDPA_CTRLCLK"),
450	PINCTRL_PIN(75, "OSE_I2S0_SCLK"),
451	PINCTRL_PIN(76, "OSE_I2S0_SFRM"),
452	PINCTRL_PIN(77, "DDPC_CTRLDATA"),
453	PINCTRL_PIN(78, "DDPC_CTRLCLK"),
454	PINCTRL_PIN(79, "SPI1_CLK_LOOPBK"),
455};
456
457static const struct intel_padgroup ehl_community4_gpps[] = {
458	INTEL_GPP(0, 0, 23, 0),		/* GPP_C */
459	INTEL_GPP(1, 24, 48, 24),	/* GPP_F */
460	INTEL_GPP(2, 49, 54, 49),	/* HVCMOS */
461	INTEL_GPP(3, 55, 79, 55),	/* GPP_E */
462};
463
464static const struct intel_community ehl_community4[] = {
465	EHL_COMMUNITY(0, 0, 79, ehl_community4_gpps),
466};
467
468static const struct intel_pinctrl_soc_data ehl_community4_soc_data = {
469	.uid = "4",
470	.pins = ehl_community4_pins,
471	.npins = ARRAY_SIZE(ehl_community4_pins),
472	.communities = ehl_community4,
473	.ncommunities = ARRAY_SIZE(ehl_community4),
474};
475
476static const struct pinctrl_pin_desc ehl_community5_pins[] = {
477	/* GPP_R */
478	PINCTRL_PIN(0, "HDA_BCLK"),
479	PINCTRL_PIN(1, "HDA_SYNC"),
480	PINCTRL_PIN(2, "HDA_SDO"),
481	PINCTRL_PIN(3, "HDA_SDI_0"),
482	PINCTRL_PIN(4, "HDA_RSTB"),
483	PINCTRL_PIN(5, "HDA_SDI_1"),
484	PINCTRL_PIN(6, "GPP_R_6"),
485	PINCTRL_PIN(7, "GPP_R_7"),
486};
487
488static const struct intel_padgroup ehl_community5_gpps[] = {
489	INTEL_GPP(0, 0, 7, 0),		/* GPP_R */
490};
491
492static const struct intel_community ehl_community5[] = {
493	EHL_COMMUNITY(0, 0, 7, ehl_community5_gpps),
494};
495
496static const struct intel_pinctrl_soc_data ehl_community5_soc_data = {
497	.uid = "5",
498	.pins = ehl_community5_pins,
499	.npins = ARRAY_SIZE(ehl_community5_pins),
500	.communities = ehl_community5,
501	.ncommunities = ARRAY_SIZE(ehl_community5),
502};
503
504static const struct intel_pinctrl_soc_data *ehl_soc_data_array[] = {
505	&ehl_community0_soc_data,
506	&ehl_community1_soc_data,
507	&ehl_community2_soc_data,
508	&ehl_community3_soc_data,
509	&ehl_community4_soc_data,
510	&ehl_community5_soc_data,
511	NULL
512};
513
514static const struct acpi_device_id ehl_pinctrl_acpi_match[] = {
515	{ "INTC1020", (kernel_ulong_t)ehl_soc_data_array },
516	{ }
517};
518MODULE_DEVICE_TABLE(acpi, ehl_pinctrl_acpi_match);
519
520static struct platform_driver ehl_pinctrl_driver = {
521	.probe = intel_pinctrl_probe_by_uid,
522	.driver = {
523		.name = "elkhartlake-pinctrl",
524		.acpi_match_table = ehl_pinctrl_acpi_match,
525		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
526	},
527};
528module_platform_driver(ehl_pinctrl_driver);
529
530MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
531MODULE_DESCRIPTION("Intel Elkhart Lake PCH pinctrl/GPIO driver");
532MODULE_LICENSE("GPL v2");
533MODULE_IMPORT_NS("PINCTRL_INTEL");