pinctrl-denverton.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Intel Denverton SoC pinctrl/GPIO driver
  4 *
  5 * Copyright (C) 2017, Intel Corporation
  6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com>
  7 */
  8
  9#include <linux/mod_devicetable.h>
 10#include <linux/module.h>
 11#include <linux/platform_device.h>
 12#include <linux/pm.h>
 13
 14#include <linux/pinctrl/pinctrl.h>
 15
 16#include "pinctrl-intel.h"
 17
 18#define DNV_PAD_OWN	0x020
 19#define DNV_PADCFGLOCK	0x090
 20#define DNV_HOSTSW_OWN	0x0C0
 21#define DNV_GPI_IS	0x100
 22#define DNV_GPI_IE	0x120
 23
 24#define DNV_COMMUNITY(b, s, e, g)			\
 25	INTEL_COMMUNITY_GPPS(b, s, e, g, DNV)
 26
 27/* Denverton */
 28static const struct pinctrl_pin_desc dnv_pins[] = {
 29	/* North ALL */
 30	PINCTRL_PIN(0, "GBE0_SDP0"),
 31	PINCTRL_PIN(1, "GBE1_SDP0"),
 32	PINCTRL_PIN(2, "GBE0_SDP1"),
 33	PINCTRL_PIN(3, "GBE1_SDP1"),
 34	PINCTRL_PIN(4, "GBE0_SDP2"),
 35	PINCTRL_PIN(5, "GBE1_SDP2"),
 36	PINCTRL_PIN(6, "GBE0_SDP3"),
 37	PINCTRL_PIN(7, "GBE1_SDP3"),
 38	PINCTRL_PIN(8, "GBE2_LED0"),
 39	PINCTRL_PIN(9, "GBE2_LED1"),
 40	PINCTRL_PIN(10, "GBE0_I2C_CLK"),
 41	PINCTRL_PIN(11, "GBE0_I2C_DATA"),
 42	PINCTRL_PIN(12, "GBE1_I2C_CLK"),
 43	PINCTRL_PIN(13, "GBE1_I2C_DATA"),
 44	PINCTRL_PIN(14, "NCSI_RXD0"),
 45	PINCTRL_PIN(15, "NCSI_CLK_IN"),
 46	PINCTRL_PIN(16, "NCSI_RXD1"),
 47	PINCTRL_PIN(17, "NCSI_CRS_DV"),
 48	PINCTRL_PIN(18, "IDSLDO_VID_TICKLE"),
 49	PINCTRL_PIN(19, "NCSI_TX_EN"),
 50	PINCTRL_PIN(20, "NCSI_TXD0"),
 51	PINCTRL_PIN(21, "NCSI_TXD1"),
 52	PINCTRL_PIN(22, "NCSI_ARB_OUT"),
 53	PINCTRL_PIN(23, "GBE0_LED0"),
 54	PINCTRL_PIN(24, "GBE0_LED1"),
 55	PINCTRL_PIN(25, "GBE1_LED0"),
 56	PINCTRL_PIN(26, "GBE1_LED1"),
 57	PINCTRL_PIN(27, "SPARE_0"),
 58	PINCTRL_PIN(28, "PCIE_CLKREQ0_N"),
 59	PINCTRL_PIN(29, "PCIE_CLKREQ1_N"),
 60	PINCTRL_PIN(30, "PCIE_CLKREQ2_N"),
 61	PINCTRL_PIN(31, "PCIE_CLKREQ3_N"),
 62	PINCTRL_PIN(32, "PCIE_CLKREQ4_N"),
 63	PINCTRL_PIN(33, "GBE_MDC"),
 64	PINCTRL_PIN(34, "GBE_MDIO"),
 65	PINCTRL_PIN(35, "SVID_ALERT_N"),
 66	PINCTRL_PIN(36, "SVID_DATA"),
 67	PINCTRL_PIN(37, "SVID_CLK"),
 68	PINCTRL_PIN(38, "THERMTRIP_N"),
 69	PINCTRL_PIN(39, "PROCHOT_N"),
 70	PINCTRL_PIN(40, "MEMHOT_N"),
 71	/* South DFX */
 72	PINCTRL_PIN(41, "DFX_PORT_CLK0"),
 73	PINCTRL_PIN(42, "DFX_PORT_CLK1"),
 74	PINCTRL_PIN(43, "DFX_PORT0"),
 75	PINCTRL_PIN(44, "DFX_PORT1"),
 76	PINCTRL_PIN(45, "DFX_PORT2"),
 77	PINCTRL_PIN(46, "DFX_PORT3"),
 78	PINCTRL_PIN(47, "DFX_PORT4"),
 79	PINCTRL_PIN(48, "DFX_PORT5"),
 80	PINCTRL_PIN(49, "DFX_PORT6"),
 81	PINCTRL_PIN(50, "DFX_PORT7"),
 82	PINCTRL_PIN(51, "DFX_PORT8"),
 83	PINCTRL_PIN(52, "DFX_PORT9"),
 84	PINCTRL_PIN(53, "DFX_PORT10"),
 85	PINCTRL_PIN(54, "DFX_PORT11"),
 86	PINCTRL_PIN(55, "DFX_PORT12"),
 87	PINCTRL_PIN(56, "DFX_PORT13"),
 88	PINCTRL_PIN(57, "DFX_PORT14"),
 89	PINCTRL_PIN(58, "DFX_PORT15"),
 90	/* South GPP0 */
 91	PINCTRL_PIN(59, "SPI_TPM_CS_N"),
 92	PINCTRL_PIN(60, "UART2_CTS"),
 93	PINCTRL_PIN(61, "PCIE_CLKREQ5_N"),
 94	PINCTRL_PIN(62, "PCIE_CLKREQ6_N"),
 95	PINCTRL_PIN(63, "PCIE_CLKREQ7_N"),
 96	PINCTRL_PIN(64, "UART0_RXD"),
 97	PINCTRL_PIN(65, "UART0_TXD"),
 98	PINCTRL_PIN(66, "CPU_RESET_N"),
 99	PINCTRL_PIN(67, "NMI"),
100	PINCTRL_PIN(68, "ERROR2_N"),
101	PINCTRL_PIN(69, "ERROR1_N"),
102	PINCTRL_PIN(70, "ERROR0_N"),
103	PINCTRL_PIN(71, "IERR_N"),
104	PINCTRL_PIN(72, "MCERR_N"),
105	PINCTRL_PIN(73, "SMB0_LEG_CLK"),
106	PINCTRL_PIN(74, "SMB0_LEG_DATA"),
107	PINCTRL_PIN(75, "SMB0_LEG_ALRT_N"),
108	PINCTRL_PIN(76, "SMB1_HOST_DATA"),
109	PINCTRL_PIN(77, "SMB1_HOST_CLK"),
110	PINCTRL_PIN(78, "SMB2_PECI_DATA"),
111	PINCTRL_PIN(79, "SMB2_PECI_CLK"),
112	PINCTRL_PIN(80, "SMB4_CSME0_DATA"),
113	PINCTRL_PIN(81, "SMB4_CSME0_CLK"),
114	PINCTRL_PIN(82, "SMB4_CSME0_ALRT_N"),
115	PINCTRL_PIN(83, "USB_OC0_N"),
116	PINCTRL_PIN(84, "FLEX_CLK_SE0"),
117	PINCTRL_PIN(85, "FLEX_CLK_SE1"),
118	PINCTRL_PIN(86, "SPARE_4"),
119	PINCTRL_PIN(87, "SMB3_IE0_CLK"),
120	PINCTRL_PIN(88, "SMB3_IE0_DATA"),
121	PINCTRL_PIN(89, "SMB3_IE0_ALRT_N"),
122	PINCTRL_PIN(90, "SATA0_LED_N"),
123	PINCTRL_PIN(91, "SATA1_LED_N"),
124	PINCTRL_PIN(92, "SATA_PDETECT0"),
125	PINCTRL_PIN(93, "SATA_PDETECT1"),
126	PINCTRL_PIN(94, "UART1_RTS"),
127	PINCTRL_PIN(95, "UART1_CTS"),
128	PINCTRL_PIN(96, "UART1_RXD"),
129	PINCTRL_PIN(97, "UART1_TXD"),
130	PINCTRL_PIN(98, "SPARE_8"),
131	PINCTRL_PIN(99, "SPARE_9"),
132	PINCTRL_PIN(100, "TCK"),
133	PINCTRL_PIN(101, "TRST_N"),
134	PINCTRL_PIN(102, "TMS"),
135	PINCTRL_PIN(103, "TDI"),
136	PINCTRL_PIN(104, "TDO"),
137	PINCTRL_PIN(105, "CX_PRDY_N"),
138	PINCTRL_PIN(106, "CX_PREQ_N"),
139	PINCTRL_PIN(107, "TAP1_TCK"),
140	PINCTRL_PIN(108, "TAP1_TRST_N"),
141	PINCTRL_PIN(109, "TAP1_TMS"),
142	PINCTRL_PIN(110, "TAP1_TDI"),
143	PINCTRL_PIN(111, "TAP1_TDO"),
144	/* South GPP1 */
145	PINCTRL_PIN(112, "SUSPWRDNACK"),
146	PINCTRL_PIN(113, "PMU_SUSCLK"),
147	PINCTRL_PIN(114, "ADR_TRIGGER"),
148	PINCTRL_PIN(115, "PMU_SLP_S45_N"),
149	PINCTRL_PIN(116, "PMU_SLP_S3_N"),
150	PINCTRL_PIN(117, "PMU_WAKE_N"),
151	PINCTRL_PIN(118, "PMU_PWRBTN_N"),
152	PINCTRL_PIN(119, "PMU_RESETBUTTON_N"),
153	PINCTRL_PIN(120, "PMU_PLTRST_N"),
154	PINCTRL_PIN(121, "SUS_STAT_N"),
155	PINCTRL_PIN(122, "SLP_S0IX_N"),
156	PINCTRL_PIN(123, "SPI_CS0_N"),
157	PINCTRL_PIN(124, "SPI_CS1_N"),
158	PINCTRL_PIN(125, "SPI_MOSI_IO0"),
159	PINCTRL_PIN(126, "SPI_MISO_IO1"),
160	PINCTRL_PIN(127, "SPI_IO2"),
161	PINCTRL_PIN(128, "SPI_IO3"),
162	PINCTRL_PIN(129, "SPI_CLK"),
163	PINCTRL_PIN(130, "SPI_CLK_LOOPBK"),
164	PINCTRL_PIN(131, "ESPI_IO0"),
165	PINCTRL_PIN(132, "ESPI_IO1"),
166	PINCTRL_PIN(133, "ESPI_IO2"),
167	PINCTRL_PIN(134, "ESPI_IO3"),
168	PINCTRL_PIN(135, "ESPI_CS0_N"),
169	PINCTRL_PIN(136, "ESPI_CLK"),
170	PINCTRL_PIN(137, "ESPI_RST_N"),
171	PINCTRL_PIN(138, "ESPI_ALRT0_N"),
172	PINCTRL_PIN(139, "ESPI_CS1_N"),
173	PINCTRL_PIN(140, "ESPI_ALRT1_N"),
174	PINCTRL_PIN(141, "ESPI_CLK_LOOPBK"),
175	PINCTRL_PIN(142, "EMMC_CMD"),
176	PINCTRL_PIN(143, "EMMC_STROBE"),
177	PINCTRL_PIN(144, "EMMC_CLK"),
178	PINCTRL_PIN(145, "EMMC_D0"),
179	PINCTRL_PIN(146, "EMMC_D1"),
180	PINCTRL_PIN(147, "EMMC_D2"),
181	PINCTRL_PIN(148, "EMMC_D3"),
182	PINCTRL_PIN(149, "EMMC_D4"),
183	PINCTRL_PIN(150, "EMMC_D5"),
184	PINCTRL_PIN(151, "EMMC_D6"),
185	PINCTRL_PIN(152, "EMMC_D7"),
186	PINCTRL_PIN(153, "SPARE_3"),
187};
188
189static const unsigned int dnv_uart0_pins[] = { 60, 61, 64, 65 };
190static const unsigned int dnv_uart0_modes[] = { 2, 3, 1, 1 };
191static const unsigned int dnv_uart1_pins[] = { 94, 95, 96, 97 };
192static const unsigned int dnv_uart2_pins[] = { 60, 61, 62, 63 };
193static const unsigned int dnv_uart2_modes[] = { 1, 2, 2, 2 };
194static const unsigned int dnv_emmc_pins[] = {
195	142, 143, 144, 145, 146, 147, 148, 149, 150, 151, 152,
196};
197
198static const struct intel_pingroup dnv_groups[] = {
199	PIN_GROUP("uart0_grp", dnv_uart0_pins, dnv_uart0_modes),
200	PIN_GROUP("uart1_grp", dnv_uart1_pins, 1),
201	PIN_GROUP("uart2_grp", dnv_uart2_pins, dnv_uart2_modes),
202	PIN_GROUP("emmc_grp", dnv_emmc_pins, 1),
203};
204
205static const char * const dnv_uart0_groups[] = { "uart0_grp" };
206static const char * const dnv_uart1_groups[] = { "uart1_grp" };
207static const char * const dnv_uart2_groups[] = { "uart2_grp" };
208static const char * const dnv_emmc_groups[] = { "emmc_grp" };
209
210static const struct intel_function dnv_functions[] = {
211	FUNCTION("uart0", dnv_uart0_groups),
212	FUNCTION("uart1", dnv_uart1_groups),
213	FUNCTION("uart2", dnv_uart2_groups),
214	FUNCTION("emmc", dnv_emmc_groups),
215};
216
217static const struct intel_padgroup dnv_north_gpps[] = {
218	INTEL_GPP(0, 0, 31, 0),		/* North ALL_0 */
219	INTEL_GPP(1, 32, 40, 32),	/* North ALL_1 */
220};
221
222static const struct intel_padgroup dnv_south_gpps[] = {
223	INTEL_GPP(0, 41, 58, 41),	/* South DFX */
224	INTEL_GPP(1, 59, 90, 59),	/* South GPP0_0 */
225	INTEL_GPP(2, 91, 111, 91),	/* South GPP0_1 */
226	INTEL_GPP(3, 112, 143, 112),	/* South GPP1_0 */
227	INTEL_GPP(4, 144, 153, 144),	/* South GPP1_1 */
228};
229
230static const struct intel_community dnv_communities[] = {
231	DNV_COMMUNITY(0, 0, 40, dnv_north_gpps),
232	DNV_COMMUNITY(1, 41, 153, dnv_south_gpps),
233};
234
235static const struct intel_pinctrl_soc_data dnv_soc_data = {
236	.pins = dnv_pins,
237	.npins = ARRAY_SIZE(dnv_pins),
238	.groups = dnv_groups,
239	.ngroups = ARRAY_SIZE(dnv_groups),
240	.functions = dnv_functions,
241	.nfunctions = ARRAY_SIZE(dnv_functions),
242	.communities = dnv_communities,
243	.ncommunities = ARRAY_SIZE(dnv_communities),
244};
245
246static const struct acpi_device_id dnv_pinctrl_acpi_match[] = {
247	{ "INTC3000", (kernel_ulong_t)&dnv_soc_data },
248	{ }
249};
250MODULE_DEVICE_TABLE(acpi, dnv_pinctrl_acpi_match);
251
252static const struct platform_device_id dnv_pinctrl_platform_ids[] = {
253	{ "denverton-pinctrl", (kernel_ulong_t)&dnv_soc_data },
254	{ }
255};
256MODULE_DEVICE_TABLE(platform, dnv_pinctrl_platform_ids);
257
258static struct platform_driver dnv_pinctrl_driver = {
259	.probe = intel_pinctrl_probe_by_hid,
260	.driver = {
261		.name = "denverton-pinctrl",
262		.acpi_match_table = dnv_pinctrl_acpi_match,
263		.pm = pm_sleep_ptr(&intel_pinctrl_pm_ops),
264	},
265	.id_table = dnv_pinctrl_platform_ids,
266};
267
268static int __init dnv_pinctrl_init(void)
269{
270	return platform_driver_register(&dnv_pinctrl_driver);
271}
272subsys_initcall(dnv_pinctrl_init);
273
274static void __exit dnv_pinctrl_exit(void)
275{
276	platform_driver_unregister(&dnv_pinctrl_driver);
277}
278module_exit(dnv_pinctrl_exit);
279
280MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
281MODULE_DESCRIPTION("Intel Denverton SoC pinctrl/GPIO driver");
282MODULE_LICENSE("GPL v2");
283MODULE_IMPORT_NS("PINCTRL_INTEL");