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pinctrl-cherryview.c
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linux-6.19.14/drivers/pinctrl/intel/pinctrl-cherryview.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Cherryview/Braswell pinctrl driver 4 * 5 * Copyright (C) 2014, 2020 Intel Corporation 6 * Author: Mika Westerberg <mika.westerberg@linux.intel.com> 7 * 8 * This driver is based on the original Cherryview GPIO driver by 9 * Ning Li <ning.li@intel.com> 10 * Alan Cox <alan@linux.intel.com> 11 */ 12 13#include <linux/acpi.h> 14#include <linux/array_size.h> 15#include <linux/cleanup.h> 16#include <linux/dmi.h> 17#include <linux/gpio/driver.h> 18#include <linux/module.h> 19#include <linux/platform_device.h> 20#include <linux/seq_file.h> 21#include <linux/types.h> 22 23#include <linux/pinctrl/consumer.h> 24#include <linux/pinctrl/pinconf-generic.h> 25#include <linux/pinctrl/pinconf.h> 26#include <linux/pinctrl/pinctrl.h> 27#include <linux/pinctrl/pinmux.h> 28 29#include "pinctrl-intel.h" 30 31#define CHV_INTSTAT 0x300 32#define CHV_INTMASK 0x380 33 34#define FAMILY_PAD_REGS_OFF 0x4400 35#define FAMILY_PAD_REGS_SIZE 0x400 36#define MAX_FAMILY_PAD_GPIO_NO 15 37#define GPIO_REGS_SIZE 8 38 39#define CHV_PADCTRL0 0x000 40#define CHV_PADCTRL0_INTSEL_SHIFT 28 41#define CHV_PADCTRL0_INTSEL_MASK GENMASK(31, 28) 42#define CHV_PADCTRL0_TERM_UP BIT(23) 43#define CHV_PADCTRL0_TERM_SHIFT 20 44#define CHV_PADCTRL0_TERM_MASK GENMASK(22, 20) 45#define CHV_PADCTRL0_TERM_20K 1 46#define CHV_PADCTRL0_TERM_5K 2 47#define CHV_PADCTRL0_TERM_1K 4 48#define CHV_PADCTRL0_PMODE_SHIFT 16 49#define CHV_PADCTRL0_PMODE_MASK GENMASK(19, 16) 50#define CHV_PADCTRL0_GPIOEN BIT(15) 51#define CHV_PADCTRL0_GPIOCFG_SHIFT 8 52#define CHV_PADCTRL0_GPIOCFG_MASK GENMASK(10, 8) 53#define CHV_PADCTRL0_GPIOCFG_GPIO 0 54#define CHV_PADCTRL0_GPIOCFG_GPO 1 55#define CHV_PADCTRL0_GPIOCFG_GPI 2 56#define CHV_PADCTRL0_GPIOCFG_HIZ 3 57#define CHV_PADCTRL0_GPIOTXSTATE BIT(1) 58#define CHV_PADCTRL0_GPIORXSTATE BIT(0) 59 60#define CHV_PADCTRL1 0x004 61#define CHV_PADCTRL1_CFGLOCK BIT(31) 62#define CHV_PADCTRL1_INVRXTX_SHIFT 4 63#define CHV_PADCTRL1_INVRXTX_MASK GENMASK(7, 4) 64#define CHV_PADCTRL1_INVRXTX_TXDATA BIT(7) 65#define CHV_PADCTRL1_INVRXTX_RXDATA BIT(6) 66#define CHV_PADCTRL1_INVRXTX_TXENABLE BIT(5) 67#define CHV_PADCTRL1_ODEN BIT(3) 68#define CHV_PADCTRL1_INTWAKECFG_MASK GENMASK(2, 0) 69#define CHV_PADCTRL1_INTWAKECFG_FALLING 1 70#define CHV_PADCTRL1_INTWAKECFG_RISING 2 71#define CHV_PADCTRL1_INTWAKECFG_BOTH 3 72#define CHV_PADCTRL1_INTWAKECFG_LEVEL 4 73 74struct intel_pad_context { 75 u32 padctrl0; 76 u32 padctrl1; 77}; 78 79#define CHV_INVALID_HWIRQ (~0U) 80 81/** 82 * struct intel_community_context - community context for Cherryview 83 * @intr_lines: Mapping between 16 HW interrupt wires and GPIO offset (in GPIO number space) 84 * @saved_intmask: Interrupt mask saved for system sleep 85 */ 86struct intel_community_context { 87 unsigned int intr_lines[16]; 88 u32 saved_intmask; 89}; 90 91#define PINMODE_INVERT_OE BIT(15) 92 93#define PINMODE(m, i) ((m) | ((i) * PINMODE_INVERT_OE)) 94 95#define CHV_COMMUNITY(g, i, a) \ 96 { \ 97 .gpps = (g), \ 98 .ngpps = ARRAY_SIZE(g), \ 99 .nirqs = (i), \ 100 .acpi_space_id = (a), \ 101 } 102 103static const struct pinctrl_pin_desc southwest_pins[] = { 104 PINCTRL_PIN(0, "FST_SPI_D2"), 105 PINCTRL_PIN(1, "FST_SPI_D0"), 106 PINCTRL_PIN(2, "FST_SPI_CLK"), 107 PINCTRL_PIN(3, "FST_SPI_D3"), 108 PINCTRL_PIN(4, "FST_SPI_CS1_B"), 109 PINCTRL_PIN(5, "FST_SPI_D1"), 110 PINCTRL_PIN(6, "FST_SPI_CS0_B"), 111 PINCTRL_PIN(7, "FST_SPI_CS2_B"), 112 113 PINCTRL_PIN(15, "UART1_RTS_B"), 114 PINCTRL_PIN(16, "UART1_RXD"), 115 PINCTRL_PIN(17, "UART2_RXD"), 116 PINCTRL_PIN(18, "UART1_CTS_B"), 117 PINCTRL_PIN(19, "UART2_RTS_B"), 118 PINCTRL_PIN(20, "UART1_TXD"), 119 PINCTRL_PIN(21, "UART2_TXD"), 120 PINCTRL_PIN(22, "UART2_CTS_B"), 121 122 PINCTRL_PIN(30, "MF_HDA_CLK"), 123 PINCTRL_PIN(31, "MF_HDA_RSTB"), 124 PINCTRL_PIN(32, "MF_HDA_SDIO"), 125 PINCTRL_PIN(33, "MF_HDA_SDO"), 126 PINCTRL_PIN(34, "MF_HDA_DOCKRSTB"), 127 PINCTRL_PIN(35, "MF_HDA_SYNC"), 128 PINCTRL_PIN(36, "MF_HDA_SDI1"), 129 PINCTRL_PIN(37, "MF_HDA_DOCKENB"), 130 131 PINCTRL_PIN(45, "I2C5_SDA"), 132 PINCTRL_PIN(46, "I2C4_SDA"), 133 PINCTRL_PIN(47, "I2C6_SDA"), 134 PINCTRL_PIN(48, "I2C5_SCL"), 135 PINCTRL_PIN(49, "I2C_NFC_SDA"), 136 PINCTRL_PIN(50, "I2C4_SCL"), 137 PINCTRL_PIN(51, "I2C6_SCL"), 138 PINCTRL_PIN(52, "I2C_NFC_SCL"), 139 140 PINCTRL_PIN(60, "I2C1_SDA"), 141 PINCTRL_PIN(61, "I2C0_SDA"), 142 PINCTRL_PIN(62, "I2C2_SDA"), 143 PINCTRL_PIN(63, "I2C1_SCL"), 144 PINCTRL_PIN(64, "I2C3_SDA"), 145 PINCTRL_PIN(65, "I2C0_SCL"), 146 PINCTRL_PIN(66, "I2C2_SCL"), 147 PINCTRL_PIN(67, "I2C3_SCL"), 148 149 PINCTRL_PIN(75, "SATA_GP0"), 150 PINCTRL_PIN(76, "SATA_GP1"), 151 PINCTRL_PIN(77, "SATA_LEDN"), 152 PINCTRL_PIN(78, "SATA_GP2"), 153 PINCTRL_PIN(79, "MF_SMB_ALERTB"), 154 PINCTRL_PIN(80, "SATA_GP3"), 155 PINCTRL_PIN(81, "MF_SMB_CLK"), 156 PINCTRL_PIN(82, "MF_SMB_DATA"), 157 158 PINCTRL_PIN(90, "PCIE_CLKREQ0B"), 159 PINCTRL_PIN(91, "PCIE_CLKREQ1B"), 160 PINCTRL_PIN(92, "GP_SSP_2_CLK"), 161 PINCTRL_PIN(93, "PCIE_CLKREQ2B"), 162 PINCTRL_PIN(94, "GP_SSP_2_RXD"), 163 PINCTRL_PIN(95, "PCIE_CLKREQ3B"), 164 PINCTRL_PIN(96, "GP_SSP_2_FS"), 165 PINCTRL_PIN(97, "GP_SSP_2_TXD"), 166}; 167 168static const unsigned southwest_uart0_pins[] = { 16, 20 }; 169static const unsigned southwest_uart1_pins[] = { 15, 16, 18, 20 }; 170static const unsigned southwest_uart2_pins[] = { 17, 19, 21, 22 }; 171static const unsigned southwest_i2c0_pins[] = { 61, 65 }; 172static const unsigned southwest_hda_pins[] = { 30, 31, 32, 33, 34, 35, 36, 37 }; 173static const unsigned southwest_lpe_pins[] = { 174 30, 31, 32, 33, 34, 35, 36, 37, 92, 94, 96, 97, 175}; 176static const unsigned southwest_i2c1_pins[] = { 60, 63 }; 177static const unsigned southwest_i2c2_pins[] = { 62, 66 }; 178static const unsigned southwest_i2c3_pins[] = { 64, 67 }; 179static const unsigned southwest_i2c4_pins[] = { 46, 50 }; 180static const unsigned southwest_i2c5_pins[] = { 45, 48 }; 181static const unsigned southwest_i2c6_pins[] = { 47, 51 }; 182static const unsigned southwest_i2c_nfc_pins[] = { 49, 52 }; 183static const unsigned southwest_spi3_pins[] = { 76, 79, 80, 81, 82 }; 184 185/* Some of LPE I2S TXD pins need to have OE inversion set */ 186static const unsigned int southwest_lpe_altfuncs[] = { 187 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 30, 31, 32, 33 */ 188 PINMODE(1, 1), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), /* 34, 35, 36, 37 */ 189 PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 0), PINMODE(1, 1), /* 92, 94, 96, 97 */ 190}; 191 192/* 193 * Two spi3 chipselects are available in different mode than the main spi3 194 * functionality, which is using mode 2. 195 */ 196static const unsigned int southwest_spi3_altfuncs[] = { 197 PINMODE(3, 0), PINMODE(2, 0), PINMODE(3, 0), PINMODE(2, 0), /* 76, 79, 80, 81 */ 198 PINMODE(2, 0), /* 82 */ 199}; 200 201static const struct intel_pingroup southwest_groups[] = { 202 PIN_GROUP("uart0_grp", southwest_uart0_pins, PINMODE(2, 0)), 203 PIN_GROUP("uart1_grp", southwest_uart1_pins, PINMODE(1, 0)), 204 PIN_GROUP("uart2_grp", southwest_uart2_pins, PINMODE(1, 0)), 205 PIN_GROUP("hda_grp", southwest_hda_pins, PINMODE(2, 0)), 206 PIN_GROUP("i2c0_grp", southwest_i2c0_pins, PINMODE(1, 1)), 207 PIN_GROUP("i2c1_grp", southwest_i2c1_pins, PINMODE(1, 1)), 208 PIN_GROUP("i2c2_grp", southwest_i2c2_pins, PINMODE(1, 1)), 209 PIN_GROUP("i2c3_grp", southwest_i2c3_pins, PINMODE(1, 1)), 210 PIN_GROUP("i2c4_grp", southwest_i2c4_pins, PINMODE(1, 1)), 211 PIN_GROUP("i2c5_grp", southwest_i2c5_pins, PINMODE(1, 1)), 212 PIN_GROUP("i2c6_grp", southwest_i2c6_pins, PINMODE(1, 1)), 213 PIN_GROUP("i2c_nfc_grp", southwest_i2c_nfc_pins, PINMODE(2, 1)), 214 PIN_GROUP("lpe_grp", southwest_lpe_pins, southwest_lpe_altfuncs), 215 PIN_GROUP("spi3_grp", southwest_spi3_pins, southwest_spi3_altfuncs), 216}; 217 218static const char * const southwest_uart0_groups[] = { "uart0_grp" }; 219static const char * const southwest_uart1_groups[] = { "uart1_grp" }; 220static const char * const southwest_uart2_groups[] = { "uart2_grp" }; 221static const char * const southwest_hda_groups[] = { "hda_grp" }; 222static const char * const southwest_lpe_groups[] = { "lpe_grp" }; 223static const char * const southwest_i2c0_groups[] = { "i2c0_grp" }; 224static const char * const southwest_i2c1_groups[] = { "i2c1_grp" }; 225static const char * const southwest_i2c2_groups[] = { "i2c2_grp" }; 226static const char * const southwest_i2c3_groups[] = { "i2c3_grp" }; 227static const char * const southwest_i2c4_groups[] = { "i2c4_grp" }; 228static const char * const southwest_i2c5_groups[] = { "i2c5_grp" }; 229static const char * const southwest_i2c6_groups[] = { "i2c6_grp" }; 230static const char * const southwest_i2c_nfc_groups[] = { "i2c_nfc_grp" }; 231static const char * const southwest_spi3_groups[] = { "spi3_grp" }; 232 233/* 234 * Only do pinmuxing for certain LPSS devices for now. Rest of the pins are 235 * enabled only as GPIOs. 236 */ 237static const struct intel_function southwest_functions[] = { 238 FUNCTION("uart0", southwest_uart0_groups), 239 FUNCTION("uart1", southwest_uart1_groups), 240 FUNCTION("uart2", southwest_uart2_groups), 241 FUNCTION("hda", southwest_hda_groups), 242 FUNCTION("lpe", southwest_lpe_groups), 243 FUNCTION("i2c0", southwest_i2c0_groups), 244 FUNCTION("i2c1", southwest_i2c1_groups), 245 FUNCTION("i2c2", southwest_i2c2_groups), 246 FUNCTION("i2c3", southwest_i2c3_groups), 247 FUNCTION("i2c4", southwest_i2c4_groups), 248 FUNCTION("i2c5", southwest_i2c5_groups), 249 FUNCTION("i2c6", southwest_i2c6_groups), 250 FUNCTION("i2c_nfc", southwest_i2c_nfc_groups), 251 FUNCTION("spi3", southwest_spi3_groups), 252}; 253 254static const struct intel_padgroup southwest_gpps[] = { 255 INTEL_GPP(0, 0, 7, 0), 256 INTEL_GPP(1, 15, 22, 15), 257 INTEL_GPP(2, 30, 37, 30), 258 INTEL_GPP(3, 45, 52, 45), 259 INTEL_GPP(4, 60, 67, 60), 260 INTEL_GPP(5, 75, 82, 75), 261 INTEL_GPP(6, 90, 97, 90), 262}; 263 264/* 265 * Southwest community can generate GPIO interrupts only for the first 8 266 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 267 */ 268static const struct intel_community southwest_communities[] = { 269 CHV_COMMUNITY(southwest_gpps, 8, 0x91), 270}; 271 272static const struct intel_pinctrl_soc_data southwest_soc_data = { 273 .uid = "1", 274 .pins = southwest_pins, 275 .npins = ARRAY_SIZE(southwest_pins), 276 .groups = southwest_groups, 277 .ngroups = ARRAY_SIZE(southwest_groups), 278 .functions = southwest_functions, 279 .nfunctions = ARRAY_SIZE(southwest_functions), 280 .communities = southwest_communities, 281 .ncommunities = ARRAY_SIZE(southwest_communities), 282}; 283 284static const struct pinctrl_pin_desc north_pins[] = { 285 PINCTRL_PIN(0, "GPIO_DFX_0"), 286 PINCTRL_PIN(1, "GPIO_DFX_3"), 287 PINCTRL_PIN(2, "GPIO_DFX_7"), 288 PINCTRL_PIN(3, "GPIO_DFX_1"), 289 PINCTRL_PIN(4, "GPIO_DFX_5"), 290 PINCTRL_PIN(5, "GPIO_DFX_4"), 291 PINCTRL_PIN(6, "GPIO_DFX_8"), 292 PINCTRL_PIN(7, "GPIO_DFX_2"), 293 PINCTRL_PIN(8, "GPIO_DFX_6"), 294 295 PINCTRL_PIN(15, "GPIO_SUS0"), 296 PINCTRL_PIN(16, "SEC_GPIO_SUS10"), 297 PINCTRL_PIN(17, "GPIO_SUS3"), 298 PINCTRL_PIN(18, "GPIO_SUS7"), 299 PINCTRL_PIN(19, "GPIO_SUS1"), 300 PINCTRL_PIN(20, "GPIO_SUS5"), 301 PINCTRL_PIN(21, "SEC_GPIO_SUS11"), 302 PINCTRL_PIN(22, "GPIO_SUS4"), 303 PINCTRL_PIN(23, "SEC_GPIO_SUS8"), 304 PINCTRL_PIN(24, "GPIO_SUS2"), 305 PINCTRL_PIN(25, "GPIO_SUS6"), 306 PINCTRL_PIN(26, "CX_PREQ_B"), 307 PINCTRL_PIN(27, "SEC_GPIO_SUS9"), 308 309 PINCTRL_PIN(30, "TRST_B"), 310 PINCTRL_PIN(31, "TCK"), 311 PINCTRL_PIN(32, "PROCHOT_B"), 312 PINCTRL_PIN(33, "SVIDO_DATA"), 313 PINCTRL_PIN(34, "TMS"), 314 PINCTRL_PIN(35, "CX_PRDY_B_2"), 315 PINCTRL_PIN(36, "TDO_2"), 316 PINCTRL_PIN(37, "CX_PRDY_B"), 317 PINCTRL_PIN(38, "SVIDO_ALERT_B"), 318 PINCTRL_PIN(39, "TDO"), 319 PINCTRL_PIN(40, "SVIDO_CLK"), 320 PINCTRL_PIN(41, "TDI"), 321 322 PINCTRL_PIN(45, "GP_CAMERASB_05"), 323 PINCTRL_PIN(46, "GP_CAMERASB_02"), 324 PINCTRL_PIN(47, "GP_CAMERASB_08"), 325 PINCTRL_PIN(48, "GP_CAMERASB_00"), 326 PINCTRL_PIN(49, "GP_CAMERASB_06"), 327 PINCTRL_PIN(50, "GP_CAMERASB_10"), 328 PINCTRL_PIN(51, "GP_CAMERASB_03"), 329 PINCTRL_PIN(52, "GP_CAMERASB_09"), 330 PINCTRL_PIN(53, "GP_CAMERASB_01"), 331 PINCTRL_PIN(54, "GP_CAMERASB_07"), 332 PINCTRL_PIN(55, "GP_CAMERASB_11"), 333 PINCTRL_PIN(56, "GP_CAMERASB_04"), 334 335 PINCTRL_PIN(60, "PANEL0_BKLTEN"), 336 PINCTRL_PIN(61, "HV_DDI0_HPD"), 337 PINCTRL_PIN(62, "HV_DDI2_DDC_SDA"), 338 PINCTRL_PIN(63, "PANEL1_BKLTCTL"), 339 PINCTRL_PIN(64, "HV_DDI1_HPD"), 340 PINCTRL_PIN(65, "PANEL0_BKLTCTL"), 341 PINCTRL_PIN(66, "HV_DDI0_DDC_SDA"), 342 PINCTRL_PIN(67, "HV_DDI2_DDC_SCL"), 343 PINCTRL_PIN(68, "HV_DDI2_HPD"), 344 PINCTRL_PIN(69, "PANEL1_VDDEN"), 345 PINCTRL_PIN(70, "PANEL1_BKLTEN"), 346 PINCTRL_PIN(71, "HV_DDI0_DDC_SCL"), 347 PINCTRL_PIN(72, "PANEL0_VDDEN"), 348}; 349 350static const struct intel_padgroup north_gpps[] = { 351 INTEL_GPP(0, 0, 8, 0), 352 INTEL_GPP(1, 15, 27, 15), 353 INTEL_GPP(2, 30, 41, 30), 354 INTEL_GPP(3, 45, 56, 45), 355 INTEL_GPP(4, 60, 72, 60), 356}; 357 358/* 359 * North community can generate GPIO interrupts only for the first 8 360 * interrupts. The upper half (8-15) can only be used to trigger GPEs. 361 */ 362static const struct intel_community north_communities[] = { 363 CHV_COMMUNITY(north_gpps, 8, 0x92), 364}; 365 366static const struct intel_pinctrl_soc_data north_soc_data = { 367 .uid = "2", 368 .pins = north_pins, 369 .npins = ARRAY_SIZE(north_pins), 370 .communities = north_communities, 371 .ncommunities = ARRAY_SIZE(north_communities), 372}; 373 374static const struct pinctrl_pin_desc east_pins[] = { 375 PINCTRL_PIN(0, "PMU_SLP_S3_B"), 376 PINCTRL_PIN(1, "PMU_BATLOW_B"), 377 PINCTRL_PIN(2, "SUS_STAT_B"), 378 PINCTRL_PIN(3, "PMU_SLP_S0IX_B"), 379 PINCTRL_PIN(4, "PMU_AC_PRESENT"), 380 PINCTRL_PIN(5, "PMU_PLTRST_B"), 381 PINCTRL_PIN(6, "PMU_SUSCLK"), 382 PINCTRL_PIN(7, "PMU_SLP_LAN_B"), 383 PINCTRL_PIN(8, "PMU_PWRBTN_B"), 384 PINCTRL_PIN(9, "PMU_SLP_S4_B"), 385 PINCTRL_PIN(10, "PMU_WAKE_B"), 386 PINCTRL_PIN(11, "PMU_WAKE_LAN_B"), 387 388 PINCTRL_PIN(15, "MF_ISH_GPIO_3"), 389 PINCTRL_PIN(16, "MF_ISH_GPIO_7"), 390 PINCTRL_PIN(17, "MF_ISH_I2C1_SCL"), 391 PINCTRL_PIN(18, "MF_ISH_GPIO_1"), 392 PINCTRL_PIN(19, "MF_ISH_GPIO_5"), 393 PINCTRL_PIN(20, "MF_ISH_GPIO_9"), 394 PINCTRL_PIN(21, "MF_ISH_GPIO_0"), 395 PINCTRL_PIN(22, "MF_ISH_GPIO_4"), 396 PINCTRL_PIN(23, "MF_ISH_GPIO_8"), 397 PINCTRL_PIN(24, "MF_ISH_GPIO_2"), 398 PINCTRL_PIN(25, "MF_ISH_GPIO_6"), 399 PINCTRL_PIN(26, "MF_ISH_I2C1_SDA"), 400}; 401 402static const struct intel_padgroup east_gpps[] = { 403 INTEL_GPP(0, 0, 11, 0), 404 INTEL_GPP(1, 15, 26, 15), 405}; 406 407static const struct intel_community east_communities[] = { 408 CHV_COMMUNITY(east_gpps, 16, 0x93), 409}; 410 411static const struct intel_pinctrl_soc_data east_soc_data = { 412 .uid = "3", 413 .pins = east_pins, 414 .npins = ARRAY_SIZE(east_pins), 415 .communities = east_communities, 416 .ncommunities = ARRAY_SIZE(east_communities), 417}; 418 419static const struct pinctrl_pin_desc southeast_pins[] = { 420 PINCTRL_PIN(0, "MF_PLT_CLK0"), 421 PINCTRL_PIN(1, "PWM1"), 422 PINCTRL_PIN(2, "MF_PLT_CLK1"), 423 PINCTRL_PIN(3, "MF_PLT_CLK4"), 424 PINCTRL_PIN(4, "MF_PLT_CLK3"), 425 PINCTRL_PIN(5, "PWM0"), 426 PINCTRL_PIN(6, "MF_PLT_CLK5"), 427 PINCTRL_PIN(7, "MF_PLT_CLK2"), 428 429 PINCTRL_PIN(15, "SDMMC2_D3_CD_B"), 430 PINCTRL_PIN(16, "SDMMC1_CLK"), 431 PINCTRL_PIN(17, "SDMMC1_D0"), 432 PINCTRL_PIN(18, "SDMMC2_D1"), 433 PINCTRL_PIN(19, "SDMMC2_CLK"), 434 PINCTRL_PIN(20, "SDMMC1_D2"), 435 PINCTRL_PIN(21, "SDMMC2_D2"), 436 PINCTRL_PIN(22, "SDMMC2_CMD"), 437 PINCTRL_PIN(23, "SDMMC1_CMD"), 438 PINCTRL_PIN(24, "SDMMC1_D1"), 439 PINCTRL_PIN(25, "SDMMC2_D0"), 440 PINCTRL_PIN(26, "SDMMC1_D3_CD_B"), 441 442 PINCTRL_PIN(30, "SDMMC3_D1"), 443 PINCTRL_PIN(31, "SDMMC3_CLK"), 444 PINCTRL_PIN(32, "SDMMC3_D3"), 445 PINCTRL_PIN(33, "SDMMC3_D2"), 446 PINCTRL_PIN(34, "SDMMC3_CMD"), 447 PINCTRL_PIN(35, "SDMMC3_D0"), 448 449 PINCTRL_PIN(45, "MF_LPC_AD2"), 450 PINCTRL_PIN(46, "LPC_CLKRUNB"), 451 PINCTRL_PIN(47, "MF_LPC_AD0"), 452 PINCTRL_PIN(48, "LPC_FRAMEB"), 453 PINCTRL_PIN(49, "MF_LPC_CLKOUT1"), 454 PINCTRL_PIN(50, "MF_LPC_AD3"), 455 PINCTRL_PIN(51, "MF_LPC_CLKOUT0"), 456 PINCTRL_PIN(52, "MF_LPC_AD1"), 457 458 PINCTRL_PIN(60, "SPI1_MISO"), 459 PINCTRL_PIN(61, "SPI1_CSO_B"), 460 PINCTRL_PIN(62, "SPI1_CLK"), 461 PINCTRL_PIN(63, "MMC1_D6"), 462 PINCTRL_PIN(64, "SPI1_MOSI"), 463 PINCTRL_PIN(65, "MMC1_D5"), 464 PINCTRL_PIN(66, "SPI1_CS1_B"), 465 PINCTRL_PIN(67, "MMC1_D4_SD_WE"), 466 PINCTRL_PIN(68, "MMC1_D7"), 467 PINCTRL_PIN(69, "MMC1_RCLK"), 468 469 PINCTRL_PIN(75, "USB_OC1_B"), 470 PINCTRL_PIN(76, "PMU_RESETBUTTON_B"), 471 PINCTRL_PIN(77, "GPIO_ALERT"), 472 PINCTRL_PIN(78, "SDMMC3_PWR_EN_B"), 473 PINCTRL_PIN(79, "ILB_SERIRQ"), 474 PINCTRL_PIN(80, "USB_OC0_B"), 475 PINCTRL_PIN(81, "SDMMC3_CD_B"), 476 PINCTRL_PIN(82, "SPKR"), 477 PINCTRL_PIN(83, "SUSPWRDNACK"), 478 PINCTRL_PIN(84, "SPARE_PIN"), 479 PINCTRL_PIN(85, "SDMMC3_1P8_EN"), 480}; 481 482static const unsigned southeast_pwm0_pins[] = { 5 }; 483static const unsigned southeast_pwm1_pins[] = { 1 }; 484static const unsigned southeast_sdmmc1_pins[] = { 485 16, 17, 20, 23, 24, 26, 63, 65, 67, 68, 69, 486}; 487static const unsigned southeast_sdmmc2_pins[] = { 15, 18, 19, 21, 22, 25 }; 488static const unsigned southeast_sdmmc3_pins[] = { 489 30, 31, 32, 33, 34, 35, 78, 81, 85, 490}; 491static const unsigned southeast_spi1_pins[] = { 60, 61, 62, 64, 66 }; 492static const unsigned southeast_spi2_pins[] = { 2, 3, 4, 6, 7 }; 493 494static const struct intel_pingroup southeast_groups[] = { 495 PIN_GROUP("pwm0_grp", southeast_pwm0_pins, PINMODE(1, 0)), 496 PIN_GROUP("pwm1_grp", southeast_pwm1_pins, PINMODE(1, 0)), 497 PIN_GROUP("sdmmc1_grp", southeast_sdmmc1_pins, PINMODE(1, 0)), 498 PIN_GROUP("sdmmc2_grp", southeast_sdmmc2_pins, PINMODE(1, 0)), 499 PIN_GROUP("sdmmc3_grp", southeast_sdmmc3_pins, PINMODE(1, 0)), 500 PIN_GROUP("spi1_grp", southeast_spi1_pins, PINMODE(1, 0)), 501 PIN_GROUP("spi2_grp", southeast_spi2_pins, PINMODE(4, 0)), 502}; 503 504static const char * const southeast_pwm0_groups[] = { "pwm0_grp" }; 505static const char * const southeast_pwm1_groups[] = { "pwm1_grp" }; 506static const char * const southeast_sdmmc1_groups[] = { "sdmmc1_grp" }; 507static const char * const southeast_sdmmc2_groups[] = { "sdmmc2_grp" }; 508static const char * const southeast_sdmmc3_groups[] = { "sdmmc3_grp" }; 509static const char * const southeast_spi1_groups[] = { "spi1_grp" }; 510static const char * const southeast_spi2_groups[] = { "spi2_grp" }; 511 512static const struct intel_function southeast_functions[] = { 513 FUNCTION("pwm0", southeast_pwm0_groups), 514 FUNCTION("pwm1", southeast_pwm1_groups), 515 FUNCTION("sdmmc1", southeast_sdmmc1_groups), 516 FUNCTION("sdmmc2", southeast_sdmmc2_groups), 517 FUNCTION("sdmmc3", southeast_sdmmc3_groups), 518 FUNCTION("spi1", southeast_spi1_groups), 519 FUNCTION("spi2", southeast_spi2_groups), 520}; 521 522static const struct intel_padgroup southeast_gpps[] = { 523 INTEL_GPP(0, 0, 7, 0), 524 INTEL_GPP(1, 15, 26, 15), 525 INTEL_GPP(2, 30, 35, 30), 526 INTEL_GPP(3, 45, 52, 45), 527 INTEL_GPP(4, 60, 69, 60), 528 INTEL_GPP(5, 75, 85, 75), 529}; 530 531static const struct intel_community southeast_communities[] = { 532 CHV_COMMUNITY(southeast_gpps, 16, 0x94), 533}; 534 535static const struct intel_pinctrl_soc_data southeast_soc_data = { 536 .uid = "4", 537 .pins = southeast_pins, 538 .npins = ARRAY_SIZE(southeast_pins), 539 .groups = southeast_groups, 540 .ngroups = ARRAY_SIZE(southeast_groups), 541 .functions = southeast_functions, 542 .nfunctions = ARRAY_SIZE(southeast_functions), 543 .communities = southeast_communities, 544 .ncommunities = ARRAY_SIZE(southeast_communities), 545}; 546 547static const struct intel_pinctrl_soc_data *chv_soc_data[] = { 548 &southwest_soc_data, 549 &north_soc_data, 550 &east_soc_data, 551 &southeast_soc_data, 552 NULL 553}; 554 555/* 556 * Lock to serialize register accesses 557 * 558 * Due to a silicon issue, a shared lock must be used to prevent 559 * concurrent accesses across the 4 GPIO controllers. 560 * 561 * See Intel Atom Z8000 Processor Series Specification Update (Rev. 005), 562 * errata #CHT34, for further information. 563 */ 564static DEFINE_RAW_SPINLOCK(chv_lock); 565 566static u32 chv_pctrl_readl(struct intel_pinctrl *pctrl, unsigned int offset) 567{ 568 const struct intel_community *community = &pctrl->communities[0]; 569 570 return readl(community->regs + offset); 571} 572 573static void chv_pctrl_writel(struct intel_pinctrl *pctrl, unsigned int offset, u32 value) 574{ 575 const struct intel_community *community = &pctrl->communities[0]; 576 void __iomem *reg = community->regs + offset; 577 578 /* Write and simple read back to confirm the bus transferring done */ 579 writel(value, reg); 580 readl(reg); 581} 582 583static void __iomem *chv_padreg(struct intel_pinctrl *pctrl, unsigned int offset, 584 unsigned int reg) 585{ 586 const struct intel_community *community = &pctrl->communities[0]; 587 unsigned int family_no = offset / MAX_FAMILY_PAD_GPIO_NO; 588 unsigned int pad_no = offset % MAX_FAMILY_PAD_GPIO_NO; 589 590 offset = FAMILY_PAD_REGS_SIZE * family_no + GPIO_REGS_SIZE * pad_no; 591 592 return community->pad_regs + offset + reg; 593} 594 595static u32 chv_readl(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset) 596{ 597 return readl(chv_padreg(pctrl, pin, offset)); 598} 599 600static void chv_writel(struct intel_pinctrl *pctrl, unsigned int pin, unsigned int offset, u32 value) 601{ 602 void __iomem *reg = chv_padreg(pctrl, pin, offset); 603 604 /* Write and simple read back to confirm the bus transferring done */ 605 writel(value, reg); 606 readl(reg); 607} 608 609/* When Pad Cfg is locked, driver can only change GPIOTXState or GPIORXState */ 610static bool chv_pad_is_locked(u32 ctrl1) 611{ 612 return ctrl1 & CHV_PADCTRL1_CFGLOCK; 613} 614 615static bool chv_pad_locked(struct intel_pinctrl *pctrl, unsigned int offset) 616{ 617 return chv_pad_is_locked(chv_readl(pctrl, offset, CHV_PADCTRL1)); 618} 619 620static void chv_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, 621 unsigned int offset) 622{ 623 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 624 u32 ctrl0, ctrl1; 625 626 scoped_guard(raw_spinlock_irqsave, &chv_lock) { 627 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 628 ctrl1 = chv_readl(pctrl, offset, CHV_PADCTRL1); 629 } 630 631 if (ctrl0 & CHV_PADCTRL0_GPIOEN) { 632 seq_puts(s, "GPIO "); 633 } else { 634 u32 mode; 635 636 mode = ctrl0 & CHV_PADCTRL0_PMODE_MASK; 637 mode >>= CHV_PADCTRL0_PMODE_SHIFT; 638 639 seq_printf(s, "mode %d ", mode); 640 } 641 642 seq_printf(s, "0x%08x 0x%08x", ctrl0, ctrl1); 643 644 if (chv_pad_is_locked(ctrl1)) 645 seq_puts(s, " [LOCKED]"); 646} 647 648static const struct pinctrl_ops chv_pinctrl_ops = { 649 .get_groups_count = intel_get_groups_count, 650 .get_group_name = intel_get_group_name, 651 .get_group_pins = intel_get_group_pins, 652 .pin_dbg_show = chv_pin_dbg_show, 653}; 654 655static int chv_pinmux_set_mux(struct pinctrl_dev *pctldev, 656 unsigned int function, unsigned int group) 657{ 658 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 659 struct device *dev = pctrl->dev; 660 const struct intel_pingroup *grp; 661 int i; 662 663 grp = &pctrl->soc->groups[group]; 664 665 guard(raw_spinlock_irqsave)(&chv_lock); 666 667 /* Check first that the pad is not locked */ 668 for (i = 0; i < grp->grp.npins; i++) { 669 if (chv_pad_locked(pctrl, grp->grp.pins[i])) { 670 dev_warn(dev, "unable to set mode for locked pin %u\n", grp->grp.pins[i]); 671 return -EBUSY; 672 } 673 } 674 675 for (i = 0; i < grp->grp.npins; i++) { 676 int pin = grp->grp.pins[i]; 677 unsigned int mode; 678 bool invert_oe; 679 u32 value; 680 681 /* Check if there is pin-specific config */ 682 if (grp->modes) 683 mode = grp->modes[i]; 684 else 685 mode = grp->mode; 686 687 /* Extract OE inversion */ 688 invert_oe = mode & PINMODE_INVERT_OE; 689 mode &= ~PINMODE_INVERT_OE; 690 691 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 692 /* Disable GPIO mode */ 693 value &= ~CHV_PADCTRL0_GPIOEN; 694 /* Set to desired mode */ 695 value &= ~CHV_PADCTRL0_PMODE_MASK; 696 value |= mode << CHV_PADCTRL0_PMODE_SHIFT; 697 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 698 699 /* Update for invert_oe */ 700 value = chv_readl(pctrl, pin, CHV_PADCTRL1) & ~CHV_PADCTRL1_INVRXTX_MASK; 701 if (invert_oe) 702 value |= CHV_PADCTRL1_INVRXTX_TXENABLE; 703 chv_writel(pctrl, pin, CHV_PADCTRL1, value); 704 705 dev_dbg(dev, "configured pin %u mode %u OE %sinverted\n", pin, mode, 706 invert_oe ? "" : "not "); 707 } 708 709 return 0; 710} 711 712static void chv_gpio_clear_triggering(struct intel_pinctrl *pctrl, 713 unsigned int offset) 714{ 715 u32 invrxtx_mask = CHV_PADCTRL1_INVRXTX_MASK; 716 u32 value; 717 718 /* 719 * One some devices the GPIO should output the inverted value from what 720 * device-drivers / ACPI code expects (inverted external buffer?). The 721 * BIOS makes this work by setting the CHV_PADCTRL1_INVRXTX_TXDATA flag, 722 * preserve this flag if the pin is already setup as GPIO. 723 */ 724 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 725 if (value & CHV_PADCTRL0_GPIOEN) 726 invrxtx_mask &= ~CHV_PADCTRL1_INVRXTX_TXDATA; 727 728 value = chv_readl(pctrl, offset, CHV_PADCTRL1); 729 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 730 value &= ~invrxtx_mask; 731 chv_writel(pctrl, offset, CHV_PADCTRL1, value); 732} 733 734static int chv_gpio_request_enable(struct pinctrl_dev *pctldev, 735 struct pinctrl_gpio_range *range, 736 unsigned int offset) 737{ 738 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 739 u32 value; 740 741 guard(raw_spinlock_irqsave)(&chv_lock); 742 743 if (chv_pad_locked(pctrl, offset)) { 744 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 745 if (!(value & CHV_PADCTRL0_GPIOEN)) { 746 /* Locked so cannot enable */ 747 return -EBUSY; 748 } 749 } else { 750 struct intel_community_context *cctx = &pctrl->context.communities[0]; 751 int i; 752 753 /* Reset the interrupt mapping */ 754 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) { 755 if (cctx->intr_lines[i] == offset) { 756 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 757 break; 758 } 759 } 760 761 /* Disable interrupt generation */ 762 chv_gpio_clear_triggering(pctrl, offset); 763 764 value = chv_readl(pctrl, offset, CHV_PADCTRL0); 765 766 /* 767 * If the pin is in HiZ mode (both TX and RX buffers are 768 * disabled) we turn it to be input now. 769 */ 770 if ((value & CHV_PADCTRL0_GPIOCFG_MASK) == 771 (CHV_PADCTRL0_GPIOCFG_HIZ << CHV_PADCTRL0_GPIOCFG_SHIFT)) { 772 value &= ~CHV_PADCTRL0_GPIOCFG_MASK; 773 value |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 774 } 775 776 /* Switch to a GPIO mode */ 777 value |= CHV_PADCTRL0_GPIOEN; 778 chv_writel(pctrl, offset, CHV_PADCTRL0, value); 779 } 780 781 return 0; 782} 783 784static void chv_gpio_disable_free(struct pinctrl_dev *pctldev, 785 struct pinctrl_gpio_range *range, 786 unsigned int offset) 787{ 788 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 789 790 guard(raw_spinlock_irqsave)(&chv_lock); 791 792 if (chv_pad_locked(pctrl, offset)) 793 return; 794 795 chv_gpio_clear_triggering(pctrl, offset); 796} 797 798static int chv_gpio_set_direction(struct pinctrl_dev *pctldev, 799 struct pinctrl_gpio_range *range, 800 unsigned int offset, bool input) 801{ 802 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 803 u32 ctrl0; 804 805 guard(raw_spinlock_irqsave)(&chv_lock); 806 807 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0) & ~CHV_PADCTRL0_GPIOCFG_MASK; 808 if (input) 809 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPI << CHV_PADCTRL0_GPIOCFG_SHIFT; 810 else 811 ctrl0 |= CHV_PADCTRL0_GPIOCFG_GPO << CHV_PADCTRL0_GPIOCFG_SHIFT; 812 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 813 814 return 0; 815} 816 817static const struct pinmux_ops chv_pinmux_ops = { 818 .get_functions_count = intel_get_functions_count, 819 .get_function_name = intel_get_function_name, 820 .get_function_groups = intel_get_function_groups, 821 .set_mux = chv_pinmux_set_mux, 822 .gpio_request_enable = chv_gpio_request_enable, 823 .gpio_disable_free = chv_gpio_disable_free, 824 .gpio_set_direction = chv_gpio_set_direction, 825}; 826 827static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin, 828 unsigned long *config) 829{ 830 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 831 enum pin_config_param param = pinconf_to_config_param(*config); 832 u32 ctrl0, ctrl1; 833 u16 arg = 0; 834 u32 term; 835 836 scoped_guard(raw_spinlock_irqsave, &chv_lock) { 837 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 838 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 839 } 840 841 term = (ctrl0 & CHV_PADCTRL0_TERM_MASK) >> CHV_PADCTRL0_TERM_SHIFT; 842 843 switch (param) { 844 case PIN_CONFIG_BIAS_DISABLE: 845 if (term) 846 return -EINVAL; 847 break; 848 849 case PIN_CONFIG_BIAS_PULL_UP: 850 if (!(ctrl0 & CHV_PADCTRL0_TERM_UP)) 851 return -EINVAL; 852 853 switch (term) { 854 case CHV_PADCTRL0_TERM_20K: 855 arg = 20000; 856 break; 857 case CHV_PADCTRL0_TERM_5K: 858 arg = 5000; 859 break; 860 case CHV_PADCTRL0_TERM_1K: 861 arg = 1000; 862 break; 863 } 864 865 break; 866 867 case PIN_CONFIG_BIAS_PULL_DOWN: 868 if (!term || (ctrl0 & CHV_PADCTRL0_TERM_UP)) 869 return -EINVAL; 870 871 switch (term) { 872 case CHV_PADCTRL0_TERM_20K: 873 arg = 20000; 874 break; 875 case CHV_PADCTRL0_TERM_5K: 876 arg = 5000; 877 break; 878 } 879 880 break; 881 882 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: { 883 u32 cfg; 884 885 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 886 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 887 if (cfg != CHV_PADCTRL0_GPIOCFG_HIZ) 888 return -EINVAL; 889 890 break; 891 } 892 893 case PIN_CONFIG_DRIVE_PUSH_PULL: 894 if (ctrl1 & CHV_PADCTRL1_ODEN) 895 return -EINVAL; 896 break; 897 898 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 899 if (!(ctrl1 & CHV_PADCTRL1_ODEN)) 900 return -EINVAL; 901 break; 902 903 default: 904 return -ENOTSUPP; 905 } 906 907 *config = pinconf_to_config_packed(param, arg); 908 return 0; 909} 910 911static int chv_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin, 912 enum pin_config_param param, u32 arg) 913{ 914 u32 ctrl0, pull; 915 916 guard(raw_spinlock_irqsave)(&chv_lock); 917 918 ctrl0 = chv_readl(pctrl, pin, CHV_PADCTRL0); 919 920 switch (param) { 921 case PIN_CONFIG_BIAS_DISABLE: 922 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 923 break; 924 925 case PIN_CONFIG_BIAS_PULL_UP: 926 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 927 928 switch (arg) { 929 case 1000: 930 /* For 1k there is only pull up */ 931 pull = CHV_PADCTRL0_TERM_1K << CHV_PADCTRL0_TERM_SHIFT; 932 break; 933 case 5000: 934 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 935 break; 936 case 20000: 937 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 938 break; 939 default: 940 return -EINVAL; 941 } 942 943 ctrl0 |= CHV_PADCTRL0_TERM_UP | pull; 944 break; 945 946 case PIN_CONFIG_BIAS_PULL_DOWN: 947 ctrl0 &= ~(CHV_PADCTRL0_TERM_MASK | CHV_PADCTRL0_TERM_UP); 948 949 switch (arg) { 950 case 5000: 951 pull = CHV_PADCTRL0_TERM_5K << CHV_PADCTRL0_TERM_SHIFT; 952 break; 953 case 20000: 954 pull = CHV_PADCTRL0_TERM_20K << CHV_PADCTRL0_TERM_SHIFT; 955 break; 956 default: 957 return -EINVAL; 958 } 959 960 ctrl0 |= pull; 961 break; 962 963 default: 964 return -EINVAL; 965 } 966 967 chv_writel(pctrl, pin, CHV_PADCTRL0, ctrl0); 968 969 return 0; 970} 971 972static int chv_config_set_oden(struct intel_pinctrl *pctrl, unsigned int pin, 973 bool enable) 974{ 975 u32 ctrl1; 976 977 guard(raw_spinlock_irqsave)(&chv_lock); 978 979 ctrl1 = chv_readl(pctrl, pin, CHV_PADCTRL1); 980 981 if (enable) 982 ctrl1 |= CHV_PADCTRL1_ODEN; 983 else 984 ctrl1 &= ~CHV_PADCTRL1_ODEN; 985 986 chv_writel(pctrl, pin, CHV_PADCTRL1, ctrl1); 987 988 return 0; 989} 990 991static int chv_config_set(struct pinctrl_dev *pctldev, unsigned int pin, 992 unsigned long *configs, unsigned int nconfigs) 993{ 994 struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); 995 struct device *dev = pctrl->dev; 996 enum pin_config_param param; 997 int i, ret; 998 u32 arg; 999 1000 if (chv_pad_locked(pctrl, pin)) 1001 return -EBUSY; 1002 1003 for (i = 0; i < nconfigs; i++) { 1004 param = pinconf_to_config_param(configs[i]); 1005 arg = pinconf_to_config_argument(configs[i]); 1006 1007 switch (param) { 1008 case PIN_CONFIG_BIAS_DISABLE: 1009 case PIN_CONFIG_BIAS_PULL_UP: 1010 case PIN_CONFIG_BIAS_PULL_DOWN: 1011 ret = chv_config_set_pull(pctrl, pin, param, arg); 1012 if (ret) 1013 return ret; 1014 break; 1015 1016 case PIN_CONFIG_DRIVE_PUSH_PULL: 1017 ret = chv_config_set_oden(pctrl, pin, false); 1018 if (ret) 1019 return ret; 1020 break; 1021 1022 case PIN_CONFIG_DRIVE_OPEN_DRAIN: 1023 ret = chv_config_set_oden(pctrl, pin, true); 1024 if (ret) 1025 return ret; 1026 break; 1027 1028 default: 1029 return -ENOTSUPP; 1030 } 1031 1032 dev_dbg(dev, "pin %d set config %d arg %u\n", pin, param, arg); 1033 } 1034 1035 return 0; 1036} 1037 1038static int chv_config_group_get(struct pinctrl_dev *pctldev, 1039 unsigned int group, 1040 unsigned long *config) 1041{ 1042 const unsigned int *pins; 1043 unsigned int npins; 1044 int ret; 1045 1046 ret = intel_get_group_pins(pctldev, group, &pins, &npins); 1047 if (ret) 1048 return ret; 1049 1050 ret = chv_config_get(pctldev, pins[0], config); 1051 if (ret) 1052 return ret; 1053 1054 return 0; 1055} 1056 1057static int chv_config_group_set(struct pinctrl_dev *pctldev, 1058 unsigned int group, unsigned long *configs, 1059 unsigned int num_configs) 1060{ 1061 const unsigned int *pins; 1062 unsigned int npins; 1063 int i, ret; 1064 1065 ret = intel_get_group_pins(pctldev, group, &pins, &npins); 1066 if (ret) 1067 return ret; 1068 1069 for (i = 0; i < npins; i++) { 1070 ret = chv_config_set(pctldev, pins[i], configs, num_configs); 1071 if (ret) 1072 return ret; 1073 } 1074 1075 return 0; 1076} 1077 1078static const struct pinconf_ops chv_pinconf_ops = { 1079 .is_generic = true, 1080 .pin_config_set = chv_config_set, 1081 .pin_config_get = chv_config_get, 1082 .pin_config_group_get = chv_config_group_get, 1083 .pin_config_group_set = chv_config_group_set, 1084}; 1085 1086static struct pinctrl_desc chv_pinctrl_desc = { 1087 .pctlops = &chv_pinctrl_ops, 1088 .pmxops = &chv_pinmux_ops, 1089 .confops = &chv_pinconf_ops, 1090 .owner = THIS_MODULE, 1091}; 1092 1093static int chv_gpio_get(struct gpio_chip *chip, unsigned int offset) 1094{ 1095 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1096 u32 ctrl0, cfg; 1097 1098 scoped_guard(raw_spinlock_irqsave, &chv_lock) 1099 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1100 1101 cfg = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1102 cfg >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1103 1104 if (cfg == CHV_PADCTRL0_GPIOCFG_GPO) 1105 return !!(ctrl0 & CHV_PADCTRL0_GPIOTXSTATE); 1106 return !!(ctrl0 & CHV_PADCTRL0_GPIORXSTATE); 1107} 1108 1109static int chv_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 1110{ 1111 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1112 u32 ctrl0; 1113 1114 guard(raw_spinlock_irqsave)(&chv_lock); 1115 1116 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1117 1118 if (value) 1119 ctrl0 |= CHV_PADCTRL0_GPIOTXSTATE; 1120 else 1121 ctrl0 &= ~CHV_PADCTRL0_GPIOTXSTATE; 1122 1123 chv_writel(pctrl, offset, CHV_PADCTRL0, ctrl0); 1124 1125 return 0; 1126} 1127 1128static int chv_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 1129{ 1130 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1131 u32 ctrl0, direction; 1132 1133 scoped_guard(raw_spinlock_irqsave, &chv_lock) 1134 ctrl0 = chv_readl(pctrl, offset, CHV_PADCTRL0); 1135 1136 direction = ctrl0 & CHV_PADCTRL0_GPIOCFG_MASK; 1137 direction >>= CHV_PADCTRL0_GPIOCFG_SHIFT; 1138 1139 if (direction == CHV_PADCTRL0_GPIOCFG_GPO) 1140 return GPIO_LINE_DIRECTION_OUT; 1141 1142 return GPIO_LINE_DIRECTION_IN; 1143} 1144 1145static int chv_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) 1146{ 1147 return pinctrl_gpio_direction_input(chip, offset); 1148} 1149 1150static int chv_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, 1151 int value) 1152{ 1153 chv_gpio_set(chip, offset, value); 1154 return pinctrl_gpio_direction_output(chip, offset); 1155} 1156 1157static const struct gpio_chip chv_gpio_chip = { 1158 .owner = THIS_MODULE, 1159 .request = gpiochip_generic_request, 1160 .free = gpiochip_generic_free, 1161 .get_direction = chv_gpio_get_direction, 1162 .direction_input = chv_gpio_direction_input, 1163 .direction_output = chv_gpio_direction_output, 1164 .get = chv_gpio_get, 1165 .set = chv_gpio_set, 1166}; 1167 1168static void chv_gpio_irq_ack(struct irq_data *d) 1169{ 1170 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1171 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1172 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1173 u32 intr_line; 1174 1175 guard(raw_spinlock)(&chv_lock); 1176 1177 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1178 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1179 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1180 chv_pctrl_writel(pctrl, CHV_INTSTAT, BIT(intr_line)); 1181} 1182 1183static void chv_gpio_irq_mask_unmask(struct gpio_chip *gc, irq_hw_number_t hwirq, bool mask) 1184{ 1185 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1186 u32 value, intr_line; 1187 1188 guard(raw_spinlock_irqsave)(&chv_lock); 1189 1190 intr_line = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1191 intr_line &= CHV_PADCTRL0_INTSEL_MASK; 1192 intr_line >>= CHV_PADCTRL0_INTSEL_SHIFT; 1193 1194 value = chv_pctrl_readl(pctrl, CHV_INTMASK); 1195 if (mask) 1196 value &= ~BIT(intr_line); 1197 else 1198 value |= BIT(intr_line); 1199 chv_pctrl_writel(pctrl, CHV_INTMASK, value); 1200} 1201 1202static void chv_gpio_irq_mask(struct irq_data *d) 1203{ 1204 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1205 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1206 1207 chv_gpio_irq_mask_unmask(gc, hwirq, true); 1208 gpiochip_disable_irq(gc, hwirq); 1209} 1210 1211static void chv_gpio_irq_unmask(struct irq_data *d) 1212{ 1213 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1214 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1215 1216 gpiochip_enable_irq(gc, hwirq); 1217 chv_gpio_irq_mask_unmask(gc, hwirq, false); 1218} 1219 1220static unsigned chv_gpio_irq_startup(struct irq_data *d) 1221{ 1222 /* 1223 * Check if the interrupt has been requested with 0 as triggering 1224 * type. If not, bail out, ... 1225 */ 1226 if (irqd_get_trigger_type(d) != IRQ_TYPE_NONE) { 1227 chv_gpio_irq_unmask(d); 1228 return 0; 1229 } 1230 1231 /* 1232 * ...otherwise it is assumed that the current values 1233 * programmed to the hardware are used (e.g BIOS configured 1234 * defaults). 1235 * 1236 * In that case ->irq_set_type() will never be called so we need to 1237 * read back the values from hardware now, set correct flow handler 1238 * and update mappings before the interrupt is being used. 1239 */ 1240 scoped_guard(raw_spinlock_irqsave, &chv_lock) { 1241 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1242 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1243 struct device *dev = pctrl->dev; 1244 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1245 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1246 irq_flow_handler_t handler; 1247 u32 intsel, value; 1248 1249 intsel = chv_readl(pctrl, hwirq, CHV_PADCTRL0); 1250 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1251 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1252 1253 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1254 if (value & CHV_PADCTRL1_INTWAKECFG_LEVEL) 1255 handler = handle_level_irq; 1256 else 1257 handler = handle_edge_irq; 1258 1259 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1260 irq_set_handler_locked(d, handler); 1261 dev_dbg(dev, "using interrupt line %u for IRQ_TYPE_NONE on pin %lu\n", 1262 intsel, hwirq); 1263 cctx->intr_lines[intsel] = hwirq; 1264 } 1265 } 1266 1267 chv_gpio_irq_unmask(d); 1268 return 0; 1269} 1270 1271static int chv_gpio_set_intr_line(struct intel_pinctrl *pctrl, unsigned int pin) 1272{ 1273 struct device *dev = pctrl->dev; 1274 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1275 const struct intel_community *community = &pctrl->communities[0]; 1276 u32 value, intsel; 1277 int i; 1278 1279 value = chv_readl(pctrl, pin, CHV_PADCTRL0); 1280 intsel = (value & CHV_PADCTRL0_INTSEL_MASK) >> CHV_PADCTRL0_INTSEL_SHIFT; 1281 1282 if (cctx->intr_lines[intsel] == pin) 1283 return 0; 1284 1285 if (cctx->intr_lines[intsel] == CHV_INVALID_HWIRQ) { 1286 dev_dbg(dev, "using interrupt line %u for pin %u\n", intsel, pin); 1287 cctx->intr_lines[intsel] = pin; 1288 return 0; 1289 } 1290 1291 /* 1292 * The interrupt line selected by the BIOS is already in use by 1293 * another pin, this is a known BIOS bug found on several models. 1294 * But this may also be caused by Linux deciding to use a pin as 1295 * IRQ which was not expected to be used as such by the BIOS authors, 1296 * so log this at info level only. 1297 */ 1298 dev_info(dev, "interrupt line %u is used by both pin %u and pin %u\n", intsel, 1299 cctx->intr_lines[intsel], pin); 1300 1301 if (chv_pad_locked(pctrl, pin)) 1302 return -EBUSY; 1303 1304 /* 1305 * The BIOS fills the interrupt lines from 0 counting up, start at 1306 * the other end to find a free interrupt line to workaround this. 1307 */ 1308 for (i = community->nirqs - 1; i >= 0; i--) { 1309 if (cctx->intr_lines[i] == CHV_INVALID_HWIRQ) 1310 break; 1311 } 1312 if (i < 0) 1313 return -EBUSY; 1314 1315 dev_info(dev, "changing the interrupt line for pin %u to %d\n", pin, i); 1316 1317 value = (value & ~CHV_PADCTRL0_INTSEL_MASK) | (i << CHV_PADCTRL0_INTSEL_SHIFT); 1318 chv_writel(pctrl, pin, CHV_PADCTRL0, value); 1319 cctx->intr_lines[i] = pin; 1320 1321 return 0; 1322} 1323 1324static int chv_gpio_irq_type(struct irq_data *d, unsigned int type) 1325{ 1326 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 1327 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1328 irq_hw_number_t hwirq = irqd_to_hwirq(d); 1329 u32 value; 1330 int ret; 1331 1332 guard(raw_spinlock_irqsave)(&chv_lock); 1333 1334 ret = chv_gpio_set_intr_line(pctrl, hwirq); 1335 if (ret) 1336 return ret; 1337 1338 /* 1339 * Pins which can be used as shared interrupt are configured in 1340 * BIOS. Driver trusts BIOS configurations and assigns different 1341 * handler according to the irq type. 1342 * 1343 * Driver needs to save the mapping between each pin and 1344 * its interrupt line. 1345 * 1. If the pin cfg is locked in BIOS: 1346 * Trust BIOS has programmed IntWakeCfg bits correctly, 1347 * driver just needs to save the mapping. 1348 * 2. If the pin cfg is not locked in BIOS: 1349 * Driver programs the IntWakeCfg bits and save the mapping. 1350 */ 1351 if (!chv_pad_locked(pctrl, hwirq)) { 1352 value = chv_readl(pctrl, hwirq, CHV_PADCTRL1); 1353 value &= ~CHV_PADCTRL1_INTWAKECFG_MASK; 1354 value &= ~CHV_PADCTRL1_INVRXTX_MASK; 1355 1356 if (type & IRQ_TYPE_EDGE_BOTH) { 1357 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) 1358 value |= CHV_PADCTRL1_INTWAKECFG_BOTH; 1359 else if (type & IRQ_TYPE_EDGE_RISING) 1360 value |= CHV_PADCTRL1_INTWAKECFG_RISING; 1361 else if (type & IRQ_TYPE_EDGE_FALLING) 1362 value |= CHV_PADCTRL1_INTWAKECFG_FALLING; 1363 } else if (type & IRQ_TYPE_LEVEL_MASK) { 1364 value |= CHV_PADCTRL1_INTWAKECFG_LEVEL; 1365 if (type & IRQ_TYPE_LEVEL_LOW) 1366 value |= CHV_PADCTRL1_INVRXTX_RXDATA; 1367 } 1368 1369 chv_writel(pctrl, hwirq, CHV_PADCTRL1, value); 1370 } 1371 1372 if (type & IRQ_TYPE_EDGE_BOTH) 1373 irq_set_handler_locked(d, handle_edge_irq); 1374 else if (type & IRQ_TYPE_LEVEL_MASK) 1375 irq_set_handler_locked(d, handle_level_irq); 1376 1377 return 0; 1378} 1379 1380static const struct irq_chip chv_gpio_irq_chip = { 1381 .name = "chv-gpio", 1382 .irq_startup = chv_gpio_irq_startup, 1383 .irq_ack = chv_gpio_irq_ack, 1384 .irq_mask = chv_gpio_irq_mask, 1385 .irq_unmask = chv_gpio_irq_unmask, 1386 .irq_set_type = chv_gpio_irq_type, 1387 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 1388 GPIOCHIP_IRQ_RESOURCE_HELPERS, 1389}; 1390 1391static void chv_gpio_irq_handler(struct irq_desc *desc) 1392{ 1393 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 1394 struct intel_pinctrl *pctrl = gpiochip_get_data(gc); 1395 struct device *dev = pctrl->dev; 1396 const struct intel_community *community = &pctrl->communities[0]; 1397 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1398 struct irq_chip *chip = irq_desc_get_chip(desc); 1399 unsigned long pending; 1400 u32 intr_line; 1401 1402 chained_irq_enter(chip, desc); 1403 1404 scoped_guard(raw_spinlock_irqsave, &chv_lock) 1405 pending = chv_pctrl_readl(pctrl, CHV_INTSTAT); 1406 1407 for_each_set_bit(intr_line, &pending, community->nirqs) { 1408 unsigned int offset; 1409 1410 offset = cctx->intr_lines[intr_line]; 1411 if (offset == CHV_INVALID_HWIRQ) { 1412 dev_warn_once(dev, "interrupt on unmapped interrupt line %u\n", intr_line); 1413 /* Some boards expect hwirq 0 to trigger in this case */ 1414 offset = 0; 1415 } 1416 1417 generic_handle_domain_irq(gc->irq.domain, offset); 1418 } 1419 1420 chained_irq_exit(chip, desc); 1421} 1422 1423/* 1424 * Certain machines seem to hardcode Linux IRQ numbers in their ACPI 1425 * tables. Since we leave GPIOs that are not capable of generating 1426 * interrupts out of the irqdomain the numbering will be different and 1427 * cause devices using the hardcoded IRQ numbers fail. In order not to 1428 * break such machines we will only mask pins from irqdomain if the machine 1429 * is not listed below. 1430 */ 1431static const struct dmi_system_id chv_no_valid_mask[] = { 1432 /* See https://bugzilla.kernel.org/show_bug.cgi?id=194945 */ 1433 { 1434 .ident = "Intel_Strago based Chromebooks (All models)", 1435 .matches = { 1436 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1437 DMI_MATCH(DMI_PRODUCT_FAMILY, "Intel_Strago"), 1438 }, 1439 }, 1440 { 1441 .ident = "HP Chromebook 11 G5 (Setzer)", 1442 .matches = { 1443 DMI_MATCH(DMI_SYS_VENDOR, "HP"), 1444 DMI_MATCH(DMI_PRODUCT_NAME, "Setzer"), 1445 }, 1446 }, 1447 { 1448 .ident = "Acer Chromebook R11 (Cyan)", 1449 .matches = { 1450 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1451 DMI_MATCH(DMI_PRODUCT_NAME, "Cyan"), 1452 }, 1453 }, 1454 { 1455 .ident = "Samsung Chromebook 3 (Celes)", 1456 .matches = { 1457 DMI_MATCH(DMI_SYS_VENDOR, "GOOGLE"), 1458 DMI_MATCH(DMI_PRODUCT_NAME, "Celes"), 1459 }, 1460 }, 1461 {} 1462}; 1463 1464static void chv_init_irq_valid_mask(struct gpio_chip *chip, 1465 unsigned long *valid_mask, 1466 unsigned int ngpios) 1467{ 1468 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1469 const struct intel_community *community = &pctrl->communities[0]; 1470 int i; 1471 1472 /* Do not add GPIOs that can only generate GPEs to the IRQ domain */ 1473 for (i = 0; i < pctrl->soc->npins; i++) { 1474 const struct pinctrl_pin_desc *desc; 1475 u32 intsel; 1476 1477 desc = &pctrl->soc->pins[i]; 1478 1479 intsel = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1480 intsel &= CHV_PADCTRL0_INTSEL_MASK; 1481 intsel >>= CHV_PADCTRL0_INTSEL_SHIFT; 1482 1483 if (intsel >= community->nirqs) 1484 clear_bit(desc->number, valid_mask); 1485 } 1486} 1487 1488static int chv_gpio_irq_init_hw(struct gpio_chip *chip) 1489{ 1490 struct intel_pinctrl *pctrl = gpiochip_get_data(chip); 1491 const struct intel_community *community = &pctrl->communities[0]; 1492 1493 /* 1494 * The same set of machines in chv_no_valid_mask[] have incorrectly 1495 * configured GPIOs that generate spurious interrupts so we use 1496 * this same list to apply another quirk for them. 1497 * 1498 * See also https://bugzilla.kernel.org/show_bug.cgi?id=197953. 1499 */ 1500 if (!pctrl->chip.irq.init_valid_mask) { 1501 /* 1502 * Mask all interrupts the community is able to generate 1503 * but leave the ones that can only generate GPEs unmasked. 1504 */ 1505 chv_pctrl_writel(pctrl, CHV_INTMASK, GENMASK(31, community->nirqs)); 1506 } 1507 1508 /* Clear all interrupts */ 1509 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1510 1511 return 0; 1512} 1513 1514static int chv_gpio_probe(struct intel_pinctrl *pctrl, int irq) 1515{ 1516 const struct intel_community *community = &pctrl->communities[0]; 1517 const struct intel_padgroup *gpp; 1518 struct gpio_chip *chip = &pctrl->chip; 1519 struct device *dev = pctrl->dev; 1520 bool need_valid_mask = !dmi_check_system(chv_no_valid_mask); 1521 int ret, i, irq_base; 1522 1523 *chip = chv_gpio_chip; 1524 1525 chip->ngpio = pctrl->soc->pins[pctrl->soc->npins - 1].number + 1; 1526 chip->label = dev_name(dev); 1527 chip->add_pin_ranges = intel_gpio_add_pin_ranges; 1528 chip->parent = dev; 1529 chip->base = -1; 1530 1531 pctrl->irq = irq; 1532 1533 gpio_irq_chip_set_chip(&chip->irq, &chv_gpio_irq_chip); 1534 chip->irq.init_hw = chv_gpio_irq_init_hw; 1535 chip->irq.parent_handler = chv_gpio_irq_handler; 1536 chip->irq.num_parents = 1; 1537 chip->irq.parents = &pctrl->irq; 1538 chip->irq.default_type = IRQ_TYPE_NONE; 1539 chip->irq.handler = handle_bad_irq; 1540 if (need_valid_mask) { 1541 chip->irq.init_valid_mask = chv_init_irq_valid_mask; 1542 } else { 1543 irq_base = devm_irq_alloc_descs(dev, -1, 0, pctrl->soc->npins, NUMA_NO_NODE); 1544 if (irq_base < 0) 1545 return dev_err_probe(dev, irq_base, "failed to allocate IRQ numbers\n"); 1546 } 1547 1548 ret = devm_gpiochip_add_data(dev, chip, pctrl); 1549 if (ret) 1550 return dev_err_probe(dev, ret, "failed to register gpiochip\n"); 1551 1552 if (!need_valid_mask) { 1553 for (i = 0; i < community->ngpps; i++) { 1554 gpp = &community->gpps[i]; 1555 1556 irq_domain_associate_many(chip->irq.domain, irq_base, 1557 gpp->base, gpp->size); 1558 irq_base += gpp->size; 1559 } 1560 } 1561 1562 return 0; 1563} 1564 1565static acpi_status chv_pinctrl_mmio_access_handler(u32 function, 1566 acpi_physical_address address, u32 bits, u64 *value, 1567 void *handler_context, void *region_context) 1568{ 1569 struct intel_pinctrl *pctrl = region_context; 1570 1571 guard(raw_spinlock_irqsave)(&chv_lock); 1572 1573 if (function == ACPI_WRITE) 1574 chv_pctrl_writel(pctrl, address, *value); 1575 else if (function == ACPI_READ) 1576 *value = chv_pctrl_readl(pctrl, address); 1577 else 1578 return AE_BAD_PARAMETER; 1579 1580 return AE_OK; 1581} 1582 1583static int chv_pinctrl_probe(struct platform_device *pdev) 1584{ 1585 const struct intel_pinctrl_soc_data *soc_data; 1586 struct intel_community_context *cctx; 1587 struct intel_community *community; 1588 struct device *dev = &pdev->dev; 1589 struct intel_pinctrl *pctrl; 1590 acpi_status status; 1591 unsigned int i; 1592 int ret, irq; 1593 1594 soc_data = intel_pinctrl_get_soc_data(pdev); 1595 if (IS_ERR(soc_data)) 1596 return PTR_ERR(soc_data); 1597 1598 pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); 1599 if (!pctrl) 1600 return -ENOMEM; 1601 1602 pctrl->dev = dev; 1603 pctrl->soc = soc_data; 1604 1605 pctrl->ncommunities = pctrl->soc->ncommunities; 1606 pctrl->communities = devm_kmemdup_array(dev, pctrl->soc->communities, pctrl->ncommunities, 1607 sizeof(*pctrl->soc->communities), GFP_KERNEL); 1608 if (!pctrl->communities) 1609 return -ENOMEM; 1610 1611 community = &pctrl->communities[0]; 1612 community->regs = devm_platform_ioremap_resource(pdev, 0); 1613 if (IS_ERR(community->regs)) 1614 return PTR_ERR(community->regs); 1615 1616 community->pad_regs = community->regs + FAMILY_PAD_REGS_OFF; 1617 1618#ifdef CONFIG_PM_SLEEP 1619 pctrl->context.pads = devm_kcalloc(dev, pctrl->soc->npins, 1620 sizeof(*pctrl->context.pads), 1621 GFP_KERNEL); 1622 if (!pctrl->context.pads) 1623 return -ENOMEM; 1624#endif 1625 1626 pctrl->context.communities = devm_kcalloc(dev, pctrl->soc->ncommunities, 1627 sizeof(*pctrl->context.communities), 1628 GFP_KERNEL); 1629 if (!pctrl->context.communities) 1630 return -ENOMEM; 1631 1632 cctx = &pctrl->context.communities[0]; 1633 for (i = 0; i < ARRAY_SIZE(cctx->intr_lines); i++) 1634 cctx->intr_lines[i] = CHV_INVALID_HWIRQ; 1635 1636 irq = platform_get_irq(pdev, 0); 1637 if (irq < 0) 1638 return irq; 1639 1640 pctrl->pctldesc = chv_pinctrl_desc; 1641 pctrl->pctldesc.name = dev_name(dev); 1642 pctrl->pctldesc.pins = pctrl->soc->pins; 1643 pctrl->pctldesc.npins = pctrl->soc->npins; 1644 1645 pctrl->pctldev = devm_pinctrl_register(dev, &pctrl->pctldesc, pctrl); 1646 if (IS_ERR(pctrl->pctldev)) 1647 return dev_err_probe(dev, PTR_ERR(pctrl->pctldev), "failed to register pinctrl\n"); 1648 1649 ret = chv_gpio_probe(pctrl, irq); 1650 if (ret) 1651 return ret; 1652 1653 status = acpi_install_address_space_handler(ACPI_HANDLE(dev), 1654 community->acpi_space_id, 1655 chv_pinctrl_mmio_access_handler, 1656 NULL, pctrl); 1657 if (ACPI_FAILURE(status)) 1658 dev_err(dev, "failed to install ACPI addr space handler\n"); 1659 1660 platform_set_drvdata(pdev, pctrl); 1661 1662 return 0; 1663} 1664 1665static void chv_pinctrl_remove(struct platform_device *pdev) 1666{ 1667 struct intel_pinctrl *pctrl = platform_get_drvdata(pdev); 1668 const struct intel_community *community = &pctrl->communities[0]; 1669 1670 acpi_remove_address_space_handler(ACPI_HANDLE(&pdev->dev), 1671 community->acpi_space_id, 1672 chv_pinctrl_mmio_access_handler); 1673} 1674 1675static int chv_pinctrl_suspend_noirq(struct device *dev) 1676{ 1677 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1678 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1679 int i; 1680 1681 guard(raw_spinlock_irqsave)(&chv_lock); 1682 1683 cctx->saved_intmask = chv_pctrl_readl(pctrl, CHV_INTMASK); 1684 1685 for (i = 0; i < pctrl->soc->npins; i++) { 1686 const struct pinctrl_pin_desc *desc; 1687 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1688 1689 desc = &pctrl->soc->pins[i]; 1690 if (chv_pad_locked(pctrl, desc->number)) 1691 continue; 1692 1693 ctx->padctrl0 = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1694 ctx->padctrl0 &= ~CHV_PADCTRL0_GPIORXSTATE; 1695 1696 ctx->padctrl1 = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1697 } 1698 1699 return 0; 1700} 1701 1702static int chv_pinctrl_resume_noirq(struct device *dev) 1703{ 1704 struct intel_pinctrl *pctrl = dev_get_drvdata(dev); 1705 struct intel_community_context *cctx = &pctrl->context.communities[0]; 1706 int i; 1707 1708 guard(raw_spinlock_irqsave)(&chv_lock); 1709 1710 /* 1711 * Mask all interrupts before restoring per-pin configuration 1712 * registers because we don't know in which state BIOS left them 1713 * upon exiting suspend. 1714 */ 1715 chv_pctrl_writel(pctrl, CHV_INTMASK, 0x0000); 1716 1717 for (i = 0; i < pctrl->soc->npins; i++) { 1718 const struct pinctrl_pin_desc *desc; 1719 struct intel_pad_context *ctx = &pctrl->context.pads[i]; 1720 u32 val; 1721 1722 desc = &pctrl->soc->pins[i]; 1723 if (chv_pad_locked(pctrl, desc->number)) 1724 continue; 1725 1726 /* Only restore if our saved state differs from the current */ 1727 val = chv_readl(pctrl, desc->number, CHV_PADCTRL0); 1728 val &= ~CHV_PADCTRL0_GPIORXSTATE; 1729 if (ctx->padctrl0 != val) { 1730 chv_writel(pctrl, desc->number, CHV_PADCTRL0, ctx->padctrl0); 1731 dev_dbg(dev, "restored pin %2u ctrl0 0x%08x\n", desc->number, 1732 chv_readl(pctrl, desc->number, CHV_PADCTRL0)); 1733 } 1734 1735 val = chv_readl(pctrl, desc->number, CHV_PADCTRL1); 1736 if (ctx->padctrl1 != val) { 1737 chv_writel(pctrl, desc->number, CHV_PADCTRL1, ctx->padctrl1); 1738 dev_dbg(dev, "restored pin %2u ctrl1 0x%08x\n", desc->number, 1739 chv_readl(pctrl, desc->number, CHV_PADCTRL1)); 1740 } 1741 } 1742 1743 /* 1744 * Now that all pins are restored to known state, we can restore 1745 * the interrupt mask register as well. 1746 */ 1747 chv_pctrl_writel(pctrl, CHV_INTSTAT, 0xffff); 1748 chv_pctrl_writel(pctrl, CHV_INTMASK, cctx->saved_intmask); 1749 1750 return 0; 1751} 1752 1753static DEFINE_NOIRQ_DEV_PM_OPS(chv_pinctrl_pm_ops, 1754 chv_pinctrl_suspend_noirq, chv_pinctrl_resume_noirq); 1755 1756static const struct acpi_device_id chv_pinctrl_acpi_match[] = { 1757 { "INT33FF", (kernel_ulong_t)chv_soc_data }, 1758 { } 1759}; 1760MODULE_DEVICE_TABLE(acpi, chv_pinctrl_acpi_match); 1761 1762static struct platform_driver chv_pinctrl_driver = { 1763 .probe = chv_pinctrl_probe, 1764 .remove = chv_pinctrl_remove, 1765 .driver = { 1766 .name = "cherryview-pinctrl", 1767 .pm = pm_sleep_ptr(&chv_pinctrl_pm_ops), 1768 .acpi_match_table = chv_pinctrl_acpi_match, 1769 }, 1770}; 1771 1772static int __init chv_pinctrl_init(void) 1773{ 1774 return platform_driver_register(&chv_pinctrl_driver); 1775} 1776subsys_initcall(chv_pinctrl_init); 1777 1778static void __exit chv_pinctrl_exit(void) 1779{ 1780 platform_driver_unregister(&chv_pinctrl_driver); 1781} 1782module_exit(chv_pinctrl_exit); 1783 1784MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); 1785MODULE_DESCRIPTION("Intel Cherryview/Braswell pinctrl driver"); 1786MODULE_LICENSE("GPL v2"); 1787MODULE_IMPORT_NS("PINCTRL_INTEL");
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