pinctrl-imx7d.c

  1// SPDX-License-Identifier: GPL-2.0
  2//
  3// Freescale imx7d pinctrl driver
  4//
  5// Author: Anson Huang <Anson.Huang@freescale.com>
  6// Copyright (C) 2014-2015 Freescale Semiconductor, Inc.
  7
  8#include <linux/err.h>
  9#include <linux/init.h>
 10#include <linux/io.h>
 11#include <linux/of.h>
 12#include <linux/platform_device.h>
 13#include <linux/pinctrl/pinctrl.h>
 14
 15#include "pinctrl-imx.h"
 16
 17enum imx7d_pads {
 18	MX7D_PAD_RESERVE0 = 0,
 19	MX7D_PAD_RESERVE1 = 1,
 20	MX7D_PAD_RESERVE2 = 2,
 21	MX7D_PAD_RESERVE3 = 3,
 22	MX7D_PAD_RESERVE4 = 4,
 23	MX7D_PAD_GPIO1_IO08 = 5,
 24	MX7D_PAD_GPIO1_IO09 = 6,
 25	MX7D_PAD_GPIO1_IO10 = 7,
 26	MX7D_PAD_GPIO1_IO11 = 8,
 27	MX7D_PAD_GPIO1_IO12 = 9,
 28	MX7D_PAD_GPIO1_IO13 = 10,
 29	MX7D_PAD_GPIO1_IO14 = 11,
 30	MX7D_PAD_GPIO1_IO15 = 12,
 31	MX7D_PAD_EPDC_DATA00 = 13,
 32	MX7D_PAD_EPDC_DATA01 = 14,
 33	MX7D_PAD_EPDC_DATA02 = 15,
 34	MX7D_PAD_EPDC_DATA03 = 16,
 35	MX7D_PAD_EPDC_DATA04 = 17,
 36	MX7D_PAD_EPDC_DATA05 = 18,
 37	MX7D_PAD_EPDC_DATA06 = 19,
 38	MX7D_PAD_EPDC_DATA07 = 20,
 39	MX7D_PAD_EPDC_DATA08 = 21,
 40	MX7D_PAD_EPDC_DATA09 = 22,
 41	MX7D_PAD_EPDC_DATA10 = 23,
 42	MX7D_PAD_EPDC_DATA11 = 24,
 43	MX7D_PAD_EPDC_DATA12 = 25,
 44	MX7D_PAD_EPDC_DATA13 = 26,
 45	MX7D_PAD_EPDC_DATA14 = 27,
 46	MX7D_PAD_EPDC_DATA15 = 28,
 47	MX7D_PAD_EPDC_SDCLK = 29,
 48	MX7D_PAD_EPDC_SDLE = 30,
 49	MX7D_PAD_EPDC_SDOE = 31,
 50	MX7D_PAD_EPDC_SDSHR = 32,
 51	MX7D_PAD_EPDC_SDCE0 = 33,
 52	MX7D_PAD_EPDC_SDCE1 = 34,
 53	MX7D_PAD_EPDC_SDCE2 = 35,
 54	MX7D_PAD_EPDC_SDCE3 = 36,
 55	MX7D_PAD_EPDC_GDCLK = 37,
 56	MX7D_PAD_EPDC_GDOE = 38,
 57	MX7D_PAD_EPDC_GDRL = 39,
 58	MX7D_PAD_EPDC_GDSP = 40,
 59	MX7D_PAD_EPDC_BDR0 = 41,
 60	MX7D_PAD_EPDC_BDR1 = 42,
 61	MX7D_PAD_EPDC_PWR_COM = 43,
 62	MX7D_PAD_EPDC_PWR_STAT = 44,
 63	MX7D_PAD_LCD_CLK = 45,
 64	MX7D_PAD_LCD_ENABLE = 46,
 65	MX7D_PAD_LCD_HSYNC = 47,
 66	MX7D_PAD_LCD_VSYNC = 48,
 67	MX7D_PAD_LCD_RESET = 49,
 68	MX7D_PAD_LCD_DATA00 = 50,
 69	MX7D_PAD_LCD_DATA01 = 51,
 70	MX7D_PAD_LCD_DATA02 = 52,
 71	MX7D_PAD_LCD_DATA03 = 53,
 72	MX7D_PAD_LCD_DATA04 = 54,
 73	MX7D_PAD_LCD_DATA05 = 55,
 74	MX7D_PAD_LCD_DATA06 = 56,
 75	MX7D_PAD_LCD_DATA07 = 57,
 76	MX7D_PAD_LCD_DATA08 = 58,
 77	MX7D_PAD_LCD_DATA09 = 59,
 78	MX7D_PAD_LCD_DATA10 = 60,
 79	MX7D_PAD_LCD_DATA11 = 61,
 80	MX7D_PAD_LCD_DATA12 = 62,
 81	MX7D_PAD_LCD_DATA13 = 63,
 82	MX7D_PAD_LCD_DATA14 = 64,
 83	MX7D_PAD_LCD_DATA15 = 65,
 84	MX7D_PAD_LCD_DATA16 = 66,
 85	MX7D_PAD_LCD_DATA17 = 67,
 86	MX7D_PAD_LCD_DATA18 = 68,
 87	MX7D_PAD_LCD_DATA19 = 69,
 88	MX7D_PAD_LCD_DATA20 = 70,
 89	MX7D_PAD_LCD_DATA21 = 71,
 90	MX7D_PAD_LCD_DATA22 = 72,
 91	MX7D_PAD_LCD_DATA23 = 73,
 92	MX7D_PAD_UART1_RX_DATA = 74,
 93	MX7D_PAD_UART1_TX_DATA = 75,
 94	MX7D_PAD_UART2_RX_DATA = 76,
 95	MX7D_PAD_UART2_TX_DATA = 77,
 96	MX7D_PAD_UART3_RX_DATA = 78,
 97	MX7D_PAD_UART3_TX_DATA = 79,
 98	MX7D_PAD_UART3_RTS_B = 80,
 99	MX7D_PAD_UART3_CTS_B = 81,
100	MX7D_PAD_I2C1_SCL = 82,
101	MX7D_PAD_I2C1_SDA = 83,
102	MX7D_PAD_I2C2_SCL = 84,
103	MX7D_PAD_I2C2_SDA = 85,
104	MX7D_PAD_I2C3_SCL = 86,
105	MX7D_PAD_I2C3_SDA = 87,
106	MX7D_PAD_I2C4_SCL = 88,
107	MX7D_PAD_I2C4_SDA = 89,
108	MX7D_PAD_ECSPI1_SCLK = 90,
109	MX7D_PAD_ECSPI1_MOSI = 91,
110	MX7D_PAD_ECSPI1_MISO = 92,
111	MX7D_PAD_ECSPI1_SS0 = 93,
112	MX7D_PAD_ECSPI2_SCLK = 94,
113	MX7D_PAD_ECSPI2_MOSI = 95,
114	MX7D_PAD_ECSPI2_MISO = 96,
115	MX7D_PAD_ECSPI2_SS0 = 97,
116	MX7D_PAD_SD1_CD_B = 98,
117	MX7D_PAD_SD1_WP = 99,
118	MX7D_PAD_SD1_RESET_B = 100,
119	MX7D_PAD_SD1_CLK = 101,
120	MX7D_PAD_SD1_CMD = 102,
121	MX7D_PAD_SD1_DATA0 = 103,
122	MX7D_PAD_SD1_DATA1 = 104,
123	MX7D_PAD_SD1_DATA2 = 105,
124	MX7D_PAD_SD1_DATA3 = 106,
125	MX7D_PAD_SD2_CD_B = 107,
126	MX7D_PAD_SD2_WP = 108,
127	MX7D_PAD_SD2_RESET_B = 109,
128	MX7D_PAD_SD2_CLK = 110,
129	MX7D_PAD_SD2_CMD = 111,
130	MX7D_PAD_SD2_DATA0 = 112,
131	MX7D_PAD_SD2_DATA1 = 113,
132	MX7D_PAD_SD2_DATA2 = 114,
133	MX7D_PAD_SD2_DATA3 = 115,
134	MX7D_PAD_SD3_CLK = 116,
135	MX7D_PAD_SD3_CMD = 117,
136	MX7D_PAD_SD3_DATA0 = 118,
137	MX7D_PAD_SD3_DATA1 = 119,
138	MX7D_PAD_SD3_DATA2 = 120,
139	MX7D_PAD_SD3_DATA3 = 121,
140	MX7D_PAD_SD3_DATA4 = 122,
141	MX7D_PAD_SD3_DATA5 = 123,
142	MX7D_PAD_SD3_DATA6 = 124,
143	MX7D_PAD_SD3_DATA7 = 125,
144	MX7D_PAD_SD3_STROBE = 126,
145	MX7D_PAD_SD3_RESET_B = 127,
146	MX7D_PAD_SAI1_RX_DATA = 128,
147	MX7D_PAD_SAI1_TX_BCLK = 129,
148	MX7D_PAD_SAI1_TX_SYNC = 130,
149	MX7D_PAD_SAI1_TX_DATA = 131,
150	MX7D_PAD_SAI1_RX_SYNC = 132,
151	MX7D_PAD_SAI1_RX_BCLK = 133,
152	MX7D_PAD_SAI1_MCLK = 134,
153	MX7D_PAD_SAI2_TX_SYNC = 135,
154	MX7D_PAD_SAI2_TX_BCLK = 136,
155	MX7D_PAD_SAI2_RX_DATA = 137,
156	MX7D_PAD_SAI2_TX_DATA = 138,
157	MX7D_PAD_ENET1_RGMII_RD0 = 139,
158	MX7D_PAD_ENET1_RGMII_RD1 = 140,
159	MX7D_PAD_ENET1_RGMII_RD2 = 141,
160	MX7D_PAD_ENET1_RGMII_RD3 = 142,
161	MX7D_PAD_ENET1_RGMII_RX_CTL = 143,
162	MX7D_PAD_ENET1_RGMII_RXC = 144,
163	MX7D_PAD_ENET1_RGMII_TD0 = 145,
164	MX7D_PAD_ENET1_RGMII_TD1 = 146,
165	MX7D_PAD_ENET1_RGMII_TD2 = 147,
166	MX7D_PAD_ENET1_RGMII_TD3 = 148,
167	MX7D_PAD_ENET1_RGMII_TX_CTL = 149,
168	MX7D_PAD_ENET1_RGMII_TXC = 150,
169	MX7D_PAD_ENET1_TX_CLK = 151,
170	MX7D_PAD_ENET1_RX_CLK = 152,
171	MX7D_PAD_ENET1_CRS = 153,
172	MX7D_PAD_ENET1_COL = 154,
173};
174
175enum imx7d_lpsr_pads {
176	MX7D_PAD_GPIO1_IO00 = 0,
177	MX7D_PAD_GPIO1_IO01 = 1,
178	MX7D_PAD_GPIO1_IO02 = 2,
179	MX7D_PAD_GPIO1_IO03 = 3,
180	MX7D_PAD_GPIO1_IO04 = 4,
181	MX7D_PAD_GPIO1_IO05 = 5,
182	MX7D_PAD_GPIO1_IO06 = 6,
183	MX7D_PAD_GPIO1_IO07 = 7,
184};
185
186/* Pad names for the pinmux subsystem */
187static const struct pinctrl_pin_desc imx7d_pinctrl_pads[] = {
188	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE0),
189	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE1),
190	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE2),
191	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE3),
192	IMX_PINCTRL_PIN(MX7D_PAD_RESERVE4),
193	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO08),
194	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO09),
195	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO10),
196	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO11),
197	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO12),
198	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO13),
199	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO14),
200	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO15),
201	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA00),
202	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA01),
203	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA02),
204	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA03),
205	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA04),
206	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA05),
207	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA06),
208	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA07),
209	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA08),
210	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA09),
211	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA10),
212	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA11),
213	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA12),
214	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA13),
215	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA14),
216	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_DATA15),
217	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCLK),
218	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDLE),
219	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDOE),
220	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDSHR),
221	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE0),
222	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE1),
223	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE2),
224	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_SDCE3),
225	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDCLK),
226	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDOE),
227	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDRL),
228	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_GDSP),
229	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR0),
230	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_BDR1),
231	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_COM),
232	IMX_PINCTRL_PIN(MX7D_PAD_EPDC_PWR_STAT),
233	IMX_PINCTRL_PIN(MX7D_PAD_LCD_CLK),
234	IMX_PINCTRL_PIN(MX7D_PAD_LCD_ENABLE),
235	IMX_PINCTRL_PIN(MX7D_PAD_LCD_HSYNC),
236	IMX_PINCTRL_PIN(MX7D_PAD_LCD_VSYNC),
237	IMX_PINCTRL_PIN(MX7D_PAD_LCD_RESET),
238	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA00),
239	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA01),
240	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA02),
241	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA03),
242	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA04),
243	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA05),
244	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA06),
245	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA07),
246	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA08),
247	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA09),
248	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA10),
249	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA11),
250	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA12),
251	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA13),
252	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA14),
253	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA15),
254	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA16),
255	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA17),
256	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA18),
257	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA19),
258	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA20),
259	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA21),
260	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA22),
261	IMX_PINCTRL_PIN(MX7D_PAD_LCD_DATA23),
262	IMX_PINCTRL_PIN(MX7D_PAD_UART1_RX_DATA),
263	IMX_PINCTRL_PIN(MX7D_PAD_UART1_TX_DATA),
264	IMX_PINCTRL_PIN(MX7D_PAD_UART2_RX_DATA),
265	IMX_PINCTRL_PIN(MX7D_PAD_UART2_TX_DATA),
266	IMX_PINCTRL_PIN(MX7D_PAD_UART3_RX_DATA),
267	IMX_PINCTRL_PIN(MX7D_PAD_UART3_TX_DATA),
268	IMX_PINCTRL_PIN(MX7D_PAD_UART3_RTS_B),
269	IMX_PINCTRL_PIN(MX7D_PAD_UART3_CTS_B),
270	IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SCL),
271	IMX_PINCTRL_PIN(MX7D_PAD_I2C1_SDA),
272	IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SCL),
273	IMX_PINCTRL_PIN(MX7D_PAD_I2C2_SDA),
274	IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SCL),
275	IMX_PINCTRL_PIN(MX7D_PAD_I2C3_SDA),
276	IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SCL),
277	IMX_PINCTRL_PIN(MX7D_PAD_I2C4_SDA),
278	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SCLK),
279	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MOSI),
280	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_MISO),
281	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI1_SS0),
282	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SCLK),
283	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MOSI),
284	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_MISO),
285	IMX_PINCTRL_PIN(MX7D_PAD_ECSPI2_SS0),
286	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CD_B),
287	IMX_PINCTRL_PIN(MX7D_PAD_SD1_WP),
288	IMX_PINCTRL_PIN(MX7D_PAD_SD1_RESET_B),
289	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CLK),
290	IMX_PINCTRL_PIN(MX7D_PAD_SD1_CMD),
291	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA0),
292	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA1),
293	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA2),
294	IMX_PINCTRL_PIN(MX7D_PAD_SD1_DATA3),
295	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CD_B),
296	IMX_PINCTRL_PIN(MX7D_PAD_SD2_WP),
297	IMX_PINCTRL_PIN(MX7D_PAD_SD2_RESET_B),
298	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CLK),
299	IMX_PINCTRL_PIN(MX7D_PAD_SD2_CMD),
300	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA0),
301	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA1),
302	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA2),
303	IMX_PINCTRL_PIN(MX7D_PAD_SD2_DATA3),
304	IMX_PINCTRL_PIN(MX7D_PAD_SD3_CLK),
305	IMX_PINCTRL_PIN(MX7D_PAD_SD3_CMD),
306	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA0),
307	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA1),
308	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA2),
309	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA3),
310	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA4),
311	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA5),
312	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA6),
313	IMX_PINCTRL_PIN(MX7D_PAD_SD3_DATA7),
314	IMX_PINCTRL_PIN(MX7D_PAD_SD3_STROBE),
315	IMX_PINCTRL_PIN(MX7D_PAD_SD3_RESET_B),
316	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_DATA),
317	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_BCLK),
318	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_SYNC),
319	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_TX_DATA),
320	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_SYNC),
321	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_RX_BCLK),
322	IMX_PINCTRL_PIN(MX7D_PAD_SAI1_MCLK),
323	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_SYNC),
324	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_BCLK),
325	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_RX_DATA),
326	IMX_PINCTRL_PIN(MX7D_PAD_SAI2_TX_DATA),
327	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD0),
328	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD1),
329	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD2),
330	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RD3),
331	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RX_CTL),
332	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_RXC),
333	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD0),
334	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD1),
335	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD2),
336	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TD3),
337	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TX_CTL),
338	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RGMII_TXC),
339	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_TX_CLK),
340	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_RX_CLK),
341	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_CRS),
342	IMX_PINCTRL_PIN(MX7D_PAD_ENET1_COL),
343};
344
345/* Pad names for the pinmux subsystem */
346static const struct pinctrl_pin_desc imx7d_lpsr_pinctrl_pads[] = {
347	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO00),
348	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO01),
349	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO02),
350	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO03),
351	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO04),
352	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO05),
353	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO06),
354	IMX_PINCTRL_PIN(MX7D_PAD_GPIO1_IO07),
355};
356
357static const struct imx_pinctrl_soc_info imx7d_pinctrl_info = {
358	.pins = imx7d_pinctrl_pads,
359	.npins = ARRAY_SIZE(imx7d_pinctrl_pads),
360	.gpr_compatible = "fsl,imx7d-iomuxc-gpr",
361};
362
363static const struct imx_pinctrl_soc_info imx7d_lpsr_pinctrl_info = {
364	.pins = imx7d_lpsr_pinctrl_pads,
365	.npins = ARRAY_SIZE(imx7d_lpsr_pinctrl_pads),
366	.flags = ZERO_OFFSET_VALID,
367};
368
369static const struct of_device_id imx7d_pinctrl_of_match[] = {
370	{ .compatible = "fsl,imx7d-iomuxc", .data = &imx7d_pinctrl_info, },
371	{ .compatible = "fsl,imx7d-iomuxc-lpsr", .data = &imx7d_lpsr_pinctrl_info },
372	{ /* sentinel */ }
373};
374
375static int imx7d_pinctrl_probe(struct platform_device *pdev)
376{
377	const struct imx_pinctrl_soc_info *pinctrl_info;
378
379	pinctrl_info = of_device_get_match_data(&pdev->dev);
380	if (!pinctrl_info)
381		return -ENODEV;
382
383	return imx_pinctrl_probe(pdev, pinctrl_info);
384}
385
386static struct platform_driver imx7d_pinctrl_driver = {
387	.driver = {
388		.name = "imx7d-pinctrl",
389		.of_match_table = imx7d_pinctrl_of_match,
390		.suppress_bind_attrs = true,
391	},
392	.probe = imx7d_pinctrl_probe,
393};
394
395static int __init imx7d_pinctrl_init(void)
396{
397	return platform_driver_register(&imx7d_pinctrl_driver);
398}
399arch_initcall(imx7d_pinctrl_init);