pinctrl-lochnagar.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Lochnagar pin and GPIO control
   4 *
   5 * Copyright (c) 2017-2018 Cirrus Logic, Inc. and
   6 *                         Cirrus Logic International Semiconductor Ltd.
   7 *
   8 * Author: Charles Keepax <ckeepax@opensource.cirrus.com>
   9 */
  10
  11#include <linux/err.h>
  12#include <linux/errno.h>
  13#include <linux/gpio/driver.h>
  14#include <linux/module.h>
  15#include <linux/of.h>
  16#include <linux/platform_device.h>
  17#include <linux/regmap.h>
  18#include <linux/string_choices.h>
  19
  20#include <linux/pinctrl/consumer.h>
  21#include <linux/pinctrl/pinconf-generic.h>
  22#include <linux/pinctrl/pinconf.h>
  23#include <linux/pinctrl/pinctrl.h>
  24#include <linux/pinctrl/pinmux.h>
  25
  26#include <linux/mfd/lochnagar.h>
  27#include <linux/mfd/lochnagar1_regs.h>
  28#include <linux/mfd/lochnagar2_regs.h>
  29
  30#include <dt-bindings/pinctrl/lochnagar.h>
  31
  32#include "../pinctrl-utils.h"
  33
  34#define LN2_NUM_GPIO_CHANNELS	16
  35
  36#define LN_CDC_AIF1_STR		"codec-aif1"
  37#define LN_CDC_AIF2_STR		"codec-aif2"
  38#define LN_CDC_AIF3_STR		"codec-aif3"
  39#define LN_DSP_AIF1_STR		"dsp-aif1"
  40#define LN_DSP_AIF2_STR		"dsp-aif2"
  41#define LN_PSIA1_STR		"psia1"
  42#define LN_PSIA2_STR		"psia2"
  43#define LN_GF_AIF1_STR		"gf-aif1"
  44#define LN_GF_AIF2_STR		"gf-aif2"
  45#define LN_GF_AIF3_STR		"gf-aif3"
  46#define LN_GF_AIF4_STR		"gf-aif4"
  47#define LN_SPDIF_AIF_STR	"spdif-aif"
  48#define LN_USB_AIF1_STR		"usb-aif1"
  49#define LN_USB_AIF2_STR		"usb-aif2"
  50#define LN_ADAT_AIF_STR		"adat-aif"
  51#define LN_SOUNDCARD_AIF_STR	"soundcard-aif"
  52
  53#define LN_PIN_GPIO(REV, ID, NAME, REG, SHIFT, INVERT) \
  54static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = { \
  55	.name = NAME, .type = LN_PTYPE_GPIO, .reg = LOCHNAGAR##REV##_##REG, \
  56	.shift = LOCHNAGAR##REV##_##SHIFT##_SHIFT, .invert = INVERT, \
  57}
  58
  59#define LN_PIN_SAIF(REV, ID, NAME) \
  60static const struct lochnagar_pin lochnagar##REV##_##ID##_pin = \
  61	{ .name = NAME, .type = LN_PTYPE_AIF, }
  62
  63#define LN_PIN_AIF(REV, ID) \
  64	LN_PIN_SAIF(REV, ID##_BCLK,  LN_##ID##_STR"-bclk"); \
  65	LN_PIN_SAIF(REV, ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
  66	LN_PIN_SAIF(REV, ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
  67	LN_PIN_SAIF(REV, ID##_TXDAT, LN_##ID##_STR"-txdat")
  68
  69#define LN1_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
  70	LN_PIN_GPIO(1, ID, NAME, REG, SHIFT, INVERT)
  71
  72#define LN1_PIN_MUX(ID, NAME) \
  73static const struct lochnagar_pin lochnagar1_##ID##_pin = \
  74	{ .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR1_##ID, }
  75
  76#define LN1_PIN_AIF(ID) LN_PIN_AIF(1, ID)
  77
  78#define LN2_PIN_GPIO(ID, NAME, REG, SHIFT, INVERT) \
  79	LN_PIN_GPIO(2, ID, NAME, REG, SHIFT, INVERT)
  80
  81#define LN2_PIN_MUX(ID, NAME) \
  82static const struct lochnagar_pin lochnagar2_##ID##_pin = \
  83	{ .name = NAME, .type = LN_PTYPE_MUX, .reg = LOCHNAGAR2_GPIO_##ID, }
  84
  85#define LN2_PIN_AIF(ID) LN_PIN_AIF(2, ID)
  86
  87#define LN2_PIN_GAI(ID) \
  88	LN2_PIN_MUX(ID##_BCLK,  LN_##ID##_STR"-bclk"); \
  89	LN2_PIN_MUX(ID##_LRCLK, LN_##ID##_STR"-lrclk"); \
  90	LN2_PIN_MUX(ID##_RXDAT, LN_##ID##_STR"-rxdat"); \
  91	LN2_PIN_MUX(ID##_TXDAT, LN_##ID##_STR"-txdat")
  92
  93#define LN_PIN(REV, ID) [LOCHNAGAR##REV##_PIN_##ID] = { \
  94	.number = LOCHNAGAR##REV##_PIN_##ID, \
  95	.name = lochnagar##REV##_##ID##_pin.name, \
  96	.drv_data = (void *)&lochnagar##REV##_##ID##_pin, \
  97}
  98
  99#define LN1_PIN(ID) LN_PIN(1, ID)
 100#define LN2_PIN(ID) LN_PIN(2, ID)
 101
 102#define LN_PINS(REV, ID) \
 103	LN_PIN(REV, ID##_BCLK), LN_PIN(REV, ID##_LRCLK), \
 104	LN_PIN(REV, ID##_RXDAT), LN_PIN(REV, ID##_TXDAT)
 105
 106#define LN1_PINS(ID) LN_PINS(1, ID)
 107#define LN2_PINS(ID) LN_PINS(2, ID)
 108
 109enum {
 110	LOCHNAGAR1_PIN_GF_GPIO2 = LOCHNAGAR1_PIN_NUM_GPIOS,
 111	LOCHNAGAR1_PIN_GF_GPIO3,
 112	LOCHNAGAR1_PIN_GF_GPIO7,
 113	LOCHNAGAR1_PIN_LED1,
 114	LOCHNAGAR1_PIN_LED2,
 115	LOCHNAGAR1_PIN_CDC_AIF1_BCLK,
 116	LOCHNAGAR1_PIN_CDC_AIF1_LRCLK,
 117	LOCHNAGAR1_PIN_CDC_AIF1_RXDAT,
 118	LOCHNAGAR1_PIN_CDC_AIF1_TXDAT,
 119	LOCHNAGAR1_PIN_CDC_AIF2_BCLK,
 120	LOCHNAGAR1_PIN_CDC_AIF2_LRCLK,
 121	LOCHNAGAR1_PIN_CDC_AIF2_RXDAT,
 122	LOCHNAGAR1_PIN_CDC_AIF2_TXDAT,
 123	LOCHNAGAR1_PIN_CDC_AIF3_BCLK,
 124	LOCHNAGAR1_PIN_CDC_AIF3_LRCLK,
 125	LOCHNAGAR1_PIN_CDC_AIF3_RXDAT,
 126	LOCHNAGAR1_PIN_CDC_AIF3_TXDAT,
 127	LOCHNAGAR1_PIN_DSP_AIF1_BCLK,
 128	LOCHNAGAR1_PIN_DSP_AIF1_LRCLK,
 129	LOCHNAGAR1_PIN_DSP_AIF1_RXDAT,
 130	LOCHNAGAR1_PIN_DSP_AIF1_TXDAT,
 131	LOCHNAGAR1_PIN_DSP_AIF2_BCLK,
 132	LOCHNAGAR1_PIN_DSP_AIF2_LRCLK,
 133	LOCHNAGAR1_PIN_DSP_AIF2_RXDAT,
 134	LOCHNAGAR1_PIN_DSP_AIF2_TXDAT,
 135	LOCHNAGAR1_PIN_PSIA1_BCLK,
 136	LOCHNAGAR1_PIN_PSIA1_LRCLK,
 137	LOCHNAGAR1_PIN_PSIA1_RXDAT,
 138	LOCHNAGAR1_PIN_PSIA1_TXDAT,
 139	LOCHNAGAR1_PIN_PSIA2_BCLK,
 140	LOCHNAGAR1_PIN_PSIA2_LRCLK,
 141	LOCHNAGAR1_PIN_PSIA2_RXDAT,
 142	LOCHNAGAR1_PIN_PSIA2_TXDAT,
 143	LOCHNAGAR1_PIN_SPDIF_AIF_BCLK,
 144	LOCHNAGAR1_PIN_SPDIF_AIF_LRCLK,
 145	LOCHNAGAR1_PIN_SPDIF_AIF_RXDAT,
 146	LOCHNAGAR1_PIN_SPDIF_AIF_TXDAT,
 147	LOCHNAGAR1_PIN_GF_AIF3_BCLK,
 148	LOCHNAGAR1_PIN_GF_AIF3_RXDAT,
 149	LOCHNAGAR1_PIN_GF_AIF3_LRCLK,
 150	LOCHNAGAR1_PIN_GF_AIF3_TXDAT,
 151	LOCHNAGAR1_PIN_GF_AIF4_BCLK,
 152	LOCHNAGAR1_PIN_GF_AIF4_RXDAT,
 153	LOCHNAGAR1_PIN_GF_AIF4_LRCLK,
 154	LOCHNAGAR1_PIN_GF_AIF4_TXDAT,
 155	LOCHNAGAR1_PIN_GF_AIF1_BCLK,
 156	LOCHNAGAR1_PIN_GF_AIF1_RXDAT,
 157	LOCHNAGAR1_PIN_GF_AIF1_LRCLK,
 158	LOCHNAGAR1_PIN_GF_AIF1_TXDAT,
 159	LOCHNAGAR1_PIN_GF_AIF2_BCLK,
 160	LOCHNAGAR1_PIN_GF_AIF2_RXDAT,
 161	LOCHNAGAR1_PIN_GF_AIF2_LRCLK,
 162	LOCHNAGAR1_PIN_GF_AIF2_TXDAT,
 163
 164	LOCHNAGAR2_PIN_SPDIF_AIF_BCLK = LOCHNAGAR2_PIN_NUM_GPIOS,
 165	LOCHNAGAR2_PIN_SPDIF_AIF_LRCLK,
 166	LOCHNAGAR2_PIN_SPDIF_AIF_RXDAT,
 167	LOCHNAGAR2_PIN_SPDIF_AIF_TXDAT,
 168	LOCHNAGAR2_PIN_USB_AIF1_BCLK,
 169	LOCHNAGAR2_PIN_USB_AIF1_LRCLK,
 170	LOCHNAGAR2_PIN_USB_AIF1_RXDAT,
 171	LOCHNAGAR2_PIN_USB_AIF1_TXDAT,
 172	LOCHNAGAR2_PIN_USB_AIF2_BCLK,
 173	LOCHNAGAR2_PIN_USB_AIF2_LRCLK,
 174	LOCHNAGAR2_PIN_USB_AIF2_RXDAT,
 175	LOCHNAGAR2_PIN_USB_AIF2_TXDAT,
 176	LOCHNAGAR2_PIN_ADAT_AIF_BCLK,
 177	LOCHNAGAR2_PIN_ADAT_AIF_LRCLK,
 178	LOCHNAGAR2_PIN_ADAT_AIF_RXDAT,
 179	LOCHNAGAR2_PIN_ADAT_AIF_TXDAT,
 180	LOCHNAGAR2_PIN_SOUNDCARD_AIF_BCLK,
 181	LOCHNAGAR2_PIN_SOUNDCARD_AIF_LRCLK,
 182	LOCHNAGAR2_PIN_SOUNDCARD_AIF_RXDAT,
 183	LOCHNAGAR2_PIN_SOUNDCARD_AIF_TXDAT,
 184};
 185
 186enum lochnagar_pin_type {
 187	LN_PTYPE_GPIO,
 188	LN_PTYPE_MUX,
 189	LN_PTYPE_AIF,
 190	LN_PTYPE_COUNT,
 191};
 192
 193struct lochnagar_pin {
 194	const char name[20];
 195
 196	enum lochnagar_pin_type type;
 197
 198	unsigned int reg;
 199	int shift;
 200	bool invert;
 201};
 202
 203LN1_PIN_GPIO(CDC_RESET,    "codec-reset",    RST,      CDC_RESET,    1);
 204LN1_PIN_GPIO(DSP_RESET,    "dsp-reset",      RST,      DSP_RESET,    1);
 205LN1_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", I2C_CTRL, CDC_CIF_MODE, 0);
 206LN1_PIN_MUX(GF_GPIO2,      "gf-gpio2");
 207LN1_PIN_MUX(GF_GPIO3,      "gf-gpio3");
 208LN1_PIN_MUX(GF_GPIO7,      "gf-gpio7");
 209LN1_PIN_MUX(LED1,          "led1");
 210LN1_PIN_MUX(LED2,          "led2");
 211LN1_PIN_AIF(CDC_AIF1);
 212LN1_PIN_AIF(CDC_AIF2);
 213LN1_PIN_AIF(CDC_AIF3);
 214LN1_PIN_AIF(DSP_AIF1);
 215LN1_PIN_AIF(DSP_AIF2);
 216LN1_PIN_AIF(PSIA1);
 217LN1_PIN_AIF(PSIA2);
 218LN1_PIN_AIF(SPDIF_AIF);
 219LN1_PIN_AIF(GF_AIF1);
 220LN1_PIN_AIF(GF_AIF2);
 221LN1_PIN_AIF(GF_AIF3);
 222LN1_PIN_AIF(GF_AIF4);
 223
 224LN2_PIN_GPIO(CDC_RESET,    "codec-reset",    MINICARD_RESETS, CDC_RESET,     1);
 225LN2_PIN_GPIO(DSP_RESET,    "dsp-reset",      MINICARD_RESETS, DSP_RESET,     1);
 226LN2_PIN_GPIO(CDC_CIF1MODE, "codec-cif1mode", COMMS_CTRL4,     CDC_CIF1MODE,  0);
 227LN2_PIN_GPIO(CDC_LDOENA,   "codec-ldoena",   POWER_CTRL,      PWR_ENA,       0);
 228LN2_PIN_GPIO(SPDIF_HWMODE, "spdif-hwmode",   SPDIF_CTRL,      SPDIF_HWMODE,  0);
 229LN2_PIN_GPIO(SPDIF_RESET,  "spdif-reset",    SPDIF_CTRL,      SPDIF_RESET,   1);
 230LN2_PIN_MUX(FPGA_GPIO1,    "fpga-gpio1");
 231LN2_PIN_MUX(FPGA_GPIO2,    "fpga-gpio2");
 232LN2_PIN_MUX(FPGA_GPIO3,    "fpga-gpio3");
 233LN2_PIN_MUX(FPGA_GPIO4,    "fpga-gpio4");
 234LN2_PIN_MUX(FPGA_GPIO5,    "fpga-gpio5");
 235LN2_PIN_MUX(FPGA_GPIO6,    "fpga-gpio6");
 236LN2_PIN_MUX(CDC_GPIO1,     "codec-gpio1");
 237LN2_PIN_MUX(CDC_GPIO2,     "codec-gpio2");
 238LN2_PIN_MUX(CDC_GPIO3,     "codec-gpio3");
 239LN2_PIN_MUX(CDC_GPIO4,     "codec-gpio4");
 240LN2_PIN_MUX(CDC_GPIO5,     "codec-gpio5");
 241LN2_PIN_MUX(CDC_GPIO6,     "codec-gpio6");
 242LN2_PIN_MUX(CDC_GPIO7,     "codec-gpio7");
 243LN2_PIN_MUX(CDC_GPIO8,     "codec-gpio8");
 244LN2_PIN_MUX(DSP_GPIO1,     "dsp-gpio1");
 245LN2_PIN_MUX(DSP_GPIO2,     "dsp-gpio2");
 246LN2_PIN_MUX(DSP_GPIO3,     "dsp-gpio3");
 247LN2_PIN_MUX(DSP_GPIO4,     "dsp-gpio4");
 248LN2_PIN_MUX(DSP_GPIO5,     "dsp-gpio5");
 249LN2_PIN_MUX(DSP_GPIO6,     "dsp-gpio6");
 250LN2_PIN_MUX(GF_GPIO2,      "gf-gpio2");
 251LN2_PIN_MUX(GF_GPIO3,      "gf-gpio3");
 252LN2_PIN_MUX(GF_GPIO7,      "gf-gpio7");
 253LN2_PIN_MUX(DSP_UART1_RX,  "dsp-uart1-rx");
 254LN2_PIN_MUX(DSP_UART1_TX,  "dsp-uart1-tx");
 255LN2_PIN_MUX(DSP_UART2_RX,  "dsp-uart2-rx");
 256LN2_PIN_MUX(DSP_UART2_TX,  "dsp-uart2-tx");
 257LN2_PIN_MUX(GF_UART2_RX,   "gf-uart2-rx");
 258LN2_PIN_MUX(GF_UART2_TX,   "gf-uart2-tx");
 259LN2_PIN_MUX(USB_UART_RX,   "usb-uart-rx");
 260LN2_PIN_MUX(CDC_PDMCLK1,   "codec-pdmclk1");
 261LN2_PIN_MUX(CDC_PDMDAT1,   "codec-pdmdat1");
 262LN2_PIN_MUX(CDC_PDMCLK2,   "codec-pdmclk2");
 263LN2_PIN_MUX(CDC_PDMDAT2,   "codec-pdmdat2");
 264LN2_PIN_MUX(CDC_DMICCLK1,  "codec-dmicclk1");
 265LN2_PIN_MUX(CDC_DMICDAT1,  "codec-dmicdat1");
 266LN2_PIN_MUX(CDC_DMICCLK2,  "codec-dmicclk2");
 267LN2_PIN_MUX(CDC_DMICDAT2,  "codec-dmicdat2");
 268LN2_PIN_MUX(CDC_DMICCLK3,  "codec-dmicclk3");
 269LN2_PIN_MUX(CDC_DMICDAT3,  "codec-dmicdat3");
 270LN2_PIN_MUX(CDC_DMICCLK4,  "codec-dmicclk4");
 271LN2_PIN_MUX(CDC_DMICDAT4,  "codec-dmicdat4");
 272LN2_PIN_MUX(DSP_DMICCLK1,  "dsp-dmicclk1");
 273LN2_PIN_MUX(DSP_DMICDAT1,  "dsp-dmicdat1");
 274LN2_PIN_MUX(DSP_DMICCLK2,  "dsp-dmicclk2");
 275LN2_PIN_MUX(DSP_DMICDAT2,  "dsp-dmicdat2");
 276LN2_PIN_MUX(I2C2_SCL,      "i2c2-scl");
 277LN2_PIN_MUX(I2C2_SDA,      "i2c2-sda");
 278LN2_PIN_MUX(I2C3_SCL,      "i2c3-scl");
 279LN2_PIN_MUX(I2C3_SDA,      "i2c3-sda");
 280LN2_PIN_MUX(I2C4_SCL,      "i2c4-scl");
 281LN2_PIN_MUX(I2C4_SDA,      "i2c4-sda");
 282LN2_PIN_MUX(DSP_STANDBY,   "dsp-standby");
 283LN2_PIN_MUX(CDC_MCLK1,     "codec-mclk1");
 284LN2_PIN_MUX(CDC_MCLK2,     "codec-mclk2");
 285LN2_PIN_MUX(DSP_CLKIN,     "dsp-clkin");
 286LN2_PIN_MUX(PSIA1_MCLK,    "psia1-mclk");
 287LN2_PIN_MUX(PSIA2_MCLK,    "psia2-mclk");
 288LN2_PIN_MUX(GF_GPIO1,      "gf-gpio1");
 289LN2_PIN_MUX(GF_GPIO5,      "gf-gpio5");
 290LN2_PIN_MUX(DSP_GPIO20,    "dsp-gpio20");
 291LN2_PIN_GAI(CDC_AIF1);
 292LN2_PIN_GAI(CDC_AIF2);
 293LN2_PIN_GAI(CDC_AIF3);
 294LN2_PIN_GAI(DSP_AIF1);
 295LN2_PIN_GAI(DSP_AIF2);
 296LN2_PIN_GAI(PSIA1);
 297LN2_PIN_GAI(PSIA2);
 298LN2_PIN_GAI(GF_AIF1);
 299LN2_PIN_GAI(GF_AIF2);
 300LN2_PIN_GAI(GF_AIF3);
 301LN2_PIN_GAI(GF_AIF4);
 302LN2_PIN_AIF(SPDIF_AIF);
 303LN2_PIN_AIF(USB_AIF1);
 304LN2_PIN_AIF(USB_AIF2);
 305LN2_PIN_AIF(ADAT_AIF);
 306LN2_PIN_AIF(SOUNDCARD_AIF);
 307
 308static const struct pinctrl_pin_desc lochnagar1_pins[] = {
 309	LN1_PIN(CDC_RESET),      LN1_PIN(DSP_RESET),    LN1_PIN(CDC_CIF1MODE),
 310	LN1_PIN(GF_GPIO2),       LN1_PIN(GF_GPIO3),     LN1_PIN(GF_GPIO7),
 311	LN1_PIN(LED1),           LN1_PIN(LED2),
 312	LN1_PINS(CDC_AIF1),      LN1_PINS(CDC_AIF2),    LN1_PINS(CDC_AIF3),
 313	LN1_PINS(DSP_AIF1),      LN1_PINS(DSP_AIF2),
 314	LN1_PINS(PSIA1),         LN1_PINS(PSIA2),
 315	LN1_PINS(SPDIF_AIF),
 316	LN1_PINS(GF_AIF1),       LN1_PINS(GF_AIF2),
 317	LN1_PINS(GF_AIF3),       LN1_PINS(GF_AIF4),
 318};
 319
 320static const struct pinctrl_pin_desc lochnagar2_pins[] = {
 321	LN2_PIN(CDC_RESET),      LN2_PIN(DSP_RESET),    LN2_PIN(CDC_CIF1MODE),
 322	LN2_PIN(CDC_LDOENA),
 323	LN2_PIN(SPDIF_HWMODE),   LN2_PIN(SPDIF_RESET),
 324	LN2_PIN(FPGA_GPIO1),     LN2_PIN(FPGA_GPIO2),   LN2_PIN(FPGA_GPIO3),
 325	LN2_PIN(FPGA_GPIO4),     LN2_PIN(FPGA_GPIO5),   LN2_PIN(FPGA_GPIO6),
 326	LN2_PIN(CDC_GPIO1),      LN2_PIN(CDC_GPIO2),    LN2_PIN(CDC_GPIO3),
 327	LN2_PIN(CDC_GPIO4),      LN2_PIN(CDC_GPIO5),    LN2_PIN(CDC_GPIO6),
 328	LN2_PIN(CDC_GPIO7),      LN2_PIN(CDC_GPIO8),
 329	LN2_PIN(DSP_GPIO1),      LN2_PIN(DSP_GPIO2),    LN2_PIN(DSP_GPIO3),
 330	LN2_PIN(DSP_GPIO4),      LN2_PIN(DSP_GPIO5),    LN2_PIN(DSP_GPIO6),
 331	LN2_PIN(DSP_GPIO20),
 332	LN2_PIN(GF_GPIO1),       LN2_PIN(GF_GPIO2),     LN2_PIN(GF_GPIO3),
 333	LN2_PIN(GF_GPIO5),       LN2_PIN(GF_GPIO7),
 334	LN2_PINS(CDC_AIF1),      LN2_PINS(CDC_AIF2),    LN2_PINS(CDC_AIF3),
 335	LN2_PINS(DSP_AIF1),      LN2_PINS(DSP_AIF2),
 336	LN2_PINS(PSIA1),         LN2_PINS(PSIA2),
 337	LN2_PINS(GF_AIF1),       LN2_PINS(GF_AIF2),
 338	LN2_PINS(GF_AIF3),       LN2_PINS(GF_AIF4),
 339	LN2_PIN(DSP_UART1_RX),   LN2_PIN(DSP_UART1_TX),
 340	LN2_PIN(DSP_UART2_RX),   LN2_PIN(DSP_UART2_TX),
 341	LN2_PIN(GF_UART2_RX),    LN2_PIN(GF_UART2_TX),
 342	LN2_PIN(USB_UART_RX),
 343	LN2_PIN(CDC_PDMCLK1),    LN2_PIN(CDC_PDMDAT1),
 344	LN2_PIN(CDC_PDMCLK2),    LN2_PIN(CDC_PDMDAT2),
 345	LN2_PIN(CDC_DMICCLK1),   LN2_PIN(CDC_DMICDAT1),
 346	LN2_PIN(CDC_DMICCLK2),   LN2_PIN(CDC_DMICDAT2),
 347	LN2_PIN(CDC_DMICCLK3),   LN2_PIN(CDC_DMICDAT3),
 348	LN2_PIN(CDC_DMICCLK4),   LN2_PIN(CDC_DMICDAT4),
 349	LN2_PIN(DSP_DMICCLK1),   LN2_PIN(DSP_DMICDAT1),
 350	LN2_PIN(DSP_DMICCLK2),   LN2_PIN(DSP_DMICDAT2),
 351	LN2_PIN(I2C2_SCL),       LN2_PIN(I2C2_SDA),
 352	LN2_PIN(I2C3_SCL),       LN2_PIN(I2C3_SDA),
 353	LN2_PIN(I2C4_SCL),       LN2_PIN(I2C4_SDA),
 354	LN2_PIN(DSP_STANDBY),
 355	LN2_PIN(CDC_MCLK1),      LN2_PIN(CDC_MCLK2),
 356	LN2_PIN(DSP_CLKIN),
 357	LN2_PIN(PSIA1_MCLK),     LN2_PIN(PSIA2_MCLK),
 358	LN2_PINS(SPDIF_AIF),
 359	LN2_PINS(USB_AIF1),      LN2_PINS(USB_AIF2),
 360	LN2_PINS(ADAT_AIF),
 361	LN2_PINS(SOUNDCARD_AIF),
 362};
 363
 364#define LN_AIF_PINS(REV, ID) \
 365	LOCHNAGAR##REV##_PIN_##ID##_BCLK, \
 366	LOCHNAGAR##REV##_PIN_##ID##_LRCLK, \
 367	LOCHNAGAR##REV##_PIN_##ID##_TXDAT, \
 368	LOCHNAGAR##REV##_PIN_##ID##_RXDAT,
 369
 370#define LN1_AIF(ID, CTRL) \
 371static const struct lochnagar_aif lochnagar1_##ID##_aif = { \
 372	.name = LN_##ID##_STR, \
 373	.pins = { LN_AIF_PINS(1, ID) }, \
 374	.src_reg = LOCHNAGAR1_##ID##_SEL, \
 375	.src_mask = LOCHNAGAR1_SRC_MASK, \
 376	.ctrl_reg = LOCHNAGAR1_##CTRL, \
 377	.ena_mask = LOCHNAGAR1_##ID##_ENA_MASK, \
 378	.master_mask = LOCHNAGAR1_##ID##_LRCLK_DIR_MASK | \
 379		       LOCHNAGAR1_##ID##_BCLK_DIR_MASK, \
 380}
 381
 382#define LN2_AIF(ID) \
 383static const struct lochnagar_aif lochnagar2_##ID##_aif = { \
 384	.name = LN_##ID##_STR, \
 385	.pins = { LN_AIF_PINS(2, ID) }, \
 386	.src_reg = LOCHNAGAR2_##ID##_CTRL,  \
 387	.src_mask = LOCHNAGAR2_AIF_SRC_MASK, \
 388	.ctrl_reg = LOCHNAGAR2_##ID##_CTRL, \
 389	.ena_mask = LOCHNAGAR2_AIF_ENA_MASK, \
 390	.master_mask = LOCHNAGAR2_AIF_LRCLK_DIR_MASK | \
 391		       LOCHNAGAR2_AIF_BCLK_DIR_MASK, \
 392}
 393
 394struct lochnagar_aif {
 395	const char name[16];
 396
 397	unsigned int pins[4];
 398
 399	u16 src_reg;
 400	u16 src_mask;
 401
 402	u16 ctrl_reg;
 403	u16 ena_mask;
 404	u16 master_mask;
 405};
 406
 407LN1_AIF(CDC_AIF1,      CDC_AIF_CTRL1);
 408LN1_AIF(CDC_AIF2,      CDC_AIF_CTRL1);
 409LN1_AIF(CDC_AIF3,      CDC_AIF_CTRL2);
 410LN1_AIF(DSP_AIF1,      DSP_AIF);
 411LN1_AIF(DSP_AIF2,      DSP_AIF);
 412LN1_AIF(PSIA1,         PSIA_AIF);
 413LN1_AIF(PSIA2,         PSIA_AIF);
 414LN1_AIF(GF_AIF1,       GF_AIF1);
 415LN1_AIF(GF_AIF2,       GF_AIF2);
 416LN1_AIF(GF_AIF3,       GF_AIF1);
 417LN1_AIF(GF_AIF4,       GF_AIF2);
 418LN1_AIF(SPDIF_AIF,     EXT_AIF_CTRL);
 419
 420LN2_AIF(CDC_AIF1);
 421LN2_AIF(CDC_AIF2);
 422LN2_AIF(CDC_AIF3);
 423LN2_AIF(DSP_AIF1);
 424LN2_AIF(DSP_AIF2);
 425LN2_AIF(PSIA1);
 426LN2_AIF(PSIA2);
 427LN2_AIF(GF_AIF1);
 428LN2_AIF(GF_AIF2);
 429LN2_AIF(GF_AIF3);
 430LN2_AIF(GF_AIF4);
 431LN2_AIF(SPDIF_AIF);
 432LN2_AIF(USB_AIF1);
 433LN2_AIF(USB_AIF2);
 434LN2_AIF(ADAT_AIF);
 435LN2_AIF(SOUNDCARD_AIF);
 436
 437#define LN2_OP_AIF	0x00
 438#define LN2_OP_GPIO	0xFE
 439
 440#define LN_FUNC(NAME, TYPE, OP) \
 441	{ .name = NAME, .type = LN_FTYPE_##TYPE, .op = OP }
 442
 443#define LN_FUNC_PIN(REV, ID, OP) \
 444	LN_FUNC(lochnagar##REV##_##ID##_pin.name, PIN, OP)
 445
 446#define LN1_FUNC_PIN(ID, OP) LN_FUNC_PIN(1, ID, OP)
 447#define LN2_FUNC_PIN(ID, OP) LN_FUNC_PIN(2, ID, OP)
 448
 449#define LN_FUNC_AIF(REV, ID, OP) \
 450	LN_FUNC(lochnagar##REV##_##ID##_aif.name, AIF, OP)
 451
 452#define LN1_FUNC_AIF(ID, OP) LN_FUNC_AIF(1, ID, OP)
 453#define LN2_FUNC_AIF(ID, OP) LN_FUNC_AIF(2, ID, OP)
 454
 455#define LN2_FUNC_GAI(ID, OP, BOP, LROP, RXOP, TXOP) \
 456	LN2_FUNC_AIF(ID, OP), \
 457	LN_FUNC(lochnagar2_##ID##_BCLK_pin.name, PIN, BOP), \
 458	LN_FUNC(lochnagar2_##ID##_LRCLK_pin.name, PIN, LROP), \
 459	LN_FUNC(lochnagar2_##ID##_RXDAT_pin.name, PIN, RXOP), \
 460	LN_FUNC(lochnagar2_##ID##_TXDAT_pin.name, PIN, TXOP)
 461
 462enum lochnagar_func_type {
 463	LN_FTYPE_PIN,
 464	LN_FTYPE_AIF,
 465	LN_FTYPE_COUNT,
 466};
 467
 468struct lochnagar_func {
 469	const char * const name;
 470
 471	enum lochnagar_func_type type;
 472
 473	u8 op;
 474};
 475
 476static const struct lochnagar_func lochnagar1_funcs[] = {
 477	LN_FUNC("dsp-gpio1",       PIN, 0x01),
 478	LN_FUNC("dsp-gpio2",       PIN, 0x02),
 479	LN_FUNC("dsp-gpio3",       PIN, 0x03),
 480	LN_FUNC("codec-gpio1",     PIN, 0x04),
 481	LN_FUNC("codec-gpio2",     PIN, 0x05),
 482	LN_FUNC("codec-gpio3",     PIN, 0x06),
 483	LN_FUNC("codec-gpio4",     PIN, 0x07),
 484	LN_FUNC("codec-gpio5",     PIN, 0x08),
 485	LN_FUNC("codec-gpio6",     PIN, 0x09),
 486	LN_FUNC("codec-gpio7",     PIN, 0x0A),
 487	LN_FUNC("codec-gpio8",     PIN, 0x0B),
 488	LN1_FUNC_PIN(GF_GPIO2,          0x0C),
 489	LN1_FUNC_PIN(GF_GPIO3,          0x0D),
 490	LN1_FUNC_PIN(GF_GPIO7,          0x0E),
 491
 492	LN1_FUNC_AIF(SPDIF_AIF,         0x01),
 493	LN1_FUNC_AIF(PSIA1,             0x02),
 494	LN1_FUNC_AIF(PSIA2,             0x03),
 495	LN1_FUNC_AIF(CDC_AIF1,          0x04),
 496	LN1_FUNC_AIF(CDC_AIF2,          0x05),
 497	LN1_FUNC_AIF(CDC_AIF3,          0x06),
 498	LN1_FUNC_AIF(DSP_AIF1,          0x07),
 499	LN1_FUNC_AIF(DSP_AIF2,          0x08),
 500	LN1_FUNC_AIF(GF_AIF3,           0x09),
 501	LN1_FUNC_AIF(GF_AIF4,           0x0A),
 502	LN1_FUNC_AIF(GF_AIF1,           0x0B),
 503	LN1_FUNC_AIF(GF_AIF2,           0x0C),
 504};
 505
 506static const struct lochnagar_func lochnagar2_funcs[] = {
 507	LN_FUNC("aif",             PIN, LN2_OP_AIF),
 508	LN2_FUNC_PIN(FPGA_GPIO1,        0x01),
 509	LN2_FUNC_PIN(FPGA_GPIO2,        0x02),
 510	LN2_FUNC_PIN(FPGA_GPIO3,        0x03),
 511	LN2_FUNC_PIN(FPGA_GPIO4,        0x04),
 512	LN2_FUNC_PIN(FPGA_GPIO5,        0x05),
 513	LN2_FUNC_PIN(FPGA_GPIO6,        0x06),
 514	LN2_FUNC_PIN(CDC_GPIO1,         0x07),
 515	LN2_FUNC_PIN(CDC_GPIO2,         0x08),
 516	LN2_FUNC_PIN(CDC_GPIO3,         0x09),
 517	LN2_FUNC_PIN(CDC_GPIO4,         0x0A),
 518	LN2_FUNC_PIN(CDC_GPIO5,         0x0B),
 519	LN2_FUNC_PIN(CDC_GPIO6,         0x0C),
 520	LN2_FUNC_PIN(CDC_GPIO7,         0x0D),
 521	LN2_FUNC_PIN(CDC_GPIO8,         0x0E),
 522	LN2_FUNC_PIN(DSP_GPIO1,         0x0F),
 523	LN2_FUNC_PIN(DSP_GPIO2,         0x10),
 524	LN2_FUNC_PIN(DSP_GPIO3,         0x11),
 525	LN2_FUNC_PIN(DSP_GPIO4,         0x12),
 526	LN2_FUNC_PIN(DSP_GPIO5,         0x13),
 527	LN2_FUNC_PIN(DSP_GPIO6,         0x14),
 528	LN2_FUNC_PIN(GF_GPIO2,          0x15),
 529	LN2_FUNC_PIN(GF_GPIO3,          0x16),
 530	LN2_FUNC_PIN(GF_GPIO7,          0x17),
 531	LN2_FUNC_PIN(GF_GPIO1,          0x18),
 532	LN2_FUNC_PIN(GF_GPIO5,          0x19),
 533	LN2_FUNC_PIN(DSP_GPIO20,        0x1A),
 534	LN_FUNC("codec-clkout",    PIN, 0x20),
 535	LN_FUNC("dsp-clkout",      PIN, 0x21),
 536	LN_FUNC("pmic-32k",        PIN, 0x22),
 537	LN_FUNC("spdif-clkout",    PIN, 0x23),
 538	LN_FUNC("clk-12m288",      PIN, 0x24),
 539	LN_FUNC("clk-11m2986",     PIN, 0x25),
 540	LN_FUNC("clk-24m576",      PIN, 0x26),
 541	LN_FUNC("clk-22m5792",     PIN, 0x27),
 542	LN_FUNC("xmos-mclk",       PIN, 0x29),
 543	LN_FUNC("gf-clkout1",      PIN, 0x2A),
 544	LN_FUNC("gf-mclk1",        PIN, 0x2B),
 545	LN_FUNC("gf-mclk3",        PIN, 0x2C),
 546	LN_FUNC("gf-mclk2",        PIN, 0x2D),
 547	LN_FUNC("gf-clkout2",      PIN, 0x2E),
 548	LN2_FUNC_PIN(CDC_MCLK1,         0x2F),
 549	LN2_FUNC_PIN(CDC_MCLK2,         0x30),
 550	LN2_FUNC_PIN(DSP_CLKIN,         0x31),
 551	LN2_FUNC_PIN(PSIA1_MCLK,        0x32),
 552	LN2_FUNC_PIN(PSIA2_MCLK,        0x33),
 553	LN_FUNC("spdif-mclk",      PIN, 0x34),
 554	LN_FUNC("codec-irq",       PIN, 0x42),
 555	LN2_FUNC_PIN(CDC_RESET,         0x43),
 556	LN2_FUNC_PIN(DSP_RESET,         0x44),
 557	LN_FUNC("dsp-irq",         PIN, 0x45),
 558	LN2_FUNC_PIN(DSP_STANDBY,       0x46),
 559	LN2_FUNC_PIN(CDC_PDMCLK1,       0x90),
 560	LN2_FUNC_PIN(CDC_PDMDAT1,       0x91),
 561	LN2_FUNC_PIN(CDC_PDMCLK2,       0x92),
 562	LN2_FUNC_PIN(CDC_PDMDAT2,       0x93),
 563	LN2_FUNC_PIN(CDC_DMICCLK1,      0xA0),
 564	LN2_FUNC_PIN(CDC_DMICDAT1,      0xA1),
 565	LN2_FUNC_PIN(CDC_DMICCLK2,      0xA2),
 566	LN2_FUNC_PIN(CDC_DMICDAT2,      0xA3),
 567	LN2_FUNC_PIN(CDC_DMICCLK3,      0xA4),
 568	LN2_FUNC_PIN(CDC_DMICDAT3,      0xA5),
 569	LN2_FUNC_PIN(CDC_DMICCLK4,      0xA6),
 570	LN2_FUNC_PIN(CDC_DMICDAT4,      0xA7),
 571	LN2_FUNC_PIN(DSP_DMICCLK1,      0xA8),
 572	LN2_FUNC_PIN(DSP_DMICDAT1,      0xA9),
 573	LN2_FUNC_PIN(DSP_DMICCLK2,      0xAA),
 574	LN2_FUNC_PIN(DSP_DMICDAT2,      0xAB),
 575	LN2_FUNC_PIN(DSP_UART1_RX,      0xC0),
 576	LN2_FUNC_PIN(DSP_UART1_TX,      0xC1),
 577	LN2_FUNC_PIN(DSP_UART2_RX,      0xC2),
 578	LN2_FUNC_PIN(DSP_UART2_TX,      0xC3),
 579	LN2_FUNC_PIN(GF_UART2_RX,       0xC4),
 580	LN2_FUNC_PIN(GF_UART2_TX,       0xC5),
 581	LN2_FUNC_PIN(USB_UART_RX,       0xC6),
 582	LN_FUNC("usb-uart-tx",     PIN, 0xC7),
 583	LN2_FUNC_PIN(I2C2_SCL,          0xE0),
 584	LN2_FUNC_PIN(I2C2_SDA,          0xE1),
 585	LN2_FUNC_PIN(I2C3_SCL,          0xE2),
 586	LN2_FUNC_PIN(I2C3_SDA,          0xE3),
 587	LN2_FUNC_PIN(I2C4_SCL,          0xE4),
 588	LN2_FUNC_PIN(I2C4_SDA,          0xE5),
 589
 590	LN2_FUNC_AIF(SPDIF_AIF,         0x01),
 591	LN2_FUNC_GAI(PSIA1,             0x02, 0x50, 0x51, 0x52, 0x53),
 592	LN2_FUNC_GAI(PSIA2,             0x03, 0x54, 0x55, 0x56, 0x57),
 593	LN2_FUNC_GAI(CDC_AIF1,          0x04, 0x59, 0x5B, 0x5A, 0x58),
 594	LN2_FUNC_GAI(CDC_AIF2,          0x05, 0x5D, 0x5F, 0x5E, 0x5C),
 595	LN2_FUNC_GAI(CDC_AIF3,          0x06, 0x61, 0x62, 0x63, 0x60),
 596	LN2_FUNC_GAI(DSP_AIF1,          0x07, 0x65, 0x67, 0x66, 0x64),
 597	LN2_FUNC_GAI(DSP_AIF2,          0x08, 0x69, 0x6B, 0x6A, 0x68),
 598	LN2_FUNC_GAI(GF_AIF3,           0x09, 0x6D, 0x6F, 0x6C, 0x6E),
 599	LN2_FUNC_GAI(GF_AIF4,           0x0A, 0x71, 0x73, 0x70, 0x72),
 600	LN2_FUNC_GAI(GF_AIF1,           0x0B, 0x75, 0x77, 0x74, 0x76),
 601	LN2_FUNC_GAI(GF_AIF2,           0x0C, 0x79, 0x7B, 0x78, 0x7A),
 602	LN2_FUNC_AIF(USB_AIF1,          0x0D),
 603	LN2_FUNC_AIF(USB_AIF2,          0x0E),
 604	LN2_FUNC_AIF(ADAT_AIF,          0x0F),
 605	LN2_FUNC_AIF(SOUNDCARD_AIF,     0x10),
 606};
 607
 608#define LN_GROUP_PIN(REV, ID) { \
 609	.name = lochnagar##REV##_##ID##_pin.name, \
 610	.type = LN_FTYPE_PIN, \
 611	.pins = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID].number, \
 612	.npins = 1, \
 613	.priv = &lochnagar##REV##_pins[LOCHNAGAR##REV##_PIN_##ID], \
 614}
 615
 616#define LN_GROUP_AIF(REV, ID) { \
 617	.name = lochnagar##REV##_##ID##_aif.name, \
 618	.type = LN_FTYPE_AIF, \
 619	.pins = lochnagar##REV##_##ID##_aif.pins, \
 620	.npins = ARRAY_SIZE(lochnagar##REV##_##ID##_aif.pins), \
 621	.priv = &lochnagar##REV##_##ID##_aif, \
 622}
 623
 624#define LN1_GROUP_PIN(ID) LN_GROUP_PIN(1, ID)
 625#define LN2_GROUP_PIN(ID) LN_GROUP_PIN(2, ID)
 626
 627#define LN1_GROUP_AIF(ID) LN_GROUP_AIF(1, ID)
 628#define LN2_GROUP_AIF(ID) LN_GROUP_AIF(2, ID)
 629
 630#define LN2_GROUP_GAI(ID) \
 631	LN2_GROUP_AIF(ID), \
 632	LN2_GROUP_PIN(ID##_BCLK), LN2_GROUP_PIN(ID##_LRCLK), \
 633	LN2_GROUP_PIN(ID##_RXDAT), LN2_GROUP_PIN(ID##_TXDAT)
 634
 635struct lochnagar_group {
 636	const char * const name;
 637
 638	enum lochnagar_func_type type;
 639
 640	const unsigned int *pins;
 641	unsigned int npins;
 642
 643	const void *priv;
 644};
 645
 646static const struct lochnagar_group lochnagar1_groups[] = {
 647	LN1_GROUP_PIN(GF_GPIO2),       LN1_GROUP_PIN(GF_GPIO3),
 648	LN1_GROUP_PIN(GF_GPIO7),
 649	LN1_GROUP_PIN(LED1),           LN1_GROUP_PIN(LED2),
 650	LN1_GROUP_AIF(CDC_AIF1),       LN1_GROUP_AIF(CDC_AIF2),
 651	LN1_GROUP_AIF(CDC_AIF3),
 652	LN1_GROUP_AIF(DSP_AIF1),       LN1_GROUP_AIF(DSP_AIF2),
 653	LN1_GROUP_AIF(PSIA1),          LN1_GROUP_AIF(PSIA2),
 654	LN1_GROUP_AIF(GF_AIF1),        LN1_GROUP_AIF(GF_AIF2),
 655	LN1_GROUP_AIF(GF_AIF3),        LN1_GROUP_AIF(GF_AIF4),
 656	LN1_GROUP_AIF(SPDIF_AIF),
 657};
 658
 659static const struct lochnagar_group lochnagar2_groups[] = {
 660	LN2_GROUP_PIN(FPGA_GPIO1),     LN2_GROUP_PIN(FPGA_GPIO2),
 661	LN2_GROUP_PIN(FPGA_GPIO3),     LN2_GROUP_PIN(FPGA_GPIO4),
 662	LN2_GROUP_PIN(FPGA_GPIO5),     LN2_GROUP_PIN(FPGA_GPIO6),
 663	LN2_GROUP_PIN(CDC_GPIO1),      LN2_GROUP_PIN(CDC_GPIO2),
 664	LN2_GROUP_PIN(CDC_GPIO3),      LN2_GROUP_PIN(CDC_GPIO4),
 665	LN2_GROUP_PIN(CDC_GPIO5),      LN2_GROUP_PIN(CDC_GPIO6),
 666	LN2_GROUP_PIN(CDC_GPIO7),      LN2_GROUP_PIN(CDC_GPIO8),
 667	LN2_GROUP_PIN(DSP_GPIO1),      LN2_GROUP_PIN(DSP_GPIO2),
 668	LN2_GROUP_PIN(DSP_GPIO3),      LN2_GROUP_PIN(DSP_GPIO4),
 669	LN2_GROUP_PIN(DSP_GPIO5),      LN2_GROUP_PIN(DSP_GPIO6),
 670	LN2_GROUP_PIN(DSP_GPIO20),
 671	LN2_GROUP_PIN(GF_GPIO1),
 672	LN2_GROUP_PIN(GF_GPIO2),       LN2_GROUP_PIN(GF_GPIO5),
 673	LN2_GROUP_PIN(GF_GPIO3),       LN2_GROUP_PIN(GF_GPIO7),
 674	LN2_GROUP_PIN(DSP_UART1_RX),   LN2_GROUP_PIN(DSP_UART1_TX),
 675	LN2_GROUP_PIN(DSP_UART2_RX),   LN2_GROUP_PIN(DSP_UART2_TX),
 676	LN2_GROUP_PIN(GF_UART2_RX),    LN2_GROUP_PIN(GF_UART2_TX),
 677	LN2_GROUP_PIN(USB_UART_RX),
 678	LN2_GROUP_PIN(CDC_PDMCLK1),    LN2_GROUP_PIN(CDC_PDMDAT1),
 679	LN2_GROUP_PIN(CDC_PDMCLK2),    LN2_GROUP_PIN(CDC_PDMDAT2),
 680	LN2_GROUP_PIN(CDC_DMICCLK1),   LN2_GROUP_PIN(CDC_DMICDAT1),
 681	LN2_GROUP_PIN(CDC_DMICCLK2),   LN2_GROUP_PIN(CDC_DMICDAT2),
 682	LN2_GROUP_PIN(CDC_DMICCLK3),   LN2_GROUP_PIN(CDC_DMICDAT3),
 683	LN2_GROUP_PIN(CDC_DMICCLK4),   LN2_GROUP_PIN(CDC_DMICDAT4),
 684	LN2_GROUP_PIN(DSP_DMICCLK1),   LN2_GROUP_PIN(DSP_DMICDAT1),
 685	LN2_GROUP_PIN(DSP_DMICCLK2),   LN2_GROUP_PIN(DSP_DMICDAT2),
 686	LN2_GROUP_PIN(I2C2_SCL),       LN2_GROUP_PIN(I2C2_SDA),
 687	LN2_GROUP_PIN(I2C3_SCL),       LN2_GROUP_PIN(I2C3_SDA),
 688	LN2_GROUP_PIN(I2C4_SCL),       LN2_GROUP_PIN(I2C4_SDA),
 689	LN2_GROUP_PIN(DSP_STANDBY),
 690	LN2_GROUP_PIN(CDC_MCLK1),      LN2_GROUP_PIN(CDC_MCLK2),
 691	LN2_GROUP_PIN(DSP_CLKIN),
 692	LN2_GROUP_PIN(PSIA1_MCLK),     LN2_GROUP_PIN(PSIA2_MCLK),
 693	LN2_GROUP_GAI(CDC_AIF1),       LN2_GROUP_GAI(CDC_AIF2),
 694	LN2_GROUP_GAI(CDC_AIF3),
 695	LN2_GROUP_GAI(DSP_AIF1),       LN2_GROUP_GAI(DSP_AIF2),
 696	LN2_GROUP_GAI(PSIA1),          LN2_GROUP_GAI(PSIA2),
 697	LN2_GROUP_GAI(GF_AIF1),        LN2_GROUP_GAI(GF_AIF2),
 698	LN2_GROUP_GAI(GF_AIF3),        LN2_GROUP_GAI(GF_AIF4),
 699	LN2_GROUP_AIF(SPDIF_AIF),
 700	LN2_GROUP_AIF(USB_AIF1),       LN2_GROUP_AIF(USB_AIF2),
 701	LN2_GROUP_AIF(ADAT_AIF),
 702	LN2_GROUP_AIF(SOUNDCARD_AIF),
 703};
 704
 705struct lochnagar_func_groups {
 706	const char **groups;
 707	unsigned int ngroups;
 708};
 709
 710struct lochnagar_pin_priv {
 711	struct lochnagar *lochnagar;
 712	struct device *dev;
 713
 714	const struct lochnagar_func *funcs;
 715	unsigned int nfuncs;
 716
 717	const struct pinctrl_pin_desc *pins;
 718	unsigned int npins;
 719
 720	const struct lochnagar_group *groups;
 721	unsigned int ngroups;
 722
 723	struct lochnagar_func_groups func_groups[LN_FTYPE_COUNT];
 724
 725	struct gpio_chip gpio_chip;
 726};
 727
 728static int lochnagar_get_groups_count(struct pinctrl_dev *pctldev)
 729{
 730	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 731
 732	return priv->ngroups;
 733}
 734
 735static const char *lochnagar_get_group_name(struct pinctrl_dev *pctldev,
 736					    unsigned int group_idx)
 737{
 738	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 739
 740	return priv->groups[group_idx].name;
 741}
 742
 743static int lochnagar_get_group_pins(struct pinctrl_dev *pctldev,
 744				    unsigned int group_idx,
 745				    const unsigned int **pins,
 746				    unsigned int *num_pins)
 747{
 748	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 749
 750	*pins = priv->groups[group_idx].pins;
 751	*num_pins = priv->groups[group_idx].npins;
 752
 753	return 0;
 754}
 755
 756static const struct pinctrl_ops lochnagar_pin_group_ops = {
 757	.get_groups_count = lochnagar_get_groups_count,
 758	.get_group_name = lochnagar_get_group_name,
 759	.get_group_pins = lochnagar_get_group_pins,
 760	.dt_node_to_map = pinconf_generic_dt_node_to_map_all,
 761	.dt_free_map = pinctrl_utils_free_map,
 762};
 763
 764static int lochnagar_get_funcs_count(struct pinctrl_dev *pctldev)
 765{
 766	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 767
 768	return priv->nfuncs;
 769}
 770
 771static const char *lochnagar_get_func_name(struct pinctrl_dev *pctldev,
 772					   unsigned int func_idx)
 773{
 774	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 775
 776	return priv->funcs[func_idx].name;
 777}
 778
 779static int lochnagar_get_func_groups(struct pinctrl_dev *pctldev,
 780				     unsigned int func_idx,
 781				     const char * const **groups,
 782				     unsigned int * const num_groups)
 783{
 784	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 785	int func_type;
 786
 787	func_type = priv->funcs[func_idx].type;
 788
 789	*groups = priv->func_groups[func_type].groups;
 790	*num_groups = priv->func_groups[func_type].ngroups;
 791
 792	return 0;
 793}
 794
 795static int lochnagar2_get_gpio_chan(struct lochnagar_pin_priv *priv,
 796				    unsigned int op)
 797{
 798	struct regmap *regmap = priv->lochnagar->regmap;
 799	unsigned int val;
 800	int free = -1;
 801	int i, ret;
 802
 803	for (i = 0; i < LN2_NUM_GPIO_CHANNELS; i++) {
 804		ret = regmap_read(regmap, LOCHNAGAR2_GPIO_CHANNEL1 + i, &val);
 805		if (ret)
 806			return ret;
 807
 808		val &= LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK;
 809
 810		if (val == op)
 811			return i + 1;
 812
 813		if (free < 0 && !val)
 814			free = i;
 815	}
 816
 817	if (free >= 0) {
 818		ret = regmap_update_bits(regmap,
 819					 LOCHNAGAR2_GPIO_CHANNEL1 + free,
 820					 LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK, op);
 821		if (ret)
 822			return ret;
 823
 824		free++;
 825
 826		dev_dbg(priv->dev, "Set channel %d to 0x%x\n", free, op);
 827
 828		return free;
 829	}
 830
 831	return -ENOSPC;
 832}
 833
 834static int lochnagar_pin_set_mux(struct lochnagar_pin_priv *priv,
 835				 const struct lochnagar_pin *pin,
 836				 unsigned int op)
 837{
 838	int ret;
 839
 840	switch (priv->lochnagar->type) {
 841	case LOCHNAGAR1:
 842		break;
 843	default:
 844		ret = lochnagar2_get_gpio_chan(priv, op);
 845		if (ret < 0) {
 846			dev_err(priv->dev, "Failed to get channel for %s: %d\n",
 847				pin->name, ret);
 848			return ret;
 849		}
 850
 851		op = ret;
 852		break;
 853	}
 854
 855	dev_dbg(priv->dev, "Set pin %s to 0x%x\n", pin->name, op);
 856
 857	ret = regmap_write(priv->lochnagar->regmap, pin->reg, op);
 858	if (ret)
 859		dev_err(priv->dev, "Failed to set %s mux: %d\n",
 860			pin->name, ret);
 861
 862	return 0;
 863}
 864
 865static int lochnagar_aif_set_mux(struct lochnagar_pin_priv *priv,
 866				 const struct lochnagar_group *group,
 867				 unsigned int op)
 868{
 869	struct regmap *regmap = priv->lochnagar->regmap;
 870	const struct lochnagar_aif *aif = group->priv;
 871	const struct lochnagar_pin *pin;
 872	int i, ret;
 873
 874	ret = regmap_update_bits(regmap, aif->src_reg, aif->src_mask, op);
 875	if (ret) {
 876		dev_err(priv->dev, "Failed to set %s source: %d\n",
 877			group->name, ret);
 878		return ret;
 879	}
 880
 881	ret = regmap_update_bits(regmap, aif->ctrl_reg,
 882				 aif->ena_mask, aif->ena_mask);
 883	if (ret) {
 884		dev_err(priv->dev, "Failed to set %s enable: %d\n",
 885			group->name, ret);
 886		return ret;
 887	}
 888
 889	for (i = 0; i < group->npins; i++) {
 890		pin = priv->pins[group->pins[i]].drv_data;
 891
 892		if (pin->type != LN_PTYPE_MUX)
 893			continue;
 894
 895		dev_dbg(priv->dev, "Set pin %s to AIF\n", pin->name);
 896
 897		ret = regmap_update_bits(regmap, pin->reg,
 898					 LOCHNAGAR2_GPIO_SRC_MASK,
 899					 LN2_OP_AIF);
 900		if (ret) {
 901			dev_err(priv->dev, "Failed to set %s to AIF: %d\n",
 902				pin->name, ret);
 903			return ret;
 904		}
 905	}
 906
 907	return 0;
 908}
 909
 910static int lochnagar_set_mux(struct pinctrl_dev *pctldev,
 911			     unsigned int func_idx, unsigned int group_idx)
 912{
 913	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 914	const struct lochnagar_func *func = &priv->funcs[func_idx];
 915	const struct lochnagar_group *group = &priv->groups[group_idx];
 916	const struct lochnagar_pin *pin;
 917
 918	switch (func->type) {
 919	case LN_FTYPE_AIF:
 920		dev_dbg(priv->dev, "Set group %s to %s\n",
 921			group->name, func->name);
 922
 923		return lochnagar_aif_set_mux(priv, group, func->op);
 924	case LN_FTYPE_PIN:
 925		pin = priv->pins[*group->pins].drv_data;
 926
 927		dev_dbg(priv->dev, "Set pin %s to %s\n", pin->name, func->name);
 928
 929		return lochnagar_pin_set_mux(priv, pin, func->op);
 930	default:
 931		return -EINVAL;
 932	}
 933}
 934
 935static int lochnagar_gpio_request(struct pinctrl_dev *pctldev,
 936				  struct pinctrl_gpio_range *range,
 937				  unsigned int offset)
 938{
 939	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
 940	struct lochnagar *lochnagar = priv->lochnagar;
 941	const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
 942	int ret;
 943
 944	dev_dbg(priv->dev, "Requesting GPIO %s\n", pin->name);
 945
 946	if (lochnagar->type == LOCHNAGAR1 || pin->type != LN_PTYPE_MUX)
 947		return 0;
 948
 949	ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO);
 950	if (ret < 0) {
 951		dev_err(priv->dev, "Failed to get low channel: %d\n", ret);
 952		return ret;
 953	}
 954
 955	ret = lochnagar2_get_gpio_chan(priv, LN2_OP_GPIO | 0x1);
 956	if (ret < 0) {
 957		dev_err(priv->dev, "Failed to get high channel: %d\n", ret);
 958		return ret;
 959	}
 960
 961	return 0;
 962}
 963
 964static int lochnagar_gpio_set_direction(struct pinctrl_dev *pctldev,
 965					struct pinctrl_gpio_range *range,
 966					unsigned int offset,
 967					bool input)
 968{
 969	/* The GPIOs only support output */
 970	if (input)
 971		return -EINVAL;
 972
 973	return 0;
 974}
 975
 976static const struct pinmux_ops lochnagar_pin_mux_ops = {
 977	.get_functions_count = lochnagar_get_funcs_count,
 978	.get_function_name = lochnagar_get_func_name,
 979	.get_function_groups = lochnagar_get_func_groups,
 980	.set_mux = lochnagar_set_mux,
 981
 982	.gpio_request_enable = lochnagar_gpio_request,
 983	.gpio_set_direction = lochnagar_gpio_set_direction,
 984
 985	.strict = true,
 986};
 987
 988static int lochnagar_aif_set_master(struct lochnagar_pin_priv *priv,
 989				    unsigned int group_idx, bool master)
 990{
 991	struct regmap *regmap = priv->lochnagar->regmap;
 992	const struct lochnagar_group *group = &priv->groups[group_idx];
 993	const struct lochnagar_aif *aif = group->priv;
 994	unsigned int val = 0;
 995	int ret;
 996
 997	if (group->type != LN_FTYPE_AIF)
 998		return -EINVAL;
 999
1000	if (!master)
1001		val = aif->master_mask;
1002
1003	dev_dbg(priv->dev, "Set AIF %s to %s\n",
1004		group->name, master ? "master" : "slave");
1005
1006	ret = regmap_update_bits(regmap, aif->ctrl_reg, aif->master_mask, val);
1007	if (ret) {
1008		dev_err(priv->dev, "Failed to set %s mode: %d\n",
1009			group->name, ret);
1010		return ret;
1011	}
1012
1013	return 0;
1014}
1015
1016static int lochnagar_conf_group_set(struct pinctrl_dev *pctldev,
1017				    unsigned int group_idx,
1018				    unsigned long *configs,
1019				    unsigned int num_configs)
1020{
1021	struct lochnagar_pin_priv *priv = pinctrl_dev_get_drvdata(pctldev);
1022	int i, ret;
1023
1024	for (i = 0; i < num_configs; i++) {
1025		unsigned int param = pinconf_to_config_param(*configs);
1026
1027		switch (param) {
1028		case PIN_CONFIG_OUTPUT_ENABLE:
1029			ret = lochnagar_aif_set_master(priv, group_idx, true);
1030			if (ret)
1031				return ret;
1032			break;
1033		case PIN_CONFIG_INPUT_ENABLE:
1034			ret = lochnagar_aif_set_master(priv, group_idx, false);
1035			if (ret)
1036				return ret;
1037			break;
1038		default:
1039			return -ENOTSUPP;
1040		}
1041
1042		configs++;
1043	}
1044
1045	return 0;
1046}
1047
1048static const struct pinconf_ops lochnagar_pin_conf_ops = {
1049	.pin_config_group_set = lochnagar_conf_group_set,
1050};
1051
1052static const struct pinctrl_desc lochnagar_pin_desc = {
1053	.name = "lochnagar-pinctrl",
1054	.owner = THIS_MODULE,
1055
1056	.pctlops = &lochnagar_pin_group_ops,
1057	.pmxops = &lochnagar_pin_mux_ops,
1058	.confops = &lochnagar_pin_conf_ops,
1059};
1060
1061static int lochnagar_gpio_set(struct gpio_chip *chip,
1062			      unsigned int offset, int value)
1063{
1064	struct lochnagar_pin_priv *priv = gpiochip_get_data(chip);
1065	struct lochnagar *lochnagar = priv->lochnagar;
1066	const struct lochnagar_pin *pin = priv->pins[offset].drv_data;
1067
1068	value = !!value;
1069
1070	dev_dbg(priv->dev, "Set GPIO %s to %s\n",
1071		pin->name, str_high_low(value));
1072
1073	switch (pin->type) {
1074	case LN_PTYPE_MUX:
1075		value |= LN2_OP_GPIO;
1076
1077		return lochnagar_pin_set_mux(priv, pin, value);
1078		break;
1079	case LN_PTYPE_GPIO:
1080		if (pin->invert)
1081			value = !value;
1082
1083		return regmap_update_bits(lochnagar->regmap, pin->reg,
1084					  BIT(pin->shift),
1085					  value << pin->shift);
1086		break;
1087	default:
1088		break;
1089	}
1090
1091	return -EINVAL;
1092}
1093
1094static int lochnagar_gpio_direction_out(struct gpio_chip *chip,
1095					unsigned int offset, int value)
1096{
1097	int ret;
1098
1099	ret = lochnagar_gpio_set(chip, offset, value);
1100	if (ret)
1101		return ret;
1102
1103	return pinctrl_gpio_direction_output(chip, offset);
1104}
1105
1106static int lochnagar_fill_func_groups(struct lochnagar_pin_priv *priv)
1107{
1108	struct lochnagar_func_groups *funcs;
1109	int i;
1110
1111	for (i = 0; i < priv->ngroups; i++)
1112		priv->func_groups[priv->groups[i].type].ngroups++;
1113
1114	for (i = 0; i < LN_FTYPE_COUNT; i++) {
1115		funcs = &priv->func_groups[i];
1116
1117		if (!funcs->ngroups)
1118			continue;
1119
1120		funcs->groups = devm_kcalloc(priv->dev, funcs->ngroups,
1121					     sizeof(*funcs->groups),
1122					     GFP_KERNEL);
1123		if (!funcs->groups)
1124			return -ENOMEM;
1125
1126		funcs->ngroups = 0;
1127	}
1128
1129	for (i = 0; i < priv->ngroups; i++) {
1130		funcs = &priv->func_groups[priv->groups[i].type];
1131
1132		funcs->groups[funcs->ngroups++] = priv->groups[i].name;
1133	}
1134
1135	return 0;
1136}
1137
1138static int lochnagar_pin_probe(struct platform_device *pdev)
1139{
1140	struct lochnagar *lochnagar = dev_get_drvdata(pdev->dev.parent);
1141	struct lochnagar_pin_priv *priv;
1142	struct pinctrl_desc *desc;
1143	struct pinctrl_dev *pctl;
1144	struct device *dev = &pdev->dev;
1145	int ret;
1146
1147	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1148	if (!priv)
1149		return -ENOMEM;
1150
1151	priv->dev = dev;
1152	priv->lochnagar = lochnagar;
1153
1154	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1155	if (!desc)
1156		return -ENOMEM;
1157
1158	*desc = lochnagar_pin_desc;
1159
1160	priv->gpio_chip.label = dev_name(dev);
1161	priv->gpio_chip.request = gpiochip_generic_request;
1162	priv->gpio_chip.free = gpiochip_generic_free;
1163	priv->gpio_chip.direction_output = lochnagar_gpio_direction_out;
1164	priv->gpio_chip.set = lochnagar_gpio_set;
1165	priv->gpio_chip.can_sleep = true;
1166	priv->gpio_chip.parent = dev;
1167	priv->gpio_chip.base = -1;
1168
1169	switch (lochnagar->type) {
1170	case LOCHNAGAR1:
1171		priv->funcs = lochnagar1_funcs;
1172		priv->nfuncs = ARRAY_SIZE(lochnagar1_funcs);
1173		priv->pins = lochnagar1_pins;
1174		priv->npins = ARRAY_SIZE(lochnagar1_pins);
1175		priv->groups = lochnagar1_groups;
1176		priv->ngroups = ARRAY_SIZE(lochnagar1_groups);
1177
1178		priv->gpio_chip.ngpio = LOCHNAGAR1_PIN_NUM_GPIOS;
1179		break;
1180	case LOCHNAGAR2:
1181		priv->funcs = lochnagar2_funcs;
1182		priv->nfuncs = ARRAY_SIZE(lochnagar2_funcs);
1183		priv->pins = lochnagar2_pins;
1184		priv->npins = ARRAY_SIZE(lochnagar2_pins);
1185		priv->groups = lochnagar2_groups;
1186		priv->ngroups = ARRAY_SIZE(lochnagar2_groups);
1187
1188		priv->gpio_chip.ngpio = LOCHNAGAR2_PIN_NUM_GPIOS;
1189		break;
1190	default:
1191		dev_err(dev, "Unknown Lochnagar type: %d\n", lochnagar->type);
1192		return -EINVAL;
1193	}
1194
1195	ret = lochnagar_fill_func_groups(priv);
1196	if (ret < 0)
1197		return ret;
1198
1199	desc->pins = priv->pins;
1200	desc->npins = priv->npins;
1201
1202	pctl = devm_pinctrl_register(dev, desc, priv);
1203	if (IS_ERR(pctl)) {
1204		ret = PTR_ERR(pctl);
1205		dev_err(priv->dev, "Failed to register pinctrl: %d\n", ret);
1206		return ret;
1207	}
1208
1209	ret = devm_gpiochip_add_data(dev, &priv->gpio_chip, priv);
1210	if (ret < 0) {
1211		dev_err(&pdev->dev, "Failed to register gpiochip: %d\n", ret);
1212		return ret;
1213	}
1214
1215	return 0;
1216}
1217
1218static const struct of_device_id lochnagar_of_match[] = {
1219	{ .compatible = "cirrus,lochnagar-pinctrl" },
1220	{}
1221};
1222MODULE_DEVICE_TABLE(of, lochnagar_of_match);
1223
1224static struct platform_driver lochnagar_pin_driver = {
1225	.driver = {
1226		.name = "lochnagar-pinctrl",
1227		.of_match_table = of_match_ptr(lochnagar_of_match),
1228	},
1229
1230	.probe = lochnagar_pin_probe,
1231};
1232module_platform_driver(lochnagar_pin_driver);
1233
1234MODULE_AUTHOR("Charles Keepax <ckeepax@opensource.cirrus.com>");
1235MODULE_DESCRIPTION("Pinctrl driver for Cirrus Logic Lochnagar Board");
1236MODULE_LICENSE("GPL v2");