pinctrl-bcm2835.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
   4 *
   5 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
   6 *
   7 * This driver is inspired by:
   8 * pinctrl-nomadik.c, please see original file for copyright information
   9 * pinctrl-tegra.c, please see original file for copyright information
  10 */
  11
  12#include <linux/bitmap.h>
  13#include <linux/bug.h>
  14#include <linux/delay.h>
  15#include <linux/device.h>
  16#include <linux/err.h>
  17#include <linux/gpio/driver.h>
  18#include <linux/io.h>
  19#include <linux/irq.h>
  20#include <linux/irqdesc.h>
  21#include <linux/init.h>
  22#include <linux/interrupt.h>
  23#include <linux/module.h>
  24#include <linux/of_address.h>
  25#include <linux/of.h>
  26#include <linux/of_irq.h>
  27#include <linux/pinctrl/consumer.h>
  28#include <linux/pinctrl/machine.h>
  29#include <linux/pinctrl/pinconf.h>
  30#include <linux/pinctrl/pinctrl.h>
  31#include <linux/pinctrl/pinmux.h>
  32#include <linux/pinctrl/pinconf-generic.h>
  33#include <linux/platform_device.h>
  34#include <linux/seq_file.h>
  35#include <linux/slab.h>
  36#include <linux/spinlock.h>
  37#include <linux/string_choices.h>
  38#include <linux/types.h>
  39#include <dt-bindings/pinctrl/bcm2835.h>
  40
  41#define MODULE_NAME "pinctrl-bcm2835"
  42#define BCM2835_NUM_GPIOS 54
  43#define BCM2711_NUM_GPIOS 58
  44#define BCM2835_NUM_BANKS 2
  45#define BCM2835_NUM_IRQS  3
  46
  47/* GPIO register offsets */
  48#define GPFSEL0		0x0	/* Function Select */
  49#define GPSET0		0x1c	/* Pin Output Set */
  50#define GPCLR0		0x28	/* Pin Output Clear */
  51#define GPLEV0		0x34	/* Pin Level */
  52#define GPEDS0		0x40	/* Pin Event Detect Status */
  53#define GPREN0		0x4c	/* Pin Rising Edge Detect Enable */
  54#define GPFEN0		0x58	/* Pin Falling Edge Detect Enable */
  55#define GPHEN0		0x64	/* Pin High Detect Enable */
  56#define GPLEN0		0x70	/* Pin Low Detect Enable */
  57#define GPAREN0		0x7c	/* Pin Async Rising Edge Detect */
  58#define GPAFEN0		0x88	/* Pin Async Falling Edge Detect */
  59#define GPPUD		0x94	/* Pin Pull-up/down Enable */
  60#define GPPUDCLK0	0x98	/* Pin Pull-up/down Enable Clock */
  61#define GP_GPIO_PUP_PDN_CNTRL_REG0 0xe4 /* 2711 Pin Pull-up/down select */
  62
  63#define FSEL_REG(p)		(GPFSEL0 + (((p) / 10) * 4))
  64#define FSEL_SHIFT(p)		(((p) % 10) * 3)
  65#define GPIO_REG_OFFSET(p)	((p) / 32)
  66#define GPIO_REG_SHIFT(p)	((p) % 32)
  67
  68#define PUD_2711_MASK		0x3
  69#define PUD_2711_REG_OFFSET(p)	((p) / 16)
  70#define PUD_2711_REG_SHIFT(p)	(((p) % 16) * 2)
  71
  72/* argument: bcm2835_pinconf_pull */
  73#define BCM2835_PINCONF_PARAM_PULL	(PIN_CONFIG_END + 1)
  74
  75#define BCM2711_PULL_NONE	0x0
  76#define BCM2711_PULL_UP		0x1
  77#define BCM2711_PULL_DOWN	0x2
  78
  79struct bcm2835_pinctrl {
  80	struct device *dev;
  81	void __iomem *base;
  82	int *wake_irq;
  83
  84	/* note: locking assumes each bank will have its own unsigned long */
  85	unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
  86	unsigned int irq_type[BCM2711_NUM_GPIOS];
  87
  88	struct pinctrl_dev *pctl_dev;
  89	struct gpio_chip gpio_chip;
  90	struct pinctrl_desc pctl_desc;
  91	struct pinctrl_gpio_range gpio_range;
  92
  93	raw_spinlock_t irq_lock[BCM2835_NUM_BANKS];
  94	/* Protect FSEL registers */
  95	spinlock_t fsel_lock;
  96};
  97
  98/* pins are just named GPIO0..GPIO53 */
  99#define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
 100static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
 101	BCM2835_GPIO_PIN(0),
 102	BCM2835_GPIO_PIN(1),
 103	BCM2835_GPIO_PIN(2),
 104	BCM2835_GPIO_PIN(3),
 105	BCM2835_GPIO_PIN(4),
 106	BCM2835_GPIO_PIN(5),
 107	BCM2835_GPIO_PIN(6),
 108	BCM2835_GPIO_PIN(7),
 109	BCM2835_GPIO_PIN(8),
 110	BCM2835_GPIO_PIN(9),
 111	BCM2835_GPIO_PIN(10),
 112	BCM2835_GPIO_PIN(11),
 113	BCM2835_GPIO_PIN(12),
 114	BCM2835_GPIO_PIN(13),
 115	BCM2835_GPIO_PIN(14),
 116	BCM2835_GPIO_PIN(15),
 117	BCM2835_GPIO_PIN(16),
 118	BCM2835_GPIO_PIN(17),
 119	BCM2835_GPIO_PIN(18),
 120	BCM2835_GPIO_PIN(19),
 121	BCM2835_GPIO_PIN(20),
 122	BCM2835_GPIO_PIN(21),
 123	BCM2835_GPIO_PIN(22),
 124	BCM2835_GPIO_PIN(23),
 125	BCM2835_GPIO_PIN(24),
 126	BCM2835_GPIO_PIN(25),
 127	BCM2835_GPIO_PIN(26),
 128	BCM2835_GPIO_PIN(27),
 129	BCM2835_GPIO_PIN(28),
 130	BCM2835_GPIO_PIN(29),
 131	BCM2835_GPIO_PIN(30),
 132	BCM2835_GPIO_PIN(31),
 133	BCM2835_GPIO_PIN(32),
 134	BCM2835_GPIO_PIN(33),
 135	BCM2835_GPIO_PIN(34),
 136	BCM2835_GPIO_PIN(35),
 137	BCM2835_GPIO_PIN(36),
 138	BCM2835_GPIO_PIN(37),
 139	BCM2835_GPIO_PIN(38),
 140	BCM2835_GPIO_PIN(39),
 141	BCM2835_GPIO_PIN(40),
 142	BCM2835_GPIO_PIN(41),
 143	BCM2835_GPIO_PIN(42),
 144	BCM2835_GPIO_PIN(43),
 145	BCM2835_GPIO_PIN(44),
 146	BCM2835_GPIO_PIN(45),
 147	BCM2835_GPIO_PIN(46),
 148	BCM2835_GPIO_PIN(47),
 149	BCM2835_GPIO_PIN(48),
 150	BCM2835_GPIO_PIN(49),
 151	BCM2835_GPIO_PIN(50),
 152	BCM2835_GPIO_PIN(51),
 153	BCM2835_GPIO_PIN(52),
 154	BCM2835_GPIO_PIN(53),
 155	BCM2835_GPIO_PIN(54),
 156	BCM2835_GPIO_PIN(55),
 157	BCM2835_GPIO_PIN(56),
 158	BCM2835_GPIO_PIN(57),
 159};
 160
 161/* one pin per group */
 162static const char * const bcm2835_gpio_groups[] = {
 163	"gpio0",
 164	"gpio1",
 165	"gpio2",
 166	"gpio3",
 167	"gpio4",
 168	"gpio5",
 169	"gpio6",
 170	"gpio7",
 171	"gpio8",
 172	"gpio9",
 173	"gpio10",
 174	"gpio11",
 175	"gpio12",
 176	"gpio13",
 177	"gpio14",
 178	"gpio15",
 179	"gpio16",
 180	"gpio17",
 181	"gpio18",
 182	"gpio19",
 183	"gpio20",
 184	"gpio21",
 185	"gpio22",
 186	"gpio23",
 187	"gpio24",
 188	"gpio25",
 189	"gpio26",
 190	"gpio27",
 191	"gpio28",
 192	"gpio29",
 193	"gpio30",
 194	"gpio31",
 195	"gpio32",
 196	"gpio33",
 197	"gpio34",
 198	"gpio35",
 199	"gpio36",
 200	"gpio37",
 201	"gpio38",
 202	"gpio39",
 203	"gpio40",
 204	"gpio41",
 205	"gpio42",
 206	"gpio43",
 207	"gpio44",
 208	"gpio45",
 209	"gpio46",
 210	"gpio47",
 211	"gpio48",
 212	"gpio49",
 213	"gpio50",
 214	"gpio51",
 215	"gpio52",
 216	"gpio53",
 217	"gpio54",
 218	"gpio55",
 219	"gpio56",
 220	"gpio57",
 221};
 222
 223enum bcm2835_fsel {
 224	BCM2835_FSEL_COUNT = 8,
 225	BCM2835_FSEL_MASK = 0x7,
 226};
 227
 228static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
 229	[BCM2835_FSEL_GPIO_IN] = "gpio_in",
 230	[BCM2835_FSEL_GPIO_OUT] = "gpio_out",
 231	[BCM2835_FSEL_ALT0] = "alt0",
 232	[BCM2835_FSEL_ALT1] = "alt1",
 233	[BCM2835_FSEL_ALT2] = "alt2",
 234	[BCM2835_FSEL_ALT3] = "alt3",
 235	[BCM2835_FSEL_ALT4] = "alt4",
 236	[BCM2835_FSEL_ALT5] = "alt5",
 237};
 238
 239static const char * const irq_type_names[] = {
 240	[IRQ_TYPE_NONE] = "none",
 241	[IRQ_TYPE_EDGE_RISING] = "edge-rising",
 242	[IRQ_TYPE_EDGE_FALLING] = "edge-falling",
 243	[IRQ_TYPE_EDGE_BOTH] = "edge-both",
 244	[IRQ_TYPE_LEVEL_HIGH] = "level-high",
 245	[IRQ_TYPE_LEVEL_LOW] = "level-low",
 246};
 247
 248static bool persist_gpio_outputs;
 249module_param(persist_gpio_outputs, bool, 0444);
 250MODULE_PARM_DESC(persist_gpio_outputs, "Enable GPIO_OUT persistence when pin is freed");
 251
 252static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
 253{
 254	return readl(pc->base + reg);
 255}
 256
 257static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
 258		u32 val)
 259{
 260	writel(val, pc->base + reg);
 261}
 262
 263static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
 264		unsigned bit)
 265{
 266	reg += GPIO_REG_OFFSET(bit) * 4;
 267	return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
 268}
 269
 270/* note NOT a read/modify/write cycle */
 271static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
 272		unsigned reg, unsigned bit)
 273{
 274	reg += GPIO_REG_OFFSET(bit) * 4;
 275	bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
 276}
 277
 278static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
 279		struct bcm2835_pinctrl *pc, unsigned pin)
 280{
 281	u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
 282	enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
 283
 284	dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
 285			bcm2835_functions[status]);
 286
 287	return status;
 288}
 289
 290static inline void bcm2835_pinctrl_fsel_set(
 291		struct bcm2835_pinctrl *pc, unsigned pin,
 292		enum bcm2835_fsel fsel)
 293{
 294	u32 val;
 295	enum bcm2835_fsel cur;
 296	unsigned long flags;
 297
 298	spin_lock_irqsave(&pc->fsel_lock, flags);
 299	val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
 300	cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
 301
 302	dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
 303		bcm2835_functions[cur]);
 304
 305	if (cur == fsel)
 306		goto unlock;
 307
 308	if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
 309		/* always transition through GPIO_IN */
 310		val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
 311		val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
 312
 313		dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
 314				bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
 315		bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
 316	}
 317
 318	val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
 319	val |= fsel << FSEL_SHIFT(pin);
 320
 321	dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
 322			bcm2835_functions[fsel]);
 323	bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
 324
 325unlock:
 326	spin_unlock_irqrestore(&pc->fsel_lock, flags);
 327}
 328
 329static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 330{
 331	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 332
 333	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
 334	return 0;
 335}
 336
 337static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
 338{
 339	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 340
 341	return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
 342}
 343
 344static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
 345{
 346	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 347	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
 348
 349	if (fsel == BCM2835_FSEL_GPIO_OUT)
 350		return GPIO_LINE_DIRECTION_OUT;
 351
 352	/*
 353	 * Alternative function doesn't clearly provide a direction. Default
 354	 * to INPUT.
 355	 */
 356	return GPIO_LINE_DIRECTION_IN;
 357}
 358
 359static int bcm2835_gpio_set(struct gpio_chip *chip, unsigned int offset,
 360			    int value)
 361{
 362	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 363
 364	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
 365
 366	return 0;
 367}
 368
 369static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
 370		unsigned offset, int value)
 371{
 372	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 373
 374	bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
 375	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_OUT);
 376	return 0;
 377}
 378
 379static int bcm2835_add_pin_ranges_fallback(struct gpio_chip *gc)
 380{
 381	struct device_node *np = dev_of_node(gc->parent);
 382	struct pinctrl_dev *pctldev = of_pinctrl_get(np);
 383
 384	if (!pctldev)
 385		return 0;
 386
 387	return gpiochip_add_pin_range(gc, pinctrl_dev_get_devname(pctldev), 0, 0,
 388				      gc->ngpio);
 389}
 390
 391static const struct gpio_chip bcm2835_gpio_chip = {
 392	.label = MODULE_NAME,
 393	.owner = THIS_MODULE,
 394	.request = gpiochip_generic_request,
 395	.free = gpiochip_generic_free,
 396	.direction_input = bcm2835_gpio_direction_input,
 397	.direction_output = bcm2835_gpio_direction_output,
 398	.get_direction = bcm2835_gpio_get_direction,
 399	.get = bcm2835_gpio_get,
 400	.set = bcm2835_gpio_set,
 401	.set_config = gpiochip_generic_config,
 402	.base = -1,
 403	.ngpio = BCM2835_NUM_GPIOS,
 404	.can_sleep = false,
 405	.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
 406};
 407
 408static const struct gpio_chip bcm2711_gpio_chip = {
 409	.label = "pinctrl-bcm2711",
 410	.owner = THIS_MODULE,
 411	.request = gpiochip_generic_request,
 412	.free = gpiochip_generic_free,
 413	.direction_input = bcm2835_gpio_direction_input,
 414	.direction_output = bcm2835_gpio_direction_output,
 415	.get_direction = bcm2835_gpio_get_direction,
 416	.get = bcm2835_gpio_get,
 417	.set = bcm2835_gpio_set,
 418	.set_config = gpiochip_generic_config,
 419	.base = -1,
 420	.ngpio = BCM2711_NUM_GPIOS,
 421	.can_sleep = false,
 422	.add_pin_ranges = bcm2835_add_pin_ranges_fallback,
 423};
 424
 425static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
 426					 unsigned int bank, u32 mask)
 427{
 428	unsigned long events;
 429	unsigned offset;
 430	unsigned gpio;
 431
 432	events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
 433	events &= mask;
 434	events &= pc->enabled_irq_map[bank];
 435	for_each_set_bit(offset, &events, 32) {
 436		gpio = (32 * bank) + offset;
 437		generic_handle_domain_irq(pc->gpio_chip.irq.domain,
 438					  gpio);
 439	}
 440}
 441
 442static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
 443{
 444	struct gpio_chip *chip = irq_desc_get_handler_data(desc);
 445	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 446	struct irq_chip *host_chip = irq_desc_get_chip(desc);
 447	int irq = irq_desc_get_irq(desc);
 448	int group = 0;
 449	int i;
 450
 451	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
 452		if (chip->irq.parents[i] == irq) {
 453			group = i;
 454			break;
 455		}
 456	}
 457	/* This should not happen, every IRQ has a bank */
 458	BUG_ON(i == BCM2835_NUM_IRQS);
 459
 460	chained_irq_enter(host_chip, desc);
 461
 462	switch (group) {
 463	case 0: /* IRQ0 covers GPIOs 0-27 */
 464		bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
 465		break;
 466	case 1: /* IRQ1 covers GPIOs 28-45 */
 467		bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
 468		bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
 469		break;
 470	case 2: /* IRQ2 covers GPIOs 46-57 */
 471		bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
 472		break;
 473	}
 474
 475	chained_irq_exit(host_chip, desc);
 476}
 477
 478static irqreturn_t bcm2835_gpio_wake_irq_handler(int irq, void *dev_id)
 479{
 480	return IRQ_HANDLED;
 481}
 482
 483static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
 484	unsigned reg, unsigned offset, bool enable)
 485{
 486	u32 value;
 487	reg += GPIO_REG_OFFSET(offset) * 4;
 488	value = bcm2835_gpio_rd(pc, reg);
 489	if (enable)
 490		value |= BIT(GPIO_REG_SHIFT(offset));
 491	else
 492		value &= ~(BIT(GPIO_REG_SHIFT(offset)));
 493	bcm2835_gpio_wr(pc, reg, value);
 494}
 495
 496/* fast path for IRQ handler */
 497static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
 498	unsigned offset, bool enable)
 499{
 500	switch (pc->irq_type[offset]) {
 501	case IRQ_TYPE_EDGE_RISING:
 502		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
 503		break;
 504
 505	case IRQ_TYPE_EDGE_FALLING:
 506		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
 507		break;
 508
 509	case IRQ_TYPE_EDGE_BOTH:
 510		__bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
 511		__bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
 512		break;
 513
 514	case IRQ_TYPE_LEVEL_HIGH:
 515		__bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
 516		break;
 517
 518	case IRQ_TYPE_LEVEL_LOW:
 519		__bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
 520		break;
 521	}
 522}
 523
 524static void bcm2835_gpio_irq_unmask(struct irq_data *data)
 525{
 526	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 527	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 528	unsigned gpio = irqd_to_hwirq(data);
 529	unsigned offset = GPIO_REG_SHIFT(gpio);
 530	unsigned bank = GPIO_REG_OFFSET(gpio);
 531	unsigned long flags;
 532
 533	gpiochip_enable_irq(chip, gpio);
 534
 535	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
 536	set_bit(offset, &pc->enabled_irq_map[bank]);
 537	bcm2835_gpio_irq_config(pc, gpio, true);
 538	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
 539}
 540
 541static void bcm2835_gpio_irq_mask(struct irq_data *data)
 542{
 543	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 544	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 545	unsigned gpio = irqd_to_hwirq(data);
 546	unsigned offset = GPIO_REG_SHIFT(gpio);
 547	unsigned bank = GPIO_REG_OFFSET(gpio);
 548	unsigned long flags;
 549
 550	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
 551	bcm2835_gpio_irq_config(pc, gpio, false);
 552	/* Clear events that were latched prior to clearing event sources */
 553	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
 554	clear_bit(offset, &pc->enabled_irq_map[bank]);
 555	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
 556
 557	gpiochip_disable_irq(chip, gpio);
 558}
 559
 560static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
 561	unsigned offset, unsigned int type)
 562{
 563	switch (type) {
 564	case IRQ_TYPE_NONE:
 565	case IRQ_TYPE_EDGE_RISING:
 566	case IRQ_TYPE_EDGE_FALLING:
 567	case IRQ_TYPE_EDGE_BOTH:
 568	case IRQ_TYPE_LEVEL_HIGH:
 569	case IRQ_TYPE_LEVEL_LOW:
 570		pc->irq_type[offset] = type;
 571		break;
 572
 573	default:
 574		return -EINVAL;
 575	}
 576	return 0;
 577}
 578
 579/* slower path for reconfiguring IRQ type */
 580static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
 581	unsigned offset, unsigned int type)
 582{
 583	switch (type) {
 584	case IRQ_TYPE_NONE:
 585		if (pc->irq_type[offset] != type) {
 586			bcm2835_gpio_irq_config(pc, offset, false);
 587			pc->irq_type[offset] = type;
 588		}
 589		break;
 590
 591	case IRQ_TYPE_EDGE_RISING:
 592		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
 593			/* RISING already enabled, disable FALLING */
 594			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
 595			bcm2835_gpio_irq_config(pc, offset, false);
 596			pc->irq_type[offset] = type;
 597		} else if (pc->irq_type[offset] != type) {
 598			bcm2835_gpio_irq_config(pc, offset, false);
 599			pc->irq_type[offset] = type;
 600			bcm2835_gpio_irq_config(pc, offset, true);
 601		}
 602		break;
 603
 604	case IRQ_TYPE_EDGE_FALLING:
 605		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
 606			/* FALLING already enabled, disable RISING */
 607			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
 608			bcm2835_gpio_irq_config(pc, offset, false);
 609			pc->irq_type[offset] = type;
 610		} else if (pc->irq_type[offset] != type) {
 611			bcm2835_gpio_irq_config(pc, offset, false);
 612			pc->irq_type[offset] = type;
 613			bcm2835_gpio_irq_config(pc, offset, true);
 614		}
 615		break;
 616
 617	case IRQ_TYPE_EDGE_BOTH:
 618		if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
 619			/* RISING already enabled, enable FALLING too */
 620			pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
 621			bcm2835_gpio_irq_config(pc, offset, true);
 622			pc->irq_type[offset] = type;
 623		} else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
 624			/* FALLING already enabled, enable RISING too */
 625			pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
 626			bcm2835_gpio_irq_config(pc, offset, true);
 627			pc->irq_type[offset] = type;
 628		} else if (pc->irq_type[offset] != type) {
 629			bcm2835_gpio_irq_config(pc, offset, false);
 630			pc->irq_type[offset] = type;
 631			bcm2835_gpio_irq_config(pc, offset, true);
 632		}
 633		break;
 634
 635	case IRQ_TYPE_LEVEL_HIGH:
 636	case IRQ_TYPE_LEVEL_LOW:
 637		if (pc->irq_type[offset] != type) {
 638			bcm2835_gpio_irq_config(pc, offset, false);
 639			pc->irq_type[offset] = type;
 640			bcm2835_gpio_irq_config(pc, offset, true);
 641		}
 642		break;
 643
 644	default:
 645		return -EINVAL;
 646	}
 647	return 0;
 648}
 649
 650static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
 651{
 652	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 653	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 654	unsigned gpio = irqd_to_hwirq(data);
 655	unsigned offset = GPIO_REG_SHIFT(gpio);
 656	unsigned bank = GPIO_REG_OFFSET(gpio);
 657	unsigned long flags;
 658	int ret;
 659
 660	raw_spin_lock_irqsave(&pc->irq_lock[bank], flags);
 661
 662	if (test_bit(offset, &pc->enabled_irq_map[bank]))
 663		ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
 664	else
 665		ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
 666
 667	if (type & IRQ_TYPE_EDGE_BOTH)
 668		irq_set_handler_locked(data, handle_edge_irq);
 669	else
 670		irq_set_handler_locked(data, handle_level_irq);
 671
 672	raw_spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
 673
 674	return ret;
 675}
 676
 677static void bcm2835_gpio_irq_ack(struct irq_data *data)
 678{
 679	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 680	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 681	unsigned gpio = irqd_to_hwirq(data);
 682
 683	bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
 684}
 685
 686static int bcm2835_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
 687{
 688	struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
 689	struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
 690	unsigned gpio = irqd_to_hwirq(data);
 691	unsigned int irqgroup;
 692	int ret = -EINVAL;
 693
 694	if (!pc->wake_irq)
 695		return ret;
 696
 697	if (gpio <= 27)
 698		irqgroup = 0;
 699	else if (gpio >= 28 && gpio <= 45)
 700		irqgroup = 1;
 701	else if (gpio >= 46 && gpio <= 57)
 702		irqgroup = 2;
 703	else
 704		return ret;
 705
 706	if (on)
 707		ret = enable_irq_wake(pc->wake_irq[irqgroup]);
 708	else
 709		ret = disable_irq_wake(pc->wake_irq[irqgroup]);
 710
 711	return ret;
 712}
 713
 714static const struct irq_chip bcm2835_gpio_irq_chip = {
 715	.name = MODULE_NAME,
 716	.irq_set_type = bcm2835_gpio_irq_set_type,
 717	.irq_ack = bcm2835_gpio_irq_ack,
 718	.irq_mask = bcm2835_gpio_irq_mask,
 719	.irq_unmask = bcm2835_gpio_irq_unmask,
 720	.irq_set_wake = bcm2835_gpio_irq_set_wake,
 721	.flags = (IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE),
 722	GPIOCHIP_IRQ_RESOURCE_HELPERS,
 723};
 724
 725static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
 726{
 727	return BCM2835_NUM_GPIOS;
 728}
 729
 730static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
 731		unsigned selector)
 732{
 733	return bcm2835_gpio_groups[selector];
 734}
 735
 736static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
 737		unsigned selector,
 738		const unsigned **pins,
 739		unsigned *num_pins)
 740{
 741	*pins = &bcm2835_gpio_pins[selector].number;
 742	*num_pins = 1;
 743
 744	return 0;
 745}
 746
 747static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
 748		struct seq_file *s,
 749		unsigned offset)
 750{
 751	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 752	struct gpio_chip *chip = &pc->gpio_chip;
 753	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
 754	const char *fname = bcm2835_functions[fsel];
 755	int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
 756	int irq = irq_find_mapping(chip->irq.domain, offset);
 757
 758	seq_printf(s, "function %s in %s; irq %d (%s)",
 759		fname, str_hi_lo(value),
 760		irq, irq_type_names[pc->irq_type[offset]]);
 761}
 762
 763static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
 764		struct pinctrl_map *maps, unsigned num_maps)
 765{
 766	int i;
 767
 768	for (i = 0; i < num_maps; i++)
 769		if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
 770			kfree(maps[i].data.configs.configs);
 771
 772	kfree(maps);
 773}
 774
 775static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
 776		struct device_node *np, u32 pin, u32 fnum,
 777		struct pinctrl_map **maps)
 778{
 779	struct pinctrl_map *map = *maps;
 780
 781	if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
 782		dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
 783		return -EINVAL;
 784	}
 785
 786	map->type = PIN_MAP_TYPE_MUX_GROUP;
 787	map->data.mux.group = bcm2835_gpio_groups[pin];
 788	map->data.mux.function = bcm2835_functions[fnum];
 789	(*maps)++;
 790
 791	return 0;
 792}
 793
 794static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
 795		struct device_node *np, u32 pin, u32 pull,
 796		struct pinctrl_map **maps)
 797{
 798	struct pinctrl_map *map = *maps;
 799	unsigned long *configs;
 800
 801	if (pull > 2) {
 802		dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
 803		return -EINVAL;
 804	}
 805
 806	configs = kzalloc(sizeof(*configs), GFP_KERNEL);
 807	if (!configs)
 808		return -ENOMEM;
 809	configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
 810
 811	map->type = PIN_MAP_TYPE_CONFIGS_PIN;
 812	map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
 813	map->data.configs.configs = configs;
 814	map->data.configs.num_configs = 1;
 815	(*maps)++;
 816
 817	return 0;
 818}
 819
 820static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
 821		struct device_node *np,
 822		struct pinctrl_map **map, unsigned int *num_maps)
 823{
 824	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 825	struct property *pins, *funcs, *pulls;
 826	int num_pins, num_funcs, num_pulls, maps_per_pin;
 827	struct pinctrl_map *maps, *cur_map;
 828	int i, err;
 829	u32 pin, func, pull;
 830
 831	/* Check for generic binding in this node */
 832	err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
 833	if (err || *num_maps)
 834		return err;
 835
 836	/* Generic binding did not find anything continue with legacy parse */
 837	pins = of_find_property(np, "brcm,pins", NULL);
 838	if (!pins) {
 839		dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
 840		return -EINVAL;
 841	}
 842
 843	funcs = of_find_property(np, "brcm,function", NULL);
 844	pulls = of_find_property(np, "brcm,pull", NULL);
 845
 846	if (!funcs && !pulls) {
 847		dev_err(pc->dev,
 848			"%pOF: neither brcm,function nor brcm,pull specified\n",
 849			np);
 850		return -EINVAL;
 851	}
 852
 853	num_pins = pins->length / 4;
 854	num_funcs = funcs ? (funcs->length / 4) : 0;
 855	num_pulls = pulls ? (pulls->length / 4) : 0;
 856
 857	if (num_funcs > 1 && num_funcs != num_pins) {
 858		dev_err(pc->dev,
 859			"%pOF: brcm,function must have 1 or %d entries\n",
 860			np, num_pins);
 861		return -EINVAL;
 862	}
 863
 864	if (num_pulls > 1 && num_pulls != num_pins) {
 865		dev_err(pc->dev,
 866			"%pOF: brcm,pull must have 1 or %d entries\n",
 867			np, num_pins);
 868		return -EINVAL;
 869	}
 870
 871	maps_per_pin = 0;
 872	if (num_funcs)
 873		maps_per_pin++;
 874	if (num_pulls)
 875		maps_per_pin++;
 876	cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
 877				 GFP_KERNEL);
 878	if (!maps)
 879		return -ENOMEM;
 880
 881	for (i = 0; i < num_pins; i++) {
 882		err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
 883		if (err)
 884			goto out;
 885		if (pin >= pc->pctl_desc.npins) {
 886			dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
 887				np, pin);
 888			err = -EINVAL;
 889			goto out;
 890		}
 891
 892		if (num_funcs) {
 893			err = of_property_read_u32_index(np, "brcm,function",
 894					(num_funcs > 1) ? i : 0, &func);
 895			if (err)
 896				goto out;
 897			err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
 898							func, &cur_map);
 899			if (err)
 900				goto out;
 901		}
 902		if (num_pulls) {
 903			err = of_property_read_u32_index(np, "brcm,pull",
 904					(num_pulls > 1) ? i : 0, &pull);
 905			if (err)
 906				goto out;
 907			err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
 908							pull, &cur_map);
 909			if (err)
 910				goto out;
 911		}
 912	}
 913
 914	*map = maps;
 915	*num_maps = num_pins * maps_per_pin;
 916
 917	return 0;
 918
 919out:
 920	bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
 921	return err;
 922}
 923
 924static const struct pinctrl_ops bcm2835_pctl_ops = {
 925	.get_groups_count = bcm2835_pctl_get_groups_count,
 926	.get_group_name = bcm2835_pctl_get_group_name,
 927	.get_group_pins = bcm2835_pctl_get_group_pins,
 928	.pin_dbg_show = bcm2835_pctl_pin_dbg_show,
 929	.dt_node_to_map = bcm2835_pctl_dt_node_to_map,
 930	.dt_free_map = bcm2835_pctl_dt_free_map,
 931};
 932
 933static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
 934		unsigned offset)
 935{
 936	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 937	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
 938
 939	if (fsel == BCM2835_FSEL_GPIO_IN)
 940		return 0;
 941
 942	if (persist_gpio_outputs && fsel == BCM2835_FSEL_GPIO_OUT)
 943		return 0;
 944
 945	/* disable by setting to GPIO_IN */
 946	bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
 947	return 0;
 948}
 949
 950static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
 951{
 952	return BCM2835_FSEL_COUNT;
 953}
 954
 955static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
 956		unsigned selector)
 957{
 958	return bcm2835_functions[selector];
 959}
 960
 961static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
 962		unsigned selector,
 963		const char * const **groups,
 964		unsigned * const num_groups)
 965{
 966	/* every pin can do every function */
 967	*groups = bcm2835_gpio_groups;
 968	*num_groups = BCM2835_NUM_GPIOS;
 969
 970	return 0;
 971}
 972
 973static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
 974		unsigned func_selector,
 975		unsigned group_selector)
 976{
 977	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 978
 979	bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
 980
 981	return 0;
 982}
 983
 984static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
 985		struct pinctrl_gpio_range *range,
 986		unsigned offset)
 987{
 988	bcm2835_pmx_free(pctldev, offset);
 989}
 990
 991static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
 992		struct pinctrl_gpio_range *range,
 993		unsigned offset,
 994		bool input)
 995{
 996	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
 997	enum bcm2835_fsel fsel = input ?
 998		BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
 999
1000	bcm2835_pinctrl_fsel_set(pc, offset, fsel);
1001
1002	return 0;
1003}
1004
1005static const struct pinmux_ops bcm2835_pmx_ops = {
1006	.free = bcm2835_pmx_free,
1007	.get_functions_count = bcm2835_pmx_get_functions_count,
1008	.get_function_name = bcm2835_pmx_get_function_name,
1009	.get_function_groups = bcm2835_pmx_get_function_groups,
1010	.set_mux = bcm2835_pmx_set,
1011	.gpio_disable_free = bcm2835_pmx_gpio_disable_free,
1012	.gpio_set_direction = bcm2835_pmx_gpio_set_direction,
1013};
1014
1015static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
1016			unsigned pin, unsigned long *config)
1017{
1018	enum pin_config_param param = pinconf_to_config_param(*config);
1019	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1020	enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, pin);
1021	u32 val;
1022
1023	/* No way to read back bias config in HW */
1024
1025	switch (param) {
1026	case PIN_CONFIG_LEVEL:
1027		if (fsel != BCM2835_FSEL_GPIO_OUT)
1028			return -EINVAL;
1029
1030		val = bcm2835_gpio_get_bit(pc, GPLEV0, pin);
1031		*config = pinconf_to_config_packed(param, val);
1032		break;
1033
1034	default:
1035		return -ENOTSUPP;
1036	}
1037
1038	return 0;
1039}
1040
1041static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
1042		unsigned int pin, unsigned int arg)
1043{
1044	u32 off, bit;
1045
1046	off = GPIO_REG_OFFSET(pin);
1047	bit = GPIO_REG_SHIFT(pin);
1048
1049	bcm2835_gpio_wr(pc, GPPUD, arg & 3);
1050	/*
1051	 * BCM2835 datasheet say to wait 150 cycles, but not of what.
1052	 * But the VideoCore firmware delay for this operation
1053	 * based nearly on the same amount of VPU cycles and this clock
1054	 * runs at 250 MHz.
1055	 */
1056	udelay(1);
1057	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
1058	udelay(1);
1059	bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
1060}
1061
1062static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
1063			unsigned int pin, unsigned long *configs,
1064			unsigned int num_configs)
1065{
1066	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1067	u32 param, arg;
1068	int i;
1069
1070	for (i = 0; i < num_configs; i++) {
1071		param = pinconf_to_config_param(configs[i]);
1072		arg = pinconf_to_config_argument(configs[i]);
1073
1074		switch (param) {
1075		/* Set legacy brcm,pull */
1076		case BCM2835_PINCONF_PARAM_PULL:
1077			bcm2835_pull_config_set(pc, pin, arg);
1078			break;
1079
1080		/* Set pull generic bindings */
1081		case PIN_CONFIG_BIAS_DISABLE:
1082			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
1083			break;
1084
1085		case PIN_CONFIG_BIAS_PULL_DOWN:
1086			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
1087			break;
1088
1089		case PIN_CONFIG_BIAS_PULL_UP:
1090			bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
1091			break;
1092
1093		/* Set output-high or output-low */
1094		case PIN_CONFIG_LEVEL:
1095			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1096			break;
1097
1098		default:
1099			return -ENOTSUPP;
1100
1101		} /* switch param type */
1102	} /* for each config */
1103
1104	return 0;
1105}
1106
1107static const struct pinconf_ops bcm2835_pinconf_ops = {
1108	.is_generic = true,
1109	.pin_config_get = bcm2835_pinconf_get,
1110	.pin_config_set = bcm2835_pinconf_set,
1111};
1112
1113static int bcm2711_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
1114			       unsigned long *config)
1115{
1116	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1117	enum pin_config_param param = pinconf_to_config_param(*config);
1118	u32 offset, shift, val;
1119
1120	offset = PUD_2711_REG_OFFSET(pin);
1121	shift = PUD_2711_REG_SHIFT(pin);
1122	val = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (offset * 4));
1123
1124	switch (param) {
1125	case PIN_CONFIG_BIAS_DISABLE:
1126		if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_NONE)
1127			return -EINVAL;
1128
1129		break;
1130
1131	case PIN_CONFIG_BIAS_PULL_UP:
1132		if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_UP)
1133			return -EINVAL;
1134
1135		*config = pinconf_to_config_packed(param, 50000);
1136		break;
1137
1138	case PIN_CONFIG_BIAS_PULL_DOWN:
1139		if (((val >> shift) & PUD_2711_MASK) != BCM2711_PULL_DOWN)
1140			return -EINVAL;
1141
1142		*config = pinconf_to_config_packed(param, 50000);
1143		break;
1144
1145	default:
1146		return bcm2835_pinconf_get(pctldev, pin, config);
1147	}
1148
1149	return 0;
1150}
1151
1152static void bcm2711_pull_config_set(struct bcm2835_pinctrl *pc,
1153				    unsigned int pin, unsigned int arg)
1154{
1155	u32 shifter;
1156	u32 value;
1157	u32 off;
1158
1159	off = PUD_2711_REG_OFFSET(pin);
1160	shifter = PUD_2711_REG_SHIFT(pin);
1161
1162	value = bcm2835_gpio_rd(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4));
1163	value &= ~(PUD_2711_MASK << shifter);
1164	value |= (arg << shifter);
1165	bcm2835_gpio_wr(pc, GP_GPIO_PUP_PDN_CNTRL_REG0 + (off * 4), value);
1166}
1167
1168static int bcm2711_pinconf_set(struct pinctrl_dev *pctldev,
1169			       unsigned int pin, unsigned long *configs,
1170			       unsigned int num_configs)
1171{
1172	struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
1173	u32 param, arg;
1174	int i;
1175
1176	for (i = 0; i < num_configs; i++) {
1177		param = pinconf_to_config_param(configs[i]);
1178		arg = pinconf_to_config_argument(configs[i]);
1179
1180		switch (param) {
1181		/* convert legacy brcm,pull */
1182		case BCM2835_PINCONF_PARAM_PULL:
1183			if (arg == BCM2835_PUD_UP)
1184				arg = BCM2711_PULL_UP;
1185			else if (arg == BCM2835_PUD_DOWN)
1186				arg = BCM2711_PULL_DOWN;
1187			else
1188				arg = BCM2711_PULL_NONE;
1189
1190			bcm2711_pull_config_set(pc, pin, arg);
1191			break;
1192
1193		/* Set pull generic bindings */
1194		case PIN_CONFIG_BIAS_DISABLE:
1195			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_NONE);
1196			break;
1197		case PIN_CONFIG_BIAS_PULL_DOWN:
1198			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_DOWN);
1199			break;
1200		case PIN_CONFIG_BIAS_PULL_UP:
1201			bcm2711_pull_config_set(pc, pin, BCM2711_PULL_UP);
1202			break;
1203
1204		/* Set output-high or output-low */
1205		case PIN_CONFIG_LEVEL:
1206			bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
1207			break;
1208
1209		default:
1210			return -ENOTSUPP;
1211		}
1212	} /* for each config */
1213
1214	return 0;
1215}
1216
1217static const struct pinconf_ops bcm2711_pinconf_ops = {
1218	.is_generic = true,
1219	.pin_config_get = bcm2711_pinconf_get,
1220	.pin_config_set = bcm2711_pinconf_set,
1221};
1222
1223static const struct pinctrl_desc bcm2835_pinctrl_desc = {
1224	.name = MODULE_NAME,
1225	.pins = bcm2835_gpio_pins,
1226	.npins = BCM2835_NUM_GPIOS,
1227	.pctlops = &bcm2835_pctl_ops,
1228	.pmxops = &bcm2835_pmx_ops,
1229	.confops = &bcm2835_pinconf_ops,
1230	.owner = THIS_MODULE,
1231};
1232
1233static const struct pinctrl_desc bcm2711_pinctrl_desc = {
1234	.name = "pinctrl-bcm2711",
1235	.pins = bcm2835_gpio_pins,
1236	.npins = BCM2711_NUM_GPIOS,
1237	.pctlops = &bcm2835_pctl_ops,
1238	.pmxops = &bcm2835_pmx_ops,
1239	.confops = &bcm2711_pinconf_ops,
1240	.owner = THIS_MODULE,
1241};
1242
1243static const struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
1244	.name = MODULE_NAME,
1245	.npins = BCM2835_NUM_GPIOS,
1246};
1247
1248static const struct pinctrl_gpio_range bcm2711_pinctrl_gpio_range = {
1249	.name = "pinctrl-bcm2711",
1250	.npins = BCM2711_NUM_GPIOS,
1251};
1252
1253struct bcm_plat_data {
1254	const struct gpio_chip *gpio_chip;
1255	const struct pinctrl_desc *pctl_desc;
1256	const struct pinctrl_gpio_range *gpio_range;
1257};
1258
1259static const struct bcm_plat_data bcm2835_plat_data = {
1260	.gpio_chip = &bcm2835_gpio_chip,
1261	.pctl_desc = &bcm2835_pinctrl_desc,
1262	.gpio_range = &bcm2835_pinctrl_gpio_range,
1263};
1264
1265static const struct bcm_plat_data bcm2711_plat_data = {
1266	.gpio_chip = &bcm2711_gpio_chip,
1267	.pctl_desc = &bcm2711_pinctrl_desc,
1268	.gpio_range = &bcm2711_pinctrl_gpio_range,
1269};
1270
1271static const struct of_device_id bcm2835_pinctrl_match[] = {
1272	{
1273		.compatible = "brcm,bcm2835-gpio",
1274		.data = &bcm2835_plat_data,
1275	},
1276	{
1277		.compatible = "brcm,bcm2711-gpio",
1278		.data = &bcm2711_plat_data,
1279	},
1280	{
1281		.compatible = "brcm,bcm7211-gpio",
1282		.data = &bcm2711_plat_data,
1283	},
1284	{}
1285};
1286MODULE_DEVICE_TABLE(of, bcm2835_pinctrl_match);
1287
1288static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1289{
1290	struct device *dev = &pdev->dev;
1291	struct device_node *np = dev->of_node;
1292	const struct bcm_plat_data *pdata;
1293	struct bcm2835_pinctrl *pc;
1294	struct gpio_irq_chip *girq;
1295	struct resource iomem;
1296	int err, i;
1297	const struct of_device_id *match;
1298	int is_7211 = 0;
1299
1300	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2711_NUM_GPIOS);
1301	BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2711_NUM_GPIOS);
1302
1303	pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1304	if (!pc)
1305		return -ENOMEM;
1306
1307	platform_set_drvdata(pdev, pc);
1308	pc->dev = dev;
1309
1310	err = of_address_to_resource(np, 0, &iomem);
1311	if (err) {
1312		dev_err(dev, "could not get IO memory\n");
1313		return err;
1314	}
1315
1316	pc->base = devm_ioremap_resource(dev, &iomem);
1317	if (IS_ERR(pc->base))
1318		return PTR_ERR(pc->base);
1319
1320	match = of_match_node(bcm2835_pinctrl_match, pdev->dev.of_node);
1321	if (!match)
1322		return -EINVAL;
1323
1324	pdata = match->data;
1325	is_7211 = of_device_is_compatible(np, "brcm,bcm7211-gpio");
1326
1327	pc->gpio_chip = *pdata->gpio_chip;
1328	pc->gpio_chip.parent = dev;
1329
1330	spin_lock_init(&pc->fsel_lock);
1331	for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1332		unsigned long events;
1333		unsigned offset;
1334
1335		/* clear event detection flags */
1336		bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1337		bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1338		bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1339		bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1340		bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1341		bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1342
1343		/* clear all the events */
1344		events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1345		for_each_set_bit(offset, &events, 32)
1346			bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1347
1348		raw_spin_lock_init(&pc->irq_lock[i]);
1349	}
1350
1351	pc->pctl_desc = *pdata->pctl_desc;
1352	pc->pctl_dev = devm_pinctrl_register(dev, &pc->pctl_desc, pc);
1353	if (IS_ERR(pc->pctl_dev)) {
1354		gpiochip_remove(&pc->gpio_chip);
1355		return PTR_ERR(pc->pctl_dev);
1356	}
1357
1358	pc->gpio_range = *pdata->gpio_range;
1359	pc->gpio_range.base = pc->gpio_chip.base;
1360	pc->gpio_range.gc = &pc->gpio_chip;
1361	pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1362
1363	girq = &pc->gpio_chip.irq;
1364	gpio_irq_chip_set_chip(girq, &bcm2835_gpio_irq_chip);
1365	girq->parent_handler = bcm2835_gpio_irq_handler;
1366	girq->num_parents = BCM2835_NUM_IRQS;
1367	girq->parents = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1368				     sizeof(*girq->parents),
1369				     GFP_KERNEL);
1370	if (!girq->parents) {
1371		err = -ENOMEM;
1372		goto out_remove;
1373	}
1374
1375	if (is_7211) {
1376		pc->wake_irq = devm_kcalloc(dev, BCM2835_NUM_IRQS,
1377					    sizeof(*pc->wake_irq),
1378					    GFP_KERNEL);
1379		if (!pc->wake_irq) {
1380			err = -ENOMEM;
1381			goto out_remove;
1382		}
1383	}
1384
1385	/*
1386	 * Use the same handler for all groups: this is necessary
1387	 * since we use one gpiochip to cover all lines - the
1388	 * irq handler then needs to figure out which group and
1389	 * bank that was firing the IRQ and look up the per-group
1390	 * and bank data.
1391	 */
1392	for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1393		int len;
1394		char *name;
1395
1396		girq->parents[i] = irq_of_parse_and_map(np, i);
1397		if (!is_7211) {
1398			if (!girq->parents[i]) {
1399				girq->num_parents = i;
1400				break;
1401			}
1402			continue;
1403		}
1404		/* Skip over the all banks interrupts */
1405		pc->wake_irq[i] = irq_of_parse_and_map(np, i +
1406						       BCM2835_NUM_IRQS + 1);
1407
1408		len = strlen(dev_name(pc->dev)) + 16;
1409		name = devm_kzalloc(pc->dev, len, GFP_KERNEL);
1410		if (!name) {
1411			err = -ENOMEM;
1412			goto out_remove;
1413		}
1414
1415		snprintf(name, len, "%s:bank%d", dev_name(pc->dev), i);
1416
1417		/* These are optional interrupts */
1418		err = devm_request_irq(dev, pc->wake_irq[i],
1419				       bcm2835_gpio_wake_irq_handler,
1420				       IRQF_SHARED, name, pc);
1421		if (err)
1422			dev_warn(dev, "unable to request wake IRQ %d\n",
1423				 pc->wake_irq[i]);
1424	}
1425
1426	girq->default_type = IRQ_TYPE_NONE;
1427	girq->handler = handle_level_irq;
1428
1429	err = gpiochip_add_data(&pc->gpio_chip, pc);
1430	if (err) {
1431		dev_err(dev, "could not add GPIO chip\n");
1432		goto out_remove;
1433	}
1434
1435	dev_info(dev, "GPIO_OUT persistence: %s\n",
1436		 str_yes_no(persist_gpio_outputs));
1437
1438	return 0;
1439
1440out_remove:
1441	pinctrl_remove_gpio_range(pc->pctl_dev, &pc->gpio_range);
1442	return err;
1443}
1444
1445static struct platform_driver bcm2835_pinctrl_driver = {
1446	.probe = bcm2835_pinctrl_probe,
1447	.driver = {
1448		.name = MODULE_NAME,
1449		.of_match_table = bcm2835_pinctrl_match,
1450		.suppress_bind_attrs = true,
1451	},
1452};
1453module_platform_driver(bcm2835_pinctrl_driver);
1454
1455MODULE_AUTHOR("Chris Boot");
1456MODULE_AUTHOR("Simon Arlott");
1457MODULE_AUTHOR("Stephen Warren");
1458MODULE_DESCRIPTION("Broadcom BCM2835/2711 pinctrl and GPIO driver");
1459MODULE_LICENSE("GPL");