phy-j721e-wiz.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Wrapper driver for SERDES used in J721E
   4 *
   5 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
   6 * Author: Kishon Vijay Abraham I <kishon@ti.com>
   7 */
   8
   9#include <dt-bindings/phy/phy.h>
  10#include <dt-bindings/phy/phy-ti.h>
  11#include <linux/slab.h>
  12#include <linux/clk.h>
  13#include <linux/clk-provider.h>
  14#include <linux/gpio.h>
  15#include <linux/gpio/consumer.h>
  16#include <linux/io.h>
  17#include <linux/module.h>
  18#include <linux/mfd/syscon.h>
  19#include <linux/mux/consumer.h>
  20#include <linux/of_address.h>
  21#include <linux/of_platform.h>
  22#include <linux/platform_device.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/regmap.h>
  25#include <linux/reset-controller.h>
  26
  27#define REF_CLK_19_2MHZ         19200000
  28#define REF_CLK_25MHZ           25000000
  29#define REF_CLK_100MHZ          100000000
  30#define REF_CLK_156_25MHZ       156250000
  31
  32/* SCM offsets */
  33#define SERDES_SUP_CTRL		0x4400
  34
  35/* SERDES offsets */
  36#define WIZ_SERDES_CTRL		0x404
  37#define WIZ_SERDES_TOP_CTRL	0x408
  38#define WIZ_SERDES_RST		0x40c
  39#define WIZ_SERDES_TYPEC	0x410
  40#define WIZ_LANECTL(n)		(0x480 + (0x40 * (n)))
  41#define WIZ_LANEDIV(n)		(0x484 + (0x40 * (n)))
  42
  43#define WIZ_MAX_INPUT_CLOCKS	4
  44/* To include mux clocks, divider clocks and gate clocks */
  45#define WIZ_MAX_OUTPUT_CLOCKS	32
  46
  47#define WIZ_MAX_LANES		4
  48#define WIZ_MUX_NUM_CLOCKS	3
  49#define WIZ_DIV_NUM_CLOCKS_16G	2
  50#define WIZ_DIV_NUM_CLOCKS_10G	1
  51
  52#define WIZ_SERDES_TYPEC_LN10_SWAP	BIT(30)
  53
  54enum wiz_lane_standard_mode {
  55	LANE_MODE_GEN1,
  56	LANE_MODE_GEN2,
  57	LANE_MODE_GEN3,
  58	LANE_MODE_GEN4,
  59};
  60
  61/*
  62 * List of master lanes used for lane swapping
  63 */
  64enum wiz_typec_master_lane {
  65	LANE0 = 0,
  66	LANE2 = 2,
  67};
  68
  69enum wiz_refclk_mux_sel {
  70	PLL0_REFCLK,
  71	PLL1_REFCLK,
  72	REFCLK_DIG,
  73};
  74
  75enum wiz_refclk_div_sel {
  76	CMN_REFCLK_DIG_DIV,
  77	CMN_REFCLK1_DIG_DIV,
  78};
  79
  80enum wiz_clock_input {
  81	WIZ_CORE_REFCLK,
  82	WIZ_EXT_REFCLK,
  83	WIZ_CORE_REFCLK1,
  84	WIZ_EXT_REFCLK1,
  85};
  86
  87static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
  88static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
  89static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
  90static const struct reg_field pll1_refclk_mux_sel =
  91					REG_FIELD(WIZ_SERDES_RST, 29, 29);
  92static const struct reg_field pll1_refclk_mux_sel_2 =
  93					REG_FIELD(WIZ_SERDES_RST, 22, 23);
  94static const struct reg_field pll0_refclk_mux_sel =
  95					REG_FIELD(WIZ_SERDES_RST, 28, 28);
  96static const struct reg_field pll0_refclk_mux_sel_2 =
  97					REG_FIELD(WIZ_SERDES_RST, 28, 29);
  98static const struct reg_field refclk_dig_sel_16g =
  99					REG_FIELD(WIZ_SERDES_RST, 24, 25);
 100static const struct reg_field refclk_dig_sel_10g =
 101					REG_FIELD(WIZ_SERDES_RST, 24, 24);
 102static const struct reg_field pma_cmn_refclk_int_mode =
 103					REG_FIELD(WIZ_SERDES_TOP_CTRL, 28, 29);
 104static const struct reg_field pma_cmn_refclk1_int_mode =
 105					REG_FIELD(WIZ_SERDES_TOP_CTRL, 20, 21);
 106static const struct reg_field pma_cmn_refclk_mode =
 107					REG_FIELD(WIZ_SERDES_TOP_CTRL, 30, 31);
 108static const struct reg_field pma_cmn_refclk_dig_div =
 109					REG_FIELD(WIZ_SERDES_TOP_CTRL, 26, 27);
 110static const struct reg_field pma_cmn_refclk1_dig_div =
 111					REG_FIELD(WIZ_SERDES_TOP_CTRL, 24, 25);
 112
 113static const struct reg_field sup_pll0_refclk_mux_sel =
 114					REG_FIELD(SERDES_SUP_CTRL, 0, 1);
 115static const struct reg_field sup_pll1_refclk_mux_sel =
 116					REG_FIELD(SERDES_SUP_CTRL, 2, 3);
 117static const struct reg_field sup_pma_cmn_refclk1_int_mode =
 118					REG_FIELD(SERDES_SUP_CTRL, 4, 5);
 119static const struct reg_field sup_refclk_dig_sel_10g =
 120					REG_FIELD(SERDES_SUP_CTRL, 6, 7);
 121static const struct reg_field sup_legacy_clk_override =
 122					REG_FIELD(SERDES_SUP_CTRL, 8, 8);
 123
 124static const char * const output_clk_names[] = {
 125	[TI_WIZ_PLL0_REFCLK] = "pll0-refclk",
 126	[TI_WIZ_PLL1_REFCLK] = "pll1-refclk",
 127	[TI_WIZ_REFCLK_DIG] = "refclk-dig",
 128	[TI_WIZ_PHY_EN_REFCLK] = "phy-en-refclk",
 129};
 130
 131static const struct reg_field p_enable[WIZ_MAX_LANES] = {
 132	REG_FIELD(WIZ_LANECTL(0), 30, 31),
 133	REG_FIELD(WIZ_LANECTL(1), 30, 31),
 134	REG_FIELD(WIZ_LANECTL(2), 30, 31),
 135	REG_FIELD(WIZ_LANECTL(3), 30, 31),
 136};
 137
 138enum p_enable { P_ENABLE = 2, P_ENABLE_FORCE = 1, P_ENABLE_DISABLE = 0 };
 139
 140static const struct reg_field p_align[WIZ_MAX_LANES] = {
 141	REG_FIELD(WIZ_LANECTL(0), 29, 29),
 142	REG_FIELD(WIZ_LANECTL(1), 29, 29),
 143	REG_FIELD(WIZ_LANECTL(2), 29, 29),
 144	REG_FIELD(WIZ_LANECTL(3), 29, 29),
 145};
 146
 147static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
 148	REG_FIELD(WIZ_LANECTL(0), 28, 28),
 149	REG_FIELD(WIZ_LANECTL(1), 28, 28),
 150	REG_FIELD(WIZ_LANECTL(2), 28, 28),
 151	REG_FIELD(WIZ_LANECTL(3), 28, 28),
 152};
 153
 154static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
 155	REG_FIELD(WIZ_LANECTL(0), 24, 25),
 156	REG_FIELD(WIZ_LANECTL(1), 24, 25),
 157	REG_FIELD(WIZ_LANECTL(2), 24, 25),
 158	REG_FIELD(WIZ_LANECTL(3), 24, 25),
 159};
 160
 161static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
 162	REG_FIELD(WIZ_LANECTL(0), 22, 23),
 163	REG_FIELD(WIZ_LANECTL(1), 22, 23),
 164	REG_FIELD(WIZ_LANECTL(2), 22, 23),
 165	REG_FIELD(WIZ_LANECTL(3), 22, 23),
 166};
 167
 168static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
 169	REG_FIELD(WIZ_LANECTL(0), 20, 21),
 170	REG_FIELD(WIZ_LANECTL(1), 20, 21),
 171	REG_FIELD(WIZ_LANECTL(2), 20, 21),
 172	REG_FIELD(WIZ_LANECTL(3), 20, 21),
 173};
 174
 175static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
 176	REG_FIELD(WIZ_LANECTL(0), 6, 7),
 177	REG_FIELD(WIZ_LANECTL(1), 6, 7),
 178	REG_FIELD(WIZ_LANECTL(2), 6, 7),
 179	REG_FIELD(WIZ_LANECTL(3), 6, 7),
 180};
 181
 182static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
 183	REG_FIELD(WIZ_LANECTL(0), 18, 19),
 184	REG_FIELD(WIZ_LANECTL(1), 18, 19),
 185	REG_FIELD(WIZ_LANECTL(2), 18, 19),
 186	REG_FIELD(WIZ_LANECTL(3), 18, 19),
 187};
 188static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
 189	REG_FIELD(WIZ_LANEDIV(0), 16, 22),
 190	REG_FIELD(WIZ_LANEDIV(1), 16, 22),
 191	REG_FIELD(WIZ_LANEDIV(2), 16, 22),
 192	REG_FIELD(WIZ_LANEDIV(3), 16, 22),
 193};
 194
 195static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
 196	REG_FIELD(WIZ_LANEDIV(0), 0, 8),
 197	REG_FIELD(WIZ_LANEDIV(1), 0, 8),
 198	REG_FIELD(WIZ_LANEDIV(2), 0, 8),
 199	REG_FIELD(WIZ_LANEDIV(3), 0, 8),
 200};
 201
 202static const struct reg_field typec_ln10_swap =
 203					REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
 204
 205static const struct reg_field typec_ln23_swap =
 206					REG_FIELD(WIZ_SERDES_TYPEC, 31, 31);
 207
 208struct wiz_clk_mux {
 209	struct clk_hw		hw;
 210	struct regmap_field	*field;
 211	const u32		*table;
 212	struct clk_init_data	clk_data;
 213};
 214
 215#define to_wiz_clk_mux(_hw) container_of(_hw, struct wiz_clk_mux, hw)
 216
 217struct wiz_clk_divider {
 218	struct clk_hw		hw;
 219	struct regmap_field	*field;
 220	const struct clk_div_table	*table;
 221	struct clk_init_data	clk_data;
 222};
 223
 224#define to_wiz_clk_div(_hw) container_of(_hw, struct wiz_clk_divider, hw)
 225
 226struct wiz_clk_mux_sel {
 227	u32			table[WIZ_MAX_INPUT_CLOCKS];
 228	const char		*node_name;
 229	u32			num_parents;
 230	u32			parents[WIZ_MAX_INPUT_CLOCKS];
 231};
 232
 233struct wiz_clk_div_sel {
 234	const struct clk_div_table *table;
 235	const char		*node_name;
 236};
 237
 238struct wiz_phy_en_refclk {
 239	struct clk_hw		hw;
 240	struct regmap_field	*phy_en_refclk;
 241	struct clk_init_data	clk_data;
 242};
 243
 244#define to_wiz_phy_en_refclk(_hw) container_of(_hw, struct wiz_phy_en_refclk, hw)
 245
 246static const struct wiz_clk_mux_sel clk_mux_sel_16g[] = {
 247	{
 248		/*
 249		 * Mux value to be configured for each of the input clocks
 250		 * in the order populated in device tree
 251		 */
 252		.table = { 1, 0 },
 253		.node_name = "pll0-refclk",
 254	},
 255	{
 256		.table = { 1, 0 },
 257		.node_name = "pll1-refclk",
 258	},
 259	{
 260		.table = { 1, 3, 0, 2 },
 261		.node_name = "refclk-dig",
 262	},
 263};
 264
 265static const struct wiz_clk_mux_sel clk_mux_sel_10g[] = {
 266	{
 267		/*
 268		 * Mux value to be configured for each of the input clocks
 269		 * in the order populated in device tree
 270		 */
 271		.num_parents = 2,
 272		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 273		.table = { 1, 0 },
 274		.node_name = "pll0-refclk",
 275	},
 276	{
 277		.num_parents = 2,
 278		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 279		.table = { 1, 0 },
 280		.node_name = "pll1-refclk",
 281	},
 282	{
 283		.num_parents = 2,
 284		.parents = { WIZ_CORE_REFCLK, WIZ_EXT_REFCLK },
 285		.table = { 1, 0 },
 286		.node_name = "refclk-dig",
 287	},
 288};
 289
 290static const struct wiz_clk_mux_sel clk_mux_sel_10g_2_refclk[] = {
 291	{
 292		.num_parents = 3,
 293		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
 294		.table = { 2, 3, 0 },
 295		.node_name = "pll0-refclk",
 296	},
 297	{
 298		.num_parents = 3,
 299		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
 300		.table = { 2, 3, 0 },
 301		.node_name = "pll1-refclk",
 302	},
 303	{
 304		.num_parents = 3,
 305		.parents = { WIZ_CORE_REFCLK, WIZ_CORE_REFCLK1, WIZ_EXT_REFCLK },
 306		.table = { 2, 3, 0 },
 307		.node_name = "refclk-dig",
 308	},
 309};
 310
 311static const struct clk_div_table clk_div_table[] = {
 312	{ .val = 0, .div = 1, },
 313	{ .val = 1, .div = 2, },
 314	{ .val = 2, .div = 4, },
 315	{ .val = 3, .div = 8, },
 316	{ /* sentinel */ },
 317};
 318
 319static const struct wiz_clk_div_sel clk_div_sel[] = {
 320	{
 321		.table = clk_div_table,
 322		.node_name = "cmn-refclk-dig-div",
 323	},
 324	{
 325		.table = clk_div_table,
 326		.node_name = "cmn-refclk1-dig-div",
 327	},
 328};
 329
 330enum wiz_type {
 331	J721E_WIZ_16G,
 332	J721E_WIZ_10G,	/* Also for J7200 SR1.0 */
 333	AM64_WIZ_10G,
 334	J7200_WIZ_10G,  /* J7200 SR2.0 */
 335	J784S4_WIZ_10G,
 336	J721S2_WIZ_10G,
 337};
 338
 339struct wiz_data {
 340	enum wiz_type type;
 341	const struct reg_field *pll0_refclk_mux_sel;
 342	const struct reg_field *pll1_refclk_mux_sel;
 343	const struct reg_field *refclk_dig_sel;
 344	const struct reg_field *pma_cmn_refclk1_dig_div;
 345	const struct reg_field *pma_cmn_refclk1_int_mode;
 346	const struct wiz_clk_mux_sel *clk_mux_sel;
 347	unsigned int clk_div_sel_num;
 348};
 349
 350#define WIZ_TYPEC_DIR_DEBOUNCE_MIN	100	/* ms */
 351#define WIZ_TYPEC_DIR_DEBOUNCE_MAX	1000
 352
 353struct wiz {
 354	struct regmap		*regmap;
 355	struct regmap		*scm_regmap;
 356	enum wiz_type		type;
 357	const struct wiz_clk_mux_sel *clk_mux_sel;
 358	const struct wiz_clk_div_sel *clk_div_sel;
 359	unsigned int		clk_div_sel_num;
 360	struct regmap_field	*por_en;
 361	struct regmap_field	*phy_reset_n;
 362	struct regmap_field	*phy_en_refclk;
 363	struct regmap_field	*p_enable[WIZ_MAX_LANES];
 364	struct regmap_field	*p_align[WIZ_MAX_LANES];
 365	struct regmap_field	*p_raw_auto_start[WIZ_MAX_LANES];
 366	struct regmap_field	*p_standard_mode[WIZ_MAX_LANES];
 367	struct regmap_field	*p_mac_div_sel0[WIZ_MAX_LANES];
 368	struct regmap_field	*p_mac_div_sel1[WIZ_MAX_LANES];
 369	struct regmap_field	*p0_fullrt_div[WIZ_MAX_LANES];
 370	struct regmap_field	*p0_mac_src_sel[WIZ_MAX_LANES];
 371	struct regmap_field	*p0_rxfclk_sel[WIZ_MAX_LANES];
 372	struct regmap_field	*p0_refclk_sel[WIZ_MAX_LANES];
 373	struct regmap_field	*pma_cmn_refclk_int_mode;
 374	struct regmap_field	*pma_cmn_refclk1_int_mode;
 375	struct regmap_field	*pma_cmn_refclk_mode;
 376	struct regmap_field	*pma_cmn_refclk_dig_div;
 377	struct regmap_field	*pma_cmn_refclk1_dig_div;
 378	struct regmap_field	*mux_sel_field[WIZ_MUX_NUM_CLOCKS];
 379	struct regmap_field	*div_sel_field[WIZ_DIV_NUM_CLOCKS_16G];
 380	struct regmap_field	*typec_ln10_swap;
 381	struct regmap_field	*typec_ln23_swap;
 382	struct regmap_field	*sup_legacy_clk_override;
 383
 384	struct device		*dev;
 385	u32			num_lanes;
 386	struct platform_device	*serdes_pdev;
 387	struct reset_controller_dev wiz_phy_reset_dev;
 388	struct gpio_desc	*gpio_typec_dir;
 389	int			typec_dir_delay;
 390	u32 lane_phy_type[WIZ_MAX_LANES];
 391	u32 master_lane_num[WIZ_MAX_LANES];
 392	struct clk		*input_clks[WIZ_MAX_INPUT_CLOCKS];
 393	struct clk		*output_clks[WIZ_MAX_OUTPUT_CLOCKS];
 394	struct clk_onecell_data	clk_data;
 395	const struct wiz_data	*data;
 396	int			mux_sel_status[WIZ_MUX_NUM_CLOCKS];
 397};
 398
 399static int wiz_reset(struct wiz *wiz)
 400{
 401	int ret;
 402
 403	ret = regmap_field_write(wiz->por_en, 0x1);
 404	if (ret)
 405		return ret;
 406
 407	mdelay(1);
 408
 409	ret = regmap_field_write(wiz->por_en, 0x0);
 410	if (ret)
 411		return ret;
 412
 413	return 0;
 414}
 415
 416static int wiz_p_mac_div_sel(struct wiz *wiz)
 417{
 418	u32 num_lanes = wiz->num_lanes;
 419	int ret;
 420	int i;
 421
 422	for (i = 0; i < num_lanes; i++) {
 423		if (wiz->lane_phy_type[i] == PHY_TYPE_SGMII ||
 424		    wiz->lane_phy_type[i] == PHY_TYPE_QSGMII ||
 425		    wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
 426			ret = regmap_field_write(wiz->p_mac_div_sel0[i], 1);
 427			if (ret)
 428				return ret;
 429
 430			ret = regmap_field_write(wiz->p_mac_div_sel1[i], 2);
 431			if (ret)
 432				return ret;
 433		}
 434	}
 435
 436	return 0;
 437}
 438
 439static int wiz_mode_select(struct wiz *wiz)
 440{
 441	u32 num_lanes = wiz->num_lanes;
 442	enum wiz_lane_standard_mode mode;
 443	int ret;
 444	int i;
 445
 446	for (i = 0; i < num_lanes; i++) {
 447		if (wiz->lane_phy_type[i] == PHY_TYPE_DP) {
 448			mode = LANE_MODE_GEN1;
 449		} else if (wiz->lane_phy_type[i] == PHY_TYPE_QSGMII) {
 450			mode = LANE_MODE_GEN2;
 451		} else if (wiz->lane_phy_type[i] == PHY_TYPE_USXGMII) {
 452			ret = regmap_field_write(wiz->p0_mac_src_sel[i], 0x3);
 453			ret = regmap_field_write(wiz->p0_rxfclk_sel[i], 0x3);
 454			ret = regmap_field_write(wiz->p0_refclk_sel[i], 0x2);
 455			mode = LANE_MODE_GEN2;
 456		} else {
 457			continue;
 458		}
 459
 460		ret = regmap_field_write(wiz->p_standard_mode[i], mode);
 461		if (ret)
 462			return ret;
 463	}
 464
 465	return 0;
 466}
 467
 468static int wiz_init_raw_interface(struct wiz *wiz, bool enable)
 469{
 470	u32 num_lanes = wiz->num_lanes;
 471	int i;
 472	int ret;
 473
 474	for (i = 0; i < num_lanes; i++) {
 475		ret = regmap_field_write(wiz->p_align[i], enable);
 476		if (ret)
 477			return ret;
 478
 479		ret = regmap_field_write(wiz->p_raw_auto_start[i], enable);
 480		if (ret)
 481			return ret;
 482	}
 483
 484	return 0;
 485}
 486
 487static int wiz_init(struct wiz *wiz)
 488{
 489	struct device *dev = wiz->dev;
 490	int ret;
 491
 492	ret = wiz_reset(wiz);
 493	if (ret) {
 494		dev_err(dev, "WIZ reset failed\n");
 495		return ret;
 496	}
 497
 498	ret = wiz_mode_select(wiz);
 499	if (ret) {
 500		dev_err(dev, "WIZ mode select failed\n");
 501		return ret;
 502	}
 503
 504	ret = wiz_p_mac_div_sel(wiz);
 505	if (ret) {
 506		dev_err(dev, "Configuring P0 MAC DIV SEL failed\n");
 507		return ret;
 508	}
 509
 510	ret = wiz_init_raw_interface(wiz, true);
 511	if (ret) {
 512		dev_err(dev, "WIZ interface initialization failed\n");
 513		return ret;
 514	}
 515
 516	return 0;
 517}
 518
 519static int wiz_regfield_init(struct wiz *wiz)
 520{
 521	struct regmap *regmap = wiz->regmap;
 522	struct regmap *scm_regmap = wiz->regmap; /* updated later to scm_regmap if applicable */
 523	int num_lanes = wiz->num_lanes;
 524	struct device *dev = wiz->dev;
 525	const struct wiz_data *data = wiz->data;
 526	int i;
 527
 528	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
 529	if (IS_ERR(wiz->por_en)) {
 530		dev_err(dev, "POR_EN reg field init failed\n");
 531		return PTR_ERR(wiz->por_en);
 532	}
 533
 534	wiz->phy_reset_n = devm_regmap_field_alloc(dev, regmap,
 535						   phy_reset_n);
 536	if (IS_ERR(wiz->phy_reset_n)) {
 537		dev_err(dev, "PHY_RESET_N reg field init failed\n");
 538		return PTR_ERR(wiz->phy_reset_n);
 539	}
 540
 541	wiz->pma_cmn_refclk_int_mode =
 542		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_int_mode);
 543	if (IS_ERR(wiz->pma_cmn_refclk_int_mode)) {
 544		dev_err(dev, "PMA_CMN_REFCLK_INT_MODE reg field init failed\n");
 545		return PTR_ERR(wiz->pma_cmn_refclk_int_mode);
 546	}
 547
 548	wiz->pma_cmn_refclk_mode =
 549		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_mode);
 550	if (IS_ERR(wiz->pma_cmn_refclk_mode)) {
 551		dev_err(dev, "PMA_CMN_REFCLK_MODE reg field init failed\n");
 552		return PTR_ERR(wiz->pma_cmn_refclk_mode);
 553	}
 554
 555	wiz->div_sel_field[CMN_REFCLK_DIG_DIV] =
 556		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk_dig_div);
 557	if (IS_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV])) {
 558		dev_err(dev, "PMA_CMN_REFCLK_DIG_DIV reg field init failed\n");
 559		return PTR_ERR(wiz->div_sel_field[CMN_REFCLK_DIG_DIV]);
 560	}
 561
 562	if (data->pma_cmn_refclk1_dig_div) {
 563		wiz->div_sel_field[CMN_REFCLK1_DIG_DIV] =
 564			devm_regmap_field_alloc(dev, regmap,
 565						*data->pma_cmn_refclk1_dig_div);
 566		if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV])) {
 567			dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
 568			return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1_DIG_DIV]);
 569		}
 570	}
 571
 572	if (wiz->scm_regmap) {
 573		scm_regmap = wiz->scm_regmap;
 574		wiz->sup_legacy_clk_override =
 575			devm_regmap_field_alloc(dev, scm_regmap, sup_legacy_clk_override);
 576		if (IS_ERR(wiz->sup_legacy_clk_override)) {
 577			dev_err(dev, "SUP_LEGACY_CLK_OVERRIDE reg field init failed\n");
 578			return PTR_ERR(wiz->sup_legacy_clk_override);
 579		}
 580	}
 581
 582	wiz->mux_sel_field[PLL0_REFCLK] =
 583		devm_regmap_field_alloc(dev, scm_regmap, *data->pll0_refclk_mux_sel);
 584	if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
 585		dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
 586		return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
 587	}
 588
 589	wiz->mux_sel_field[PLL1_REFCLK] =
 590		devm_regmap_field_alloc(dev, scm_regmap, *data->pll1_refclk_mux_sel);
 591	if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
 592		dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
 593		return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
 594	}
 595
 596	wiz->mux_sel_field[REFCLK_DIG] = devm_regmap_field_alloc(dev, scm_regmap,
 597								 *data->refclk_dig_sel);
 598	if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
 599		dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
 600		return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
 601	}
 602
 603	if (data->pma_cmn_refclk1_int_mode) {
 604		wiz->pma_cmn_refclk1_int_mode =
 605			devm_regmap_field_alloc(dev, scm_regmap, *data->pma_cmn_refclk1_int_mode);
 606		if (IS_ERR(wiz->pma_cmn_refclk1_int_mode)) {
 607			dev_err(dev, "PMA_CMN_REFCLK1_INT_MODE reg field init failed\n");
 608			return PTR_ERR(wiz->pma_cmn_refclk1_int_mode);
 609		}
 610	}
 611
 612	for (i = 0; i < num_lanes; i++) {
 613		wiz->p_enable[i] = devm_regmap_field_alloc(dev, regmap,
 614							   p_enable[i]);
 615		if (IS_ERR(wiz->p_enable[i])) {
 616			dev_err(dev, "P%d_ENABLE reg field init failed\n", i);
 617			return PTR_ERR(wiz->p_enable[i]);
 618		}
 619
 620		wiz->p_align[i] = devm_regmap_field_alloc(dev, regmap,
 621							  p_align[i]);
 622		if (IS_ERR(wiz->p_align[i])) {
 623			dev_err(dev, "P%d_ALIGN reg field init failed\n", i);
 624			return PTR_ERR(wiz->p_align[i]);
 625		}
 626
 627		wiz->p_raw_auto_start[i] =
 628		  devm_regmap_field_alloc(dev, regmap, p_raw_auto_start[i]);
 629		if (IS_ERR(wiz->p_raw_auto_start[i])) {
 630			dev_err(dev, "P%d_RAW_AUTO_START reg field init fail\n",
 631				i);
 632			return PTR_ERR(wiz->p_raw_auto_start[i]);
 633		}
 634
 635		wiz->p_standard_mode[i] =
 636		  devm_regmap_field_alloc(dev, regmap, p_standard_mode[i]);
 637		if (IS_ERR(wiz->p_standard_mode[i])) {
 638			dev_err(dev, "P%d_STANDARD_MODE reg field init fail\n",
 639				i);
 640			return PTR_ERR(wiz->p_standard_mode[i]);
 641		}
 642
 643		wiz->p0_fullrt_div[i] = devm_regmap_field_alloc(dev, regmap, p0_fullrt_div[i]);
 644		if (IS_ERR(wiz->p0_fullrt_div[i])) {
 645			dev_err(dev, "P%d_FULLRT_DIV reg field init failed\n", i);
 646			return PTR_ERR(wiz->p0_fullrt_div[i]);
 647		}
 648
 649		wiz->p0_mac_src_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_mac_src_sel[i]);
 650		if (IS_ERR(wiz->p0_mac_src_sel[i])) {
 651			dev_err(dev, "P%d_MAC_SRC_SEL reg field init failed\n", i);
 652			return PTR_ERR(wiz->p0_mac_src_sel[i]);
 653		}
 654
 655		wiz->p0_rxfclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_rxfclk_sel[i]);
 656		if (IS_ERR(wiz->p0_rxfclk_sel[i])) {
 657			dev_err(dev, "P%d_RXFCLK_SEL reg field init failed\n", i);
 658			return PTR_ERR(wiz->p0_rxfclk_sel[i]);
 659		}
 660
 661		wiz->p0_refclk_sel[i] = devm_regmap_field_alloc(dev, regmap, p0_refclk_sel[i]);
 662		if (IS_ERR(wiz->p0_refclk_sel[i])) {
 663			dev_err(dev, "P%d_REFCLK_SEL reg field init failed\n", i);
 664			return PTR_ERR(wiz->p0_refclk_sel[i]);
 665		}
 666
 667		wiz->p_mac_div_sel0[i] =
 668		  devm_regmap_field_alloc(dev, regmap, p_mac_div_sel0[i]);
 669		if (IS_ERR(wiz->p_mac_div_sel0[i])) {
 670			dev_err(dev, "P%d_MAC_DIV_SEL0 reg field init fail\n",
 671				i);
 672			return PTR_ERR(wiz->p_mac_div_sel0[i]);
 673		}
 674
 675		wiz->p_mac_div_sel1[i] =
 676		  devm_regmap_field_alloc(dev, regmap, p_mac_div_sel1[i]);
 677		if (IS_ERR(wiz->p_mac_div_sel1[i])) {
 678			dev_err(dev, "P%d_MAC_DIV_SEL1 reg field init fail\n",
 679				i);
 680			return PTR_ERR(wiz->p_mac_div_sel1[i]);
 681		}
 682	}
 683
 684	wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
 685						       typec_ln10_swap);
 686	if (IS_ERR(wiz->typec_ln10_swap)) {
 687		dev_err(dev, "LN10_SWAP reg field init failed\n");
 688		return PTR_ERR(wiz->typec_ln10_swap);
 689	}
 690
 691	wiz->typec_ln23_swap = devm_regmap_field_alloc(dev, regmap,
 692						       typec_ln23_swap);
 693	if (IS_ERR(wiz->typec_ln23_swap)) {
 694		dev_err(dev, "LN23_SWAP reg field init failed\n");
 695		return PTR_ERR(wiz->typec_ln23_swap);
 696	}
 697
 698	wiz->phy_en_refclk = devm_regmap_field_alloc(dev, regmap, phy_en_refclk);
 699	if (IS_ERR(wiz->phy_en_refclk)) {
 700		dev_err(dev, "PHY_EN_REFCLK reg field init failed\n");
 701		return PTR_ERR(wiz->phy_en_refclk);
 702	}
 703
 704	return 0;
 705}
 706
 707static int wiz_phy_en_refclk_enable(struct clk_hw *hw)
 708{
 709	struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
 710	struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
 711
 712	regmap_field_write(phy_en_refclk, 1);
 713
 714	return 0;
 715}
 716
 717static void wiz_phy_en_refclk_disable(struct clk_hw *hw)
 718{
 719	struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
 720	struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
 721
 722	regmap_field_write(phy_en_refclk, 0);
 723}
 724
 725static int wiz_phy_en_refclk_is_enabled(struct clk_hw *hw)
 726{
 727	struct wiz_phy_en_refclk *wiz_phy_en_refclk = to_wiz_phy_en_refclk(hw);
 728	struct regmap_field *phy_en_refclk = wiz_phy_en_refclk->phy_en_refclk;
 729	int val;
 730
 731	regmap_field_read(phy_en_refclk, &val);
 732
 733	return !!val;
 734}
 735
 736static const struct clk_ops wiz_phy_en_refclk_ops = {
 737	.enable = wiz_phy_en_refclk_enable,
 738	.disable = wiz_phy_en_refclk_disable,
 739	.is_enabled = wiz_phy_en_refclk_is_enabled,
 740};
 741
 742static int wiz_phy_en_refclk_register(struct wiz *wiz)
 743{
 744	struct wiz_phy_en_refclk *wiz_phy_en_refclk;
 745	struct device *dev = wiz->dev;
 746	struct clk_init_data *init;
 747	struct clk *clk;
 748	char *clk_name;
 749	unsigned int sz;
 750
 751	wiz_phy_en_refclk = devm_kzalloc(dev, sizeof(*wiz_phy_en_refclk), GFP_KERNEL);
 752	if (!wiz_phy_en_refclk)
 753		return -ENOMEM;
 754
 755	init = &wiz_phy_en_refclk->clk_data;
 756
 757	init->ops = &wiz_phy_en_refclk_ops;
 758	init->flags = 0;
 759
 760	sz = strlen(dev_name(dev)) + strlen(output_clk_names[TI_WIZ_PHY_EN_REFCLK]) + 2;
 761
 762	clk_name = kzalloc(sz, GFP_KERNEL);
 763	if (!clk_name)
 764		return -ENOMEM;
 765
 766	snprintf(clk_name, sz, "%s_%s", dev_name(dev), output_clk_names[TI_WIZ_PHY_EN_REFCLK]);
 767	init->name = clk_name;
 768
 769	wiz_phy_en_refclk->phy_en_refclk = wiz->phy_en_refclk;
 770	wiz_phy_en_refclk->hw.init = init;
 771
 772	clk = devm_clk_register(dev, &wiz_phy_en_refclk->hw);
 773
 774	kfree(clk_name);
 775
 776	if (IS_ERR(clk))
 777		return PTR_ERR(clk);
 778
 779	wiz->output_clks[TI_WIZ_PHY_EN_REFCLK] = clk;
 780
 781	return 0;
 782}
 783
 784static u8 wiz_clk_mux_get_parent(struct clk_hw *hw)
 785{
 786	struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
 787	struct regmap_field *field = mux->field;
 788	unsigned int val;
 789
 790	regmap_field_read(field, &val);
 791	return clk_mux_val_to_index(hw, (u32 *)mux->table, 0, val);
 792}
 793
 794static int wiz_clk_mux_set_parent(struct clk_hw *hw, u8 index)
 795{
 796	struct wiz_clk_mux *mux = to_wiz_clk_mux(hw);
 797	struct regmap_field *field = mux->field;
 798	int val;
 799
 800	val = mux->table[index];
 801	return regmap_field_write(field, val);
 802}
 803
 804static const struct clk_ops wiz_clk_mux_ops = {
 805	.determine_rate = __clk_mux_determine_rate,
 806	.set_parent = wiz_clk_mux_set_parent,
 807	.get_parent = wiz_clk_mux_get_parent,
 808};
 809
 810static int wiz_mux_clk_register(struct wiz *wiz, struct regmap_field *field,
 811				const struct wiz_clk_mux_sel *mux_sel, int clk_index)
 812{
 813	struct device *dev = wiz->dev;
 814	struct clk_init_data *init;
 815	const char **parent_names;
 816	unsigned int num_parents;
 817	struct wiz_clk_mux *mux;
 818	char clk_name[100];
 819	struct clk *clk;
 820	int ret = 0, i;
 821
 822	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 823	if (!mux)
 824		return -ENOMEM;
 825
 826	num_parents = mux_sel->num_parents;
 827
 828	parent_names = kzalloc((sizeof(char *) * num_parents), GFP_KERNEL);
 829	if (!parent_names)
 830		return -ENOMEM;
 831
 832	for (i = 0; i < num_parents; i++) {
 833		clk = wiz->input_clks[mux_sel->parents[i]];
 834		if (IS_ERR_OR_NULL(clk)) {
 835			dev_err(dev, "Failed to get parent clk for %s\n",
 836				output_clk_names[clk_index]);
 837			ret = -EINVAL;
 838			goto err;
 839		}
 840		parent_names[i] = __clk_get_name(clk);
 841	}
 842
 843	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), output_clk_names[clk_index]);
 844
 845	init = &mux->clk_data;
 846
 847	init->ops = &wiz_clk_mux_ops;
 848	init->flags = CLK_SET_RATE_NO_REPARENT;
 849	init->parent_names = parent_names;
 850	init->num_parents = num_parents;
 851	init->name = clk_name;
 852
 853	mux->field = field;
 854	mux->table = mux_sel->table;
 855	mux->hw.init = init;
 856
 857	clk = devm_clk_register(dev, &mux->hw);
 858	if (IS_ERR(clk)) {
 859		ret = PTR_ERR(clk);
 860		goto err;
 861	}
 862
 863	wiz->output_clks[clk_index] = clk;
 864
 865err:
 866	kfree(parent_names);
 867
 868	return ret;
 869}
 870
 871static int wiz_mux_of_clk_register(struct wiz *wiz, struct device_node *node,
 872				   struct regmap_field *field, const u32 *table)
 873{
 874	struct device *dev = wiz->dev;
 875	struct clk_init_data *init;
 876	const char **parent_names;
 877	unsigned int num_parents;
 878	struct wiz_clk_mux *mux;
 879	char clk_name[100];
 880	struct clk *clk;
 881	int ret;
 882
 883	mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
 884	if (!mux)
 885		return -ENOMEM;
 886
 887	num_parents = of_clk_get_parent_count(node);
 888	if (num_parents < 2) {
 889		dev_err(dev, "SERDES clock must have parents\n");
 890		return -EINVAL;
 891	}
 892
 893	parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents),
 894				    GFP_KERNEL);
 895	if (!parent_names)
 896		return -ENOMEM;
 897
 898	of_clk_parent_fill(node, parent_names, num_parents);
 899
 900	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 901		 node->name);
 902
 903	init = &mux->clk_data;
 904
 905	init->ops = &wiz_clk_mux_ops;
 906	init->flags = CLK_SET_RATE_NO_REPARENT;
 907	init->parent_names = parent_names;
 908	init->num_parents = num_parents;
 909	init->name = clk_name;
 910
 911	mux->field = field;
 912	mux->table = table;
 913	mux->hw.init = init;
 914
 915	clk = devm_clk_register(dev, &mux->hw);
 916	if (IS_ERR(clk))
 917		return PTR_ERR(clk);
 918
 919	ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
 920	if (ret)
 921		dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
 922
 923	return ret;
 924}
 925
 926static unsigned long wiz_clk_div_recalc_rate(struct clk_hw *hw,
 927					     unsigned long parent_rate)
 928{
 929	struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 930	struct regmap_field *field = div->field;
 931	int val;
 932
 933	regmap_field_read(field, &val);
 934
 935	return divider_recalc_rate(hw, parent_rate, val, div->table, 0x0, 2);
 936}
 937
 938static long wiz_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
 939				   unsigned long *prate)
 940{
 941	struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 942
 943	return divider_round_rate(hw, rate, prate, div->table, 2, 0x0);
 944}
 945
 946static int wiz_clk_div_set_rate(struct clk_hw *hw, unsigned long rate,
 947				unsigned long parent_rate)
 948{
 949	struct wiz_clk_divider *div = to_wiz_clk_div(hw);
 950	struct regmap_field *field = div->field;
 951	int val;
 952
 953	val = divider_get_val(rate, parent_rate, div->table, 2, 0x0);
 954	if (val < 0)
 955		return val;
 956
 957	return regmap_field_write(field, val);
 958}
 959
 960static const struct clk_ops wiz_clk_div_ops = {
 961	.recalc_rate = wiz_clk_div_recalc_rate,
 962	.round_rate = wiz_clk_div_round_rate,
 963	.set_rate = wiz_clk_div_set_rate,
 964};
 965
 966static int wiz_div_clk_register(struct wiz *wiz, struct device_node *node,
 967				struct regmap_field *field,
 968				const struct clk_div_table *table)
 969{
 970	struct device *dev = wiz->dev;
 971	struct wiz_clk_divider *div;
 972	struct clk_init_data *init;
 973	const char **parent_names;
 974	char clk_name[100];
 975	struct clk *clk;
 976	int ret;
 977
 978	div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
 979	if (!div)
 980		return -ENOMEM;
 981
 982	snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev),
 983		 node->name);
 984
 985	parent_names = devm_kzalloc(dev, sizeof(char *), GFP_KERNEL);
 986	if (!parent_names)
 987		return -ENOMEM;
 988
 989	of_clk_parent_fill(node, parent_names, 1);
 990
 991	init = &div->clk_data;
 992
 993	init->ops = &wiz_clk_div_ops;
 994	init->flags = 0;
 995	init->parent_names = parent_names;
 996	init->num_parents = 1;
 997	init->name = clk_name;
 998
 999	div->field = field;
1000	div->table = table;
1001	div->hw.init = init;
1002
1003	clk = devm_clk_register(dev, &div->hw);
1004	if (IS_ERR(clk))
1005		return PTR_ERR(clk);
1006
1007	ret = of_clk_add_provider(node, of_clk_src_simple_get, clk);
1008	if (ret)
1009		dev_err(dev, "Failed to add clock provider: %s\n", clk_name);
1010
1011	return ret;
1012}
1013
1014static void wiz_clock_cleanup(struct wiz *wiz, struct device_node *node)
1015{
1016	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1017	struct device *dev = wiz->dev;
1018	struct device_node *clk_node;
1019	int i;
1020
1021	switch (wiz->type) {
1022	case AM64_WIZ_10G:
1023	case J7200_WIZ_10G:
1024	case J784S4_WIZ_10G:
1025	case J721S2_WIZ_10G:
1026		of_clk_del_provider(dev->of_node);
1027		return;
1028	default:
1029		break;
1030	}
1031
1032	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1033		clk_node = of_get_child_by_name(node, clk_mux_sel[i].node_name);
1034		of_clk_del_provider(clk_node);
1035		of_node_put(clk_node);
1036	}
1037
1038	for (i = 0; i < wiz->clk_div_sel_num; i++) {
1039		clk_node = of_get_child_by_name(node, clk_div_sel[i].node_name);
1040		of_clk_del_provider(clk_node);
1041		of_node_put(clk_node);
1042	}
1043
1044	of_clk_del_provider(wiz->dev->of_node);
1045}
1046
1047static int wiz_clock_register(struct wiz *wiz)
1048{
1049	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1050	struct device *dev = wiz->dev;
1051	struct device_node *node = dev->of_node;
1052	int clk_index;
1053	int ret;
1054	int i;
1055
1056	clk_index = TI_WIZ_PLL0_REFCLK;
1057	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++, clk_index++) {
1058		ret = wiz_mux_clk_register(wiz, wiz->mux_sel_field[i], &clk_mux_sel[i], clk_index);
1059		if (ret) {
1060			dev_err(dev, "Failed to register clk: %s\n", output_clk_names[clk_index]);
1061			return ret;
1062		}
1063	}
1064
1065	ret = wiz_phy_en_refclk_register(wiz);
1066	if (ret) {
1067		dev_err(dev, "Failed to add phy-en-refclk\n");
1068		return ret;
1069	}
1070
1071	wiz->clk_data.clks = wiz->output_clks;
1072	wiz->clk_data.clk_num = WIZ_MAX_OUTPUT_CLOCKS;
1073	ret = of_clk_add_provider(node, of_clk_src_onecell_get, &wiz->clk_data);
1074	if (ret)
1075		dev_err(dev, "Failed to add clock provider: %s\n", node->name);
1076
1077	return ret;
1078}
1079
1080static void wiz_clock_init(struct wiz *wiz)
1081{
1082	unsigned long rate;
1083
1084	rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]);
1085	if (rate >= REF_CLK_100MHZ)
1086		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x1);
1087	else
1088		regmap_field_write(wiz->pma_cmn_refclk_int_mode, 0x3);
1089
1090	switch (wiz->type) {
1091	case AM64_WIZ_10G:
1092	case J7200_WIZ_10G:
1093		switch (rate) {
1094		case REF_CLK_100MHZ:
1095			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x2);
1096			break;
1097		case REF_CLK_156_25MHZ:
1098			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0x3);
1099			break;
1100		default:
1101			regmap_field_write(wiz->div_sel_field[CMN_REFCLK_DIG_DIV], 0);
1102			break;
1103		}
1104		break;
1105	default:
1106		break;
1107	}
1108
1109	if (wiz->input_clks[WIZ_CORE_REFCLK1]) {
1110		rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]);
1111		if (rate >= REF_CLK_100MHZ)
1112			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x1);
1113		else
1114			regmap_field_write(wiz->pma_cmn_refclk1_int_mode, 0x3);
1115	}
1116
1117	rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]);
1118	if (rate >= REF_CLK_100MHZ)
1119		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x0);
1120	else
1121		regmap_field_write(wiz->pma_cmn_refclk_mode, 0x2);
1122}
1123
1124static int wiz_clock_probe(struct wiz *wiz, struct device_node *node)
1125{
1126	const struct wiz_clk_mux_sel *clk_mux_sel = wiz->clk_mux_sel;
1127	struct device *dev = wiz->dev;
1128	struct device_node *clk_node;
1129	const char *node_name;
1130	struct clk *clk;
1131	int ret;
1132	int i;
1133
1134	clk = devm_clk_get(dev, "core_ref_clk");
1135	if (IS_ERR(clk))
1136		return dev_err_probe(dev, PTR_ERR(clk),
1137				     "core_ref_clk clock not found\n");
1138
1139	wiz->input_clks[WIZ_CORE_REFCLK] = clk;
1140
1141	if (wiz->data->pma_cmn_refclk1_int_mode) {
1142		clk = devm_clk_get(dev, "core_ref1_clk");
1143		if (IS_ERR(clk))
1144			return dev_err_probe(dev, PTR_ERR(clk),
1145					     "core_ref1_clk clock not found\n");
1146
1147		wiz->input_clks[WIZ_CORE_REFCLK1] = clk;
1148	}
1149
1150	clk = devm_clk_get(dev, "ext_ref_clk");
1151	if (IS_ERR(clk))
1152		return dev_err_probe(dev, PTR_ERR(clk),
1153				     "ext_ref_clk clock not found\n");
1154
1155	wiz->input_clks[WIZ_EXT_REFCLK] = clk;
1156
1157	wiz_clock_init(wiz);
1158
1159	switch (wiz->type) {
1160	case AM64_WIZ_10G:
1161	case J7200_WIZ_10G:
1162	case J784S4_WIZ_10G:
1163	case J721S2_WIZ_10G:
1164		ret = wiz_clock_register(wiz);
1165		if (ret)
1166			return dev_err_probe(dev, ret, "Failed to register wiz clocks\n");
1167
1168		return 0;
1169	default:
1170		break;
1171	}
1172
1173	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++) {
1174		node_name = clk_mux_sel[i].node_name;
1175		clk_node = of_get_child_by_name(node, node_name);
1176		if (!clk_node) {
1177			ret = dev_err_probe(dev, -EINVAL, "Unable to get %s node\n", node_name);
1178			goto err;
1179		}
1180
1181		ret = wiz_mux_of_clk_register(wiz, clk_node, wiz->mux_sel_field[i],
1182					      clk_mux_sel[i].table);
1183		of_node_put(clk_node);
1184		if (ret) {
1185			dev_err_probe(dev, ret, "Failed to register %s clock\n",
1186				      node_name);
1187			goto err;
1188		}
1189
1190	}
1191
1192	for (i = 0; i < wiz->clk_div_sel_num; i++) {
1193		node_name = clk_div_sel[i].node_name;
1194		clk_node = of_get_child_by_name(node, node_name);
1195		if (!clk_node) {
1196			ret = dev_err_probe(dev, -EINVAL, "Unable to get %s node\n", node_name);
1197			goto err;
1198		}
1199
1200		ret = wiz_div_clk_register(wiz, clk_node, wiz->div_sel_field[i],
1201					   clk_div_sel[i].table);
1202		of_node_put(clk_node);
1203		if (ret) {
1204			dev_err_probe(dev, ret, "Failed to register %s clock\n",
1205				      node_name);
1206			goto err;
1207		}
1208	}
1209
1210	return 0;
1211err:
1212	wiz_clock_cleanup(wiz, node);
1213
1214	return ret;
1215}
1216
1217static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,
1218				unsigned long id)
1219{
1220	struct device *dev = rcdev->dev;
1221	struct wiz *wiz = dev_get_drvdata(dev);
1222	int ret = 0;
1223
1224	if (id == 0) {
1225		ret = regmap_field_write(wiz->phy_reset_n, false);
1226		return ret;
1227	}
1228
1229	ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_DISABLE);
1230	return ret;
1231}
1232
1233static int wiz_phy_fullrt_div(struct wiz *wiz, int lane)
1234{
1235	switch (wiz->type) {
1236	case AM64_WIZ_10G:
1237		if (wiz->lane_phy_type[lane] == PHY_TYPE_PCIE)
1238			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x1);
1239		break;
1240
1241	case J721E_WIZ_16G:
1242	case J721E_WIZ_10G:
1243	case J7200_WIZ_10G:
1244	case J721S2_WIZ_10G:
1245	case J784S4_WIZ_10G:
1246		if (wiz->lane_phy_type[lane] == PHY_TYPE_SGMII)
1247			return regmap_field_write(wiz->p0_fullrt_div[lane], 0x2);
1248		break;
1249	default:
1250		return 0;
1251	}
1252	return 0;
1253}
1254
1255static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
1256				  unsigned long id)
1257{
1258	struct device *dev = rcdev->dev;
1259	struct wiz *wiz = dev_get_drvdata(dev);
1260	int ret;
1261
1262	if (id == 0) {
1263		/* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
1264		if (wiz->gpio_typec_dir) {
1265			if (wiz->typec_dir_delay)
1266				msleep_interruptible(wiz->typec_dir_delay);
1267
1268			if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
1269				regmap_field_write(wiz->typec_ln10_swap, 1);
1270			else
1271				regmap_field_write(wiz->typec_ln10_swap, 0);
1272		} else {
1273			/* if no typec-dir gpio is specified and PHY type is USB3
1274			 * with master lane number is '0' or '2', then set LN10 or
1275			 * LN23 SWAP bit to '1' respectively.
1276			 */
1277			u32 num_lanes = wiz->num_lanes;
1278			int i;
1279
1280			for (i = 0; i < num_lanes; i++) {
1281				if (wiz->lane_phy_type[i] == PHY_TYPE_USB3) {
1282					switch (wiz->master_lane_num[i]) {
1283					case LANE0:
1284						regmap_field_write(wiz->typec_ln10_swap, 1);
1285						break;
1286					case LANE2:
1287						regmap_field_write(wiz->typec_ln23_swap, 1);
1288						break;
1289					default:
1290						break;
1291					}
1292				}
1293			}
1294		}
1295	}
1296
1297	if (id == 0) {
1298		ret = regmap_field_write(wiz->phy_reset_n, true);
1299		return ret;
1300	}
1301
1302	ret = wiz_phy_fullrt_div(wiz, id - 1);
1303	if (ret)
1304		return ret;
1305
1306	if (wiz->lane_phy_type[id - 1] == PHY_TYPE_DP)
1307		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE);
1308	else
1309		ret = regmap_field_write(wiz->p_enable[id - 1], P_ENABLE_FORCE);
1310
1311	return ret;
1312}
1313
1314static const struct reset_control_ops wiz_phy_reset_ops = {
1315	.assert = wiz_phy_reset_assert,
1316	.deassert = wiz_phy_reset_deassert,
1317};
1318
1319static const struct regmap_config wiz_regmap_config = {
1320	.reg_bits = 32,
1321	.val_bits = 32,
1322	.reg_stride = 4,
1323};
1324
1325static struct wiz_data j721e_16g_data = {
1326	.type = J721E_WIZ_16G,
1327	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1328	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1329	.refclk_dig_sel = &refclk_dig_sel_16g,
1330	.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
1331	.clk_mux_sel = clk_mux_sel_16g,
1332	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
1333};
1334
1335static struct wiz_data j721e_10g_data = {
1336	.type = J721E_WIZ_10G,
1337	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1338	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1339	.refclk_dig_sel = &refclk_dig_sel_10g,
1340	.clk_mux_sel = clk_mux_sel_10g,
1341	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1342};
1343
1344static struct wiz_data am64_10g_data = {
1345	.type = AM64_WIZ_10G,
1346	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1347	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1348	.refclk_dig_sel = &refclk_dig_sel_10g,
1349	.clk_mux_sel = clk_mux_sel_10g,
1350	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1351};
1352
1353static struct wiz_data j7200_pg2_10g_data = {
1354	.type = J7200_WIZ_10G,
1355	.pll0_refclk_mux_sel = &sup_pll0_refclk_mux_sel,
1356	.pll1_refclk_mux_sel = &sup_pll1_refclk_mux_sel,
1357	.refclk_dig_sel = &sup_refclk_dig_sel_10g,
1358	.pma_cmn_refclk1_int_mode = &sup_pma_cmn_refclk1_int_mode,
1359	.clk_mux_sel = clk_mux_sel_10g_2_refclk,
1360	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1361};
1362
1363static struct wiz_data j784s4_10g_data = {
1364	.type = J784S4_WIZ_10G,
1365	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel_2,
1366	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel_2,
1367	.refclk_dig_sel = &refclk_dig_sel_16g,
1368	.pma_cmn_refclk1_int_mode = &pma_cmn_refclk1_int_mode,
1369	.clk_mux_sel = clk_mux_sel_10g_2_refclk,
1370	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1371};
1372
1373static struct wiz_data j721s2_10g_data = {
1374	.type = J721S2_WIZ_10G,
1375	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
1376	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
1377	.refclk_dig_sel = &refclk_dig_sel_10g,
1378	.clk_mux_sel = clk_mux_sel_10g,
1379	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
1380};
1381
1382static const struct of_device_id wiz_id_table[] = {
1383	{
1384		.compatible = "ti,j721e-wiz-16g", .data = &j721e_16g_data,
1385	},
1386	{
1387		.compatible = "ti,j721e-wiz-10g", .data = &j721e_10g_data,
1388	},
1389	{
1390		.compatible = "ti,am64-wiz-10g", .data = &am64_10g_data,
1391	},
1392	{
1393		.compatible = "ti,j7200-wiz-10g", .data = &j7200_pg2_10g_data,
1394	},
1395	{
1396		.compatible = "ti,j784s4-wiz-10g", .data = &j784s4_10g_data,
1397	},
1398	{
1399		.compatible = "ti,j721s2-wiz-10g", .data = &j721s2_10g_data,
1400	},
1401	{}
1402};
1403MODULE_DEVICE_TABLE(of, wiz_id_table);
1404
1405static int wiz_get_lane_phy_types(struct device *dev, struct wiz *wiz)
1406{
1407	struct device_node *serdes;
1408
1409	serdes = of_get_child_by_name(dev->of_node, "serdes");
1410	if (!serdes) {
1411		dev_err(dev, "%s: Getting \"serdes\"-node failed\n", __func__);
1412		return -EINVAL;
1413	}
1414
1415	for_each_child_of_node_scoped(serdes, subnode) {
1416		u32 reg, num_lanes = 1, phy_type = PHY_NONE;
1417		int ret, i;
1418
1419		if (!(of_node_name_eq(subnode, "phy") ||
1420		      of_node_name_eq(subnode, "link")))
1421			continue;
1422
1423		ret = of_property_read_u32(subnode, "reg", &reg);
1424		if (ret) {
1425			dev_err(dev,
1426				"%s: Reading \"reg\" from \"%s\" failed: %d\n",
1427				__func__, subnode->name, ret);
1428			of_node_put(serdes);
1429			return ret;
1430		}
1431		of_property_read_u32(subnode, "cdns,num-lanes", &num_lanes);
1432		of_property_read_u32(subnode, "cdns,phy-type", &phy_type);
1433
1434		dev_dbg(dev, "%s: Lanes %u-%u have phy-type %u\n", __func__,
1435			reg, reg + num_lanes - 1, phy_type);
1436
1437		for (i = reg; i < reg + num_lanes; i++) {
1438			wiz->master_lane_num[i] = reg;
1439			wiz->lane_phy_type[i] = phy_type;
1440		}
1441	}
1442
1443	of_node_put(serdes);
1444	return 0;
1445}
1446
1447static int wiz_probe(struct platform_device *pdev)
1448{
1449	struct reset_controller_dev *phy_reset_dev;
1450	struct device *dev = &pdev->dev;
1451	struct device_node *node = dev->of_node;
1452	struct platform_device *serdes_pdev;
1453	bool already_configured = false;
1454	struct device_node *child_node;
1455	struct regmap *regmap;
1456	struct resource res;
1457	void __iomem *base;
1458	struct wiz *wiz;
1459	int ret, val, i;
1460	u32 num_lanes;
1461	const struct wiz_data *data;
1462
1463	wiz = devm_kzalloc(dev, sizeof(*wiz), GFP_KERNEL);
1464	if (!wiz)
1465		return -ENOMEM;
1466
1467	data = of_device_get_match_data(dev);
1468	if (!data) {
1469		dev_err(dev, "NULL device data\n");
1470		return -EINVAL;
1471	}
1472
1473	wiz->data = data;
1474	wiz->type = data->type;
1475
1476	child_node = of_get_child_by_name(node, "serdes");
1477	if (!child_node) {
1478		dev_err(dev, "Failed to get SERDES child DT node\n");
1479		return -ENODEV;
1480	}
1481
1482	ret = of_address_to_resource(child_node, 0, &res);
1483	if (ret) {
1484		dev_err(dev, "Failed to get memory resource\n");
1485		goto err_addr_to_resource;
1486	}
1487
1488	base = devm_ioremap(dev, res.start, resource_size(&res));
1489	if (!base) {
1490		ret = -ENOMEM;
1491		goto err_addr_to_resource;
1492	}
1493
1494	regmap = devm_regmap_init_mmio(dev, base, &wiz_regmap_config);
1495	if (IS_ERR(regmap)) {
1496		dev_err(dev, "Failed to initialize regmap\n");
1497		ret = PTR_ERR(regmap);
1498		goto err_addr_to_resource;
1499	}
1500
1501	wiz->scm_regmap = syscon_regmap_lookup_by_phandle(node, "ti,scm");
1502	if (IS_ERR(wiz->scm_regmap)) {
1503		if (wiz->type == J7200_WIZ_10G) {
1504			dev_err(dev, "Couldn't get ti,scm regmap\n");
1505			ret = -ENODEV;
1506			goto err_addr_to_resource;
1507		}
1508
1509		wiz->scm_regmap = NULL;
1510	}
1511
1512	ret = of_property_read_u32(node, "num-lanes", &num_lanes);
1513	if (ret) {
1514		dev_err(dev, "Failed to read num-lanes property\n");
1515		goto err_addr_to_resource;
1516	}
1517
1518	if (num_lanes > WIZ_MAX_LANES) {
1519		dev_err(dev, "Cannot support %d lanes\n", num_lanes);
1520		ret = -ENODEV;
1521		goto err_addr_to_resource;
1522	}
1523
1524	wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
1525						      GPIOD_IN);
1526	if (IS_ERR(wiz->gpio_typec_dir)) {
1527		ret = PTR_ERR(wiz->gpio_typec_dir);
1528		if (ret != -EPROBE_DEFER)
1529			dev_err(dev, "Failed to request typec-dir gpio: %d\n",
1530				ret);
1531		goto err_addr_to_resource;
1532	}
1533
1534	if (wiz->gpio_typec_dir) {
1535		ret = of_property_read_u32(node, "typec-dir-debounce-ms",
1536					   &wiz->typec_dir_delay);
1537		if (ret && ret != -EINVAL) {
1538			dev_err(dev, "Invalid typec-dir-debounce property\n");
1539			goto err_addr_to_resource;
1540		}
1541
1542		/* use min. debounce from Type-C spec if not provided in DT  */
1543		if (ret == -EINVAL)
1544			wiz->typec_dir_delay = WIZ_TYPEC_DIR_DEBOUNCE_MIN;
1545
1546		if (wiz->typec_dir_delay < WIZ_TYPEC_DIR_DEBOUNCE_MIN ||
1547		    wiz->typec_dir_delay > WIZ_TYPEC_DIR_DEBOUNCE_MAX) {
1548			ret = -EINVAL;
1549			dev_err(dev, "Invalid typec-dir-debounce property\n");
1550			goto err_addr_to_resource;
1551		}
1552	}
1553
1554	ret = wiz_get_lane_phy_types(dev, wiz);
1555	if (ret)
1556		goto err_addr_to_resource;
1557
1558	wiz->dev = dev;
1559	wiz->regmap = regmap;
1560	wiz->num_lanes = num_lanes;
1561	wiz->clk_mux_sel = data->clk_mux_sel;
1562	wiz->clk_div_sel = clk_div_sel;
1563	wiz->clk_div_sel_num = data->clk_div_sel_num;
1564
1565	platform_set_drvdata(pdev, wiz);
1566
1567	ret = wiz_regfield_init(wiz);
1568	if (ret) {
1569		dev_err(dev, "Failed to initialize regfields\n");
1570		goto err_addr_to_resource;
1571	}
1572
1573	/* Enable supplemental Control override if available */
1574	if (wiz->scm_regmap)
1575		regmap_field_write(wiz->sup_legacy_clk_override, 1);
1576
1577	phy_reset_dev = &wiz->wiz_phy_reset_dev;
1578	phy_reset_dev->dev = dev;
1579	phy_reset_dev->ops = &wiz_phy_reset_ops;
1580	phy_reset_dev->owner = THIS_MODULE;
1581	phy_reset_dev->of_node = node;
1582	/* Reset for each of the lane and one for the entire SERDES */
1583	phy_reset_dev->nr_resets = num_lanes + 1;
1584
1585	ret = devm_reset_controller_register(dev, phy_reset_dev);
1586	if (ret < 0) {
1587		dev_warn(dev, "Failed to register reset controller\n");
1588		goto err_addr_to_resource;
1589	}
1590
1591	pm_runtime_enable(dev);
1592	ret = pm_runtime_get_sync(dev);
1593	if (ret < 0) {
1594		dev_err(dev, "pm_runtime_get_sync failed\n");
1595		goto err_get_sync;
1596	}
1597
1598	ret = wiz_clock_probe(wiz, node);
1599	if (ret < 0) {
1600		dev_warn(dev, "Failed to initialize clocks\n");
1601		goto err_get_sync;
1602	}
1603
1604	for (i = 0; i < wiz->num_lanes; i++) {
1605		regmap_field_read(wiz->p_enable[i], &val);
1606		if (val & (P_ENABLE | P_ENABLE_FORCE)) {
1607			already_configured = true;
1608			break;
1609		}
1610	}
1611
1612	if (!already_configured) {
1613		ret = wiz_init(wiz);
1614		if (ret) {
1615			dev_err(dev, "WIZ initialization failed\n");
1616			goto err_wiz_init;
1617		}
1618	}
1619
1620	serdes_pdev = of_platform_device_create(child_node, NULL, dev);
1621	if (!serdes_pdev) {
1622		dev_WARN(dev, "Unable to create SERDES platform device\n");
1623		ret = -ENOMEM;
1624		goto err_wiz_init;
1625	}
1626	wiz->serdes_pdev = serdes_pdev;
1627
1628	of_node_put(child_node);
1629	return 0;
1630
1631err_wiz_init:
1632	wiz_clock_cleanup(wiz, node);
1633
1634err_get_sync:
1635	pm_runtime_put(dev);
1636	pm_runtime_disable(dev);
1637
1638err_addr_to_resource:
1639	of_node_put(child_node);
1640
1641	return ret;
1642}
1643
1644static void wiz_remove(struct platform_device *pdev)
1645{
1646	struct device *dev = &pdev->dev;
1647	struct device_node *node = dev->of_node;
1648	struct platform_device *serdes_pdev;
1649	struct wiz *wiz;
1650
1651	wiz = dev_get_drvdata(dev);
1652	serdes_pdev = wiz->serdes_pdev;
1653
1654	of_platform_device_destroy(&serdes_pdev->dev, NULL);
1655	wiz_clock_cleanup(wiz, node);
1656	pm_runtime_put(dev);
1657	pm_runtime_disable(dev);
1658}
1659
1660static int wiz_suspend_noirq(struct device *dev)
1661{
1662	struct wiz *wiz = dev_get_drvdata(dev);
1663	int i;
1664
1665	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++)
1666		regmap_field_read(wiz->mux_sel_field[i], &wiz->mux_sel_status[i]);
1667
1668	return 0;
1669}
1670
1671static int wiz_resume_noirq(struct device *dev)
1672{
1673	struct device_node *node = dev->of_node;
1674	struct wiz *wiz = dev_get_drvdata(dev);
1675	int ret, i;
1676
1677	for (i = 0; i < WIZ_MUX_NUM_CLOCKS; i++)
1678		regmap_field_write(wiz->mux_sel_field[i], wiz->mux_sel_status[i]);
1679
1680	/* Enable supplemental Control override if available */
1681	if (wiz->sup_legacy_clk_override)
1682		regmap_field_write(wiz->sup_legacy_clk_override, 1);
1683
1684	wiz_clock_init(wiz);
1685
1686	ret = wiz_init(wiz);
1687	if (ret) {
1688		dev_err(dev, "WIZ initialization failed\n");
1689		goto err_wiz_init;
1690	}
1691
1692	return 0;
1693
1694err_wiz_init:
1695	wiz_clock_cleanup(wiz, node);
1696
1697	return ret;
1698}
1699
1700static DEFINE_NOIRQ_DEV_PM_OPS(wiz_pm_ops, wiz_suspend_noirq, wiz_resume_noirq);
1701
1702static struct platform_driver wiz_driver = {
1703	.probe		= wiz_probe,
1704	.remove		= wiz_remove,
1705	.driver		= {
1706		.name	= "wiz",
1707		.of_match_table = wiz_id_table,
1708		.pm	= pm_sleep_ptr(&wiz_pm_ops),
1709	},
1710};
1711module_platform_driver(wiz_driver);
1712
1713MODULE_AUTHOR("Texas Instruments Inc.");
1714MODULE_DESCRIPTION("TI J721E WIZ driver");
1715MODULE_LICENSE("GPL v2");