xusb-tegra186.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Copyright (c) 2016-2022, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#include <linux/delay.h>
   7#include <linux/io.h>
   8#include <linux/module.h>
   9#include <linux/of.h>
  10#include <linux/phy/phy.h>
  11#include <linux/regulator/consumer.h>
  12#include <linux/platform_device.h>
  13#include <linux/clk.h>
  14#include <linux/slab.h>
  15
  16#include <soc/tegra/fuse.h>
  17
  18#include "xusb.h"
  19
  20/* FUSE USB_CALIB registers */
  21#define HS_CURR_LEVEL_PADX_SHIFT(x)	((x) ? (11 + (x - 1) * 6) : 0)
  22#define HS_CURR_LEVEL_PAD_MASK		0x3f
  23#define HS_TERM_RANGE_ADJ_SHIFT		7
  24#define HS_TERM_RANGE_ADJ_MASK		0xf
  25#define HS_SQUELCH_SHIFT		29
  26#define HS_SQUELCH_MASK			0x7
  27
  28#define RPD_CTRL_SHIFT			0
  29#define RPD_CTRL_MASK			0x1f
  30
  31/* XUSB PADCTL registers */
  32#define XUSB_PADCTL_USB2_PAD_MUX	0x4
  33#define  USB2_PORT_SHIFT(x)		((x) * 2)
  34#define  USB2_PORT_MASK			0x3
  35#define   PORT_XUSB			1
  36#define  HSIC_PORT_SHIFT(x)		((x) + 20)
  37#define  HSIC_PORT_MASK			0x1
  38#define   PORT_HSIC			0
  39
  40#define XUSB_PADCTL_USB2_PORT_CAP	0x8
  41#define XUSB_PADCTL_SS_PORT_CAP		0xc
  42#define  PORTX_CAP_SHIFT(x)		((x) * 4)
  43#define  PORT_CAP_MASK			0x3
  44#define   PORT_CAP_DISABLED		0x0
  45#define   PORT_CAP_HOST			0x1
  46#define   PORT_CAP_DEVICE		0x2
  47#define   PORT_CAP_OTG			0x3
  48
  49#define XUSB_PADCTL_ELPG_PROGRAM		0x20
  50#define  USB2_PORT_WAKE_INTERRUPT_ENABLE(x)		BIT(x)
  51#define  USB2_PORT_WAKEUP_EVENT(x)			BIT((x) +  7)
  52#define  SS_PORT_WAKE_INTERRUPT_ENABLE(x)		BIT((x) + 14)
  53#define  SS_PORT_WAKEUP_EVENT(x)			BIT((x) + 21)
  54#define  USB2_HSIC_PORT_WAKE_INTERRUPT_ENABLE(x)	BIT((x) + 28)
  55#define  USB2_HSIC_PORT_WAKEUP_EVENT(x)			BIT((x) + 30)
  56#define  ALL_WAKE_EVENTS						\
  57	(USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) |	\
  58	USB2_PORT_WAKEUP_EVENT(2) | SS_PORT_WAKEUP_EVENT(0) |		\
  59	SS_PORT_WAKEUP_EVENT(1) | SS_PORT_WAKEUP_EVENT(2) |		\
  60	USB2_HSIC_PORT_WAKEUP_EVENT(0))
  61
  62#define XUSB_PADCTL_ELPG_PROGRAM_1		0x24
  63#define  SSPX_ELPG_CLAMP_EN(x)			BIT(0 + (x) * 3)
  64#define  SSPX_ELPG_CLAMP_EN_EARLY(x)		BIT(1 + (x) * 3)
  65#define  SSPX_ELPG_VCORE_DOWN(x)		BIT(2 + (x) * 3)
  66#define XUSB_PADCTL_SS_PORT_CFG			0x2c
  67#define   PORTX_SPEED_SUPPORT_SHIFT(x)		((x) * 4)
  68#define   PORTX_SPEED_SUPPORT_MASK		(0x3)
  69#define     PORT_SPEED_SUPPORT_GEN1		(0x0)
  70
  71#define XUSB_PADCTL_USB2_OTG_PADX_CTL0(x)	(0x88 + (x) * 0x40)
  72#define  HS_CURR_LEVEL(x)			((x) & 0x3f)
  73#define  TERM_SEL				BIT(25)
  74#define  USB2_OTG_PD				BIT(26)
  75#define  USB2_OTG_PD2				BIT(27)
  76#define  USB2_OTG_PD2_OVRD_EN			BIT(28)
  77#define  USB2_OTG_PD_ZI				BIT(29)
  78
  79#define XUSB_PADCTL_USB2_OTG_PADX_CTL1(x)	(0x8c + (x) * 0x40)
  80#define  USB2_OTG_PD_DR				BIT(2)
  81#define  TERM_RANGE_ADJ(x)			(((x) & 0xf) << 3)
  82#define  RPD_CTRL(x)				(((x) & 0x1f) << 26)
  83
  84#define XUSB_PADCTL_USB2_BIAS_PAD_CTL0		0x284
  85#define  BIAS_PAD_PD				BIT(11)
  86#define  HS_SQUELCH_LEVEL(x)			(((x) & 0x7) << 0)
  87#define  HS_DISCON_LEVEL(x)			(((x) & 0x7) << 3)
  88
  89#define XUSB_PADCTL_USB2_BIAS_PAD_CTL1		0x288
  90#define  USB2_TRK_START_TIMER(x)		(((x) & 0x7f) << 12)
  91#define  USB2_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 19)
  92#define  USB2_PD_TRK				BIT(26)
  93#define  USB2_TRK_COMPLETED			BIT(31)
  94
  95#define XUSB_PADCTL_USB2_BIAS_PAD_CTL2		0x28c
  96#define  USB2_TRK_HW_MODE			BIT(0)
  97#define  CYA_TRK_CODE_UPDATE_ON_IDLE		BIT(31)
  98
  99#define XUSB_PADCTL_HSIC_PADX_CTL0(x)		(0x300 + (x) * 0x20)
 100#define  HSIC_PD_TX_DATA0			BIT(1)
 101#define  HSIC_PD_TX_STROBE			BIT(3)
 102#define  HSIC_PD_RX_DATA0			BIT(4)
 103#define  HSIC_PD_RX_STROBE			BIT(6)
 104#define  HSIC_PD_ZI_DATA0			BIT(7)
 105#define  HSIC_PD_ZI_STROBE			BIT(9)
 106#define  HSIC_RPD_DATA0				BIT(13)
 107#define  HSIC_RPD_STROBE			BIT(15)
 108#define  HSIC_RPU_DATA0				BIT(16)
 109#define  HSIC_RPU_STROBE			BIT(18)
 110
 111#define XUSB_PADCTL_HSIC_PAD_TRK_CTL0		0x340
 112#define  HSIC_TRK_START_TIMER(x)		(((x) & 0x7f) << 5)
 113#define  HSIC_TRK_DONE_RESET_TIMER(x)		(((x) & 0x7f) << 12)
 114#define  HSIC_PD_TRK				BIT(19)
 115
 116#define USB2_VBUS_ID				0x360
 117#define  VBUS_OVERRIDE				BIT(14)
 118#define  ID_OVERRIDE(x)				(((x) & 0xf) << 18)
 119#define  ID_OVERRIDE_FLOATING			ID_OVERRIDE(8)
 120#define  ID_OVERRIDE_GROUNDED			ID_OVERRIDE(0)
 121
 122/* XUSB AO registers */
 123#define XUSB_AO_USB_DEBOUNCE_DEL		(0x4)
 124#define   UHSIC_LINE_DEB_CNT(x)			(((x) & 0xf) << 4)
 125#define   UTMIP_LINE_DEB_CNT(x)			((x) & 0xf)
 126
 127#define XUSB_AO_UTMIP_TRIGGERS(x)		(0x40 + (x) * 4)
 128#define   CLR_WALK_PTR				BIT(0)
 129#define   CAP_CFG				BIT(1)
 130#define   CLR_WAKE_ALARM			BIT(3)
 131
 132#define XUSB_AO_UHSIC_TRIGGERS(x)		(0x60 + (x) * 4)
 133#define   HSIC_CLR_WALK_PTR			BIT(0)
 134#define   HSIC_CLR_WAKE_ALARM			BIT(3)
 135#define   HSIC_CAP_CFG				BIT(4)
 136
 137#define XUSB_AO_UTMIP_SAVED_STATE(x)		(0x70 + (x) * 4)
 138#define   SPEED(x)				((x) & 0x3)
 139#define     UTMI_HS				SPEED(0)
 140#define     UTMI_FS				SPEED(1)
 141#define     UTMI_LS				SPEED(2)
 142#define     UTMI_RST				SPEED(3)
 143
 144#define XUSB_AO_UHSIC_SAVED_STATE(x)		(0x90 + (x) * 4)
 145#define   MODE(x)				((x) & 0x1)
 146#define   MODE_HS				MODE(0)
 147#define   MODE_RST				MODE(1)
 148
 149#define XUSB_AO_UTMIP_SLEEPWALK_STATUS(x)	(0xa0 + (x) * 4)
 150
 151#define XUSB_AO_UTMIP_SLEEPWALK_CFG(x)		(0xd0 + (x) * 4)
 152#define XUSB_AO_UHSIC_SLEEPWALK_CFG(x)		(0xf0 + (x) * 4)
 153#define   FAKE_USBOP_VAL			BIT(0)
 154#define   FAKE_USBON_VAL			BIT(1)
 155#define   FAKE_USBOP_EN				BIT(2)
 156#define   FAKE_USBON_EN				BIT(3)
 157#define   FAKE_STROBE_VAL			BIT(0)
 158#define   FAKE_DATA_VAL				BIT(1)
 159#define   FAKE_STROBE_EN			BIT(2)
 160#define   FAKE_DATA_EN				BIT(3)
 161#define   WAKE_WALK_EN				BIT(14)
 162#define   MASTER_ENABLE				BIT(15)
 163#define   LINEVAL_WALK_EN			BIT(16)
 164#define   WAKE_VAL(x)				(((x) & 0xf) << 17)
 165#define     WAKE_VAL_NONE			WAKE_VAL(12)
 166#define     WAKE_VAL_ANY			WAKE_VAL(15)
 167#define     WAKE_VAL_DS10			WAKE_VAL(2)
 168#define   LINE_WAKEUP_EN			BIT(21)
 169#define   MASTER_CFG_SEL			BIT(22)
 170
 171#define XUSB_AO_UTMIP_SLEEPWALK(x)		(0x100 + (x) * 4)
 172/* phase A */
 173#define   USBOP_RPD_A				BIT(0)
 174#define   USBON_RPD_A				BIT(1)
 175#define   AP_A					BIT(4)
 176#define   AN_A					BIT(5)
 177#define   HIGHZ_A				BIT(6)
 178#define   MASTER_ENABLE_A			BIT(7)
 179/* phase B */
 180#define   USBOP_RPD_B				BIT(8)
 181#define   USBON_RPD_B				BIT(9)
 182#define   AP_B					BIT(12)
 183#define   AN_B					BIT(13)
 184#define   HIGHZ_B				BIT(14)
 185#define   MASTER_ENABLE_B			BIT(15)
 186/* phase C */
 187#define   USBOP_RPD_C				BIT(16)
 188#define   USBON_RPD_C				BIT(17)
 189#define   AP_C					BIT(20)
 190#define   AN_C					BIT(21)
 191#define   HIGHZ_C				BIT(22)
 192#define   MASTER_ENABLE_C			BIT(23)
 193/* phase D */
 194#define   USBOP_RPD_D				BIT(24)
 195#define   USBON_RPD_D				BIT(25)
 196#define   AP_D					BIT(28)
 197#define   AN_D					BIT(29)
 198#define   HIGHZ_D				BIT(30)
 199#define   MASTER_ENABLE_D			BIT(31)
 200#define   MASTER_ENABLE_B_C_D					\
 201	 (MASTER_ENABLE_B | MASTER_ENABLE_C | MASTER_ENABLE_D)
 202
 203#define XUSB_AO_UHSIC_SLEEPWALK(x)		(0x120 + (x) * 4)
 204/* phase A */
 205#define   RPD_STROBE_A				BIT(0)
 206#define   RPD_DATA0_A				BIT(1)
 207#define   RPU_STROBE_A				BIT(2)
 208#define   RPU_DATA0_A				BIT(3)
 209/* phase B */
 210#define   RPD_STROBE_B				BIT(8)
 211#define   RPD_DATA0_B				BIT(9)
 212#define   RPU_STROBE_B				BIT(10)
 213#define   RPU_DATA0_B				BIT(11)
 214/* phase C */
 215#define   RPD_STROBE_C				BIT(16)
 216#define   RPD_DATA0_C				BIT(17)
 217#define   RPU_STROBE_C				BIT(18)
 218#define   RPU_DATA0_C				BIT(19)
 219/* phase D */
 220#define   RPD_STROBE_D				BIT(24)
 221#define   RPD_DATA0_D				BIT(25)
 222#define   RPU_STROBE_D				BIT(26)
 223#define   RPU_DATA0_D				BIT(27)
 224
 225#define XUSB_AO_UTMIP_PAD_CFG(x)		(0x130 + (x) * 4)
 226#define   FSLS_USE_XUSB_AO			BIT(3)
 227#define   TRK_CTRL_USE_XUSB_AO			BIT(4)
 228#define   RPD_CTRL_USE_XUSB_AO			BIT(5)
 229#define   RPU_USE_XUSB_AO			BIT(6)
 230#define   VREG_USE_XUSB_AO			BIT(7)
 231#define   USBOP_VAL_PD				BIT(8)
 232#define   USBON_VAL_PD				BIT(9)
 233#define   E_DPD_OVRD_EN				BIT(10)
 234#define   E_DPD_OVRD_VAL			BIT(11)
 235
 236#define XUSB_AO_UHSIC_PAD_CFG(x)		(0x150 + (x) * 4)
 237#define   STROBE_VAL_PD				BIT(0)
 238#define   DATA0_VAL_PD				BIT(1)
 239#define   USE_XUSB_AO				BIT(4)
 240
 241#define TEGRA_UTMI_PAD_MAX 4
 242
 243#define TEGRA186_LANE(_name, _offset, _shift, _mask, _type)		\
 244	{								\
 245		.name = _name,						\
 246		.offset = _offset,					\
 247		.shift = _shift,					\
 248		.mask = _mask,						\
 249		.num_funcs = ARRAY_SIZE(tegra186_##_type##_functions),	\
 250		.funcs = tegra186_##_type##_functions,			\
 251	}
 252
 253struct tegra_xusb_fuse_calibration {
 254	u32 *hs_curr_level;
 255	u32 hs_squelch;
 256	u32 hs_term_range_adj;
 257	u32 rpd_ctrl;
 258};
 259
 260struct tegra186_xusb_padctl_context {
 261	u32 vbus_id;
 262	u32 usb2_pad_mux;
 263	u32 usb2_port_cap;
 264	u32 ss_port_cap;
 265};
 266
 267struct tegra186_xusb_padctl {
 268	struct tegra_xusb_padctl base;
 269	void __iomem *ao_regs;
 270
 271	struct tegra_xusb_fuse_calibration calib;
 272
 273	/* UTMI bias and tracking */
 274	struct clk *usb2_trk_clk;
 275	DECLARE_BITMAP(utmi_pad_enabled, TEGRA_UTMI_PAD_MAX);
 276
 277	/* padctl context */
 278	struct tegra186_xusb_padctl_context context;
 279};
 280
 281static inline void ao_writel(struct tegra186_xusb_padctl *priv, u32 value, unsigned int offset)
 282{
 283	writel(value, priv->ao_regs + offset);
 284}
 285
 286static inline u32 ao_readl(struct tegra186_xusb_padctl *priv, unsigned int offset)
 287{
 288	return readl(priv->ao_regs + offset);
 289}
 290
 291static inline struct tegra186_xusb_padctl *
 292to_tegra186_xusb_padctl(struct tegra_xusb_padctl *padctl)
 293{
 294	return container_of(padctl, struct tegra186_xusb_padctl, base);
 295}
 296
 297/* USB 2.0 UTMI PHY support */
 298static struct tegra_xusb_lane *
 299tegra186_usb2_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
 300			 unsigned int index)
 301{
 302	struct tegra_xusb_usb2_lane *usb2;
 303	int err;
 304
 305	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
 306	if (!usb2)
 307		return ERR_PTR(-ENOMEM);
 308
 309	INIT_LIST_HEAD(&usb2->base.list);
 310	usb2->base.soc = &pad->soc->lanes[index];
 311	usb2->base.index = index;
 312	usb2->base.pad = pad;
 313	usb2->base.np = np;
 314
 315	err = tegra_xusb_lane_parse_dt(&usb2->base, np);
 316	if (err < 0) {
 317		kfree(usb2);
 318		return ERR_PTR(err);
 319	}
 320
 321	return &usb2->base;
 322}
 323
 324static void tegra186_usb2_lane_remove(struct tegra_xusb_lane *lane)
 325{
 326	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
 327
 328	kfree(usb2);
 329}
 330
 331static int tegra186_utmi_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
 332					      enum usb_device_speed speed)
 333{
 334	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 335	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 336	unsigned int index = lane->index;
 337	u32 value;
 338
 339	mutex_lock(&padctl->lock);
 340
 341	/* ensure sleepwalk logic is disabled */
 342	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 343	value &= ~MASTER_ENABLE;
 344	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 345
 346	/* ensure sleepwalk logics are in low power mode */
 347	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 348	value |= MASTER_CFG_SEL;
 349	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 350
 351	/* set debounce time */
 352	value = ao_readl(priv, XUSB_AO_USB_DEBOUNCE_DEL);
 353	value &= ~UTMIP_LINE_DEB_CNT(~0);
 354	value |= UTMIP_LINE_DEB_CNT(1);
 355	ao_writel(priv, value, XUSB_AO_USB_DEBOUNCE_DEL);
 356
 357	/* ensure fake events of sleepwalk logic are desiabled */
 358	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 359	value &= ~(FAKE_USBOP_VAL | FAKE_USBON_VAL |
 360		FAKE_USBOP_EN | FAKE_USBON_EN);
 361	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 362
 363	/* ensure wake events of sleepwalk logic are not latched */
 364	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 365	value &= ~LINE_WAKEUP_EN;
 366	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 367
 368	/* disable wake event triggers of sleepwalk logic */
 369	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 370	value &= ~WAKE_VAL(~0);
 371	value |= WAKE_VAL_NONE;
 372	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 373
 374	/* power down the line state detectors of the pad */
 375	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
 376	value |= (USBOP_VAL_PD | USBON_VAL_PD);
 377	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
 378
 379	/* save state per speed */
 380	value = ao_readl(priv, XUSB_AO_UTMIP_SAVED_STATE(index));
 381	value &= ~SPEED(~0);
 382
 383	switch (speed) {
 384	case USB_SPEED_HIGH:
 385		value |= UTMI_HS;
 386		break;
 387
 388	case USB_SPEED_FULL:
 389		value |= UTMI_FS;
 390		break;
 391
 392	case USB_SPEED_LOW:
 393		value |= UTMI_LS;
 394		break;
 395
 396	default:
 397		value |= UTMI_RST;
 398		break;
 399	}
 400
 401	ao_writel(priv, value, XUSB_AO_UTMIP_SAVED_STATE(index));
 402
 403	/* enable the trigger of the sleepwalk logic */
 404	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 405	value |= LINEVAL_WALK_EN;
 406	value &= ~WAKE_WALK_EN;
 407	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 408
 409	/* reset the walk pointer and clear the alarm of the sleepwalk logic,
 410	 * as well as capture the configuration of the USB2.0 pad
 411	 */
 412	value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
 413	value |= (CLR_WALK_PTR | CLR_WAKE_ALARM | CAP_CFG);
 414	ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
 415
 416	/* setup the pull-ups and pull-downs of the signals during the four
 417	 * stages of sleepwalk.
 418	 * if device is connected, program sleepwalk logic to maintain a J and
 419	 * keep driving K upon seeing remote wake.
 420	 */
 421	value = USBOP_RPD_A | USBOP_RPD_B | USBOP_RPD_C | USBOP_RPD_D;
 422	value |= USBON_RPD_A | USBON_RPD_B | USBON_RPD_C | USBON_RPD_D;
 423
 424	switch (speed) {
 425	case USB_SPEED_HIGH:
 426	case USB_SPEED_FULL:
 427		/* J state: D+/D- = high/low, K state: D+/D- = low/high */
 428		value |= HIGHZ_A;
 429		value |= AP_A;
 430		value |= AN_B | AN_C | AN_D;
 431		if (padctl->soc->supports_lp_cfg_en)
 432			value |= MASTER_ENABLE_B_C_D;
 433		break;
 434
 435	case USB_SPEED_LOW:
 436		/* J state: D+/D- = low/high, K state: D+/D- = high/low */
 437		value |= HIGHZ_A;
 438		value |= AN_A;
 439		value |= AP_B | AP_C | AP_D;
 440		if (padctl->soc->supports_lp_cfg_en)
 441			value |= MASTER_ENABLE_B_C_D;
 442		break;
 443
 444	default:
 445		value |= HIGHZ_A | HIGHZ_B | HIGHZ_C | HIGHZ_D;
 446		break;
 447	}
 448
 449	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
 450
 451	/* power up the line state detectors of the pad */
 452	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
 453	value &= ~(USBOP_VAL_PD | USBON_VAL_PD);
 454	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
 455
 456	usleep_range(150, 200);
 457
 458	/* switch the electric control of the USB2.0 pad to XUSB_AO */
 459	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
 460	value |= FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
 461		 RPU_USE_XUSB_AO | VREG_USE_XUSB_AO;
 462	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
 463
 464	/* set the wake signaling trigger events */
 465	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 466	value &= ~WAKE_VAL(~0);
 467	value |= WAKE_VAL_ANY;
 468	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 469
 470	/* enable the wake detection */
 471	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 472	value |= MASTER_ENABLE | LINE_WAKEUP_EN;
 473	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 474
 475	mutex_unlock(&padctl->lock);
 476
 477	return 0;
 478}
 479
 480static int tegra186_utmi_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
 481{
 482	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 483	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 484	unsigned int index = lane->index;
 485	u32 value;
 486
 487	mutex_lock(&padctl->lock);
 488
 489	/* disable the wake detection */
 490	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 491	value &= ~(MASTER_ENABLE | LINE_WAKEUP_EN);
 492	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 493
 494	/* switch the electric control of the USB2.0 pad to XUSB vcore logic */
 495	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
 496	value &= ~(FSLS_USE_XUSB_AO | TRK_CTRL_USE_XUSB_AO | RPD_CTRL_USE_XUSB_AO |
 497		   RPU_USE_XUSB_AO | VREG_USE_XUSB_AO);
 498	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
 499
 500	/* disable wake event triggers of sleepwalk logic */
 501	value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 502	value &= ~WAKE_VAL(~0);
 503	value |= WAKE_VAL_NONE;
 504	ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK_CFG(index));
 505
 506	if (padctl->soc->supports_lp_cfg_en) {
 507		/* disable the four stages of sleepwalk */
 508		value = ao_readl(priv, XUSB_AO_UTMIP_SLEEPWALK(index));
 509		value &= ~(MASTER_ENABLE_A | MASTER_ENABLE_B_C_D);
 510		ao_writel(priv, value, XUSB_AO_UTMIP_SLEEPWALK(index));
 511	}
 512
 513	/* power down the line state detectors of the port */
 514	value = ao_readl(priv, XUSB_AO_UTMIP_PAD_CFG(index));
 515	value |= USBOP_VAL_PD | USBON_VAL_PD;
 516	ao_writel(priv, value, XUSB_AO_UTMIP_PAD_CFG(index));
 517
 518	/* clear alarm of the sleepwalk logic */
 519	value = ao_readl(priv, XUSB_AO_UTMIP_TRIGGERS(index));
 520	value |= CLR_WAKE_ALARM;
 521	ao_writel(priv, value, XUSB_AO_UTMIP_TRIGGERS(index));
 522
 523	mutex_unlock(&padctl->lock);
 524
 525	return 0;
 526}
 527
 528static int tegra186_utmi_enable_phy_wake(struct tegra_xusb_lane *lane)
 529{
 530	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 531	unsigned int index = lane->index;
 532	u32 value;
 533
 534	mutex_lock(&padctl->lock);
 535
 536	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 537	value &= ~ALL_WAKE_EVENTS;
 538	value |= USB2_PORT_WAKEUP_EVENT(index);
 539	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 540
 541	usleep_range(10, 20);
 542
 543	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 544	value &= ~ALL_WAKE_EVENTS;
 545	value |= USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
 546	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 547
 548	mutex_unlock(&padctl->lock);
 549
 550	return 0;
 551}
 552
 553static int tegra186_utmi_disable_phy_wake(struct tegra_xusb_lane *lane)
 554{
 555	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 556	unsigned int index = lane->index;
 557	u32 value;
 558
 559	mutex_lock(&padctl->lock);
 560
 561	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 562	value &= ~ALL_WAKE_EVENTS;
 563	value &= ~USB2_PORT_WAKE_INTERRUPT_ENABLE(index);
 564	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 565
 566	usleep_range(10, 20);
 567
 568	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 569	value &= ~ALL_WAKE_EVENTS;
 570	value |= USB2_PORT_WAKEUP_EVENT(index);
 571	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
 572
 573	mutex_unlock(&padctl->lock);
 574
 575	return 0;
 576}
 577
 578static bool tegra186_utmi_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
 579{
 580	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 581	unsigned int index = lane->index;
 582	u32 value;
 583
 584	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
 585	if ((value & USB2_PORT_WAKE_INTERRUPT_ENABLE(index)) &&
 586	    (value & USB2_PORT_WAKEUP_EVENT(index)))
 587		return true;
 588
 589	return false;
 590}
 591
 592static const struct tegra_xusb_lane_ops tegra186_usb2_lane_ops = {
 593	.probe = tegra186_usb2_lane_probe,
 594	.remove = tegra186_usb2_lane_remove,
 595	.enable_phy_sleepwalk = tegra186_utmi_enable_phy_sleepwalk,
 596	.disable_phy_sleepwalk = tegra186_utmi_disable_phy_sleepwalk,
 597	.enable_phy_wake = tegra186_utmi_enable_phy_wake,
 598	.disable_phy_wake = tegra186_utmi_disable_phy_wake,
 599	.remote_wake_detected = tegra186_utmi_phy_remote_wake_detected,
 600};
 601
 602static void tegra186_utmi_bias_pad_power_on(struct tegra_xusb_padctl *padctl)
 603{
 604	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 605	struct device *dev = padctl->dev;
 606	u32 value;
 607	int err;
 608
 609	if (!bitmap_empty(priv->utmi_pad_enabled, TEGRA_UTMI_PAD_MAX))
 610		return;
 611
 612	err = clk_prepare_enable(priv->usb2_trk_clk);
 613	if (err < 0)
 614		dev_warn(dev, "failed to enable USB2 trk clock: %d\n", err);
 615
 616	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 617	value &= ~USB2_TRK_START_TIMER(~0);
 618	value |= USB2_TRK_START_TIMER(0x1e);
 619	value &= ~USB2_TRK_DONE_RESET_TIMER(~0);
 620	value |= USB2_TRK_DONE_RESET_TIMER(0xa);
 621	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 622
 623	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
 624	value &= ~BIAS_PAD_PD;
 625	value &= ~HS_SQUELCH_LEVEL(~0);
 626	value |= HS_SQUELCH_LEVEL(priv->calib.hs_squelch);
 627	value &= ~HS_DISCON_LEVEL(~0);
 628	value |= HS_DISCON_LEVEL(0x7);
 629	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL0);
 630
 631	udelay(1);
 632
 633	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 634	value &= ~USB2_PD_TRK;
 635	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 636
 637	if (padctl->soc->poll_trk_completed) {
 638		err = padctl_readl_poll(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1,
 639					USB2_TRK_COMPLETED, USB2_TRK_COMPLETED, 100);
 640		if (err) {
 641			/* The failure with polling on trk complete will not
 642			 * cause the failure of powering on the bias pad.
 643			 */
 644			dev_warn(dev, "failed to poll USB2 trk completed: %d\n", err);
 645		}
 646
 647		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 648		value |= USB2_TRK_COMPLETED;
 649		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 650	} else {
 651		udelay(100);
 652	}
 653
 654	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
 655	if (padctl->soc->trk_update_on_idle)
 656		value &= ~CYA_TRK_CODE_UPDATE_ON_IDLE;
 657	if (padctl->soc->trk_hw_mode)
 658		value |= USB2_TRK_HW_MODE;
 659	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
 660
 661	if (!padctl->soc->trk_hw_mode)
 662		clk_disable_unprepare(priv->usb2_trk_clk);
 663}
 664
 665static void tegra186_utmi_bias_pad_power_off(struct tegra_xusb_padctl *padctl)
 666{
 667	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 668	u32 value;
 669
 670	if (!bitmap_empty(priv->utmi_pad_enabled, TEGRA_UTMI_PAD_MAX))
 671		return;
 672
 673	value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 674	value |= USB2_PD_TRK;
 675	padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL1);
 676
 677	if (padctl->soc->trk_hw_mode) {
 678		value = padctl_readl(padctl, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
 679		value &= ~USB2_TRK_HW_MODE;
 680		padctl_writel(padctl, value, XUSB_PADCTL_USB2_BIAS_PAD_CTL2);
 681		clk_disable_unprepare(priv->usb2_trk_clk);
 682	}
 683
 684}
 685
 686static void tegra186_utmi_pad_power_on(struct phy *phy)
 687{
 688	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 689	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 690	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 691	struct tegra_xusb_usb2_port *port;
 692	struct device *dev = padctl->dev;
 693	unsigned int index = lane->index;
 694	u32 value;
 695
 696	if (!phy)
 697		return;
 698
 699	mutex_lock(&padctl->lock);
 700	if (test_bit(index, priv->utmi_pad_enabled)) {
 701		mutex_unlock(&padctl->lock);
 702		return;
 703	}
 704
 705	port = tegra_xusb_find_usb2_port(padctl, index);
 706	if (!port) {
 707		dev_err(dev, "no port found for USB2 lane %u\n", index);
 708		mutex_unlock(&padctl->lock);
 709		return;
 710	}
 711
 712	dev_dbg(dev, "power on UTMI pad %u\n", index);
 713
 714	tegra186_utmi_bias_pad_power_on(padctl);
 715
 716	udelay(2);
 717
 718	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
 719	value &= ~USB2_OTG_PD;
 720	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
 721
 722	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
 723	value &= ~USB2_OTG_PD_DR;
 724	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
 725
 726	set_bit(index, priv->utmi_pad_enabled);
 727	mutex_unlock(&padctl->lock);
 728}
 729
 730static void tegra186_utmi_pad_power_down(struct phy *phy)
 731{
 732	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 733	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 734	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 735	unsigned int index = lane->index;
 736	u32 value;
 737
 738	if (!phy)
 739		return;
 740
 741	mutex_lock(&padctl->lock);
 742	if (!test_bit(index, priv->utmi_pad_enabled)) {
 743		mutex_unlock(&padctl->lock);
 744		return;
 745	}
 746
 747	dev_dbg(padctl->dev, "power down UTMI pad %u\n", index);
 748
 749	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
 750	value |= USB2_OTG_PD;
 751	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
 752
 753	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
 754	value |= USB2_OTG_PD_DR;
 755	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
 756
 757	udelay(2);
 758
 759	clear_bit(index, priv->utmi_pad_enabled);
 760
 761	tegra186_utmi_bias_pad_power_off(padctl);
 762
 763	mutex_unlock(&padctl->lock);
 764}
 765
 766static int tegra186_xusb_padctl_vbus_override(struct tegra_xusb_padctl *padctl,
 767					       bool status)
 768{
 769	u32 value;
 770
 771	dev_dbg(padctl->dev, "%s vbus override\n", status ? "set" : "clear");
 772
 773	value = padctl_readl(padctl, USB2_VBUS_ID);
 774
 775	if (status) {
 776		value |= VBUS_OVERRIDE;
 777		value &= ~ID_OVERRIDE(~0);
 778		value |= ID_OVERRIDE_FLOATING;
 779	} else {
 780		value &= ~VBUS_OVERRIDE;
 781	}
 782
 783	padctl_writel(padctl, value, USB2_VBUS_ID);
 784
 785	return 0;
 786}
 787
 788static int tegra186_xusb_padctl_id_override(struct tegra_xusb_padctl *padctl,
 789					    struct tegra_xusb_usb2_port *port, bool status)
 790{
 791	u32 value, id_override;
 792	int err = 0;
 793
 794	dev_dbg(padctl->dev, "%s id override\n", status ? "set" : "clear");
 795
 796	value = padctl_readl(padctl, USB2_VBUS_ID);
 797	id_override = value & ID_OVERRIDE(~0);
 798
 799	if (status) {
 800		if (value & VBUS_OVERRIDE) {
 801			value &= ~VBUS_OVERRIDE;
 802			padctl_writel(padctl, value, USB2_VBUS_ID);
 803			usleep_range(1000, 2000);
 804
 805			value = padctl_readl(padctl, USB2_VBUS_ID);
 806		}
 807
 808		if (id_override != ID_OVERRIDE_GROUNDED) {
 809			value &= ~ID_OVERRIDE(~0);
 810			value |= ID_OVERRIDE_GROUNDED;
 811			padctl_writel(padctl, value, USB2_VBUS_ID);
 812
 813			err = regulator_enable(port->supply);
 814			if (err) {
 815				dev_err(padctl->dev, "Failed to enable regulator: %d\n", err);
 816				return err;
 817			}
 818		}
 819	} else {
 820		if (id_override == ID_OVERRIDE_GROUNDED) {
 821			/*
 822			 * The regulator is disabled only when the role transitions
 823			 * from USB_ROLE_HOST to USB_ROLE_NONE.
 824			 */
 825			err = regulator_disable(port->supply);
 826			if (err) {
 827				dev_err(padctl->dev, "Failed to disable regulator: %d\n", err);
 828				return err;
 829			}
 830
 831			value &= ~ID_OVERRIDE(~0);
 832			value |= ID_OVERRIDE_FLOATING;
 833			padctl_writel(padctl, value, USB2_VBUS_ID);
 834		}
 835	}
 836
 837	return 0;
 838}
 839
 840static int tegra186_utmi_phy_set_mode(struct phy *phy, enum phy_mode mode,
 841				      int submode)
 842{
 843	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 844	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 845	struct tegra_xusb_usb2_port *port = tegra_xusb_find_usb2_port(padctl,
 846								lane->index);
 847	int err = 0;
 848
 849	mutex_lock(&padctl->lock);
 850
 851	dev_dbg(&port->base.dev, "%s: mode %d", __func__, mode);
 852
 853	if (mode == PHY_MODE_USB_OTG) {
 854		if (submode == USB_ROLE_HOST) {
 855			err = tegra186_xusb_padctl_id_override(padctl, port, true);
 856			if (err)
 857				goto out;
 858		} else if (submode == USB_ROLE_DEVICE) {
 859			tegra186_xusb_padctl_vbus_override(padctl, true);
 860		} else if (submode == USB_ROLE_NONE) {
 861			err = tegra186_xusb_padctl_id_override(padctl, port, false);
 862			if (err)
 863				goto out;
 864			tegra186_xusb_padctl_vbus_override(padctl, false);
 865		}
 866	}
 867out:
 868	mutex_unlock(&padctl->lock);
 869	return err;
 870}
 871
 872static int tegra186_utmi_phy_power_on(struct phy *phy)
 873{
 874	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 875	struct tegra_xusb_usb2_lane *usb2 = to_usb2_lane(lane);
 876	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 877	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
 878	struct tegra_xusb_usb2_port *port;
 879	unsigned int index = lane->index;
 880	struct device *dev = padctl->dev;
 881	u32 value;
 882
 883	port = tegra_xusb_find_usb2_port(padctl, index);
 884	if (!port) {
 885		dev_err(dev, "no port found for USB2 lane %u\n", index);
 886		return -ENODEV;
 887	}
 888
 889	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
 890	value &= ~(USB2_PORT_MASK << USB2_PORT_SHIFT(index));
 891	value |= (PORT_XUSB << USB2_PORT_SHIFT(index));
 892	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PAD_MUX);
 893
 894	value = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
 895	value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
 896
 897	if (port->mode == USB_DR_MODE_UNKNOWN)
 898		value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
 899	else if (port->mode == USB_DR_MODE_PERIPHERAL)
 900		value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
 901	else if (port->mode == USB_DR_MODE_HOST)
 902		value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
 903	else if (port->mode == USB_DR_MODE_OTG)
 904		value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
 905
 906	padctl_writel(padctl, value, XUSB_PADCTL_USB2_PORT_CAP);
 907
 908	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
 909	value &= ~USB2_OTG_PD_ZI;
 910	value |= TERM_SEL;
 911	value &= ~HS_CURR_LEVEL(~0);
 912
 913	if (usb2->hs_curr_level_offset) {
 914		int hs_current_level;
 915
 916		hs_current_level = (int)priv->calib.hs_curr_level[index] +
 917						usb2->hs_curr_level_offset;
 918
 919		if (hs_current_level < 0)
 920			hs_current_level = 0;
 921		if (hs_current_level > 0x3f)
 922			hs_current_level = 0x3f;
 923
 924		value |= HS_CURR_LEVEL(hs_current_level);
 925	} else {
 926		value |= HS_CURR_LEVEL(priv->calib.hs_curr_level[index]);
 927	}
 928
 929	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL0(index));
 930
 931	value = padctl_readl(padctl, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
 932	value &= ~TERM_RANGE_ADJ(~0);
 933	value |= TERM_RANGE_ADJ(priv->calib.hs_term_range_adj);
 934	value &= ~RPD_CTRL(~0);
 935	value |= RPD_CTRL(priv->calib.rpd_ctrl);
 936	padctl_writel(padctl, value, XUSB_PADCTL_USB2_OTG_PADX_CTL1(index));
 937
 938	tegra186_utmi_pad_power_on(phy);
 939
 940	return 0;
 941}
 942
 943static int tegra186_utmi_phy_power_off(struct phy *phy)
 944{
 945	tegra186_utmi_pad_power_down(phy);
 946
 947	return 0;
 948}
 949
 950static int tegra186_utmi_phy_init(struct phy *phy)
 951{
 952	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 953	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 954	struct tegra_xusb_usb2_port *port;
 955	unsigned int index = lane->index;
 956	struct device *dev = padctl->dev;
 957	int err;
 958	u32 reg;
 959
 960	port = tegra_xusb_find_usb2_port(padctl, index);
 961	if (!port) {
 962		dev_err(dev, "no port found for USB2 lane %u\n", index);
 963		return -ENODEV;
 964	}
 965
 966	if (port->mode == USB_DR_MODE_OTG ||
 967	    port->mode == USB_DR_MODE_PERIPHERAL) {
 968		/* reset VBUS&ID OVERRIDE */
 969		reg = padctl_readl(padctl, USB2_VBUS_ID);
 970		reg &= ~VBUS_OVERRIDE;
 971		reg &= ~ID_OVERRIDE(~0);
 972		reg |= ID_OVERRIDE_FLOATING;
 973		padctl_writel(padctl, reg, USB2_VBUS_ID);
 974	}
 975
 976	if (port->supply && port->mode == USB_DR_MODE_HOST) {
 977		err = regulator_enable(port->supply);
 978		if (err) {
 979			dev_err(dev, "failed to enable port %u VBUS: %d\n",
 980				index, err);
 981			return err;
 982		}
 983	}
 984
 985	return 0;
 986}
 987
 988static int tegra186_utmi_phy_exit(struct phy *phy)
 989{
 990	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
 991	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
 992	struct tegra_xusb_usb2_port *port;
 993	unsigned int index = lane->index;
 994	struct device *dev = padctl->dev;
 995	int err;
 996
 997	port = tegra_xusb_find_usb2_port(padctl, index);
 998	if (!port) {
 999		dev_err(dev, "no port found for USB2 lane %u\n", index);
1000		return -ENODEV;
1001	}
1002
1003	if (port->supply && port->mode == USB_DR_MODE_HOST) {
1004		err = regulator_disable(port->supply);
1005		if (err) {
1006			dev_err(dev, "failed to disable port %u VBUS: %d\n",
1007				index, err);
1008			return err;
1009		}
1010	}
1011
1012	return 0;
1013}
1014
1015static const struct phy_ops utmi_phy_ops = {
1016	.init = tegra186_utmi_phy_init,
1017	.exit = tegra186_utmi_phy_exit,
1018	.power_on = tegra186_utmi_phy_power_on,
1019	.power_off = tegra186_utmi_phy_power_off,
1020	.set_mode = tegra186_utmi_phy_set_mode,
1021	.owner = THIS_MODULE,
1022};
1023
1024static struct tegra_xusb_pad *
1025tegra186_usb2_pad_probe(struct tegra_xusb_padctl *padctl,
1026			const struct tegra_xusb_pad_soc *soc,
1027			struct device_node *np)
1028{
1029	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1030	struct tegra_xusb_usb2_pad *usb2;
1031	struct tegra_xusb_pad *pad;
1032	int err;
1033
1034	usb2 = kzalloc(sizeof(*usb2), GFP_KERNEL);
1035	if (!usb2)
1036		return ERR_PTR(-ENOMEM);
1037
1038	pad = &usb2->base;
1039	pad->ops = &tegra186_usb2_lane_ops;
1040	pad->soc = soc;
1041
1042	err = tegra_xusb_pad_init(pad, padctl, np);
1043	if (err < 0) {
1044		kfree(usb2);
1045		goto out;
1046	}
1047
1048	priv->usb2_trk_clk = devm_clk_get(&pad->dev, "trk");
1049	if (IS_ERR(priv->usb2_trk_clk)) {
1050		err = PTR_ERR(priv->usb2_trk_clk);
1051		dev_dbg(&pad->dev, "failed to get usb2 trk clock: %d\n", err);
1052		goto unregister;
1053	}
1054
1055	err = tegra_xusb_pad_register(pad, &utmi_phy_ops);
1056	if (err < 0)
1057		goto unregister;
1058
1059	dev_set_drvdata(&pad->dev, pad);
1060
1061	return pad;
1062
1063unregister:
1064	device_unregister(&pad->dev);
1065out:
1066	return ERR_PTR(err);
1067}
1068
1069static void tegra186_usb2_pad_remove(struct tegra_xusb_pad *pad)
1070{
1071	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1072
1073	kfree(usb2);
1074}
1075
1076static const struct tegra_xusb_pad_ops tegra186_usb2_pad_ops = {
1077	.probe = tegra186_usb2_pad_probe,
1078	.remove = tegra186_usb2_pad_remove,
1079};
1080
1081static const char * const tegra186_usb2_functions[] = {
1082	"xusb",
1083};
1084
1085static int tegra186_usb2_port_enable(struct tegra_xusb_port *port)
1086{
1087	return 0;
1088}
1089
1090static void tegra186_usb2_port_disable(struct tegra_xusb_port *port)
1091{
1092}
1093
1094static struct tegra_xusb_lane *
1095tegra186_usb2_port_map(struct tegra_xusb_port *port)
1096{
1097	return tegra_xusb_find_lane(port->padctl, "usb2", port->index);
1098}
1099
1100static const struct tegra_xusb_port_ops tegra186_usb2_port_ops = {
1101	.release = tegra_xusb_usb2_port_release,
1102	.remove = tegra_xusb_usb2_port_remove,
1103	.enable = tegra186_usb2_port_enable,
1104	.disable = tegra186_usb2_port_disable,
1105	.map = tegra186_usb2_port_map,
1106};
1107
1108/* SuperSpeed PHY support */
1109static struct tegra_xusb_lane *
1110tegra186_usb3_lane_probe(struct tegra_xusb_pad *pad, struct device_node *np,
1111			 unsigned int index)
1112{
1113	struct tegra_xusb_usb3_lane *usb3;
1114	int err;
1115
1116	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1117	if (!usb3)
1118		return ERR_PTR(-ENOMEM);
1119
1120	INIT_LIST_HEAD(&usb3->base.list);
1121	usb3->base.soc = &pad->soc->lanes[index];
1122	usb3->base.index = index;
1123	usb3->base.pad = pad;
1124	usb3->base.np = np;
1125
1126	err = tegra_xusb_lane_parse_dt(&usb3->base, np);
1127	if (err < 0) {
1128		kfree(usb3);
1129		return ERR_PTR(err);
1130	}
1131
1132	return &usb3->base;
1133}
1134
1135static void tegra186_usb3_lane_remove(struct tegra_xusb_lane *lane)
1136{
1137	struct tegra_xusb_usb3_lane *usb3 = to_usb3_lane(lane);
1138
1139	kfree(usb3);
1140}
1141
1142static int tegra186_usb3_enable_phy_sleepwalk(struct tegra_xusb_lane *lane,
1143					      enum usb_device_speed speed)
1144{
1145	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1146	unsigned int index = lane->index;
1147	u32 value;
1148
1149	mutex_lock(&padctl->lock);
1150
1151	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1152	value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1153	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1154
1155	usleep_range(100, 200);
1156
1157	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1158	value |= SSPX_ELPG_CLAMP_EN(index);
1159	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1160
1161	usleep_range(250, 350);
1162
1163	mutex_unlock(&padctl->lock);
1164
1165	return 0;
1166}
1167
1168static int tegra186_usb3_disable_phy_sleepwalk(struct tegra_xusb_lane *lane)
1169{
1170	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1171	unsigned int index = lane->index;
1172	u32 value;
1173
1174	mutex_lock(&padctl->lock);
1175
1176	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1177	value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1178	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1179
1180	usleep_range(100, 200);
1181
1182	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1183	value &= ~SSPX_ELPG_CLAMP_EN(index);
1184	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1185
1186	mutex_unlock(&padctl->lock);
1187
1188	return 0;
1189}
1190
1191static int tegra186_usb3_enable_phy_wake(struct tegra_xusb_lane *lane)
1192{
1193	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1194	unsigned int index = lane->index;
1195	u32 value;
1196
1197	mutex_lock(&padctl->lock);
1198
1199	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1200	value &= ~ALL_WAKE_EVENTS;
1201	value |= SS_PORT_WAKEUP_EVENT(index);
1202	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1203
1204	usleep_range(10, 20);
1205
1206	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1207	value &= ~ALL_WAKE_EVENTS;
1208	value |= SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1209	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1210
1211	mutex_unlock(&padctl->lock);
1212
1213	return 0;
1214}
1215
1216static int tegra186_usb3_disable_phy_wake(struct tegra_xusb_lane *lane)
1217{
1218	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1219	unsigned int index = lane->index;
1220	u32 value;
1221
1222	mutex_lock(&padctl->lock);
1223
1224	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1225	value &= ~ALL_WAKE_EVENTS;
1226	value &= ~SS_PORT_WAKE_INTERRUPT_ENABLE(index);
1227	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1228
1229	usleep_range(10, 20);
1230
1231	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1232	value &= ~ALL_WAKE_EVENTS;
1233	value |= SS_PORT_WAKEUP_EVENT(index);
1234	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM);
1235
1236	mutex_unlock(&padctl->lock);
1237
1238	return 0;
1239}
1240
1241static bool tegra186_usb3_phy_remote_wake_detected(struct tegra_xusb_lane *lane)
1242{
1243	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1244	unsigned int index = lane->index;
1245	u32 value;
1246
1247	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM);
1248	if ((value & SS_PORT_WAKE_INTERRUPT_ENABLE(index)) && (value & SS_PORT_WAKEUP_EVENT(index)))
1249		return true;
1250
1251	return false;
1252}
1253
1254static const struct tegra_xusb_lane_ops tegra186_usb3_lane_ops = {
1255	.probe = tegra186_usb3_lane_probe,
1256	.remove = tegra186_usb3_lane_remove,
1257	.enable_phy_sleepwalk = tegra186_usb3_enable_phy_sleepwalk,
1258	.disable_phy_sleepwalk = tegra186_usb3_disable_phy_sleepwalk,
1259	.enable_phy_wake = tegra186_usb3_enable_phy_wake,
1260	.disable_phy_wake = tegra186_usb3_disable_phy_wake,
1261	.remote_wake_detected = tegra186_usb3_phy_remote_wake_detected,
1262};
1263
1264static int tegra186_usb3_port_enable(struct tegra_xusb_port *port)
1265{
1266	return 0;
1267}
1268
1269static void tegra186_usb3_port_disable(struct tegra_xusb_port *port)
1270{
1271}
1272
1273static struct tegra_xusb_lane *
1274tegra186_usb3_port_map(struct tegra_xusb_port *port)
1275{
1276	return tegra_xusb_find_lane(port->padctl, "usb3", port->index);
1277}
1278
1279static const struct tegra_xusb_port_ops tegra186_usb3_port_ops = {
1280	.release = tegra_xusb_usb3_port_release,
1281	.enable = tegra186_usb3_port_enable,
1282	.disable = tegra186_usb3_port_disable,
1283	.map = tegra186_usb3_port_map,
1284};
1285
1286static int tegra186_usb3_phy_power_on(struct phy *phy)
1287{
1288	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1289	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1290	struct tegra_xusb_usb3_port *port;
1291	struct tegra_xusb_usb2_port *usb2;
1292	unsigned int index = lane->index;
1293	struct device *dev = padctl->dev;
1294	u32 value;
1295
1296	port = tegra_xusb_find_usb3_port(padctl, index);
1297	if (!port) {
1298		dev_err(dev, "no port found for USB3 lane %u\n", index);
1299		return -ENODEV;
1300	}
1301
1302	usb2 = tegra_xusb_find_usb2_port(padctl, port->port);
1303	if (!usb2) {
1304		dev_err(dev, "no companion port found for USB3 lane %u\n",
1305			index);
1306		return -ENODEV;
1307	}
1308
1309	mutex_lock(&padctl->lock);
1310
1311	value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1312	value &= ~(PORT_CAP_MASK << PORTX_CAP_SHIFT(index));
1313
1314	if (usb2->mode == USB_DR_MODE_UNKNOWN)
1315		value |= (PORT_CAP_DISABLED << PORTX_CAP_SHIFT(index));
1316	else if (usb2->mode == USB_DR_MODE_PERIPHERAL)
1317		value |= (PORT_CAP_DEVICE << PORTX_CAP_SHIFT(index));
1318	else if (usb2->mode == USB_DR_MODE_HOST)
1319		value |= (PORT_CAP_HOST << PORTX_CAP_SHIFT(index));
1320	else if (usb2->mode == USB_DR_MODE_OTG)
1321		value |= (PORT_CAP_OTG << PORTX_CAP_SHIFT(index));
1322
1323	padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CAP);
1324
1325	if (padctl->soc->supports_gen2 && port->disable_gen2) {
1326		value = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CFG);
1327		value &= ~(PORTX_SPEED_SUPPORT_MASK <<
1328			PORTX_SPEED_SUPPORT_SHIFT(index));
1329		value |= (PORT_SPEED_SUPPORT_GEN1 <<
1330			PORTX_SPEED_SUPPORT_SHIFT(index));
1331		padctl_writel(padctl, value, XUSB_PADCTL_SS_PORT_CFG);
1332	}
1333
1334	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1335	value &= ~SSPX_ELPG_VCORE_DOWN(index);
1336	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1337
1338	usleep_range(100, 200);
1339
1340	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1341	value &= ~SSPX_ELPG_CLAMP_EN_EARLY(index);
1342	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1343
1344	usleep_range(100, 200);
1345
1346	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1347	value &= ~SSPX_ELPG_CLAMP_EN(index);
1348	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1349
1350	mutex_unlock(&padctl->lock);
1351
1352	return 0;
1353}
1354
1355static int tegra186_usb3_phy_power_off(struct phy *phy)
1356{
1357	struct tegra_xusb_lane *lane = phy_get_drvdata(phy);
1358	struct tegra_xusb_padctl *padctl = lane->pad->padctl;
1359	struct tegra_xusb_usb3_port *port;
1360	unsigned int index = lane->index;
1361	struct device *dev = padctl->dev;
1362	u32 value;
1363
1364	port = tegra_xusb_find_usb3_port(padctl, index);
1365	if (!port) {
1366		dev_err(dev, "no port found for USB3 lane %u\n", index);
1367		return -ENODEV;
1368	}
1369
1370	mutex_lock(&padctl->lock);
1371
1372	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1373	value |= SSPX_ELPG_CLAMP_EN_EARLY(index);
1374	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1375
1376	usleep_range(100, 200);
1377
1378	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1379	value |= SSPX_ELPG_CLAMP_EN(index);
1380	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1381
1382	usleep_range(250, 350);
1383
1384	value = padctl_readl(padctl, XUSB_PADCTL_ELPG_PROGRAM_1);
1385	value |= SSPX_ELPG_VCORE_DOWN(index);
1386	padctl_writel(padctl, value, XUSB_PADCTL_ELPG_PROGRAM_1);
1387
1388	mutex_unlock(&padctl->lock);
1389
1390	return 0;
1391}
1392
1393static int tegra186_usb3_phy_init(struct phy *phy)
1394{
1395	return 0;
1396}
1397
1398static int tegra186_usb3_phy_exit(struct phy *phy)
1399{
1400	return 0;
1401}
1402
1403static const struct phy_ops usb3_phy_ops = {
1404	.init = tegra186_usb3_phy_init,
1405	.exit = tegra186_usb3_phy_exit,
1406	.power_on = tegra186_usb3_phy_power_on,
1407	.power_off = tegra186_usb3_phy_power_off,
1408	.owner = THIS_MODULE,
1409};
1410
1411static struct tegra_xusb_pad *
1412tegra186_usb3_pad_probe(struct tegra_xusb_padctl *padctl,
1413			const struct tegra_xusb_pad_soc *soc,
1414			struct device_node *np)
1415{
1416	struct tegra_xusb_usb3_pad *usb3;
1417	struct tegra_xusb_pad *pad;
1418	int err;
1419
1420	usb3 = kzalloc(sizeof(*usb3), GFP_KERNEL);
1421	if (!usb3)
1422		return ERR_PTR(-ENOMEM);
1423
1424	pad = &usb3->base;
1425	pad->ops = &tegra186_usb3_lane_ops;
1426	pad->soc = soc;
1427
1428	err = tegra_xusb_pad_init(pad, padctl, np);
1429	if (err < 0) {
1430		kfree(usb3);
1431		goto out;
1432	}
1433
1434	err = tegra_xusb_pad_register(pad, &usb3_phy_ops);
1435	if (err < 0)
1436		goto unregister;
1437
1438	dev_set_drvdata(&pad->dev, pad);
1439
1440	return pad;
1441
1442unregister:
1443	device_unregister(&pad->dev);
1444out:
1445	return ERR_PTR(err);
1446}
1447
1448static void tegra186_usb3_pad_remove(struct tegra_xusb_pad *pad)
1449{
1450	struct tegra_xusb_usb2_pad *usb2 = to_usb2_pad(pad);
1451
1452	kfree(usb2);
1453}
1454
1455static const struct tegra_xusb_pad_ops tegra186_usb3_pad_ops = {
1456	.probe = tegra186_usb3_pad_probe,
1457	.remove = tegra186_usb3_pad_remove,
1458};
1459
1460static const char * const tegra186_usb3_functions[] = {
1461	"xusb",
1462};
1463
1464static int
1465tegra186_xusb_read_fuse_calibration(struct tegra186_xusb_padctl *padctl)
1466{
1467	struct device *dev = padctl->base.dev;
1468	unsigned int i, count;
1469	u32 value, *level;
1470	int err;
1471
1472	count = padctl->base.soc->ports.usb2.count;
1473
1474	level = devm_kcalloc(dev, count, sizeof(u32), GFP_KERNEL);
1475	if (!level)
1476		return -ENOMEM;
1477
1478	err = tegra_fuse_readl(TEGRA_FUSE_SKU_CALIB_0, &value);
1479	if (err)
1480		return dev_err_probe(dev, err,
1481				     "failed to read calibration fuse\n");
1482
1483	dev_dbg(dev, "FUSE_USB_CALIB_0 %#x\n", value);
1484
1485	for (i = 0; i < count; i++)
1486		level[i] = (value >> HS_CURR_LEVEL_PADX_SHIFT(i)) &
1487				HS_CURR_LEVEL_PAD_MASK;
1488
1489	padctl->calib.hs_curr_level = level;
1490
1491	padctl->calib.hs_squelch = (value >> HS_SQUELCH_SHIFT) &
1492					HS_SQUELCH_MASK;
1493	padctl->calib.hs_term_range_adj = (value >> HS_TERM_RANGE_ADJ_SHIFT) &
1494						HS_TERM_RANGE_ADJ_MASK;
1495
1496	err = tegra_fuse_readl(TEGRA_FUSE_USB_CALIB_EXT_0, &value);
1497	if (err) {
1498		dev_err(dev, "failed to read calibration fuse: %d\n", err);
1499		return err;
1500	}
1501
1502	dev_dbg(dev, "FUSE_USB_CALIB_EXT_0 %#x\n", value);
1503
1504	padctl->calib.rpd_ctrl = (value >> RPD_CTRL_SHIFT) & RPD_CTRL_MASK;
1505
1506	return 0;
1507}
1508
1509static struct tegra_xusb_padctl *
1510tegra186_xusb_padctl_probe(struct device *dev,
1511			   const struct tegra_xusb_padctl_soc *soc)
1512{
1513	struct platform_device *pdev = to_platform_device(dev);
1514	struct tegra186_xusb_padctl *priv;
1515	struct resource *res;
1516	int err;
1517
1518	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1519	if (!priv)
1520		return ERR_PTR(-ENOMEM);
1521
1522	priv->base.dev = dev;
1523	priv->base.soc = soc;
1524
1525	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ao");
1526	priv->ao_regs = devm_ioremap_resource(dev, res);
1527	if (IS_ERR(priv->ao_regs))
1528		return ERR_CAST(priv->ao_regs);
1529
1530	err = tegra186_xusb_read_fuse_calibration(priv);
1531	if (err < 0)
1532		return ERR_PTR(err);
1533
1534	return &priv->base;
1535}
1536
1537static void tegra186_xusb_padctl_save(struct tegra_xusb_padctl *padctl)
1538{
1539	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1540
1541	priv->context.vbus_id = padctl_readl(padctl, USB2_VBUS_ID);
1542	priv->context.usb2_pad_mux = padctl_readl(padctl, XUSB_PADCTL_USB2_PAD_MUX);
1543	priv->context.usb2_port_cap = padctl_readl(padctl, XUSB_PADCTL_USB2_PORT_CAP);
1544	priv->context.ss_port_cap = padctl_readl(padctl, XUSB_PADCTL_SS_PORT_CAP);
1545}
1546
1547static void tegra186_xusb_padctl_restore(struct tegra_xusb_padctl *padctl)
1548{
1549	struct tegra186_xusb_padctl *priv = to_tegra186_xusb_padctl(padctl);
1550
1551	padctl_writel(padctl, priv->context.usb2_pad_mux, XUSB_PADCTL_USB2_PAD_MUX);
1552	padctl_writel(padctl, priv->context.usb2_port_cap, XUSB_PADCTL_USB2_PORT_CAP);
1553	padctl_writel(padctl, priv->context.ss_port_cap, XUSB_PADCTL_SS_PORT_CAP);
1554	padctl_writel(padctl, priv->context.vbus_id, USB2_VBUS_ID);
1555}
1556
1557static int tegra186_xusb_padctl_suspend_noirq(struct tegra_xusb_padctl *padctl)
1558{
1559	tegra186_xusb_padctl_save(padctl);
1560
1561	return 0;
1562}
1563
1564static int tegra186_xusb_padctl_resume_noirq(struct tegra_xusb_padctl *padctl)
1565{
1566	tegra186_xusb_padctl_restore(padctl);
1567
1568	return 0;
1569}
1570
1571static void tegra186_xusb_padctl_remove(struct tegra_xusb_padctl *padctl)
1572{
1573}
1574
1575static const struct tegra_xusb_padctl_ops tegra186_xusb_padctl_ops = {
1576	.probe = tegra186_xusb_padctl_probe,
1577	.remove = tegra186_xusb_padctl_remove,
1578	.suspend_noirq = tegra186_xusb_padctl_suspend_noirq,
1579	.resume_noirq = tegra186_xusb_padctl_resume_noirq,
1580	.vbus_override = tegra186_xusb_padctl_vbus_override,
1581	.utmi_pad_power_on = tegra186_utmi_pad_power_on,
1582	.utmi_pad_power_down = tegra186_utmi_pad_power_down,
1583};
1584
1585#if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC)
1586static const char * const tegra186_xusb_padctl_supply_names[] = {
1587	"avdd-pll-erefeut",
1588	"avdd-usb",
1589	"vclamp-usb",
1590	"vddio-hsic",
1591};
1592
1593static const struct tegra_xusb_lane_soc tegra186_usb2_lanes[] = {
1594	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1595	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1596	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1597};
1598
1599static const struct tegra_xusb_pad_soc tegra186_usb2_pad = {
1600	.name = "usb2",
1601	.num_lanes = ARRAY_SIZE(tegra186_usb2_lanes),
1602	.lanes = tegra186_usb2_lanes,
1603	.ops = &tegra186_usb2_pad_ops,
1604};
1605
1606static const struct tegra_xusb_lane_soc tegra186_usb3_lanes[] = {
1607	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1608	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1609	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1610};
1611
1612static const struct tegra_xusb_pad_soc tegra186_usb3_pad = {
1613	.name = "usb3",
1614	.num_lanes = ARRAY_SIZE(tegra186_usb3_lanes),
1615	.lanes = tegra186_usb3_lanes,
1616	.ops = &tegra186_usb3_pad_ops,
1617};
1618
1619static const struct tegra_xusb_pad_soc * const tegra186_pads[] = {
1620	&tegra186_usb2_pad,
1621	&tegra186_usb3_pad,
1622#if 0 /* TODO implement */
1623	&tegra186_hsic_pad,
1624#endif
1625};
1626
1627const struct tegra_xusb_padctl_soc tegra186_xusb_padctl_soc = {
1628	.num_pads = ARRAY_SIZE(tegra186_pads),
1629	.pads = tegra186_pads,
1630	.ports = {
1631		.usb2 = {
1632			.ops = &tegra186_usb2_port_ops,
1633			.count = 3,
1634		},
1635#if 0 /* TODO implement */
1636		.hsic = {
1637			.ops = &tegra186_hsic_port_ops,
1638			.count = 1,
1639		},
1640#endif
1641		.usb3 = {
1642			.ops = &tegra186_usb3_port_ops,
1643			.count = 3,
1644		},
1645	},
1646	.ops = &tegra186_xusb_padctl_ops,
1647	.supply_names = tegra186_xusb_padctl_supply_names,
1648	.num_supplies = ARRAY_SIZE(tegra186_xusb_padctl_supply_names),
1649};
1650EXPORT_SYMBOL_GPL(tegra186_xusb_padctl_soc);
1651#endif
1652
1653#if IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
1654	IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC)
1655static const char * const tegra194_xusb_padctl_supply_names[] = {
1656	"avdd-usb",
1657	"vclamp-usb",
1658};
1659
1660static const struct tegra_xusb_lane_soc tegra194_usb2_lanes[] = {
1661	TEGRA186_LANE("usb2-0", 0,  0, 0, usb2),
1662	TEGRA186_LANE("usb2-1", 0,  0, 0, usb2),
1663	TEGRA186_LANE("usb2-2", 0,  0, 0, usb2),
1664	TEGRA186_LANE("usb2-3", 0,  0, 0, usb2),
1665};
1666
1667static const struct tegra_xusb_pad_soc tegra194_usb2_pad = {
1668	.name = "usb2",
1669	.num_lanes = ARRAY_SIZE(tegra194_usb2_lanes),
1670	.lanes = tegra194_usb2_lanes,
1671	.ops = &tegra186_usb2_pad_ops,
1672};
1673
1674static const struct tegra_xusb_lane_soc tegra194_usb3_lanes[] = {
1675	TEGRA186_LANE("usb3-0", 0,  0, 0, usb3),
1676	TEGRA186_LANE("usb3-1", 0,  0, 0, usb3),
1677	TEGRA186_LANE("usb3-2", 0,  0, 0, usb3),
1678	TEGRA186_LANE("usb3-3", 0,  0, 0, usb3),
1679};
1680
1681static const struct tegra_xusb_pad_soc tegra194_usb3_pad = {
1682	.name = "usb3",
1683	.num_lanes = ARRAY_SIZE(tegra194_usb3_lanes),
1684	.lanes = tegra194_usb3_lanes,
1685	.ops = &tegra186_usb3_pad_ops,
1686};
1687
1688static const struct tegra_xusb_pad_soc * const tegra194_pads[] = {
1689	&tegra194_usb2_pad,
1690	&tegra194_usb3_pad,
1691};
1692
1693const struct tegra_xusb_padctl_soc tegra194_xusb_padctl_soc = {
1694	.num_pads = ARRAY_SIZE(tegra194_pads),
1695	.pads = tegra194_pads,
1696	.ports = {
1697		.usb2 = {
1698			.ops = &tegra186_usb2_port_ops,
1699			.count = 4,
1700		},
1701		.usb3 = {
1702			.ops = &tegra186_usb3_port_ops,
1703			.count = 4,
1704		},
1705	},
1706	.ops = &tegra186_xusb_padctl_ops,
1707	.supply_names = tegra194_xusb_padctl_supply_names,
1708	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1709	.supports_gen2 = true,
1710	.poll_trk_completed = true,
1711};
1712EXPORT_SYMBOL_GPL(tegra194_xusb_padctl_soc);
1713
1714const struct tegra_xusb_padctl_soc tegra234_xusb_padctl_soc = {
1715	.num_pads = ARRAY_SIZE(tegra194_pads),
1716	.pads = tegra194_pads,
1717	.ports = {
1718		.usb2 = {
1719			.ops = &tegra186_usb2_port_ops,
1720			.count = 4,
1721		},
1722		.usb3 = {
1723			.ops = &tegra186_usb3_port_ops,
1724			.count = 4,
1725		},
1726	},
1727	.ops = &tegra186_xusb_padctl_ops,
1728	.supply_names = tegra194_xusb_padctl_supply_names,
1729	.num_supplies = ARRAY_SIZE(tegra194_xusb_padctl_supply_names),
1730	.supports_gen2 = true,
1731	.poll_trk_completed = true,
1732	.trk_hw_mode = false,
1733	.trk_update_on_idle = true,
1734	.supports_lp_cfg_en = true,
1735};
1736EXPORT_SYMBOL_GPL(tegra234_xusb_padctl_soc);
1737#endif
1738
1739MODULE_AUTHOR("JC Kuo <jckuo@nvidia.com>");
1740MODULE_DESCRIPTION("NVIDIA Tegra186 XUSB Pad Controller driver");
1741MODULE_LICENSE("GPL v2");