phy-exynosautov920-ufs.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * UFS PHY driver data for Samsung ExynosAuto v920 SoC
  4 *
  5 * Copyright (C) 2024 Samsung Electronics Co., Ltd.
  6 */
  7
  8#include "phy-samsung-ufs.h"
  9
 10#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL			0x708
 11#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK		0x1
 12#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
 13#define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
 14
 15#define EXYNOSAUTOV920_CDR_LOCK_OFFSET				0xce4
 16
 17#define PHY_EXYNOSAUTOV920_LANE_OFFSET				0x200
 18#define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
 19	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
 20
 21/* Calibration for phy initialization */
 22static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 23	PHY_COMN_REG_CFG(0x29, 0x22, PWR_MODE_ANY),
 24	PHY_COMN_REG_CFG(0x43, 0x10, PWR_MODE_ANY),
 25	PHY_COMN_REG_CFG(0x3c, 0x14, PWR_MODE_ANY),
 26	PHY_COMN_REG_CFG(0x46, 0x48, PWR_MODE_ANY),
 27	PHY_COMN_REG_CFG(0x04, 0x95, PWR_MODE_ANY),
 28	PHY_COMN_REG_CFG(0x06, 0x30, PWR_MODE_ANY),
 29
 30	PHY_TRSV_REG_CFG_AUTOV920(0x200, 0x00, PWR_MODE_ANY),
 31	PHY_TRSV_REG_CFG_AUTOV920(0x201, 0x06, PWR_MODE_ANY),
 32	PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
 33	PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0a, PWR_MODE_ANY),
 34	PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
 35	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
 36	PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0c, PWR_MODE_ANY),
 37	PHY_TRSV_REG_CFG_AUTOV920(0x2e1, 0xc0, PWR_MODE_ANY),
 38	PHY_TRSV_REG_CFG_AUTOV920(0x22d, 0xf8, PWR_MODE_ANY),
 39	PHY_TRSV_REG_CFG_AUTOV920(0x234, 0x60, PWR_MODE_ANY),
 40	PHY_TRSV_REG_CFG_AUTOV920(0x238, 0x13, PWR_MODE_ANY),
 41	PHY_TRSV_REG_CFG_AUTOV920(0x239, 0x48, PWR_MODE_ANY),
 42	PHY_TRSV_REG_CFG_AUTOV920(0x23a, 0x01, PWR_MODE_ANY),
 43	PHY_TRSV_REG_CFG_AUTOV920(0x23b, 0x29, PWR_MODE_ANY),
 44	PHY_TRSV_REG_CFG_AUTOV920(0x23c, 0x2a, PWR_MODE_ANY),
 45	PHY_TRSV_REG_CFG_AUTOV920(0x23d, 0x01, PWR_MODE_ANY),
 46	PHY_TRSV_REG_CFG_AUTOV920(0x23e, 0x14, PWR_MODE_ANY),
 47	PHY_TRSV_REG_CFG_AUTOV920(0x23f, 0x13, PWR_MODE_ANY),
 48
 49	PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4a, PWR_MODE_ANY),
 50	PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
 51	PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
 52	PHY_TRSV_REG_CFG_AUTOV920(0x25d, 0x00, PWR_MODE_ANY),
 53	PHY_TRSV_REG_CFG_AUTOV920(0x25e, 0x3f, PWR_MODE_ANY),
 54	PHY_TRSV_REG_CFG_AUTOV920(0x25f, 0xff, PWR_MODE_ANY),
 55	PHY_TRSV_REG_CFG_AUTOV920(0x26f, 0xf0, PWR_MODE_ANY),
 56	PHY_TRSV_REG_CFG_AUTOV920(0x273, 0x33, PWR_MODE_ANY),
 57	PHY_TRSV_REG_CFG_AUTOV920(0x274, 0x50, PWR_MODE_ANY),
 58
 59	PHY_TRSV_REG_CFG_AUTOV920(0x284, 0x02, PWR_MODE_ANY),
 60	PHY_TRSV_REG_CFG_AUTOV920(0x285, 0x02, PWR_MODE_ANY),
 61	PHY_TRSV_REG_CFG_AUTOV920(0x2a2, 0x04, PWR_MODE_ANY),
 62	PHY_TRSV_REG_CFG_AUTOV920(0x27d, 0x01, PWR_MODE_ANY),
 63	PHY_TRSV_REG_CFG_AUTOV920(0x2fa, 0x01, PWR_MODE_ANY),
 64
 65	PHY_TRSV_REG_CFG_AUTOV920(0x286, 0x03, PWR_MODE_ANY),
 66	PHY_TRSV_REG_CFG_AUTOV920(0x287, 0x03, PWR_MODE_ANY),
 67	PHY_TRSV_REG_CFG_AUTOV920(0x288, 0x03, PWR_MODE_ANY),
 68	PHY_TRSV_REG_CFG_AUTOV920(0x289, 0x03, PWR_MODE_ANY),
 69	PHY_TRSV_REG_CFG_AUTOV920(0x2b3, 0x04, PWR_MODE_ANY),
 70	PHY_TRSV_REG_CFG_AUTOV920(0x2b6, 0x0b, PWR_MODE_ANY),
 71	PHY_TRSV_REG_CFG_AUTOV920(0x2b7, 0x0b, PWR_MODE_ANY),
 72	PHY_TRSV_REG_CFG_AUTOV920(0x2b8, 0x0b, PWR_MODE_ANY),
 73	PHY_TRSV_REG_CFG_AUTOV920(0x2b9, 0x0b, PWR_MODE_ANY),
 74	PHY_TRSV_REG_CFG_AUTOV920(0x2ba, 0x0b, PWR_MODE_ANY),
 75	PHY_TRSV_REG_CFG_AUTOV920(0x2bb, 0x06, PWR_MODE_ANY),
 76	PHY_TRSV_REG_CFG_AUTOV920(0x2bc, 0x06, PWR_MODE_ANY),
 77	PHY_TRSV_REG_CFG_AUTOV920(0x2bd, 0x06, PWR_MODE_ANY),
 78	PHY_TRSV_REG_CFG_AUTOV920(0x2be, 0x06, PWR_MODE_ANY),
 79	PHY_TRSV_REG_CFG_AUTOV920(0x34b, 0x01, PWR_MODE_ANY),
 80	PHY_TRSV_REG_CFG_AUTOV920(0x34c, 0x24, PWR_MODE_ANY),
 81	PHY_TRSV_REG_CFG_AUTOV920(0x34d, 0x23, PWR_MODE_ANY),
 82	PHY_TRSV_REG_CFG_AUTOV920(0x34e, 0x45, PWR_MODE_ANY),
 83	PHY_TRSV_REG_CFG_AUTOV920(0x34f, 0x00, PWR_MODE_ANY),
 84	PHY_TRSV_REG_CFG_AUTOV920(0x350, 0x31, PWR_MODE_ANY),
 85	PHY_TRSV_REG_CFG_AUTOV920(0x351, 0x00, PWR_MODE_ANY),
 86	PHY_TRSV_REG_CFG_AUTOV920(0x352, 0x02, PWR_MODE_ANY),
 87	PHY_TRSV_REG_CFG_AUTOV920(0x353, 0x00, PWR_MODE_ANY),
 88	PHY_TRSV_REG_CFG_AUTOV920(0x354, 0x01, PWR_MODE_ANY),
 89
 90	PHY_COMN_REG_CFG(0x43, 0x18, PWR_MODE_ANY),
 91	PHY_COMN_REG_CFG(0x43, 0x00, PWR_MODE_ANY),
 92
 93	END_UFS_PHY_CFG,
 94};
 95
 96/* Calibration for HS mode series A/B */
 97static const struct samsung_ufs_phy_cfg exynosautov920_pre_pwr_hs_cfg[] = {
 98	PHY_TRSV_REG_CFG_AUTOV920(0x369, 0x11, PWR_MODE_ANY),
 99	PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x03, PWR_MODE_ANY),
100
101	END_UFS_PHY_CFG,
102};
103
104static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {
105	END_UFS_PHY_CFG,
106};
107
108#define DELAY_IN_US	40
109#define RETRY_CNT	100
110#define EXYNOSAUTOV920_CDR_LOCK_MASK	0x8
111
112int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)
113{
114	struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
115	u32 reg, i;
116
117	struct samsung_ufs_phy_cfg cfg[4] = {
118		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
119		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
120		PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
121		END_UFS_PHY_CFG,
122	};
123
124	for (i = 0; i < RETRY_CNT; i++) {
125		udelay(DELAY_IN_US);
126
127		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET +
128			(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane));
129
130		if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
131					== EXYNOSAUTOV920_CDR_LOCK_MASK) {
132			samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
133			return 0;
134		}
135
136		udelay(DELAY_IN_US);
137
138		/* Disable and enable CDR */
139		samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
140		samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
141	}
142
143	dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
144	return -ETIMEDOUT;
145}
146
147static const struct samsung_ufs_phy_cfg *exynosautov920_ufs_phy_cfgs[CFG_TAG_MAX] = {
148	[CFG_PRE_INIT]          = exynosautov920_pre_init_cfg,
149	[CFG_PRE_PWR_HS]        = exynosautov920_pre_pwr_hs_cfg,
150	[CFG_POST_PWR_HS]       = exynosautov920_post_pwr_hs_cfg,
151};
152
153static const char * const exynosautov920_ufs_phy_clks[] = {
154	"ref_clk",
155};
156
157const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
158	.cfgs = exynosautov920_ufs_phy_cfgs,
159	.isol = {
160		.offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL,
161		.mask = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_MASK,
162		.en = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN,
163	},
164	.clk_list = exynosautov920_ufs_phy_clks,
165	.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
166	.cdr_lock_status_offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
167	.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
168};