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phy-exynos5-usbdrd.c
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linux-6.19.14/drivers/phy/samsung/phy-exynos5-usbdrd.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Samsung Exynos5 SoC series USB DRD PHY driver 4 * 5 * Phy provider for USB 3.0 DRD controller on Exynos5 SoC series 6 * 7 * Copyright (C) 2014 Samsung Electronics Co., Ltd. 8 * Author: Vivek Gautam <gautam.vivek@samsung.com> 9 */ 10 11#include <linux/bitfield.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/io.h> 15#include <linux/kernel.h> 16#include <linux/module.h> 17#include <linux/of.h> 18#include <linux/iopoll.h> 19#include <linux/phy/phy.h> 20#include <linux/platform_device.h> 21#include <linux/mutex.h> 22#include <linux/mfd/syscon.h> 23#include <linux/regmap.h> 24#include <linux/regulator/consumer.h> 25#include <linux/soc/samsung/exynos-regs-pmu.h> 26#include <linux/usb/typec.h> 27#include <linux/usb/typec_mux.h> 28 29/* Exynos USB PHY registers */ 30#define EXYNOS5_FSEL_9MHZ6 0x0 31#define EXYNOS5_FSEL_10MHZ 0x1 32#define EXYNOS5_FSEL_12MHZ 0x2 33#define EXYNOS5_FSEL_19MHZ2 0x3 34#define EXYNOS5_FSEL_20MHZ 0x4 35#define EXYNOS5_FSEL_24MHZ 0x5 36#define EXYNOS5_FSEL_26MHZ 0x6 37#define EXYNOS5_FSEL_50MHZ 0x7 38 39/* USB 3.2 DRD 4nm PHY link controller registers */ 40#define EXYNOS2200_DRD_CLKRST 0x0c 41#define EXYNOS2200_CLKRST_LINK_PCLK_SEL BIT(1) 42 43#define EXYNOS2200_DRD_UTMI 0x10 44#define EXYNOS2200_UTMI_FORCE_VBUSVALID BIT(1) 45#define EXYNOS2200_UTMI_FORCE_BVALID BIT(0) 46 47#define EXYNOS2200_DRD_HSP_MISC 0x114 48#define HSP_MISC_SET_REQ_IN2 BIT(4) 49#define HSP_MISC_RES_TUNE GENMASK(1, 0) 50#define RES_TUNE_PHY1_PHY2 0x1 51#define RES_TUNE_PHY1 0x2 52#define RES_TUNE_PHY2 0x3 53 54/* Exynos5: USB 3.0 DRD PHY registers */ 55#define EXYNOS5_DRD_LINKSYSTEM 0x04 56#define LINKSYSTEM_XHCI_VERSION_CONTROL BIT(27) 57#define LINKSYSTEM_FORCE_VBUSVALID BIT(8) 58#define LINKSYSTEM_FORCE_BVALID BIT(7) 59#define LINKSYSTEM_FLADJ GENMASK(6, 1) 60 61#define EXYNOS5_DRD_PHYUTMI 0x08 62#define PHYUTMI_UTMI_SUSPEND_COM_N BIT(12) 63#define PHYUTMI_UTMI_L1_SUSPEND_COM_N BIT(11) 64#define PHYUTMI_VBUSVLDEXTSEL BIT(10) 65#define PHYUTMI_VBUSVLDEXT BIT(9) 66#define PHYUTMI_TXBITSTUFFENH BIT(8) 67#define PHYUTMI_TXBITSTUFFEN BIT(7) 68#define PHYUTMI_OTGDISABLE BIT(6) 69#define PHYUTMI_IDPULLUP BIT(5) 70#define PHYUTMI_DRVVBUS BIT(4) 71#define PHYUTMI_DPPULLDOWN BIT(3) 72#define PHYUTMI_DMPULLDOWN BIT(2) 73#define PHYUTMI_FORCESUSPEND BIT(1) 74#define PHYUTMI_FORCESLEEP BIT(0) 75 76#define EXYNOS5_DRD_PHYPIPE 0x0c 77 78#define EXYNOS5_DRD_PHYCLKRST 0x10 79#define PHYCLKRST_EN_UTMISUSPEND BIT(31) 80#define PHYCLKRST_SSC_REFCLKSEL GENMASK(30, 23) 81#define PHYCLKRST_SSC_RANGE GENMASK(22, 21) 82#define PHYCLKRST_SSC_EN BIT(20) 83#define PHYCLKRST_REF_SSP_EN BIT(19) 84#define PHYCLKRST_REF_CLKDIV2 BIT(18) 85#define PHYCLKRST_MPLL_MULTIPLIER GENMASK(17, 11) 86#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF 0x19 87#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF 0x32 88#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF 0x68 89#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF 0x7d 90#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF 0x02 91#define PHYCLKRST_FSEL_PIPE GENMASK(10, 8) 92#define PHYCLKRST_FSEL_UTMI GENMASK(7, 5) 93#define PHYCLKRST_FSEL_PAD_100MHZ 0x27 94#define PHYCLKRST_FSEL_PAD_24MHZ 0x2a 95#define PHYCLKRST_FSEL_PAD_20MHZ 0x31 96#define PHYCLKRST_FSEL_PAD_19_2MHZ 0x38 97#define PHYCLKRST_RETENABLEN BIT(4) 98#define PHYCLKRST_REFCLKSEL GENMASK(3, 2) 99#define PHYCLKRST_REFCLKSEL_PAD_REFCLK 0x2 100#define PHYCLKRST_REFCLKSEL_EXT_REFCLK 0x3 101#define PHYCLKRST_PORTRESET BIT(1) 102#define PHYCLKRST_COMMONONN BIT(0) 103 104#define EXYNOS5_DRD_PHYREG0 0x14 105#define PHYREG0_SSC_REF_CLK_SEL BIT(21) 106#define PHYREG0_SSC_RANGE BIT(20) 107#define PHYREG0_CR_WRITE BIT(19) 108#define PHYREG0_CR_READ BIT(18) 109#define PHYREG0_CR_DATA_IN GENMASK(17, 2) 110#define PHYREG0_CR_CAP_DATA BIT(1) 111#define PHYREG0_CR_CAP_ADDR BIT(0) 112 113#define EXYNOS5_DRD_PHYREG1 0x18 114#define PHYREG0_CR_DATA_OUT GENMASK(16, 1) 115#define PHYREG1_CR_ACK BIT(0) 116 117#define EXYNOS5_DRD_PHYPARAM0 0x1c 118#define PHYPARAM0_REF_USE_PAD BIT(31) 119#define PHYPARAM0_REF_LOSLEVEL GENMASK(30, 26) 120#define PHYPARAM0_REF_LOSLEVEL_VAL 0x9 121#define PHYPARAM0_TXVREFTUNE GENMASK(25, 22) 122#define PHYPARAM0_TXRISETUNE GENMASK(21, 20) 123#define PHYPARAM0_TXRESTUNE GENMASK(19, 18) 124#define PHYPARAM0_TXPREEMPPULSETUNE BIT(17) 125#define PHYPARAM0_TXPREEMPAMPTUNE GENMASK(16, 15) 126#define PHYPARAM0_TXHSXVTUNE GENMASK(14, 13) 127#define PHYPARAM0_TXFSLSTUNE GENMASK(12, 9) 128#define PHYPARAM0_SQRXTUNE GENMASK(8, 6) 129#define PHYPARAM0_OTGTUNE GENMASK(5, 3) 130#define PHYPARAM0_COMPDISTUNE GENMASK(2, 0) 131 132#define EXYNOS5_DRD_PHYPARAM1 0x20 133#define PHYPARAM1_PCS_TXDEEMPH GENMASK(4, 0) 134#define PHYPARAM1_PCS_TXDEEMPH_VAL 0x1c 135 136#define EXYNOS5_DRD_PHYTERM 0x24 137 138#define EXYNOS5_DRD_PHYTEST 0x28 139#define PHYTEST_POWERDOWN_SSP BIT(3) 140#define PHYTEST_POWERDOWN_HSP BIT(2) 141 142#define EXYNOS5_DRD_PHYADP 0x2c 143 144#define EXYNOS5_DRD_PHYUTMICLKSEL 0x30 145#define PHYUTMICLKSEL_UTMI_CLKSEL BIT(2) 146 147#define EXYNOS5_DRD_PHYRESUME 0x34 148 149#define EXYNOS5_DRD_LINKPORT 0x44 150#define LINKPORT_HOST_U3_PORT_DISABLE BIT(8) 151#define LINKPORT_HOST_U2_PORT_DISABLE BIT(7) 152#define LINKPORT_HOST_PORT_OVCR_U3 BIT(5) 153#define LINKPORT_HOST_PORT_OVCR_U2 BIT(4) 154#define LINKPORT_HOST_PORT_OVCR_U3_SEL BIT(3) 155#define LINKPORT_HOST_PORT_OVCR_U2_SEL BIT(2) 156 157/* USB 3.0 DRD PHY SS Function Control Reg; accessed by CR_PORT */ 158#define EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN (0x15) 159#define LOSLEVEL_OVRD_IN_LOS_BIAS_5420 (0x5 << 13) 160#define LOSLEVEL_OVRD_IN_LOS_BIAS_DEFAULT (0x0 << 13) 161#define LOSLEVEL_OVRD_IN_EN (0x1 << 10) 162#define LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT (0x9 << 0) 163 164#define EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN (0x12) 165#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420 (0x5 << 13) 166#define TX_VBOOSTLEVEL_OVRD_IN_VBOOST_DEFAULT (0x4 << 13) 167 168#define EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG (0x1010) 169#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M (0x4 << 4) 170#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M (0x8 << 4) 171#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_25M_26M (0x8 << 4) 172#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M (0x20 << 4) 173#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_62M5 (0x20 << 4) 174#define LANE0_TX_DEBUG_RXDET_MEAS_TIME_96M_100M (0x40 << 4) 175 176/* Exynos7870: USB DRD PHY registers */ 177#define EXYNOS7870_DRD_PHYPCSVAL 0x3C 178#define PHYPCSVAL_PCS_RX_LOS_MASK GENMASK(9, 0) 179 180#define EXYNOS7870_DRD_PHYPARAM2 0x50 181#define PHYPARAM2_TX_VBOOST_LVL GENMASK(6, 4) 182#define PHYPARAM2_LOS_BIAS GENMASK(2, 0) 183 184#define EXYNOS7870_DRD_HSPHYCTRL 0x54 185#define HSPHYCTRL_PHYSWRSTALL BIT(31) 186#define HSPHYCTRL_SIDDQ BIT(6) 187#define HSPHYCTRL_PHYSWRST BIT(0) 188 189#define EXYNOS7870_DRD_HSPHYPLLTUNE 0x70 190#define HSPHYPLLTUNE_PLL_B_TUNE BIT(6) 191#define HSPHYPLLTUNE_PLL_I_TUNE GENMASK(5, 4) 192#define HSPHYPLLTUNE_PLL_P_TUNE GENMASK(3, 0) 193 194/* Exynos850: USB DRD PHY registers */ 195#define EXYNOS850_DRD_LINKCTRL 0x04 196#define LINKCTRL_FORCE_RXELECIDLE BIT(18) 197#define LINKCTRL_FORCE_PHYSTATUS BIT(17) 198#define LINKCTRL_FORCE_PIPE_EN BIT(16) 199#define LINKCTRL_FORCE_QACT BIT(8) 200#define LINKCTRL_BUS_FILTER_BYPASS GENMASK(7, 4) 201 202#define EXYNOS850_DRD_LINKPORT 0x08 203#define LINKPORT_HOST_NUM_U3 GENMASK(19, 16) 204#define LINKPORT_HOST_NUM_U2 GENMASK(15, 12) 205 206#define EXYNOS850_DRD_CLKRST 0x20 207/* 208 * On versions without SS ports (like E850), bit 3 is for the 2.0 phy (HS), 209 * while on versions with (like gs101), bits 2 and 3 are for the 3.0 phy (SS) 210 * and bits 12 & 13 for the 2.0 phy. 211 */ 212#define CLKRST_PHY20_SW_POR BIT(13) 213#define CLKRST_PHY20_SW_POR_SEL BIT(12) 214#define CLKRST_LINK_PCLK_SEL BIT(7) 215#define CLKRST_PHY_SW_RST BIT(3) 216#define CLKRST_PHY_RESET_SEL BIT(2) 217#define CLKRST_PORT_RST BIT(1) 218#define CLKRST_LINK_SW_RST BIT(0) 219 220#define EXYNOS850_DRD_SSPPLLCTL 0x30 221#define SSPPLLCTL_FSEL GENMASK(2, 0) 222 223#define EXYNOS850_DRD_UTMI 0x50 224#define UTMI_FORCE_VBUSVALID BIT(5) 225#define UTMI_FORCE_BVALID BIT(4) 226#define UTMI_DP_PULLDOWN BIT(3) 227#define UTMI_DM_PULLDOWN BIT(2) 228#define UTMI_FORCE_SUSPEND BIT(1) 229#define UTMI_FORCE_SLEEP BIT(0) 230 231#define EXYNOS850_DRD_HSP 0x54 232#define HSP_FSV_OUT_EN BIT(24) 233#define HSP_VBUSVLDEXTSEL BIT(13) 234#define HSP_VBUSVLDEXT BIT(12) 235#define HSP_EN_UTMISUSPEND BIT(9) 236#define HSP_COMMONONN BIT(8) 237 238#define EXYNOS850_DRD_HSPPARACON 0x58 239#define HSPPARACON_TXVREF GENMASK(31, 28) 240#define HSPPARACON_TXRISE GENMASK(25, 24) 241#define HSPPARACON_TXRES GENMASK(22, 21) 242#define HSPPARACON_TXPREEMPPULSE BIT(20) 243#define HSPPARACON_TXPREEMPAMP GENMASK(19, 18) 244#define HSPPARACON_TXHSXV GENMASK(17, 16) 245#define HSPPARACON_TXFSLS GENMASK(15, 12) 246#define HSPPARACON_SQRX GENMASK(10, 8) 247#define HSPPARACON_OTG GENMASK(6, 4) 248#define HSPPARACON_COMPDIS GENMASK(2, 0) 249 250#define EXYNOS850_DRD_HSP_TEST 0x5c 251#define HSP_TEST_SIDDQ BIT(24) 252 253/* Exynos9 - GS101 */ 254#define EXYNOS850_DRD_SECPMACTL 0x48 255#define SECPMACTL_PMA_ROPLL_REF_CLK_SEL GENMASK(13, 12) 256#define SECPMACTL_PMA_LCPLL_REF_CLK_SEL GENMASK(11, 10) 257#define SECPMACTL_PMA_REF_FREQ_SEL GENMASK(9, 8) 258#define SECPMACTL_PMA_LOW_PWR BIT(4) 259#define SECPMACTL_PMA_TRSV_SW_RST BIT(3) 260#define SECPMACTL_PMA_CMN_SW_RST BIT(2) 261#define SECPMACTL_PMA_INIT_SW_RST BIT(1) 262#define SECPMACTL_PMA_APB_SW_RST BIT(0) 263 264/* PMA registers */ 265#define EXYNOS9_PMA_USBDP_CMN_REG0008 0x0020 266#define CMN_REG0008_OVRD_AUX_EN BIT(3) 267#define CMN_REG0008_AUX_EN BIT(2) 268 269#define EXYNOS9_PMA_USBDP_CMN_REG00B8 0x02e0 270#define CMN_REG00B8_LANE_MUX_SEL_DP GENMASK(3, 0) 271#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 BIT(3) 272#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE2 BIT(2) 273#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 BIT(1) 274#define CMN_REG00B8_LANE_MUX_SEL_DP_LANE0 BIT(0) 275 276#define EXYNOS9_PMA_USBDP_CMN_REG01C0 0x0700 277#define CMN_REG01C0_ANA_LCPLL_LOCK_DONE BIT(7) 278#define CMN_REG01C0_ANA_LCPLL_AFC_DONE BIT(6) 279 280/* these have similar register layout, for lanes 0 and 2 */ 281#define EXYNOS9_PMA_USBDP_TRSV_REG03C3 0x0f0c 282#define EXYNOS9_PMA_USBDP_TRSV_REG07C3 0x1f0c 283#define TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE BIT(3) 284#define TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE BIT(2) 285#define TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE BIT(1) 286#define TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE BIT(0) 287 288/* TRSV_REG0413 and TRSV_REG0813 have similar register layout */ 289#define EXYNOS9_PMA_USBDP_TRSV_REG0413 0x104c 290#define TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN BIT(7) 291#define TRSV_REG0413_OVRD_LN1_TX_RXD_EN BIT(5) 292 293#define EXYNOS9_PMA_USBDP_TRSV_REG0813 0x204c 294#define TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN BIT(7) 295#define TRSV_REG0813_OVRD_LN3_TX_RXD_EN BIT(5) 296 297/* PCS registers */ 298#define EXYNOS9_PCS_NS_VEC_PS1_N1 0x010c 299#define EXYNOS9_PCS_NS_VEC_PS2_N0 0x0110 300#define EXYNOS9_PCS_NS_VEC_PS3_N0 0x0118 301#define NS_VEC_NS_REQ GENMASK(31, 24) 302#define NS_VEC_ENABLE_TIMER BIT(22) 303#define NS_VEC_SEL_TIMEOUT GENMASK(21, 20) 304#define NS_VEC_INV_MASK GENMASK(19, 16) 305#define NS_VEC_COND_MASK GENMASK(11, 8) 306#define NS_VEC_EXP_COND GENMASK(3, 0) 307 308#define EXYNOS9_PCS_OUT_VEC_2 0x014c 309#define EXYNOS9_PCS_OUT_VEC_3 0x0150 310#define PCS_OUT_VEC_B9_DYNAMIC BIT(19) 311#define PCS_OUT_VEC_B9_SEL_OUT BIT(18) 312#define PCS_OUT_VEC_B8_DYNAMIC BIT(17) 313#define PCS_OUT_VEC_B8_SEL_OUT BIT(16) 314#define PCS_OUT_VEC_B7_DYNAMIC BIT(15) 315#define PCS_OUT_VEC_B7_SEL_OUT BIT(14) 316#define PCS_OUT_VEC_B6_DYNAMIC BIT(13) 317#define PCS_OUT_VEC_B6_SEL_OUT BIT(12) 318#define PCS_OUT_VEC_B5_DYNAMIC BIT(11) 319#define PCS_OUT_VEC_B5_SEL_OUT BIT(10) 320#define PCS_OUT_VEC_B4_DYNAMIC BIT(9) 321#define PCS_OUT_VEC_B4_SEL_OUT BIT(8) 322#define PCS_OUT_VEC_B3_DYNAMIC BIT(7) 323#define PCS_OUT_VEC_B3_SEL_OUT BIT(6) 324#define PCS_OUT_VEC_B2_DYNAMIC BIT(5) 325#define PCS_OUT_VEC_B2_SEL_OUT BIT(4) 326#define PCS_OUT_VEC_B1_DYNAMIC BIT(3) 327#define PCS_OUT_VEC_B1_SEL_OUT BIT(2) 328#define PCS_OUT_VEC_B0_DYNAMIC BIT(1) 329#define PCS_OUT_VEC_B0_SEL_OUT BIT(0) 330 331#define EXYNOS9_PCS_TIMEOUT_0 0x0170 332 333#define EXYNOS9_PCS_TIMEOUT_3 0x017c 334 335#define EXYNOS9_PCS_EBUF_PARAM 0x0304 336#define EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE GENMASK(29, 24) 337 338#define EXYNOS9_PCS_BACK_END_MODE_VEC 0x030c 339#define BACK_END_MODE_VEC_FORCE_EBUF_EMPTY_MODE BIT(1) 340#define BACK_END_MODE_VEC_DISABLE_DATA_MASK BIT(0) 341 342#define EXYNOS9_PCS_RX_CONTROL 0x03f0 343#define RX_CONTROL_EN_BLOCK_ALIGNER_TYPE_B BIT(22) 344 345#define EXYNOS9_PCS_RX_CONTROL_DEBUG 0x03f4 346#define RX_CONTROL_DEBUG_EN_TS_CHECK BIT(5) 347#define RX_CONTROL_DEBUG_NUM_COM_FOUND GENMASK(3, 0) 348 349#define EXYNOS9_PCS_LOCAL_COEF 0x040c 350#define LOCAL_COEF_PMA_CENTER_COEF GENMASK(21, 16) 351#define LOCAL_COEF_LF GENMASK(13, 8) 352#define LOCAL_COEF_FS GENMASK(5, 0) 353 354#define EXYNOS9_PCS_HS_TX_COEF_MAP_0 0x0410 355#define HS_TX_COEF_MAP_0_SSTX_DEEMP GENMASK(17, 12) 356#define HS_TX_COEF_MAP_0_SSTX_LEVEL GENMASK(11, 6) 357#define HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT GENMASK(5, 0) 358 359 360#define KHZ 1000 361#define MHZ (KHZ * KHZ) 362 363#define PHY_TUNING_ENTRY_PHY(o, m, v) { \ 364 .off = (o), \ 365 .mask = (m), \ 366 .val = (v), \ 367 .region = PTR_PHY \ 368 } 369 370#define PHY_TUNING_ENTRY_PCS(o, m, v) { \ 371 .off = (o), \ 372 .mask = (m), \ 373 .val = (v), \ 374 .region = PTR_PCS \ 375 } 376 377#define PHY_TUNING_ENTRY_PMA(o, m, v) { \ 378 .off = (o), \ 379 .mask = (m), \ 380 .val = (v), \ 381 .region = PTR_PMA, \ 382 } 383 384#define PHY_TUNING_ENTRY_LAST { .region = PTR_INVALID } 385 386#define for_each_phy_tune(tune) \ 387 for (; (tune)->region != PTR_INVALID; ++(tune)) 388 389struct exynos5_usbdrd_phy_tuning { 390 u32 off; 391 u32 mask; 392 u32 val; 393 char region; 394#define PTR_INVALID 0 395#define PTR_PHY 1 396#define PTR_PCS 2 397#define PTR_PMA 3 398}; 399 400enum exynos5_usbdrd_phy_tuning_state { 401 PTS_UTMI_POSTINIT, 402 PTS_PIPE3_PREINIT, 403 PTS_PIPE3_INIT, 404 PTS_PIPE3_POSTINIT, 405 PTS_PIPE3_POSTLOCK, 406 PTS_MAX, 407}; 408 409enum exynos5_usbdrd_phy_id { 410 EXYNOS5_DRDPHY_UTMI, 411 EXYNOS5_DRDPHY_PIPE3, 412 EXYNOS5_DRDPHYS_NUM, 413}; 414 415struct phy_usb_instance; 416struct exynos5_usbdrd_phy; 417 418struct exynos5_usbdrd_phy_config { 419 u32 id; 420 void (*phy_isol)(struct phy_usb_instance *inst, bool isolate); 421 void (*phy_init)(struct exynos5_usbdrd_phy *phy_drd); 422 unsigned int (*set_refclk)(struct phy_usb_instance *inst); 423}; 424 425struct exynos5_usbdrd_phy_drvdata { 426 const struct exynos5_usbdrd_phy_config *phy_cfg; 427 const struct exynos5_usbdrd_phy_tuning **phy_tunes; 428 const struct phy_ops *phy_ops; 429 const char * const *clk_names; 430 int n_clks; 431 const char * const *core_clk_names; 432 int n_core_clks; 433 const char * const *regulator_names; 434 int n_regulators; 435 u32 pmu_offset_usbdrd0_phy; 436 u32 pmu_offset_usbdrd0_phy_ss; 437 u32 pmu_offset_usbdrd1_phy; 438}; 439 440/** 441 * struct exynos5_usbdrd_phy - driver data for USB 3.0 PHY 442 * @dev: pointer to device instance of this platform device 443 * @reg_phy: usb phy controller register memory base 444 * @reg_pcs: usb phy physical coding sublayer register memory base 445 * @reg_pma: usb phy physical media attachment register memory base 446 * @clks: clocks for register access 447 * @core_clks: core clocks for phy (ref, pipe3, utmi+, ITP, etc. as required) 448 * @drv_data: pointer to SoC level driver data structure 449 * @hs_phy: pointer to non-Samsung IP high-speed phy controller 450 * @phy_mutex: mutex protecting phy_init/exit & TCPC callbacks 451 * @phys: array for 'EXYNOS5_DRDPHYS_NUM' number of PHY 452 * instances each with its 'phy' and 'phy_cfg'. 453 * @extrefclk: frequency select settings when using 'separate 454 * reference clocks' for SS and HS operations 455 * @regulators: regulators for phy 456 * @sw: TypeC orientation switch handle 457 * @orientation: TypeC connector orientation - normal or flipped 458 */ 459struct exynos5_usbdrd_phy { 460 struct device *dev; 461 void __iomem *reg_phy; 462 void __iomem *reg_pcs; 463 void __iomem *reg_pma; 464 struct clk_bulk_data *clks; 465 struct clk_bulk_data *core_clks; 466 const struct exynos5_usbdrd_phy_drvdata *drv_data; 467 struct phy *hs_phy; 468 struct mutex phy_mutex; 469 struct phy_usb_instance { 470 struct phy *phy; 471 u32 index; 472 struct regmap *reg_pmu; 473 u32 pmu_offset; 474 const struct exynos5_usbdrd_phy_config *phy_cfg; 475 } phys[EXYNOS5_DRDPHYS_NUM]; 476 u32 extrefclk; 477 struct regulator_bulk_data *regulators; 478 479 struct typec_switch_dev *sw; 480 enum typec_orientation orientation; 481}; 482 483static inline 484struct exynos5_usbdrd_phy *to_usbdrd_phy(struct phy_usb_instance *inst) 485{ 486 return container_of((inst), struct exynos5_usbdrd_phy, 487 phys[(inst)->index]); 488} 489 490/* 491 * exynos5_rate_to_clk() converts the supplied clock rate to the value that 492 * can be written to the phy register. 493 */ 494static unsigned int exynos5_rate_to_clk(unsigned long rate, u32 *reg) 495{ 496 /* EXYNOS5_FSEL_MASK */ 497 498 switch (rate) { 499 case 9600 * KHZ: 500 *reg = EXYNOS5_FSEL_9MHZ6; 501 break; 502 case 10 * MHZ: 503 *reg = EXYNOS5_FSEL_10MHZ; 504 break; 505 case 12 * MHZ: 506 *reg = EXYNOS5_FSEL_12MHZ; 507 break; 508 case 19200 * KHZ: 509 *reg = EXYNOS5_FSEL_19MHZ2; 510 break; 511 case 20 * MHZ: 512 *reg = EXYNOS5_FSEL_20MHZ; 513 break; 514 case 24 * MHZ: 515 *reg = EXYNOS5_FSEL_24MHZ; 516 break; 517 case 26 * MHZ: 518 *reg = EXYNOS5_FSEL_26MHZ; 519 break; 520 case 50 * MHZ: 521 *reg = EXYNOS5_FSEL_50MHZ; 522 break; 523 default: 524 return -EINVAL; 525 } 526 527 return 0; 528} 529 530static void exynos5_usbdrd_phy_isol(struct phy_usb_instance *inst, 531 bool isolate) 532{ 533 unsigned int val; 534 535 if (!inst->reg_pmu) 536 return; 537 538 val = isolate ? 0 : EXYNOS4_PHY_ENABLE; 539 540 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, 541 EXYNOS4_PHY_ENABLE, val); 542} 543 544/* 545 * Sets the pipe3 phy's clk as EXTREFCLK (XXTI) which is internal clock 546 * from clock core. Further sets multiplier values and spread spectrum 547 * clock settings for SuperSpeed operations. 548 */ 549static unsigned int 550exynos5_usbdrd_pipe3_set_refclk(struct phy_usb_instance *inst) 551{ 552 u32 reg; 553 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 554 555 /* restore any previous reference clock settings */ 556 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 557 558 /* Use EXTREFCLK as ref clock */ 559 reg &= ~PHYCLKRST_REFCLKSEL; 560 reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK); 561 562 /* FSEL settings corresponding to reference clock */ 563 reg &= ~(PHYCLKRST_FSEL_PIPE | 564 PHYCLKRST_MPLL_MULTIPLIER | 565 PHYCLKRST_SSC_REFCLKSEL); 566 switch (phy_drd->extrefclk) { 567 case EXYNOS5_FSEL_50MHZ: 568 reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 569 FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 570 PHYCLKRST_MPLL_MULTIPLIER_50M_REF)); 571 break; 572 case EXYNOS5_FSEL_24MHZ: 573 reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 574 FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 575 PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF)); 576 break; 577 case EXYNOS5_FSEL_20MHZ: 578 reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x00) | 579 FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 580 PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF)); 581 break; 582 case EXYNOS5_FSEL_19MHZ2: 583 reg |= (FIELD_PREP(PHYCLKRST_SSC_REFCLKSEL, 0x88) | 584 FIELD_PREP(PHYCLKRST_MPLL_MULTIPLIER, 585 PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF)); 586 break; 587 default: 588 dev_dbg(phy_drd->dev, "unsupported ref clk\n"); 589 break; 590 } 591 592 return reg; 593} 594 595/* 596 * Sets the utmi phy's clk as EXTREFCLK (XXTI) which is internal clock 597 * from clock core. Further sets the FSEL values for HighSpeed operations. 598 */ 599static unsigned int 600exynos5_usbdrd_utmi_set_refclk(struct phy_usb_instance *inst) 601{ 602 u32 reg; 603 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 604 605 /* restore any previous reference clock settings */ 606 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 607 608 reg &= ~PHYCLKRST_REFCLKSEL; 609 reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_EXT_REFCLK); 610 611 reg &= ~(PHYCLKRST_FSEL_UTMI | 612 PHYCLKRST_MPLL_MULTIPLIER | 613 PHYCLKRST_SSC_REFCLKSEL); 614 reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); 615 616 return reg; 617} 618 619static void 620exynos5_usbdrd_apply_phy_tunes(struct exynos5_usbdrd_phy *phy_drd, 621 enum exynos5_usbdrd_phy_tuning_state state) 622{ 623 const struct exynos5_usbdrd_phy_tuning *tune; 624 625 tune = phy_drd->drv_data->phy_tunes[state]; 626 if (!tune) 627 return; 628 629 for_each_phy_tune(tune) { 630 void __iomem *reg_base; 631 u32 reg = 0; 632 633 switch (tune->region) { 634 case PTR_PHY: 635 reg_base = phy_drd->reg_phy; 636 break; 637 case PTR_PCS: 638 reg_base = phy_drd->reg_pcs; 639 break; 640 case PTR_PMA: 641 reg_base = phy_drd->reg_pma; 642 break; 643 default: 644 dev_warn_once(phy_drd->dev, 645 "unknown phy region %d\n", tune->region); 646 continue; 647 } 648 649 if (~tune->mask) { 650 reg = readl(reg_base + tune->off); 651 reg &= ~tune->mask; 652 } 653 reg |= tune->val; 654 writel(reg, reg_base + tune->off); 655 } 656} 657 658static void exynos5_usbdrd_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) 659{ 660 u32 reg; 661 662 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 663 /* Set Tx De-Emphasis level */ 664 reg &= ~PHYPARAM1_PCS_TXDEEMPH; 665 reg |= FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL); 666 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 667 668 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); 669 reg &= ~PHYTEST_POWERDOWN_SSP; 670 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); 671} 672 673static void 674exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(struct exynos5_usbdrd_phy *phy_drd) 675{ 676 void __iomem *regs_base = phy_drd->reg_phy; 677 u32 reg; 678 679 /* link pipe_clock selection to pclk of PMA */ 680 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 681 reg |= CLKRST_LINK_PCLK_SEL; 682 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 683 684 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); 685 reg &= ~SECPMACTL_PMA_REF_FREQ_SEL; 686 reg |= FIELD_PREP(SECPMACTL_PMA_REF_FREQ_SEL, 1); 687 /* SFR reset */ 688 reg |= (SECPMACTL_PMA_LOW_PWR | SECPMACTL_PMA_APB_SW_RST); 689 reg &= ~(SECPMACTL_PMA_ROPLL_REF_CLK_SEL | 690 SECPMACTL_PMA_LCPLL_REF_CLK_SEL); 691 /* PMA power off */ 692 reg |= (SECPMACTL_PMA_TRSV_SW_RST | SECPMACTL_PMA_CMN_SW_RST | 693 SECPMACTL_PMA_INIT_SW_RST); 694 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL); 695 696 udelay(1); 697 698 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); 699 reg &= ~SECPMACTL_PMA_LOW_PWR; 700 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL); 701 702 udelay(1); 703 704 /* release override */ 705 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 706 reg &= ~LINKCTRL_FORCE_PIPE_EN; 707 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 708 709 udelay(1); 710 711 /* APB enable */ 712 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); 713 reg &= ~SECPMACTL_PMA_APB_SW_RST; 714 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL); 715} 716 717static void 718exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(struct exynos5_usbdrd_phy *phy_drd) 719{ 720 void __iomem *regs_base = phy_drd->reg_pma; 721 u32 reg; 722 723 /* lane configuration: USB on all lanes */ 724 reg = readl(regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); 725 reg &= ~CMN_REG00B8_LANE_MUX_SEL_DP; 726 /* 727 * USB on lanes 0 & 1 in normal mode, or 2 & 3 if reversed, DP on the 728 * other ones. 729 */ 730 reg |= FIELD_PREP(CMN_REG00B8_LANE_MUX_SEL_DP, 731 ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) 732 ? (CMN_REG00B8_LANE_MUX_SEL_DP_LANE3 733 | CMN_REG00B8_LANE_MUX_SEL_DP_LANE2) 734 : (CMN_REG00B8_LANE_MUX_SEL_DP_LANE1 735 | CMN_REG00B8_LANE_MUX_SEL_DP_LANE0))); 736 writel(reg, regs_base + EXYNOS9_PMA_USBDP_CMN_REG00B8); 737 738 /* override of TX receiver detector and comparator: lane 1 */ 739 reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); 740 if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) { 741 reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; 742 reg &= ~TRSV_REG0413_OVRD_LN1_TX_RXD_EN; 743 } else { 744 reg |= TRSV_REG0413_OVRD_LN1_TX_RXD_COMP_EN; 745 reg |= TRSV_REG0413_OVRD_LN1_TX_RXD_EN; 746 } 747 writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0413); 748 749 /* lane 3 */ 750 reg = readl(regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); 751 if (phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) { 752 reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; 753 reg |= TRSV_REG0813_OVRD_LN3_TX_RXD_EN; 754 } else { 755 reg &= ~TRSV_REG0813_OVRD_LN3_TX_RXD_COMP_EN; 756 reg &= ~TRSV_REG0813_OVRD_LN3_TX_RXD_EN; 757 } 758 writel(reg, regs_base + EXYNOS9_PMA_USBDP_TRSV_REG0813); 759} 760 761static int 762exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock(struct exynos5_usbdrd_phy *phy_drd) 763{ 764 static const unsigned int timeout_us = 40000; 765 static const unsigned int sleep_us = 40; 766 static const u32 locked = (CMN_REG01C0_ANA_LCPLL_LOCK_DONE | 767 CMN_REG01C0_ANA_LCPLL_AFC_DONE); 768 u32 reg; 769 int err; 770 771 err = readl_poll_timeout( 772 phy_drd->reg_pma + EXYNOS9_PMA_USBDP_CMN_REG01C0, 773 reg, (reg & locked) == locked, sleep_us, timeout_us); 774 if (err) 775 dev_err(phy_drd->dev, 776 "timed out waiting for PLL lock: %#.8x\n", reg); 777 778 return err; 779} 780 781static void 782exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(struct exynos5_usbdrd_phy *phy_drd) 783{ 784 static const unsigned int timeout_us = 40000; 785 static const unsigned int sleep_us = 40; 786 static const u32 locked = 787 (TRSV_REG03C3_LN0_MON_RX_CDR_AFC_DONE 788 | TRSV_REG03C3_LN0_MON_RX_CDR_CAL_DONE 789 | TRSV_REG03C3_LN0_MON_RX_CDR_FLD_PLL_MODE_DONE 790 | TRSV_REG03C3_LN0_MON_RX_CDR_LOCK_DONE); 791 u32 reg; 792 int err; 793 794 err = readl_poll_timeout( 795 /* lane depends on cable orientation */ 796 (phy_drd->reg_pma 797 + ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) 798 ? EXYNOS9_PMA_USBDP_TRSV_REG03C3 799 : EXYNOS9_PMA_USBDP_TRSV_REG07C3)), 800 reg, (reg & locked) == locked, sleep_us, timeout_us); 801 if (err) 802 dev_err(phy_drd->dev, 803 "timed out waiting for CDR(l%d) lock: %#.8x\n", 804 ((phy_drd->orientation == TYPEC_ORIENTATION_NORMAL) 805 ? 0 806 : 2), reg); 807} 808 809static void exynos5_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) 810{ 811 u32 reg; 812 813 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 814 /* Set Loss-of-Signal Detector sensitivity */ 815 reg &= ~PHYPARAM0_REF_LOSLEVEL; 816 reg |= FIELD_PREP(PHYPARAM0_REF_LOSLEVEL, PHYPARAM0_REF_LOSLEVEL_VAL); 817 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 818 819 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 820 /* Set Tx De-Emphasis level */ 821 reg &= ~PHYPARAM1_PCS_TXDEEMPH; 822 reg |= FIELD_PREP(PHYPARAM1_PCS_TXDEEMPH, PHYPARAM1_PCS_TXDEEMPH_VAL); 823 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM1); 824 825 /* UTMI Power Control */ 826 writel(PHYUTMI_OTGDISABLE, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); 827 828 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); 829 reg &= ~PHYTEST_POWERDOWN_HSP; 830 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); 831} 832 833static int exynos5_usbdrd_phy_init(struct phy *phy) 834{ 835 int ret; 836 u32 reg; 837 struct phy_usb_instance *inst = phy_get_drvdata(phy); 838 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 839 840 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 841 if (ret) 842 return ret; 843 844 /* Reset USB 3.0 PHY */ 845 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 846 writel(0x0, phy_drd->reg_phy + EXYNOS5_DRD_PHYRESUME); 847 848 /* 849 * Setting the Frame length Adj value[6:1] to default 0x20 850 * See xHCI 1.0 spec, 5.2.4 851 */ 852 reg = LINKSYSTEM_XHCI_VERSION_CONTROL | 853 FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); 854 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 855 856 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 857 /* Select PHY CLK source */ 858 reg &= ~PHYPARAM0_REF_USE_PAD; 859 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYPARAM0); 860 861 /* This bit must be set for both HS and SS operations */ 862 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); 863 reg |= PHYUTMICLKSEL_UTMI_CLKSEL; 864 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMICLKSEL); 865 866 /* UTMI or PIPE3 specific init */ 867 inst->phy_cfg->phy_init(phy_drd); 868 869 /* reference clock settings */ 870 reg = inst->phy_cfg->set_refclk(inst); 871 872 /* Digital power supply in normal operating mode */ 873 reg |= PHYCLKRST_RETENABLEN | 874 /* Enable ref clock for SS function */ 875 PHYCLKRST_REF_SSP_EN | 876 /* Enable spread spectrum */ 877 PHYCLKRST_SSC_EN | 878 /* Power down HS Bias and PLL blocks in suspend mode */ 879 PHYCLKRST_COMMONONN | 880 /* Reset the port */ 881 PHYCLKRST_PORTRESET; 882 883 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 884 885 fsleep(10); 886 887 reg &= ~PHYCLKRST_PORTRESET; 888 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 889 890 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 891 892 return 0; 893} 894 895static int exynos5_usbdrd_phy_exit(struct phy *phy) 896{ 897 int ret; 898 u32 reg; 899 struct phy_usb_instance *inst = phy_get_drvdata(phy); 900 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 901 902 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 903 if (ret) 904 return ret; 905 906 reg = PHYUTMI_OTGDISABLE | 907 PHYUTMI_FORCESUSPEND | 908 PHYUTMI_FORCESLEEP; 909 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); 910 911 /* Resetting the PHYCLKRST enable bits to reduce leakage current */ 912 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 913 reg &= ~(PHYCLKRST_REF_SSP_EN | 914 PHYCLKRST_SSC_EN | 915 PHYCLKRST_COMMONONN); 916 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 917 918 /* Control PHYTEST to remove leakage current */ 919 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); 920 reg |= PHYTEST_POWERDOWN_SSP | 921 PHYTEST_POWERDOWN_HSP; 922 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYTEST); 923 924 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 925 926 return 0; 927} 928 929static int exynos5_usbdrd_phy_power_on(struct phy *phy) 930{ 931 int ret; 932 struct phy_usb_instance *inst = phy_get_drvdata(phy); 933 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 934 935 dev_dbg(phy_drd->dev, "Request to power_on usbdrd_phy phy\n"); 936 937 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_core_clks, 938 phy_drd->core_clks); 939 if (ret) 940 return ret; 941 942 /* Enable VBUS supply */ 943 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, 944 phy_drd->regulators); 945 if (ret) { 946 dev_err(phy_drd->dev, "Failed to enable PHY regulator(s)\n"); 947 goto fail_vbus; 948 } 949 950 /* Power-on PHY */ 951 inst->phy_cfg->phy_isol(inst, false); 952 953 return 0; 954 955fail_vbus: 956 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, 957 phy_drd->core_clks); 958 959 return ret; 960} 961 962static int exynos5_usbdrd_phy_power_off(struct phy *phy) 963{ 964 struct phy_usb_instance *inst = phy_get_drvdata(phy); 965 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 966 967 dev_dbg(phy_drd->dev, "Request to power_off usbdrd_phy phy\n"); 968 969 /* Power-off the PHY */ 970 inst->phy_cfg->phy_isol(inst, true); 971 972 /* Disable VBUS supply */ 973 regulator_bulk_disable(phy_drd->drv_data->n_regulators, 974 phy_drd->regulators); 975 976 clk_bulk_disable_unprepare(phy_drd->drv_data->n_core_clks, 977 phy_drd->core_clks); 978 979 return 0; 980} 981 982static int crport_handshake(struct exynos5_usbdrd_phy *phy_drd, 983 u32 val, u32 cmd) 984{ 985 unsigned int result; 986 int err; 987 988 writel(val | cmd, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 989 990 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1, 991 result, (result & PHYREG1_CR_ACK), 1, 100); 992 if (err == -ETIMEDOUT) { 993 dev_err(phy_drd->dev, "CRPORT handshake timeout1 (0x%08x)\n", val); 994 return err; 995 } 996 997 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 998 999 err = readl_poll_timeout(phy_drd->reg_phy + EXYNOS5_DRD_PHYREG1, 1000 result, !(result & PHYREG1_CR_ACK), 1, 100); 1001 if (err == -ETIMEDOUT) { 1002 dev_err(phy_drd->dev, "CRPORT handshake timeout2 (0x%08x)\n", val); 1003 return err; 1004 } 1005 1006 return 0; 1007} 1008 1009static int crport_ctrl_write(struct exynos5_usbdrd_phy *phy_drd, 1010 u32 addr, u32 data) 1011{ 1012 u32 val; 1013 int ret; 1014 1015 /* Write Address */ 1016 val = FIELD_PREP(PHYREG0_CR_DATA_IN, addr); 1017 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 1018 ret = crport_handshake(phy_drd, val, PHYREG0_CR_CAP_ADDR); 1019 if (ret) 1020 return ret; 1021 1022 /* Write Data */ 1023 val = FIELD_PREP(PHYREG0_CR_DATA_IN, data); 1024 writel(val, phy_drd->reg_phy + EXYNOS5_DRD_PHYREG0); 1025 ret = crport_handshake(phy_drd, val, PHYREG0_CR_CAP_DATA); 1026 if (ret) 1027 return ret; 1028 1029 ret = crport_handshake(phy_drd, val, PHYREG0_CR_WRITE); 1030 1031 return ret; 1032} 1033 1034/* 1035 * Calibrate few PHY parameters using CR_PORT register to meet 1036 * SuperSpeed requirements on Exynos5420 and Exynos5800 systems, 1037 * which have 28nm USB 3.0 DRD PHY. 1038 */ 1039static int exynos5420_usbdrd_phy_calibrate(struct exynos5_usbdrd_phy *phy_drd) 1040{ 1041 unsigned int temp; 1042 int ret = 0; 1043 1044 /* 1045 * Change los_bias to (0x5) for 28nm PHY from a 1046 * default value (0x0); los_level is set as default 1047 * (0x9) as also reflected in los_level[30:26] bits 1048 * of PHYPARAM0 register. 1049 */ 1050 temp = LOSLEVEL_OVRD_IN_LOS_BIAS_5420 | 1051 LOSLEVEL_OVRD_IN_EN | 1052 LOSLEVEL_OVRD_IN_LOS_LEVEL_DEFAULT; 1053 ret = crport_ctrl_write(phy_drd, 1054 EXYNOS5_DRD_PHYSS_LOSLEVEL_OVRD_IN, 1055 temp); 1056 if (ret) { 1057 dev_err(phy_drd->dev, 1058 "Failed setting Loss-of-Signal level for SuperSpeed\n"); 1059 return ret; 1060 } 1061 1062 /* 1063 * Set tx_vboost_lvl to (0x5) for 28nm PHY Tuning, 1064 * to raise Tx signal level from its default value of (0x4) 1065 */ 1066 temp = TX_VBOOSTLEVEL_OVRD_IN_VBOOST_5420; 1067 ret = crport_ctrl_write(phy_drd, 1068 EXYNOS5_DRD_PHYSS_TX_VBOOSTLEVEL_OVRD_IN, 1069 temp); 1070 if (ret) { 1071 dev_err(phy_drd->dev, 1072 "Failed setting Tx-Vboost-Level for SuperSpeed\n"); 1073 return ret; 1074 } 1075 1076 /* 1077 * Set proper time to wait for RxDetect measurement, for 1078 * desired reference clock of PHY, by tuning the CR_PORT 1079 * register LANE0.TX_DEBUG which is internal to PHY. 1080 * This fixes issue with few USB 3.0 devices, which are 1081 * not detected (not even generate interrupts on the bus 1082 * on insertion) without this change. 1083 * e.g. Samsung SUM-TSB16S 3.0 USB drive. 1084 */ 1085 switch (phy_drd->extrefclk) { 1086 case EXYNOS5_FSEL_50MHZ: 1087 temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_48M_50M_52M; 1088 break; 1089 case EXYNOS5_FSEL_20MHZ: 1090 case EXYNOS5_FSEL_19MHZ2: 1091 temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_19M2_20M; 1092 break; 1093 case EXYNOS5_FSEL_24MHZ: 1094 default: 1095 temp = LANE0_TX_DEBUG_RXDET_MEAS_TIME_24M; 1096 break; 1097 } 1098 1099 ret = crport_ctrl_write(phy_drd, 1100 EXYNOS5_DRD_PHYSS_LANE0_TX_DEBUG, 1101 temp); 1102 if (ret) 1103 dev_err(phy_drd->dev, 1104 "Fail to set RxDet measurement time for SuperSpeed\n"); 1105 1106 return ret; 1107} 1108 1109static struct phy *exynos5_usbdrd_phy_xlate(struct device *dev, 1110 const struct of_phandle_args *args) 1111{ 1112 struct exynos5_usbdrd_phy *phy_drd = dev_get_drvdata(dev); 1113 1114 if (WARN_ON(args->args[0] >= EXYNOS5_DRDPHYS_NUM)) 1115 return ERR_PTR(-ENODEV); 1116 1117 return phy_drd->phys[args->args[0]].phy; 1118} 1119 1120static int exynos5_usbdrd_phy_calibrate(struct phy *phy) 1121{ 1122 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1123 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1124 1125 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) 1126 return exynos5420_usbdrd_phy_calibrate(phy_drd); 1127 return 0; 1128} 1129 1130static const struct phy_ops exynos5_usbdrd_phy_ops = { 1131 .init = exynos5_usbdrd_phy_init, 1132 .exit = exynos5_usbdrd_phy_exit, 1133 .power_on = exynos5_usbdrd_phy_power_on, 1134 .power_off = exynos5_usbdrd_phy_power_off, 1135 .calibrate = exynos5_usbdrd_phy_calibrate, 1136 .owner = THIS_MODULE, 1137}; 1138 1139static void exynos7870_usbdrd_phy_isol(struct phy_usb_instance *inst, 1140 bool isolate) 1141{ 1142 unsigned int val; 1143 1144 if (!inst->reg_pmu) 1145 return; 1146 1147 val = isolate ? 0 : EXYNOS7870_USB2PHY_ENABLE; 1148 1149 regmap_update_bits(inst->reg_pmu, inst->pmu_offset, 1150 EXYNOS7870_USB2PHY_ENABLE, val); 1151} 1152 1153static void exynos7870_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) 1154{ 1155 u32 reg; 1156 1157 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 1158 /* Use PADREFCLK as ref clock */ 1159 reg &= ~PHYCLKRST_REFCLKSEL; 1160 reg |= FIELD_PREP(PHYCLKRST_REFCLKSEL, PHYCLKRST_REFCLKSEL_PAD_REFCLK); 1161 /* Select ref clock rate */ 1162 reg &= ~PHYCLKRST_FSEL_UTMI; 1163 reg &= ~PHYCLKRST_FSEL_PIPE; 1164 reg |= FIELD_PREP(PHYCLKRST_FSEL_UTMI, phy_drd->extrefclk); 1165 /* Enable suspend and reset the port */ 1166 reg |= PHYCLKRST_EN_UTMISUSPEND; 1167 reg |= PHYCLKRST_COMMONONN; 1168 reg |= PHYCLKRST_PORTRESET; 1169 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 1170 udelay(10); 1171 1172 /* Clear the port reset bit */ 1173 reg &= ~PHYCLKRST_PORTRESET; 1174 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYCLKRST); 1175 1176 /* Change PHY PLL tune value */ 1177 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); 1178 if (phy_drd->extrefclk == EXYNOS5_FSEL_24MHZ) 1179 reg |= HSPHYPLLTUNE_PLL_B_TUNE; 1180 else 1181 reg &= ~HSPHYPLLTUNE_PLL_B_TUNE; 1182 reg &= ~HSPHYPLLTUNE_PLL_P_TUNE; 1183 reg |= FIELD_PREP(HSPHYPLLTUNE_PLL_P_TUNE, 14); 1184 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYPLLTUNE); 1185 1186 /* High-Speed PHY control */ 1187 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1188 reg &= ~HSPHYCTRL_SIDDQ; 1189 reg &= ~HSPHYCTRL_PHYSWRST; 1190 reg &= ~HSPHYCTRL_PHYSWRSTALL; 1191 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1192 udelay(500); 1193 1194 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 1195 /* 1196 * Setting the Frame length Adj value[6:1] to default 0x20 1197 * See xHCI 1.0 spec, 5.2.4 1198 */ 1199 reg |= LINKSYSTEM_XHCI_VERSION_CONTROL; 1200 reg &= ~LINKSYSTEM_FLADJ; 1201 reg |= FIELD_PREP(LINKSYSTEM_FLADJ, 0x20); 1202 /* Set VBUSVALID signal as the VBUS pad is not used */ 1203 reg |= LINKSYSTEM_FORCE_BVALID; 1204 reg |= LINKSYSTEM_FORCE_VBUSVALID; 1205 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 1206 1207 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); 1208 /* Release force_sleep & force_suspend */ 1209 reg &= ~PHYUTMI_FORCESLEEP; 1210 reg &= ~PHYUTMI_FORCESUSPEND; 1211 /* DP/DM pull down control */ 1212 reg &= ~PHYUTMI_DMPULLDOWN; 1213 reg &= ~PHYUTMI_DPPULLDOWN; 1214 reg &= ~PHYUTMI_DRVVBUS; 1215 /* Set DP-pull up as the VBUS pad is not used */ 1216 reg |= PHYUTMI_VBUSVLDEXTSEL; 1217 reg |= PHYUTMI_VBUSVLDEXT; 1218 /* Disable OTG block and VBUS valid comparator */ 1219 reg |= PHYUTMI_OTGDISABLE; 1220 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); 1221 1222 /* Configure OVC IO usage */ 1223 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT); 1224 reg |= LINKPORT_HOST_PORT_OVCR_U3_SEL | LINKPORT_HOST_PORT_OVCR_U2_SEL; 1225 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKPORT); 1226 1227 /* High-Speed PHY swrst */ 1228 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1229 reg |= HSPHYCTRL_PHYSWRST; 1230 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1231 udelay(20); 1232 1233 /* Clear the PHY swrst bit */ 1234 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1235 reg &= ~HSPHYCTRL_PHYSWRST; 1236 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1237 1238 if (phy_drd->drv_data->phy_tunes) 1239 exynos5_usbdrd_apply_phy_tunes(phy_drd, 1240 PTS_UTMI_POSTINIT); 1241} 1242 1243static int exynos7870_usbdrd_phy_init(struct phy *phy) 1244{ 1245 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1246 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1247 int ret; 1248 1249 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1250 if (ret) 1251 return ret; 1252 1253 /* UTMI or PIPE3 specific init */ 1254 inst->phy_cfg->phy_init(phy_drd); 1255 1256 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1257 1258 return 0; 1259} 1260 1261static int exynos7870_usbdrd_phy_exit(struct phy *phy) 1262{ 1263 int ret; 1264 u32 reg; 1265 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1266 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1267 1268 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1269 if (ret) 1270 return ret; 1271 1272 /* 1273 * Disable the VBUS signal and the ID pull-up resistor. 1274 * Enable force-suspend and force-sleep modes. 1275 */ 1276 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); 1277 reg &= ~(PHYUTMI_DRVVBUS | PHYUTMI_VBUSVLDEXT | PHYUTMI_VBUSVLDEXTSEL); 1278 reg &= ~PHYUTMI_IDPULLUP; 1279 reg |= PHYUTMI_FORCESUSPEND | PHYUTMI_FORCESLEEP; 1280 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_PHYUTMI); 1281 1282 /* Power down PHY analog blocks */ 1283 reg = readl(phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1284 reg |= HSPHYCTRL_SIDDQ; 1285 writel(reg, phy_drd->reg_phy + EXYNOS7870_DRD_HSPHYCTRL); 1286 1287 /* Clear VBUSVALID signal as the VBUS pad is not used */ 1288 reg = readl(phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 1289 reg &= ~(LINKSYSTEM_FORCE_BVALID | LINKSYSTEM_FORCE_VBUSVALID); 1290 writel(reg, phy_drd->reg_phy + EXYNOS5_DRD_LINKSYSTEM); 1291 1292 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1293 1294 return 0; 1295} 1296 1297static const struct phy_ops exynos7870_usbdrd_phy_ops = { 1298 .init = exynos7870_usbdrd_phy_init, 1299 .exit = exynos7870_usbdrd_phy_exit, 1300 .power_on = exynos5_usbdrd_phy_power_on, 1301 .power_off = exynos5_usbdrd_phy_power_off, 1302 .owner = THIS_MODULE, 1303}; 1304 1305static void exynos2200_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) 1306{ 1307 /* Configure non-Samsung IP PHY, responsible for UTMI */ 1308 phy_init(phy_drd->hs_phy); 1309} 1310 1311static void exynos2200_usbdrd_link_init(struct exynos5_usbdrd_phy *phy_drd) 1312{ 1313 void __iomem *regs_base = phy_drd->reg_phy; 1314 u32 reg; 1315 1316 /* 1317 * Disable HWACG (hardware auto clock gating control). This will force 1318 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure 1319 * the PHY clock is not gated by the hardware. 1320 */ 1321 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1322 reg |= LINKCTRL_FORCE_QACT; 1323 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1324 1325 /* De-assert link reset */ 1326 reg = readl(regs_base + EXYNOS2200_DRD_CLKRST); 1327 reg &= ~CLKRST_LINK_SW_RST; 1328 writel(reg, regs_base + EXYNOS2200_DRD_CLKRST); 1329 1330 /* Set link VBUS Valid */ 1331 reg = readl(regs_base + EXYNOS2200_DRD_UTMI); 1332 reg |= EXYNOS2200_UTMI_FORCE_BVALID | EXYNOS2200_UTMI_FORCE_VBUSVALID; 1333 writel(reg, regs_base + EXYNOS2200_DRD_UTMI); 1334} 1335 1336static void 1337exynos2200_usbdrd_link_attach_detach_pipe3_phy(struct phy_usb_instance *inst) 1338{ 1339 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1340 void __iomem *regs_base = phy_drd->reg_phy; 1341 u32 reg; 1342 1343 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1344 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { 1345 /* force pipe3 signal for link */ 1346 reg &= ~LINKCTRL_FORCE_PHYSTATUS; 1347 reg |= LINKCTRL_FORCE_PIPE_EN | LINKCTRL_FORCE_RXELECIDLE; 1348 } else { 1349 /* disable forcing pipe interface */ 1350 reg &= ~LINKCTRL_FORCE_PIPE_EN; 1351 } 1352 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1353 1354 reg = readl(regs_base + EXYNOS2200_DRD_HSP_MISC); 1355 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { 1356 /* calibrate only eUSB phy */ 1357 reg |= FIELD_PREP(HSP_MISC_RES_TUNE, RES_TUNE_PHY1); 1358 reg |= HSP_MISC_SET_REQ_IN2; 1359 } else { 1360 /* calibrate for dual phy */ 1361 reg |= FIELD_PREP(HSP_MISC_RES_TUNE, RES_TUNE_PHY1_PHY2); 1362 reg &= ~HSP_MISC_SET_REQ_IN2; 1363 } 1364 writel(reg, regs_base + EXYNOS2200_DRD_HSP_MISC); 1365 1366 reg = readl(regs_base + EXYNOS2200_DRD_CLKRST); 1367 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) 1368 reg &= ~EXYNOS2200_CLKRST_LINK_PCLK_SEL; 1369 else 1370 reg |= EXYNOS2200_CLKRST_LINK_PCLK_SEL; 1371 1372 writel(reg, regs_base + EXYNOS2200_DRD_CLKRST); 1373} 1374 1375static int exynos2200_usbdrd_phy_init(struct phy *phy) 1376{ 1377 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1378 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1379 int ret; 1380 1381 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { 1382 /* Power-on PHY ... */ 1383 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, 1384 phy_drd->regulators); 1385 if (ret) { 1386 dev_err(phy_drd->dev, 1387 "Failed to enable PHY regulator(s)\n"); 1388 return ret; 1389 } 1390 } 1391 /* 1392 * ... and ungate power via PMU. Without this here, we get an SError 1393 * trying to access PMA registers 1394 */ 1395 exynos5_usbdrd_phy_isol(inst, false); 1396 1397 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1398 if (ret) 1399 return ret; 1400 1401 /* Set up the link controller */ 1402 exynos2200_usbdrd_link_init(phy_drd); 1403 1404 /* UTMI or PIPE3 link preparation */ 1405 exynos2200_usbdrd_link_attach_detach_pipe3_phy(inst); 1406 1407 /* UTMI or PIPE3 specific init */ 1408 inst->phy_cfg->phy_init(phy_drd); 1409 1410 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1411 1412 return 0; 1413} 1414 1415static int exynos2200_usbdrd_phy_exit(struct phy *phy) 1416{ 1417 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1418 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1419 void __iomem *regs_base = phy_drd->reg_phy; 1420 u32 reg; 1421 int ret; 1422 1423 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1424 if (ret) 1425 return ret; 1426 1427 reg = readl(regs_base + EXYNOS2200_DRD_UTMI); 1428 reg &= ~(EXYNOS2200_UTMI_FORCE_BVALID | EXYNOS2200_UTMI_FORCE_VBUSVALID); 1429 writel(reg, regs_base + EXYNOS2200_DRD_UTMI); 1430 1431 reg = readl(regs_base + EXYNOS2200_DRD_CLKRST); 1432 reg |= CLKRST_LINK_SW_RST; 1433 writel(reg, regs_base + EXYNOS2200_DRD_CLKRST); 1434 1435 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1436 1437 exynos5_usbdrd_phy_isol(inst, true); 1438 return regulator_bulk_disable(phy_drd->drv_data->n_regulators, 1439 phy_drd->regulators); 1440} 1441 1442static const struct phy_ops exynos2200_usbdrd_phy_ops = { 1443 .init = exynos2200_usbdrd_phy_init, 1444 .exit = exynos2200_usbdrd_phy_exit, 1445 .owner = THIS_MODULE, 1446}; 1447 1448static void 1449exynos5_usbdrd_usb_v3p1_pipe_override(struct exynos5_usbdrd_phy *phy_drd) 1450{ 1451 void __iomem *regs_base = phy_drd->reg_phy; 1452 u32 reg; 1453 1454 /* force pipe3 signal for link */ 1455 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1456 reg &= ~LINKCTRL_FORCE_PHYSTATUS; 1457 reg |= LINKCTRL_FORCE_PIPE_EN | LINKCTRL_FORCE_RXELECIDLE; 1458 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1459 1460 /* PMA disable */ 1461 reg = readl(regs_base + EXYNOS850_DRD_SECPMACTL); 1462 reg |= SECPMACTL_PMA_LOW_PWR; 1463 writel(reg, regs_base + EXYNOS850_DRD_SECPMACTL); 1464} 1465 1466static void exynos850_usbdrd_utmi_init(struct exynos5_usbdrd_phy *phy_drd) 1467{ 1468 void __iomem *regs_base = phy_drd->reg_phy; 1469 u32 reg; 1470 u32 ss_ports; 1471 1472 /* 1473 * Disable HWACG (hardware auto clock gating control). This will force 1474 * QACTIVE signal in Q-Channel interface to HIGH level, to make sure 1475 * the PHY clock is not gated by the hardware. 1476 */ 1477 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1478 reg |= LINKCTRL_FORCE_QACT; 1479 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1480 1481 reg = readl(regs_base + EXYNOS850_DRD_LINKPORT); 1482 ss_ports = FIELD_GET(LINKPORT_HOST_NUM_U3, reg); 1483 1484 /* Start PHY Reset (POR=high) */ 1485 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 1486 if (ss_ports) { 1487 reg |= CLKRST_PHY20_SW_POR; 1488 reg |= CLKRST_PHY20_SW_POR_SEL; 1489 reg |= CLKRST_PHY_RESET_SEL; 1490 } 1491 reg |= CLKRST_PHY_SW_RST; 1492 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 1493 1494 /* Enable UTMI+ */ 1495 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 1496 reg &= ~(UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP | UTMI_DP_PULLDOWN | 1497 UTMI_DM_PULLDOWN); 1498 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 1499 1500 /* Set PHY clock and control HS PHY */ 1501 reg = readl(regs_base + EXYNOS850_DRD_HSP); 1502 reg |= HSP_EN_UTMISUSPEND | HSP_COMMONONN; 1503 writel(reg, regs_base + EXYNOS850_DRD_HSP); 1504 1505 /* Set VBUS Valid and D+ pull-up control by VBUS pad usage */ 1506 reg = readl(regs_base + EXYNOS850_DRD_LINKCTRL); 1507 reg |= FIELD_PREP(LINKCTRL_BUS_FILTER_BYPASS, 0xf); 1508 writel(reg, regs_base + EXYNOS850_DRD_LINKCTRL); 1509 1510 if (!phy_drd->sw) { 1511 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 1512 reg |= UTMI_FORCE_BVALID | UTMI_FORCE_VBUSVALID; 1513 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 1514 1515 reg = readl(regs_base + EXYNOS850_DRD_HSP); 1516 reg |= HSP_VBUSVLDEXT | HSP_VBUSVLDEXTSEL; 1517 writel(reg, regs_base + EXYNOS850_DRD_HSP); 1518 } 1519 1520 reg = readl(regs_base + EXYNOS850_DRD_SSPPLLCTL); 1521 reg &= ~SSPPLLCTL_FSEL; 1522 switch (phy_drd->extrefclk) { 1523 case EXYNOS5_FSEL_50MHZ: 1524 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 7); 1525 break; 1526 case EXYNOS5_FSEL_26MHZ: 1527 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 6); 1528 break; 1529 case EXYNOS5_FSEL_24MHZ: 1530 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 2); 1531 break; 1532 case EXYNOS5_FSEL_20MHZ: 1533 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 1); 1534 break; 1535 case EXYNOS5_FSEL_19MHZ2: 1536 reg |= FIELD_PREP(SSPPLLCTL_FSEL, 0); 1537 break; 1538 default: 1539 dev_warn(phy_drd->dev, "unsupported ref clk: %#.2x\n", 1540 phy_drd->extrefclk); 1541 break; 1542 } 1543 writel(reg, regs_base + EXYNOS850_DRD_SSPPLLCTL); 1544 1545 if (phy_drd->drv_data->phy_tunes) 1546 exynos5_usbdrd_apply_phy_tunes(phy_drd, 1547 PTS_UTMI_POSTINIT); 1548 1549 /* Power up PHY analog blocks */ 1550 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); 1551 reg &= ~HSP_TEST_SIDDQ; 1552 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); 1553 1554 /* Finish PHY reset (POR=low) */ 1555 fsleep(10); /* required before doing POR=low */ 1556 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 1557 if (ss_ports) { 1558 reg |= CLKRST_PHY20_SW_POR_SEL; 1559 reg &= ~CLKRST_PHY20_SW_POR; 1560 } 1561 reg &= ~(CLKRST_PHY_SW_RST | CLKRST_PORT_RST); 1562 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 1563 fsleep(75); /* required after POR=low for guaranteed PHY clock */ 1564 1565 /* Disable single ended signal out */ 1566 reg = readl(regs_base + EXYNOS850_DRD_HSP); 1567 reg &= ~HSP_FSV_OUT_EN; 1568 writel(reg, regs_base + EXYNOS850_DRD_HSP); 1569 1570 if (ss_ports) 1571 exynos5_usbdrd_usb_v3p1_pipe_override(phy_drd); 1572} 1573 1574static int exynos850_usbdrd_phy_init(struct phy *phy) 1575{ 1576 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1577 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1578 int ret; 1579 1580 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1581 if (ret) 1582 return ret; 1583 1584 /* UTMI or PIPE3 specific init */ 1585 scoped_guard(mutex, &phy_drd->phy_mutex) 1586 inst->phy_cfg->phy_init(phy_drd); 1587 1588 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1589 1590 return 0; 1591} 1592 1593static int exynos850_usbdrd_phy_exit(struct phy *phy) 1594{ 1595 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1596 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1597 void __iomem *regs_base = phy_drd->reg_phy; 1598 u32 reg; 1599 int ret; 1600 1601 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1602 if (ret) 1603 return ret; 1604 1605 guard(mutex)(&phy_drd->phy_mutex); 1606 1607 /* Set PHY clock and control HS PHY */ 1608 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 1609 reg &= ~(UTMI_DP_PULLDOWN | UTMI_DM_PULLDOWN); 1610 reg |= UTMI_FORCE_SUSPEND | UTMI_FORCE_SLEEP; 1611 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 1612 1613 /* Power down PHY analog blocks */ 1614 reg = readl(regs_base + EXYNOS850_DRD_HSP_TEST); 1615 reg |= HSP_TEST_SIDDQ; 1616 writel(reg, regs_base + EXYNOS850_DRD_HSP_TEST); 1617 1618 /* Link reset */ 1619 reg = readl(regs_base + EXYNOS850_DRD_CLKRST); 1620 reg |= CLKRST_LINK_SW_RST; 1621 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 1622 fsleep(10); /* required before doing POR=low */ 1623 reg &= ~CLKRST_LINK_SW_RST; 1624 writel(reg, regs_base + EXYNOS850_DRD_CLKRST); 1625 1626 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1627 1628 return 0; 1629} 1630 1631static const struct phy_ops exynos850_usbdrd_phy_ops = { 1632 .init = exynos850_usbdrd_phy_init, 1633 .exit = exynos850_usbdrd_phy_exit, 1634 .power_on = exynos5_usbdrd_phy_power_on, 1635 .power_off = exynos5_usbdrd_phy_power_off, 1636 .owner = THIS_MODULE, 1637}; 1638 1639static void exynos5_usbdrd_gs101_pipe3_init(struct exynos5_usbdrd_phy *phy_drd) 1640{ 1641 void __iomem *regs_pma = phy_drd->reg_pma; 1642 void __iomem *regs_phy = phy_drd->reg_phy; 1643 u32 reg; 1644 1645 exynos5_usbdrd_usbdp_g2_v4_ctrl_pma_ready(phy_drd); 1646 1647 /* force aux off */ 1648 reg = readl(regs_pma + EXYNOS9_PMA_USBDP_CMN_REG0008); 1649 reg &= ~CMN_REG0008_AUX_EN; 1650 reg |= CMN_REG0008_OVRD_AUX_EN; 1651 writel(reg, regs_pma + EXYNOS9_PMA_USBDP_CMN_REG0008); 1652 1653 exynos5_usbdrd_apply_phy_tunes(phy_drd, PTS_PIPE3_PREINIT); 1654 exynos5_usbdrd_apply_phy_tunes(phy_drd, PTS_PIPE3_INIT); 1655 exynos5_usbdrd_apply_phy_tunes(phy_drd, PTS_PIPE3_POSTINIT); 1656 1657 exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(phy_drd); 1658 1659 /* reset release from port */ 1660 reg = readl(regs_phy + EXYNOS850_DRD_SECPMACTL); 1661 reg &= ~(SECPMACTL_PMA_TRSV_SW_RST | SECPMACTL_PMA_CMN_SW_RST | 1662 SECPMACTL_PMA_INIT_SW_RST); 1663 writel(reg, regs_phy + EXYNOS850_DRD_SECPMACTL); 1664 1665 if (!exynos5_usbdrd_usbdp_g2_v4_pma_check_pll_lock(phy_drd)) 1666 exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock(phy_drd); 1667} 1668 1669static int exynos5_usbdrd_gs101_phy_init(struct phy *phy) 1670{ 1671 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1672 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1673 int ret; 1674 1675 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { 1676 /* Power-on PHY ... */ 1677 ret = regulator_bulk_enable(phy_drd->drv_data->n_regulators, 1678 phy_drd->regulators); 1679 if (ret) { 1680 dev_err(phy_drd->dev, 1681 "Failed to enable PHY regulator(s)\n"); 1682 return ret; 1683 } 1684 } 1685 /* 1686 * ... and ungate power via PMU. Without this here, we get an SError 1687 * trying to access PMA registers 1688 */ 1689 exynos5_usbdrd_phy_isol(inst, false); 1690 1691 return exynos850_usbdrd_phy_init(phy); 1692} 1693 1694static int exynos5_usbdrd_gs101_phy_exit(struct phy *phy) 1695{ 1696 struct phy_usb_instance *inst = phy_get_drvdata(phy); 1697 struct exynos5_usbdrd_phy *phy_drd = to_usbdrd_phy(inst); 1698 int ret; 1699 1700 if (inst->phy_cfg->id == EXYNOS5_DRDPHY_UTMI) { 1701 ret = exynos850_usbdrd_phy_exit(phy); 1702 if (ret) 1703 return ret; 1704 } 1705 1706 exynos5_usbdrd_phy_isol(inst, true); 1707 1708 if (inst->phy_cfg->id != EXYNOS5_DRDPHY_UTMI) 1709 return 0; 1710 1711 return regulator_bulk_disable(phy_drd->drv_data->n_regulators, 1712 phy_drd->regulators); 1713} 1714 1715static const struct phy_ops gs101_usbdrd_phy_ops = { 1716 .init = exynos5_usbdrd_gs101_phy_init, 1717 .exit = exynos5_usbdrd_gs101_phy_exit, 1718 .owner = THIS_MODULE, 1719}; 1720 1721static int exynos5_usbdrd_phy_clk_handle(struct exynos5_usbdrd_phy *phy_drd) 1722{ 1723 int ret; 1724 struct clk *ref_clk; 1725 unsigned long ref_rate; 1726 1727 phy_drd->clks = devm_kcalloc(phy_drd->dev, phy_drd->drv_data->n_clks, 1728 sizeof(*phy_drd->clks), GFP_KERNEL); 1729 if (!phy_drd->clks) 1730 return -ENOMEM; 1731 1732 for (int i = 0; i < phy_drd->drv_data->n_clks; ++i) 1733 phy_drd->clks[i].id = phy_drd->drv_data->clk_names[i]; 1734 1735 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_clks, 1736 phy_drd->clks); 1737 if (ret) 1738 return dev_err_probe(phy_drd->dev, ret, 1739 "failed to get phy clock(s)\n"); 1740 1741 phy_drd->core_clks = devm_kcalloc(phy_drd->dev, 1742 phy_drd->drv_data->n_core_clks, 1743 sizeof(*phy_drd->core_clks), 1744 GFP_KERNEL); 1745 if (!phy_drd->core_clks) 1746 return -ENOMEM; 1747 1748 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) 1749 phy_drd->core_clks[i].id = phy_drd->drv_data->core_clk_names[i]; 1750 1751 ret = devm_clk_bulk_get(phy_drd->dev, phy_drd->drv_data->n_core_clks, 1752 phy_drd->core_clks); 1753 if (ret) 1754 return dev_err_probe(phy_drd->dev, ret, 1755 "failed to get phy core clock(s)\n"); 1756 1757 if (phy_drd->drv_data->n_core_clks) { 1758 ref_clk = NULL; 1759 for (int i = 0; i < phy_drd->drv_data->n_core_clks; ++i) { 1760 if (!strcmp(phy_drd->core_clks[i].id, "ref")) { 1761 ref_clk = phy_drd->core_clks[i].clk; 1762 break; 1763 } 1764 } 1765 if (!ref_clk) 1766 return dev_err_probe(phy_drd->dev, -ENODEV, 1767 "failed to find phy reference clock\n"); 1768 1769 ref_rate = clk_get_rate(ref_clk); 1770 ret = exynos5_rate_to_clk(ref_rate, &phy_drd->extrefclk); 1771 if (ret) 1772 return dev_err_probe(phy_drd->dev, ret, 1773 "clock rate (%ld) not supported\n", 1774 ref_rate); 1775 } 1776 1777 return 0; 1778} 1779 1780static const struct exynos5_usbdrd_phy_config phy_cfg_exynos2200[] = { 1781 { 1782 .id = EXYNOS5_DRDPHY_UTMI, 1783 .phy_isol = exynos5_usbdrd_phy_isol, 1784 .phy_init = exynos2200_usbdrd_utmi_init, 1785 }, 1786}; 1787 1788static int exynos5_usbdrd_orien_sw_set(struct typec_switch_dev *sw, 1789 enum typec_orientation orientation) 1790{ 1791 struct exynos5_usbdrd_phy *phy_drd = typec_switch_get_drvdata(sw); 1792 int ret; 1793 1794 ret = clk_bulk_prepare_enable(phy_drd->drv_data->n_clks, phy_drd->clks); 1795 if (ret) { 1796 dev_err(phy_drd->dev, "Failed to enable PHY clocks(s)\n"); 1797 return ret; 1798 } 1799 1800 scoped_guard(mutex, &phy_drd->phy_mutex) { 1801 void __iomem * const regs_base = phy_drd->reg_phy; 1802 unsigned int reg; 1803 1804 if (orientation == TYPEC_ORIENTATION_NONE) { 1805 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 1806 reg &= ~(UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID); 1807 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 1808 1809 reg = readl(regs_base + EXYNOS850_DRD_HSP); 1810 reg |= HSP_VBUSVLDEXTSEL; 1811 reg &= ~HSP_VBUSVLDEXT; 1812 writel(reg, regs_base + EXYNOS850_DRD_HSP); 1813 } else { 1814 reg = readl(regs_base + EXYNOS850_DRD_UTMI); 1815 reg |= UTMI_FORCE_VBUSVALID | UTMI_FORCE_BVALID; 1816 writel(reg, regs_base + EXYNOS850_DRD_UTMI); 1817 1818 reg = readl(regs_base + EXYNOS850_DRD_HSP); 1819 reg |= HSP_VBUSVLDEXTSEL | HSP_VBUSVLDEXT; 1820 writel(reg, regs_base + EXYNOS850_DRD_HSP); 1821 } 1822 1823 phy_drd->orientation = orientation; 1824 } 1825 1826 clk_bulk_disable_unprepare(phy_drd->drv_data->n_clks, phy_drd->clks); 1827 1828 return 0; 1829} 1830 1831static void exynos5_usbdrd_orien_switch_unregister(void *data) 1832{ 1833 struct exynos5_usbdrd_phy *phy_drd = data; 1834 1835 typec_switch_unregister(phy_drd->sw); 1836} 1837 1838static int exynos5_usbdrd_setup_notifiers(struct exynos5_usbdrd_phy *phy_drd) 1839{ 1840 int ret; 1841 1842 if (!IS_ENABLED(CONFIG_TYPEC)) 1843 return 0; 1844 1845 if (device_property_present(phy_drd->dev, "orientation-switch")) { 1846 struct typec_switch_desc sw_desc = { }; 1847 1848 sw_desc.drvdata = phy_drd; 1849 sw_desc.fwnode = dev_fwnode(phy_drd->dev); 1850 sw_desc.set = exynos5_usbdrd_orien_sw_set; 1851 1852 phy_drd->sw = typec_switch_register(phy_drd->dev, &sw_desc); 1853 if (IS_ERR(phy_drd->sw)) 1854 return dev_err_probe(phy_drd->dev, 1855 PTR_ERR(phy_drd->sw), 1856 "Failed to register TypeC orientation switch\n"); 1857 1858 ret = devm_add_action_or_reset(phy_drd->dev, 1859 exynos5_usbdrd_orien_switch_unregister, 1860 phy_drd); 1861 if (ret) 1862 return dev_err_probe(phy_drd->dev, ret, 1863 "Failed to register TypeC orientation devm action\n"); 1864 } 1865 1866 return 0; 1867} 1868 1869static const struct exynos5_usbdrd_phy_config phy_cfg_exynos5[] = { 1870 { 1871 .id = EXYNOS5_DRDPHY_UTMI, 1872 .phy_isol = exynos5_usbdrd_phy_isol, 1873 .phy_init = exynos5_usbdrd_utmi_init, 1874 .set_refclk = exynos5_usbdrd_utmi_set_refclk, 1875 }, 1876 { 1877 .id = EXYNOS5_DRDPHY_PIPE3, 1878 .phy_isol = exynos5_usbdrd_phy_isol, 1879 .phy_init = exynos5_usbdrd_pipe3_init, 1880 .set_refclk = exynos5_usbdrd_pipe3_set_refclk, 1881 }, 1882}; 1883 1884static const struct exynos5_usbdrd_phy_config phy_cfg_exynos7870[] = { 1885 { 1886 .id = EXYNOS5_DRDPHY_UTMI, 1887 .phy_isol = exynos7870_usbdrd_phy_isol, 1888 .phy_init = exynos7870_usbdrd_utmi_init, 1889 }, 1890}; 1891 1892static const struct exynos5_usbdrd_phy_config phy_cfg_exynos850[] = { 1893 { 1894 .id = EXYNOS5_DRDPHY_UTMI, 1895 .phy_isol = exynos5_usbdrd_phy_isol, 1896 .phy_init = exynos850_usbdrd_utmi_init, 1897 }, 1898}; 1899 1900static 1901const struct exynos5_usbdrd_phy_tuning exynos7870_tunes_utmi_postinit[] = { 1902 PHY_TUNING_ENTRY_PHY(EXYNOS5_DRD_PHYPARAM0, 1903 (PHYPARAM0_TXVREFTUNE | PHYPARAM0_TXRISETUNE | 1904 PHYPARAM0_TXRESTUNE | PHYPARAM0_TXPREEMPPULSETUNE | 1905 PHYPARAM0_TXPREEMPAMPTUNE | PHYPARAM0_TXHSXVTUNE | 1906 PHYPARAM0_TXFSLSTUNE | PHYPARAM0_SQRXTUNE | 1907 PHYPARAM0_OTGTUNE | PHYPARAM0_COMPDISTUNE), 1908 (FIELD_PREP_CONST(PHYPARAM0_TXVREFTUNE, 14) | 1909 FIELD_PREP_CONST(PHYPARAM0_TXRISETUNE, 1) | 1910 FIELD_PREP_CONST(PHYPARAM0_TXRESTUNE, 3) | 1911 FIELD_PREP_CONST(PHYPARAM0_TXPREEMPAMPTUNE, 0) | 1912 FIELD_PREP_CONST(PHYPARAM0_TXHSXVTUNE, 0) | 1913 FIELD_PREP_CONST(PHYPARAM0_TXFSLSTUNE, 3) | 1914 FIELD_PREP_CONST(PHYPARAM0_SQRXTUNE, 6) | 1915 FIELD_PREP_CONST(PHYPARAM0_OTGTUNE, 2) | 1916 FIELD_PREP_CONST(PHYPARAM0_COMPDISTUNE, 3))), 1917 PHY_TUNING_ENTRY_LAST 1918}; 1919 1920static const struct exynos5_usbdrd_phy_tuning *exynos7870_tunes[PTS_MAX] = { 1921 [PTS_UTMI_POSTINIT] = exynos7870_tunes_utmi_postinit, 1922}; 1923 1924static const char * const exynos5_clk_names[] = { 1925 "phy", 1926}; 1927 1928static const char * const exynos5_core_clk_names[] = { 1929 "ref", 1930}; 1931 1932static const char * const exynos5433_core_clk_names[] = { 1933 "ref", "phy_pipe", "phy_utmi", "itp", 1934}; 1935 1936static const char * const exynos5_regulator_names[] = { 1937 "vbus", "vbus-boost", 1938}; 1939 1940static const struct exynos5_usbdrd_phy_drvdata exynos2200_usb32drd_phy = { 1941 .phy_cfg = phy_cfg_exynos2200, 1942 .phy_ops = &exynos2200_usbdrd_phy_ops, 1943 .pmu_offset_usbdrd0_phy = EXYNOS2200_PHY_CTRL_USB20, 1944 .clk_names = exynos5_clk_names, 1945 .n_clks = ARRAY_SIZE(exynos5_clk_names), 1946 /* clocks and regulators are specific to the underlying PHY blocks */ 1947 .core_clk_names = NULL, 1948 .n_core_clks = 0, 1949 .regulator_names = NULL, 1950 .n_regulators = 0, 1951}; 1952 1953static const struct exynos5_usbdrd_phy_drvdata exynos5420_usbdrd_phy = { 1954 .phy_cfg = phy_cfg_exynos5, 1955 .phy_ops = &exynos5_usbdrd_phy_ops, 1956 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 1957 .pmu_offset_usbdrd1_phy = EXYNOS5420_USBDRD1_PHY_CONTROL, 1958 .clk_names = exynos5_clk_names, 1959 .n_clks = ARRAY_SIZE(exynos5_clk_names), 1960 .core_clk_names = exynos5_core_clk_names, 1961 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 1962 .regulator_names = exynos5_regulator_names, 1963 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 1964}; 1965 1966static const struct exynos5_usbdrd_phy_drvdata exynos5250_usbdrd_phy = { 1967 .phy_cfg = phy_cfg_exynos5, 1968 .phy_ops = &exynos5_usbdrd_phy_ops, 1969 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 1970 .clk_names = exynos5_clk_names, 1971 .n_clks = ARRAY_SIZE(exynos5_clk_names), 1972 .core_clk_names = exynos5_core_clk_names, 1973 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 1974 .regulator_names = exynos5_regulator_names, 1975 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 1976}; 1977 1978static const struct exynos5_usbdrd_phy_drvdata exynos5433_usbdrd_phy = { 1979 .phy_cfg = phy_cfg_exynos5, 1980 .phy_ops = &exynos5_usbdrd_phy_ops, 1981 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 1982 .pmu_offset_usbdrd1_phy = EXYNOS5433_USBHOST30_PHY_CONTROL, 1983 .clk_names = exynos5_clk_names, 1984 .n_clks = ARRAY_SIZE(exynos5_clk_names), 1985 .core_clk_names = exynos5433_core_clk_names, 1986 .n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names), 1987 .regulator_names = exynos5_regulator_names, 1988 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 1989}; 1990 1991static const struct exynos5_usbdrd_phy_drvdata exynos7_usbdrd_phy = { 1992 .phy_cfg = phy_cfg_exynos5, 1993 .phy_ops = &exynos5_usbdrd_phy_ops, 1994 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 1995 .clk_names = exynos5_clk_names, 1996 .n_clks = ARRAY_SIZE(exynos5_clk_names), 1997 .core_clk_names = exynos5433_core_clk_names, 1998 .n_core_clks = ARRAY_SIZE(exynos5433_core_clk_names), 1999 .regulator_names = exynos5_regulator_names, 2000 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 2001}; 2002 2003static const struct exynos5_usbdrd_phy_drvdata exynos7870_usbdrd_phy = { 2004 .phy_cfg = phy_cfg_exynos7870, 2005 .phy_tunes = exynos7870_tunes, 2006 .phy_ops = &exynos7870_usbdrd_phy_ops, 2007 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 2008 .clk_names = exynos5_clk_names, 2009 .n_clks = ARRAY_SIZE(exynos5_clk_names), 2010 .core_clk_names = exynos5_core_clk_names, 2011 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 2012 .regulator_names = exynos5_regulator_names, 2013 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 2014}; 2015 2016static const struct exynos5_usbdrd_phy_drvdata exynos850_usbdrd_phy = { 2017 .phy_cfg = phy_cfg_exynos850, 2018 .phy_ops = &exynos850_usbdrd_phy_ops, 2019 .pmu_offset_usbdrd0_phy = EXYNOS5_USBDRD_PHY_CONTROL, 2020 .clk_names = exynos5_clk_names, 2021 .n_clks = ARRAY_SIZE(exynos5_clk_names), 2022 .core_clk_names = exynos5_core_clk_names, 2023 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 2024 .regulator_names = exynos5_regulator_names, 2025 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 2026}; 2027 2028static const struct exynos5_usbdrd_phy_tuning exynos990_tunes_utmi_postinit[] = { 2029 PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON, 2030 (HSPPARACON_TXVREF | 2031 HSPPARACON_TXPREEMPAMP | HSPPARACON_SQRX | 2032 HSPPARACON_COMPDIS), 2033 (FIELD_PREP_CONST(HSPPARACON_TXVREF, 7) | 2034 FIELD_PREP_CONST(HSPPARACON_TXPREEMPAMP, 3) | 2035 FIELD_PREP_CONST(HSPPARACON_SQRX, 5) | 2036 FIELD_PREP_CONST(HSPPARACON_COMPDIS, 7))), 2037 PHY_TUNING_ENTRY_LAST 2038}; 2039 2040static const struct exynos5_usbdrd_phy_tuning *exynos990_tunes[PTS_MAX] = { 2041 [PTS_UTMI_POSTINIT] = exynos990_tunes_utmi_postinit, 2042}; 2043 2044static const struct exynos5_usbdrd_phy_drvdata exynos990_usbdrd_phy = { 2045 .phy_cfg = phy_cfg_exynos850, 2046 .phy_ops = &exynos850_usbdrd_phy_ops, 2047 .phy_tunes = exynos990_tunes, 2048 .pmu_offset_usbdrd0_phy = EXYNOS990_PHY_CTRL_USB20, 2049 .clk_names = exynos5_clk_names, 2050 .n_clks = ARRAY_SIZE(exynos5_clk_names), 2051 .core_clk_names = exynos5_core_clk_names, 2052 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 2053 .regulator_names = exynos5_regulator_names, 2054 .n_regulators = ARRAY_SIZE(exynos5_regulator_names), 2055}; 2056 2057static const struct exynos5_usbdrd_phy_config phy_cfg_gs101[] = { 2058 { 2059 .id = EXYNOS5_DRDPHY_UTMI, 2060 .phy_isol = exynos5_usbdrd_phy_isol, 2061 .phy_init = exynos850_usbdrd_utmi_init, 2062 }, 2063 { 2064 .id = EXYNOS5_DRDPHY_PIPE3, 2065 .phy_isol = exynos5_usbdrd_phy_isol, 2066 .phy_init = exynos5_usbdrd_gs101_pipe3_init, 2067 }, 2068}; 2069 2070static const struct exynos5_usbdrd_phy_tuning gs101_tunes_utmi_postinit[] = { 2071 PHY_TUNING_ENTRY_PHY(EXYNOS850_DRD_HSPPARACON, 2072 (HSPPARACON_TXVREF | HSPPARACON_TXRES | 2073 HSPPARACON_TXPREEMPAMP | HSPPARACON_SQRX | 2074 HSPPARACON_COMPDIS), 2075 (FIELD_PREP_CONST(HSPPARACON_TXVREF, 6) | 2076 FIELD_PREP_CONST(HSPPARACON_TXRES, 1) | 2077 FIELD_PREP_CONST(HSPPARACON_TXPREEMPAMP, 3) | 2078 FIELD_PREP_CONST(HSPPARACON_SQRX, 5) | 2079 FIELD_PREP_CONST(HSPPARACON_COMPDIS, 7))), 2080 PHY_TUNING_ENTRY_LAST 2081}; 2082 2083static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_preinit[] = { 2084 /* preinit */ 2085 /* CDR data mode exit GEN1 ON / GEN2 OFF */ 2086 PHY_TUNING_ENTRY_PMA(0x0c8c, -1, 0xff), 2087 PHY_TUNING_ENTRY_PMA(0x1c8c, -1, 0xff), 2088 PHY_TUNING_ENTRY_PMA(0x0c9c, -1, 0x7d), 2089 PHY_TUNING_ENTRY_PMA(0x1c9c, -1, 0x7d), 2090 /* improve EDS distribution */ 2091 PHY_TUNING_ENTRY_PMA(0x0e7c, -1, 0x06), 2092 PHY_TUNING_ENTRY_PMA(0x09e0, -1, 0x00), 2093 PHY_TUNING_ENTRY_PMA(0x09e4, -1, 0x36), 2094 PHY_TUNING_ENTRY_PMA(0x1e7c, -1, 0x06), 2095 PHY_TUNING_ENTRY_PMA(0x19e0, -1, 0x00), 2096 PHY_TUNING_ENTRY_PMA(0x19e4, -1, 0x36), 2097 /* fix bootloader bug */ 2098 PHY_TUNING_ENTRY_PMA(0x1e90, -1, 0x02), 2099 PHY_TUNING_ENTRY_PMA(0x1e94, -1, 0x0b), 2100 /* improve LVCC */ 2101 PHY_TUNING_ENTRY_PMA(0x08f0, -1, 0x30), 2102 PHY_TUNING_ENTRY_PMA(0x18f0, -1, 0x30), 2103 /* LFPS RX VIH shmoo hole */ 2104 PHY_TUNING_ENTRY_PMA(0x0a08, -1, 0x0c), 2105 PHY_TUNING_ENTRY_PMA(0x1a08, -1, 0x0c), 2106 /* remove unrelated option for v4 phy */ 2107 PHY_TUNING_ENTRY_PMA(0x0a0c, -1, 0x05), 2108 PHY_TUNING_ENTRY_PMA(0x1a0c, -1, 0x05), 2109 /* improve Gen2 LVCC */ 2110 PHY_TUNING_ENTRY_PMA(0x00f8, -1, 0x1c), 2111 PHY_TUNING_ENTRY_PMA(0x00fc, -1, 0x54), 2112 /* Change Vth of RCV_DET because of TD 7.40 Polling Retry Test */ 2113 PHY_TUNING_ENTRY_PMA(0x104c, -1, 0x07), 2114 PHY_TUNING_ENTRY_PMA(0x204c, -1, 0x07), 2115 /* reduce Ux Exit time, assuming 26MHz clock */ 2116 /* Gen1 */ 2117 PHY_TUNING_ENTRY_PMA(0x0ca8, -1, 0x00), 2118 PHY_TUNING_ENTRY_PMA(0x0cac, -1, 0x04), 2119 PHY_TUNING_ENTRY_PMA(0x1ca8, -1, 0x00), 2120 PHY_TUNING_ENTRY_PMA(0x1cac, -1, 0x04), 2121 /* Gen2 */ 2122 PHY_TUNING_ENTRY_PMA(0x0cb8, -1, 0x00), 2123 PHY_TUNING_ENTRY_PMA(0x0cbc, -1, 0x04), 2124 PHY_TUNING_ENTRY_PMA(0x1cb8, -1, 0x00), 2125 PHY_TUNING_ENTRY_PMA(0x1cbc, -1, 0x04), 2126 /* RX impedance setting */ 2127 PHY_TUNING_ENTRY_PMA(0x0bb0, 0x03, 0x01), 2128 PHY_TUNING_ENTRY_PMA(0x0bb4, 0xf0, 0xa0), 2129 PHY_TUNING_ENTRY_PMA(0x1bb0, 0x03, 0x01), 2130 PHY_TUNING_ENTRY_PMA(0x1bb4, 0xf0, 0xa0), 2131 2132 PHY_TUNING_ENTRY_LAST 2133}; 2134 2135static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_init[] = { 2136 /* init */ 2137 /* abnormal common pattern mask */ 2138 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_BACK_END_MODE_VEC, 2139 BACK_END_MODE_VEC_DISABLE_DATA_MASK, 0), 2140 /* de-serializer enabled when U2 */ 2141 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_2, PCS_OUT_VEC_B4_DYNAMIC, 2142 PCS_OUT_VEC_B4_SEL_OUT), 2143 /* TX Keeper Disable, Squelch on when U3 */ 2144 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_3, PCS_OUT_VEC_B7_DYNAMIC, 2145 PCS_OUT_VEC_B7_SEL_OUT | PCS_OUT_VEC_B2_SEL_OUT), 2146 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS1_N1, -1, 2147 (FIELD_PREP_CONST(NS_VEC_NS_REQ, 5) | 2148 NS_VEC_ENABLE_TIMER | 2149 FIELD_PREP_CONST(NS_VEC_SEL_TIMEOUT, 3))), 2150 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS2_N0, -1, 2151 (FIELD_PREP_CONST(NS_VEC_NS_REQ, 1) | 2152 NS_VEC_ENABLE_TIMER | 2153 FIELD_PREP_CONST(NS_VEC_SEL_TIMEOUT, 3) | 2154 FIELD_PREP_CONST(NS_VEC_COND_MASK, 2) | 2155 FIELD_PREP_CONST(NS_VEC_EXP_COND, 2))), 2156 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_NS_VEC_PS3_N0, -1, 2157 (FIELD_PREP_CONST(NS_VEC_NS_REQ, 1) | 2158 NS_VEC_ENABLE_TIMER | 2159 FIELD_PREP_CONST(NS_VEC_SEL_TIMEOUT, 3) | 2160 FIELD_PREP_CONST(NS_VEC_COND_MASK, 7) | 2161 FIELD_PREP_CONST(NS_VEC_EXP_COND, 7))), 2162 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_0, -1, 112), 2163 /* Block Aligner Type B */ 2164 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL, 0, 2165 RX_CONTROL_EN_BLOCK_ALIGNER_TYPE_B), 2166 /* Block align at TS1/TS2 for Gen2 stability (Gen2 only) */ 2167 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_RX_CONTROL_DEBUG, 2168 RX_CONTROL_DEBUG_NUM_COM_FOUND, 2169 (RX_CONTROL_DEBUG_EN_TS_CHECK | 2170 /* 2171 * increase pcs ts1 adding packet-cnt 1 --> 4 2172 * lnx_rx_valid_rstn_delay_rise_sp/ssp : 2173 * 19.6us(0x200) -> 15.3us(0x4) 2174 */ 2175 FIELD_PREP_CONST(RX_CONTROL_DEBUG_NUM_COM_FOUND, 4))), 2176 /* Gen1 Tx DRIVER pre-shoot, de-emphasis, level ctrl */ 2177 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_HS_TX_COEF_MAP_0, 2178 (HS_TX_COEF_MAP_0_SSTX_DEEMP | HS_TX_COEF_MAP_0_SSTX_LEVEL | 2179 HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT), 2180 (FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_DEEMP, 8) | 2181 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_LEVEL, 0xb) | 2182 FIELD_PREP_CONST(HS_TX_COEF_MAP_0_SSTX_PRE_SHOOT, 0))), 2183 /* Gen2 Tx DRIVER level ctrl */ 2184 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_LOCAL_COEF, 2185 LOCAL_COEF_PMA_CENTER_COEF, 2186 FIELD_PREP_CONST(LOCAL_COEF_PMA_CENTER_COEF, 0xb)), 2187 /* Gen2 U1 exit LFPS duration : 900ns ~ 1.2us */ 2188 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_TIMEOUT_3, -1, 4096), 2189 /* set skp_remove_th 0x2 -> 0x7 for avoiding retry problem. */ 2190 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_EBUF_PARAM, 2191 EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE, 2192 FIELD_PREP_CONST(EBUF_PARAM_SKP_REMOVE_TH_EMPTY_MODE, 0x7)), 2193 2194 PHY_TUNING_ENTRY_LAST 2195}; 2196 2197static const struct exynos5_usbdrd_phy_tuning gs101_tunes_pipe3_postlock[] = { 2198 /* Squelch off when U3 */ 2199 PHY_TUNING_ENTRY_PCS(EXYNOS9_PCS_OUT_VEC_3, PCS_OUT_VEC_B2_SEL_OUT, 0), 2200 2201 PHY_TUNING_ENTRY_LAST 2202}; 2203 2204static const struct exynos5_usbdrd_phy_tuning *gs101_tunes[PTS_MAX] = { 2205 [PTS_UTMI_POSTINIT] = gs101_tunes_utmi_postinit, 2206 [PTS_PIPE3_PREINIT] = gs101_tunes_pipe3_preinit, 2207 [PTS_PIPE3_INIT] = gs101_tunes_pipe3_init, 2208 [PTS_PIPE3_POSTLOCK] = gs101_tunes_pipe3_postlock, 2209}; 2210 2211static const char * const gs101_clk_names[] = { 2212 "phy", "ctrl_aclk", "ctrl_pclk", "scl_pclk", 2213}; 2214 2215static const char * const gs101_regulator_names[] = { 2216 "pll", 2217 "dvdd-usb20", "vddh-usb20", "vdd33-usb20", 2218 "vdda-usbdp", "vddh-usbdp", 2219}; 2220 2221static const struct exynos5_usbdrd_phy_drvdata gs101_usbd31rd_phy = { 2222 .phy_cfg = phy_cfg_gs101, 2223 .phy_tunes = gs101_tunes, 2224 .phy_ops = &gs101_usbdrd_phy_ops, 2225 .pmu_offset_usbdrd0_phy = GS101_PHY_CTRL_USB20, 2226 .pmu_offset_usbdrd0_phy_ss = GS101_PHY_CTRL_USBDP, 2227 .clk_names = gs101_clk_names, 2228 .n_clks = ARRAY_SIZE(gs101_clk_names), 2229 .core_clk_names = exynos5_core_clk_names, 2230 .n_core_clks = ARRAY_SIZE(exynos5_core_clk_names), 2231 .regulator_names = gs101_regulator_names, 2232 .n_regulators = ARRAY_SIZE(gs101_regulator_names), 2233}; 2234 2235static const struct of_device_id exynos5_usbdrd_phy_of_match[] = { 2236 { 2237 .compatible = "google,gs101-usb31drd-phy", 2238 .data = &gs101_usbd31rd_phy 2239 }, { 2240 .compatible = "samsung,exynos2200-usb32drd-phy", 2241 .data = &exynos2200_usb32drd_phy, 2242 }, { 2243 .compatible = "samsung,exynos5250-usbdrd-phy", 2244 .data = &exynos5250_usbdrd_phy 2245 }, { 2246 .compatible = "samsung,exynos5420-usbdrd-phy", 2247 .data = &exynos5420_usbdrd_phy 2248 }, { 2249 .compatible = "samsung,exynos5433-usbdrd-phy", 2250 .data = &exynos5433_usbdrd_phy 2251 }, { 2252 .compatible = "samsung,exynos7-usbdrd-phy", 2253 .data = &exynos7_usbdrd_phy 2254 }, { 2255 .compatible = "samsung,exynos7870-usbdrd-phy", 2256 .data = &exynos7870_usbdrd_phy 2257 }, { 2258 .compatible = "samsung,exynos850-usbdrd-phy", 2259 .data = &exynos850_usbdrd_phy 2260 }, { 2261 .compatible = "samsung,exynos990-usbdrd-phy", 2262 .data = &exynos990_usbdrd_phy 2263 }, 2264 { }, 2265}; 2266MODULE_DEVICE_TABLE(of, exynos5_usbdrd_phy_of_match); 2267 2268static int exynos5_usbdrd_phy_probe(struct platform_device *pdev) 2269{ 2270 struct device *dev = &pdev->dev; 2271 struct device_node *node = dev->of_node; 2272 struct exynos5_usbdrd_phy *phy_drd; 2273 struct phy_provider *phy_provider; 2274 const struct exynos5_usbdrd_phy_drvdata *drv_data; 2275 struct regmap *reg_pmu; 2276 u32 pmu_offset; 2277 int i, ret; 2278 int channel; 2279 2280 phy_drd = devm_kzalloc(dev, sizeof(*phy_drd), GFP_KERNEL); 2281 if (!phy_drd) 2282 return -ENOMEM; 2283 2284 dev_set_drvdata(dev, phy_drd); 2285 phy_drd->dev = dev; 2286 2287 drv_data = of_device_get_match_data(dev); 2288 if (!drv_data) 2289 return -EINVAL; 2290 phy_drd->drv_data = drv_data; 2291 2292 ret = devm_mutex_init(dev, &phy_drd->phy_mutex); 2293 if (ret) 2294 return ret; 2295 2296 if (of_property_present(dev->of_node, "reg-names")) { 2297 void __iomem *reg; 2298 2299 reg = devm_platform_ioremap_resource_byname(pdev, "phy"); 2300 if (IS_ERR(reg)) 2301 return PTR_ERR(reg); 2302 phy_drd->reg_phy = reg; 2303 2304 reg = devm_platform_ioremap_resource_byname(pdev, "pcs"); 2305 if (IS_ERR(reg)) 2306 return PTR_ERR(reg); 2307 phy_drd->reg_pcs = reg; 2308 2309 reg = devm_platform_ioremap_resource_byname(pdev, "pma"); 2310 if (IS_ERR(reg)) 2311 return PTR_ERR(reg); 2312 phy_drd->reg_pma = reg; 2313 } else { 2314 /* DTB with just a single region */ 2315 phy_drd->reg_phy = devm_platform_ioremap_resource(pdev, 0); 2316 if (IS_ERR(phy_drd->reg_phy)) 2317 return PTR_ERR(phy_drd->reg_phy); 2318 } 2319 2320 /* 2321 * USB32DRD 4nm controller implements Synopsys eUSB2.0 PHY 2322 * and Synopsys SS/USBDP COMBOPHY, managed by external code. 2323 */ 2324 if (of_property_present(dev->of_node, "phy-names")) { 2325 phy_drd->hs_phy = devm_of_phy_get(dev, dev->of_node, "hs"); 2326 if (IS_ERR(phy_drd->hs_phy)) 2327 return dev_err_probe(dev, PTR_ERR(phy_drd->hs_phy), 2328 "failed to get hs_phy\n"); 2329 } 2330 2331 ret = exynos5_usbdrd_phy_clk_handle(phy_drd); 2332 if (ret) 2333 return ret; 2334 2335 reg_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, 2336 "samsung,pmu-syscon"); 2337 if (IS_ERR(reg_pmu)) 2338 return dev_err_probe(dev, PTR_ERR(reg_pmu), 2339 "Failed to lookup PMU regmap\n"); 2340 2341 /* 2342 * Exynos5420 SoC has multiple channels for USB 3.0 PHY, with 2343 * each having separate power control registers. 2344 * 'channel' facilitates to set such registers. 2345 */ 2346 channel = of_alias_get_id(node, "usbdrdphy"); 2347 if (channel < 0) 2348 dev_dbg(dev, "Not a multi-controller usbdrd phy\n"); 2349 2350 /* Get regulators */ 2351 phy_drd->regulators = devm_kcalloc(dev, 2352 drv_data->n_regulators, 2353 sizeof(*phy_drd->regulators), 2354 GFP_KERNEL); 2355 if (!phy_drd->regulators) 2356 return -ENOMEM; 2357 regulator_bulk_set_supply_names(phy_drd->regulators, 2358 drv_data->regulator_names, 2359 drv_data->n_regulators); 2360 ret = devm_regulator_bulk_get(dev, drv_data->n_regulators, 2361 phy_drd->regulators); 2362 if (ret) 2363 return dev_err_probe(dev, ret, "failed to get regulators\n"); 2364 2365 ret = exynos5_usbdrd_setup_notifiers(phy_drd); 2366 if (ret) 2367 return ret; 2368 2369 dev_vdbg(dev, "Creating usbdrd_phy phy\n"); 2370 2371 for (i = 0; i < EXYNOS5_DRDPHYS_NUM; i++) { 2372 struct phy *phy = devm_phy_create(dev, NULL, drv_data->phy_ops); 2373 2374 if (IS_ERR(phy)) 2375 return dev_err_probe(dev, PTR_ERR(phy), 2376 "Failed to create usbdrd_phy phy\n"); 2377 2378 phy_drd->phys[i].phy = phy; 2379 phy_drd->phys[i].index = i; 2380 phy_drd->phys[i].reg_pmu = reg_pmu; 2381 switch (channel) { 2382 case 1: 2383 pmu_offset = drv_data->pmu_offset_usbdrd1_phy; 2384 break; 2385 case 0: 2386 default: 2387 pmu_offset = drv_data->pmu_offset_usbdrd0_phy; 2388 if (i == EXYNOS5_DRDPHY_PIPE3 && drv_data 2389 ->pmu_offset_usbdrd0_phy_ss) 2390 pmu_offset = drv_data->pmu_offset_usbdrd0_phy_ss; 2391 break; 2392 } 2393 phy_drd->phys[i].pmu_offset = pmu_offset; 2394 phy_drd->phys[i].phy_cfg = &drv_data->phy_cfg[i]; 2395 phy_set_drvdata(phy, &phy_drd->phys[i]); 2396 } 2397 2398 phy_provider = devm_of_phy_provider_register(dev, 2399 exynos5_usbdrd_phy_xlate); 2400 if (IS_ERR(phy_provider)) 2401 return dev_err_probe(phy_drd->dev, PTR_ERR(phy_provider), 2402 "Failed to register phy provider\n"); 2403 2404 return 0; 2405} 2406 2407static struct platform_driver exynos5_usb3drd_phy = { 2408 .probe = exynos5_usbdrd_phy_probe, 2409 .driver = { 2410 .of_match_table = exynos5_usbdrd_phy_of_match, 2411 .name = "exynos5_usb3drd_phy", 2412 .suppress_bind_attrs = true, 2413 } 2414}; 2415 2416module_platform_driver(exynos5_usb3drd_phy); 2417MODULE_DESCRIPTION("Samsung Exynos5 SoCs USB 3.0 DRD controller PHY driver"); 2418MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>"); 2419MODULE_LICENSE("GPL v2");
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