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phy-rockchip-usbdp.c
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linux-6.19.14/drivers/phy/rockchip/phy-rockchip-usbdp.c
1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Rockchip USBDP Combo PHY with Samsung IP block driver 4 * 5 * Copyright (C) 2021-2024 Rockchip Electronics Co., Ltd 6 * Copyright (C) 2024 Collabora Ltd 7 */ 8 9#include <dt-bindings/phy/phy.h> 10#include <linux/bitfield.h> 11#include <linux/bits.h> 12#include <linux/clk.h> 13#include <linux/delay.h> 14#include <linux/gpio.h> 15#include <linux/mfd/syscon.h> 16#include <linux/mod_devicetable.h> 17#include <linux/module.h> 18#include <linux/mutex.h> 19#include <linux/phy/phy.h> 20#include <linux/platform_device.h> 21#include <linux/property.h> 22#include <linux/regmap.h> 23#include <linux/reset.h> 24#include <linux/usb/ch9.h> 25#include <linux/usb/typec_dp.h> 26#include <linux/usb/typec_mux.h> 27 28/* USBDP PHY Register Definitions */ 29#define UDPHY_PCS 0x4000 30#define UDPHY_PMA 0x8000 31 32/* VO0 GRF Registers */ 33#define DP_SINK_HPD_CFG BIT(11) 34#define DP_SINK_HPD_SEL BIT(10) 35#define DP_AUX_DIN_SEL BIT(9) 36#define DP_AUX_DOUT_SEL BIT(8) 37#define DP_LANE_SEL_N(n) GENMASK(2 * (n) + 1, 2 * (n)) 38#define DP_LANE_SEL_ALL GENMASK(7, 0) 39 40/* PMA CMN Registers */ 41#define CMN_LANE_MUX_AND_EN_OFFSET 0x0288 /* cmn_reg00A2 */ 42#define CMN_DP_LANE_MUX_N(n) BIT((n) + 4) 43#define CMN_DP_LANE_EN_N(n) BIT(n) 44#define CMN_DP_LANE_MUX_ALL GENMASK(7, 4) 45#define CMN_DP_LANE_EN_ALL GENMASK(3, 0) 46 47#define CMN_DP_LINK_OFFSET 0x28c /* cmn_reg00A3 */ 48#define CMN_DP_TX_LINK_BW GENMASK(6, 5) 49#define CMN_DP_TX_LANE_SWAP_EN BIT(2) 50 51#define CMN_SSC_EN_OFFSET 0x2d0 /* cmn_reg00B4 */ 52#define CMN_ROPLL_SSC_EN BIT(1) 53#define CMN_LCPLL_SSC_EN BIT(0) 54 55#define CMN_ANA_LCPLL_DONE_OFFSET 0x0350 /* cmn_reg00D4 */ 56#define CMN_ANA_LCPLL_LOCK_DONE BIT(7) 57#define CMN_ANA_LCPLL_AFC_DONE BIT(6) 58 59#define CMN_ANA_ROPLL_DONE_OFFSET 0x0354 /* cmn_reg00D5 */ 60#define CMN_ANA_ROPLL_LOCK_DONE BIT(1) 61#define CMN_ANA_ROPLL_AFC_DONE BIT(0) 62 63#define CMN_DP_RSTN_OFFSET 0x038c /* cmn_reg00E3 */ 64#define CMN_DP_INIT_RSTN BIT(3) 65#define CMN_DP_CMN_RSTN BIT(2) 66#define CMN_CDR_WTCHDG_EN BIT(1) 67#define CMN_CDR_WTCHDG_MSK_CDR_EN BIT(0) 68 69#define TRSV_ANA_TX_CLK_OFFSET_N(n) (0x854 + (n) * 0x800) /* trsv_reg0215 */ 70#define LN_ANA_TX_SER_TXCLK_INV BIT(1) 71 72#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET 0x0b84 /* trsv_reg02E1 */ 73#define TRSV_LN0_MON_RX_CDR_LOCK_DONE BIT(0) 74 75#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET 0x1b84 /* trsv_reg06E1 */ 76#define TRSV_LN2_MON_RX_CDR_LOCK_DONE BIT(0) 77 78#define BIT_WRITEABLE_SHIFT 16 79#define PHY_AUX_DP_DATA_POL_NORMAL 0 80#define PHY_AUX_DP_DATA_POL_INVERT 1 81#define PHY_LANE_MUX_USB 0 82#define PHY_LANE_MUX_DP 1 83 84enum { 85 DP_BW_RBR, 86 DP_BW_HBR, 87 DP_BW_HBR2, 88 DP_BW_HBR3, 89}; 90 91enum { 92 UDPHY_MODE_NONE = 0, 93 UDPHY_MODE_USB = BIT(0), 94 UDPHY_MODE_DP = BIT(1), 95 UDPHY_MODE_DP_USB = BIT(1) | BIT(0), 96}; 97 98struct rk_udphy_grf_reg { 99 unsigned int offset; 100 unsigned int disable; 101 unsigned int enable; 102}; 103 104#define _RK_UDPHY_GEN_GRF_REG(offset, mask, disable, enable) \ 105{\ 106 offset, \ 107 FIELD_PREP_CONST(mask, disable) | (mask << BIT_WRITEABLE_SHIFT), \ 108 FIELD_PREP_CONST(mask, enable) | (mask << BIT_WRITEABLE_SHIFT), \ 109} 110 111#define RK_UDPHY_GEN_GRF_REG(offset, bitend, bitstart, disable, enable) \ 112 _RK_UDPHY_GEN_GRF_REG(offset, GENMASK(bitend, bitstart), disable, enable) 113 114struct rk_udphy_grf_cfg { 115 /* u2phy-grf */ 116 struct rk_udphy_grf_reg bvalid_phy_con; 117 struct rk_udphy_grf_reg bvalid_grf_con; 118 119 /* usb-grf */ 120 struct rk_udphy_grf_reg usb3otg0_cfg; 121 struct rk_udphy_grf_reg usb3otg1_cfg; 122 123 /* usbdpphy-grf */ 124 struct rk_udphy_grf_reg low_pwrn; 125 struct rk_udphy_grf_reg rx_lfps; 126}; 127 128struct rk_udphy_vogrf_cfg { 129 /* vo-grf */ 130 struct rk_udphy_grf_reg hpd_trigger; 131 u32 dp_lane_reg; 132}; 133 134struct rk_udphy_dp_tx_drv_ctrl { 135 u32 trsv_reg0204; 136 u32 trsv_reg0205; 137 u32 trsv_reg0206; 138 u32 trsv_reg0207; 139}; 140 141struct rk_udphy_cfg { 142 unsigned int num_phys; 143 unsigned int phy_ids[2]; 144 /* resets to be requested */ 145 const char * const *rst_list; 146 int num_rsts; 147 148 struct rk_udphy_grf_cfg grfcfg; 149 struct rk_udphy_vogrf_cfg vogrfcfg[2]; 150 const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4]; 151 const struct rk_udphy_dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4]; 152}; 153 154struct rk_udphy { 155 struct device *dev; 156 struct regmap *pma_regmap; 157 struct regmap *u2phygrf; 158 struct regmap *udphygrf; 159 struct regmap *usbgrf; 160 struct regmap *vogrf; 161 struct typec_switch_dev *sw; 162 struct typec_mux_dev *mux; 163 struct mutex mutex; /* mutex to protect access to individual PHYs */ 164 165 /* clocks and rests */ 166 int num_clks; 167 struct clk_bulk_data *clks; 168 struct clk *refclk; 169 int num_rsts; 170 struct reset_control_bulk_data *rsts; 171 172 /* PHY status management */ 173 bool flip; 174 bool mode_change; 175 u8 mode; 176 u8 status; 177 178 /* utilized for USB */ 179 bool hs; /* flag for high-speed */ 180 181 /* utilized for DP */ 182 struct gpio_desc *sbu1_dc_gpio; 183 struct gpio_desc *sbu2_dc_gpio; 184 u32 lane_mux_sel[4]; 185 u32 dp_lane_sel[4]; 186 u32 dp_aux_dout_sel; 187 u32 dp_aux_din_sel; 188 bool dp_sink_hpd_sel; 189 bool dp_sink_hpd_cfg; 190 unsigned int link_rate; 191 unsigned int lanes; 192 u8 bw; 193 int id; 194 195 bool dp_in_use; 196 197 /* PHY const config */ 198 const struct rk_udphy_cfg *cfgs; 199 200 /* PHY devices */ 201 struct phy *phy_dp; 202 struct phy *phy_u3; 203}; 204 205static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = { 206 /* voltage swing 0, pre-emphasis 0->3 */ 207 { 208 { 0x20, 0x10, 0x42, 0xe5 }, 209 { 0x26, 0x14, 0x42, 0xe5 }, 210 { 0x29, 0x18, 0x42, 0xe5 }, 211 { 0x2b, 0x1c, 0x43, 0xe7 }, 212 }, 213 214 /* voltage swing 1, pre-emphasis 0->2 */ 215 { 216 { 0x23, 0x10, 0x42, 0xe7 }, 217 { 0x2a, 0x17, 0x43, 0xe7 }, 218 { 0x2b, 0x1a, 0x43, 0xe7 }, 219 }, 220 221 /* voltage swing 2, pre-emphasis 0->1 */ 222 { 223 { 0x27, 0x10, 0x42, 0xe7 }, 224 { 0x2b, 0x17, 0x43, 0xe7 }, 225 }, 226 227 /* voltage swing 3, pre-emphasis 0 */ 228 { 229 { 0x29, 0x10, 0x43, 0xe7 }, 230 }, 231}; 232 233static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = { 234 /* voltage swing 0, pre-emphasis 0->3 */ 235 { 236 { 0x20, 0x10, 0x42, 0xe5 }, 237 { 0x26, 0x14, 0x42, 0xe5 }, 238 { 0x29, 0x18, 0x42, 0xe5 }, 239 { 0x2b, 0x1c, 0x43, 0xe7 }, 240 }, 241 242 /* voltage swing 1, pre-emphasis 0->2 */ 243 { 244 { 0x23, 0x10, 0x42, 0xe7 }, 245 { 0x2a, 0x17, 0x43, 0xe7 }, 246 { 0x2b, 0x1a, 0x43, 0xe7 }, 247 }, 248 249 /* voltage swing 2, pre-emphasis 0->1 */ 250 { 251 { 0x27, 0x10, 0x43, 0x67 }, 252 { 0x2b, 0x17, 0x43, 0xe7 }, 253 }, 254 255 /* voltage swing 3, pre-emphasis 0 */ 256 { 257 { 0x29, 0x10, 0x43, 0xe7 }, 258 }, 259}; 260 261static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = { 262 /* voltage swing 0, pre-emphasis 0->3 */ 263 { 264 { 0x21, 0x10, 0x42, 0xe5 }, 265 { 0x26, 0x14, 0x42, 0xe5 }, 266 { 0x26, 0x16, 0x43, 0xe5 }, 267 { 0x2a, 0x19, 0x43, 0xe7 }, 268 }, 269 270 /* voltage swing 1, pre-emphasis 0->2 */ 271 { 272 { 0x24, 0x10, 0x42, 0xe7 }, 273 { 0x2a, 0x17, 0x43, 0xe7 }, 274 { 0x2b, 0x1a, 0x43, 0xe7 }, 275 }, 276 277 /* voltage swing 2, pre-emphasis 0->1 */ 278 { 279 { 0x28, 0x10, 0x42, 0xe7 }, 280 { 0x2b, 0x17, 0x43, 0xe7 }, 281 }, 282 283 /* voltage swing 3, pre-emphasis 0 */ 284 { 285 { 0x28, 0x10, 0x43, 0xe7 }, 286 }, 287}; 288 289static const struct rk_udphy_dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = { 290 /* voltage swing 0, pre-emphasis 0->3 */ 291 { 292 { 0x21, 0x10, 0x42, 0xe5 }, 293 { 0x26, 0x14, 0x42, 0xe5 }, 294 { 0x26, 0x16, 0x43, 0xe5 }, 295 { 0x29, 0x18, 0x43, 0xe7 }, 296 }, 297 298 /* voltage swing 1, pre-emphasis 0->2 */ 299 { 300 { 0x24, 0x10, 0x42, 0xe7 }, 301 { 0x2a, 0x18, 0x43, 0xe7 }, 302 { 0x2b, 0x1b, 0x43, 0xe7 } 303 }, 304 305 /* voltage swing 2, pre-emphasis 0->1 */ 306 { 307 { 0x27, 0x10, 0x42, 0xe7 }, 308 { 0x2b, 0x18, 0x43, 0xe7 } 309 }, 310 311 /* voltage swing 3, pre-emphasis 0 */ 312 { 313 { 0x28, 0x10, 0x43, 0xe7 }, 314 }, 315}; 316 317static const struct reg_sequence rk_udphy_24m_refclk_cfg[] = { 318 {0x0090, 0x68}, {0x0094, 0x68}, 319 {0x0128, 0x24}, {0x012c, 0x44}, 320 {0x0130, 0x3f}, {0x0134, 0x44}, 321 {0x015c, 0xa9}, {0x0160, 0x71}, 322 {0x0164, 0x71}, {0x0168, 0xa9}, 323 {0x0174, 0xa9}, {0x0178, 0x71}, 324 {0x017c, 0x71}, {0x0180, 0xa9}, 325 {0x018c, 0x41}, {0x0190, 0x00}, 326 {0x0194, 0x05}, {0x01ac, 0x2a}, 327 {0x01b0, 0x17}, {0x01b4, 0x17}, 328 {0x01b8, 0x2a}, {0x01c8, 0x04}, 329 {0x01cc, 0x08}, {0x01d0, 0x08}, 330 {0x01d4, 0x04}, {0x01d8, 0x20}, 331 {0x01dc, 0x01}, {0x01e0, 0x09}, 332 {0x01e4, 0x03}, {0x01f0, 0x29}, 333 {0x01f4, 0x02}, {0x01f8, 0x02}, 334 {0x01fc, 0x29}, {0x0208, 0x2a}, 335 {0x020c, 0x17}, {0x0210, 0x17}, 336 {0x0214, 0x2a}, {0x0224, 0x20}, 337 {0x03f0, 0x0a}, {0x03f4, 0x07}, 338 {0x03f8, 0x07}, {0x03fc, 0x0c}, 339 {0x0404, 0x12}, {0x0408, 0x1a}, 340 {0x040c, 0x1a}, {0x0410, 0x3f}, 341 {0x0ce0, 0x68}, {0x0ce8, 0xd0}, 342 {0x0cf0, 0x87}, {0x0cf8, 0x70}, 343 {0x0d00, 0x70}, {0x0d08, 0xa9}, 344 {0x1ce0, 0x68}, {0x1ce8, 0xd0}, 345 {0x1cf0, 0x87}, {0x1cf8, 0x70}, 346 {0x1d00, 0x70}, {0x1d08, 0xa9}, 347 {0x0a3c, 0xd0}, {0x0a44, 0xd0}, 348 {0x0a48, 0x01}, {0x0a4c, 0x0d}, 349 {0x0a54, 0xe0}, {0x0a5c, 0xe0}, 350 {0x0a64, 0xa8}, {0x1a3c, 0xd0}, 351 {0x1a44, 0xd0}, {0x1a48, 0x01}, 352 {0x1a4c, 0x0d}, {0x1a54, 0xe0}, 353 {0x1a5c, 0xe0}, {0x1a64, 0xa8} 354}; 355 356static const struct reg_sequence rk_udphy_26m_refclk_cfg[] = { 357 {0x0830, 0x07}, {0x085c, 0x80}, 358 {0x1030, 0x07}, {0x105c, 0x80}, 359 {0x1830, 0x07}, {0x185c, 0x80}, 360 {0x2030, 0x07}, {0x205c, 0x80}, 361 {0x0228, 0x38}, {0x0104, 0x44}, 362 {0x0248, 0x44}, {0x038c, 0x02}, 363 {0x0878, 0x04}, {0x1878, 0x04}, 364 {0x0898, 0x77}, {0x1898, 0x77}, 365 {0x0054, 0x01}, {0x00e0, 0x38}, 366 {0x0060, 0x24}, {0x0064, 0x77}, 367 {0x0070, 0x76}, {0x0234, 0xe8}, 368 {0x0af4, 0x15}, {0x1af4, 0x15}, 369 {0x081c, 0xe5}, {0x181c, 0xe5}, 370 {0x099c, 0x48}, {0x199c, 0x48}, 371 {0x09a4, 0x07}, {0x09a8, 0x22}, 372 {0x19a4, 0x07}, {0x19a8, 0x22}, 373 {0x09b8, 0x3e}, {0x19b8, 0x3e}, 374 {0x09e4, 0x02}, {0x19e4, 0x02}, 375 {0x0a34, 0x1e}, {0x1a34, 0x1e}, 376 {0x0a98, 0x2f}, {0x1a98, 0x2f}, 377 {0x0c30, 0x0e}, {0x0c48, 0x06}, 378 {0x1c30, 0x0e}, {0x1c48, 0x06}, 379 {0x028c, 0x18}, {0x0af0, 0x00}, 380 {0x1af0, 0x00} 381}; 382 383static const struct reg_sequence rk_udphy_init_sequence[] = { 384 {0x0104, 0x44}, {0x0234, 0xe8}, 385 {0x0248, 0x44}, {0x028c, 0x18}, 386 {0x081c, 0xe5}, {0x0878, 0x00}, 387 {0x0994, 0x1c}, {0x0af0, 0x00}, 388 {0x181c, 0xe5}, {0x1878, 0x00}, 389 {0x1994, 0x1c}, {0x1af0, 0x00}, 390 {0x0428, 0x60}, {0x0d58, 0x33}, 391 {0x1d58, 0x33}, {0x0990, 0x74}, 392 {0x0d64, 0x17}, {0x08c8, 0x13}, 393 {0x1990, 0x74}, {0x1d64, 0x17}, 394 {0x18c8, 0x13}, {0x0d90, 0x40}, 395 {0x0da8, 0x40}, {0x0dc0, 0x40}, 396 {0x0dd8, 0x40}, {0x1d90, 0x40}, 397 {0x1da8, 0x40}, {0x1dc0, 0x40}, 398 {0x1dd8, 0x40}, {0x03c0, 0x30}, 399 {0x03c4, 0x06}, {0x0e10, 0x00}, 400 {0x1e10, 0x00}, {0x043c, 0x0f}, 401 {0x0d2c, 0xff}, {0x1d2c, 0xff}, 402 {0x0d34, 0x0f}, {0x1d34, 0x0f}, 403 {0x08fc, 0x2a}, {0x0914, 0x28}, 404 {0x0a30, 0x03}, {0x0e38, 0x03}, 405 {0x0ecc, 0x27}, {0x0ed0, 0x22}, 406 {0x0ed4, 0x26}, {0x18fc, 0x2a}, 407 {0x1914, 0x28}, {0x1a30, 0x03}, 408 {0x1e38, 0x03}, {0x1ecc, 0x27}, 409 {0x1ed0, 0x22}, {0x1ed4, 0x26}, 410 {0x0048, 0x0f}, {0x0060, 0x3c}, 411 {0x0064, 0xf7}, {0x006c, 0x20}, 412 {0x0070, 0x7d}, {0x0074, 0x68}, 413 {0x0af4, 0x1a}, {0x1af4, 0x1a}, 414 {0x0440, 0x3f}, {0x10d4, 0x08}, 415 {0x20d4, 0x08}, {0x00d4, 0x30}, 416 {0x0024, 0x6e}, 417}; 418 419static inline int rk_udphy_grfreg_write(struct regmap *base, 420 const struct rk_udphy_grf_reg *reg, bool en) 421{ 422 return regmap_write(base, reg->offset, en ? reg->enable : reg->disable); 423} 424 425static int rk_udphy_clk_init(struct rk_udphy *udphy, struct device *dev) 426{ 427 int i; 428 429 udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks); 430 if (udphy->num_clks < 1) 431 return -ENODEV; 432 433 /* used for configure phy reference clock frequency */ 434 for (i = 0; i < udphy->num_clks; i++) { 435 if (!strncmp(udphy->clks[i].id, "refclk", 6)) { 436 udphy->refclk = udphy->clks[i].clk; 437 break; 438 } 439 } 440 441 if (!udphy->refclk) 442 return dev_err_probe(udphy->dev, -EINVAL, "no refclk found\n"); 443 444 return 0; 445} 446 447static int rk_udphy_reset_assert_all(struct rk_udphy *udphy) 448{ 449 return reset_control_bulk_assert(udphy->num_rsts, udphy->rsts); 450} 451 452static int rk_udphy_reset_deassert_all(struct rk_udphy *udphy) 453{ 454 return reset_control_bulk_deassert(udphy->num_rsts, udphy->rsts); 455} 456 457static int rk_udphy_reset_deassert(struct rk_udphy *udphy, char *name) 458{ 459 struct reset_control_bulk_data *list = udphy->rsts; 460 int idx; 461 462 for (idx = 0; idx < udphy->num_rsts; idx++) { 463 if (!strcmp(list[idx].id, name)) 464 return reset_control_deassert(list[idx].rstc); 465 } 466 467 return -EINVAL; 468} 469 470static int rk_udphy_reset_init(struct rk_udphy *udphy, struct device *dev) 471{ 472 const struct rk_udphy_cfg *cfg = udphy->cfgs; 473 int idx; 474 475 udphy->num_rsts = cfg->num_rsts; 476 udphy->rsts = devm_kcalloc(dev, udphy->num_rsts, 477 sizeof(*udphy->rsts), GFP_KERNEL); 478 if (!udphy->rsts) 479 return -ENOMEM; 480 481 for (idx = 0; idx < cfg->num_rsts; idx++) 482 udphy->rsts[idx].id = cfg->rst_list[idx]; 483 484 return devm_reset_control_bulk_get_exclusive(dev, cfg->num_rsts, 485 udphy->rsts); 486} 487 488static void rk_udphy_u3_port_disable(struct rk_udphy *udphy, u8 disable) 489{ 490 const struct rk_udphy_cfg *cfg = udphy->cfgs; 491 const struct rk_udphy_grf_reg *preg; 492 493 preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg; 494 rk_udphy_grfreg_write(udphy->usbgrf, preg, disable); 495} 496 497static void rk_udphy_usb_bvalid_enable(struct rk_udphy *udphy, u8 enable) 498{ 499 const struct rk_udphy_cfg *cfg = udphy->cfgs; 500 501 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable); 502 rk_udphy_grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable); 503} 504 505/* 506 * In usb/dp combo phy driver, here are 2 ways to mapping lanes. 507 * 508 * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping) 509 * --------------------------------------------------------------------------- 510 * Type-C Pin B11-B10 A2-A3 A11-A10 B2-B3 511 * PHY Pad ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 512 * C/E(Normal) dpln3 dpln2 dpln0 dpln1 513 * C/E(Flip ) dpln0 dpln1 dpln3 dpln2 514 * D/F(Normal) usbrx usbtx dpln0 dpln1 515 * D/F(Flip ) dpln0 dpln1 usbrx usbtx 516 * A(Normal ) dpln3 dpln1 dpln2 dpln0 517 * A(Flip ) dpln2 dpln0 dpln3 dpln1 518 * B(Normal ) usbrx usbtx dpln1 dpln0 519 * B(Flip ) dpln1 dpln0 usbrx usbtx 520 * --------------------------------------------------------------------------- 521 * 522 * 2 Mapping the lanes in dtsi 523 * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>; 524 * sample as follow: 525 * --------------------------------------------------------------------------- 526 * B11-B10 A2-A3 A11-A10 B2-B3 527 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 528 * <0 1 2 3> dpln0 dpln1 dpln2 dpln3 529 * <2 3 0 1> dpln2 dpln3 dpln0 dpln1 530 * --------------------------------------------------------------------------- 531 * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>; 532 * sample as follow: 533 * --------------------------------------------------------------------------- 534 * B11-B10 A2-A3 A11-A10 B2-B3 535 * rockchip,dp-lane-mux ln0(tx/rx) ln1(tx) ln2(tx/rx) ln3(tx) 536 * <0 1> dpln0 dpln1 usbrx usbtx 537 * <2 3> usbrx usbtx dpln0 dpln1 538 * --------------------------------------------------------------------------- 539 */ 540 541static void rk_udphy_dplane_select(struct rk_udphy *udphy) 542{ 543 const struct rk_udphy_cfg *cfg = udphy->cfgs; 544 u32 value = 0; 545 546 switch (udphy->mode) { 547 case UDPHY_MODE_DP: 548 value |= 2 << udphy->dp_lane_sel[2] * 2; 549 value |= 3 << udphy->dp_lane_sel[3] * 2; 550 fallthrough; 551 552 case UDPHY_MODE_DP_USB: 553 value |= 0 << udphy->dp_lane_sel[0] * 2; 554 value |= 1 << udphy->dp_lane_sel[1] * 2; 555 break; 556 557 case UDPHY_MODE_USB: 558 break; 559 560 default: 561 break; 562 } 563 564 regmap_write(udphy->vogrf, cfg->vogrfcfg[udphy->id].dp_lane_reg, 565 ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) | 566 FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) | 567 FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value); 568} 569 570static int rk_udphy_dplane_get(struct rk_udphy *udphy) 571{ 572 int dp_lanes; 573 574 switch (udphy->mode) { 575 case UDPHY_MODE_DP: 576 dp_lanes = 4; 577 break; 578 579 case UDPHY_MODE_DP_USB: 580 dp_lanes = 2; 581 break; 582 583 case UDPHY_MODE_USB: 584 default: 585 dp_lanes = 0; 586 break; 587 } 588 589 return dp_lanes; 590} 591 592static void rk_udphy_dplane_enable(struct rk_udphy *udphy, int dp_lanes) 593{ 594 u32 val = 0; 595 int i; 596 597 for (i = 0; i < dp_lanes; i++) 598 val |= BIT(udphy->dp_lane_sel[i]); 599 600 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL, 601 FIELD_PREP(CMN_DP_LANE_EN_ALL, val)); 602 603 if (!dp_lanes) 604 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 605 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 606} 607 608static void rk_udphy_dp_hpd_event_trigger(struct rk_udphy *udphy, bool hpd) 609{ 610 const struct rk_udphy_cfg *cfg = udphy->cfgs; 611 612 udphy->dp_sink_hpd_sel = true; 613 udphy->dp_sink_hpd_cfg = hpd; 614 615 if (!udphy->dp_in_use) 616 return; 617 618 rk_udphy_grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd); 619} 620 621static void rk_udphy_set_typec_default_mapping(struct rk_udphy *udphy) 622{ 623 if (udphy->flip) { 624 udphy->dp_lane_sel[0] = 0; 625 udphy->dp_lane_sel[1] = 1; 626 udphy->dp_lane_sel[2] = 3; 627 udphy->dp_lane_sel[3] = 2; 628 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 629 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 630 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 631 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 632 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT; 633 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT; 634 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1); 635 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); 636 } else { 637 udphy->dp_lane_sel[0] = 2; 638 udphy->dp_lane_sel[1] = 3; 639 udphy->dp_lane_sel[2] = 1; 640 udphy->dp_lane_sel[3] = 0; 641 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 642 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 643 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 644 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 645 udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL; 646 udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL; 647 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); 648 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1); 649 } 650 651 udphy->mode = UDPHY_MODE_DP_USB; 652} 653 654static int rk_udphy_orien_sw_set(struct typec_switch_dev *sw, 655 enum typec_orientation orien) 656{ 657 struct rk_udphy *udphy = typec_switch_get_drvdata(sw); 658 659 mutex_lock(&udphy->mutex); 660 661 if (orien == TYPEC_ORIENTATION_NONE) { 662 gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0); 663 gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0); 664 /* unattached */ 665 rk_udphy_usb_bvalid_enable(udphy, false); 666 goto unlock_ret; 667 } 668 669 udphy->flip = orien == TYPEC_ORIENTATION_REVERSE; 670 rk_udphy_set_typec_default_mapping(udphy); 671 rk_udphy_usb_bvalid_enable(udphy, true); 672 673unlock_ret: 674 mutex_unlock(&udphy->mutex); 675 return 0; 676} 677 678static void rk_udphy_orien_switch_unregister(void *data) 679{ 680 struct rk_udphy *udphy = data; 681 682 typec_switch_unregister(udphy->sw); 683} 684 685static int rk_udphy_setup_orien_switch(struct rk_udphy *udphy) 686{ 687 struct typec_switch_desc sw_desc = { }; 688 689 sw_desc.drvdata = udphy; 690 sw_desc.fwnode = dev_fwnode(udphy->dev); 691 sw_desc.set = rk_udphy_orien_sw_set; 692 693 udphy->sw = typec_switch_register(udphy->dev, &sw_desc); 694 if (IS_ERR(udphy->sw)) { 695 dev_err(udphy->dev, "Error register typec orientation switch: %ld\n", 696 PTR_ERR(udphy->sw)); 697 return PTR_ERR(udphy->sw); 698 } 699 700 return devm_add_action_or_reset(udphy->dev, 701 rk_udphy_orien_switch_unregister, udphy); 702} 703 704static int rk_udphy_refclk_set(struct rk_udphy *udphy) 705{ 706 unsigned long rate; 707 int ret; 708 709 /* configure phy reference clock */ 710 rate = clk_get_rate(udphy->refclk); 711 dev_dbg(udphy->dev, "refclk freq %ld\n", rate); 712 713 switch (rate) { 714 case 24000000: 715 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_24m_refclk_cfg, 716 ARRAY_SIZE(rk_udphy_24m_refclk_cfg)); 717 if (ret) 718 return ret; 719 break; 720 721 case 26000000: 722 /* register default is 26MHz */ 723 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_26m_refclk_cfg, 724 ARRAY_SIZE(rk_udphy_26m_refclk_cfg)); 725 if (ret) 726 return ret; 727 break; 728 729 default: 730 dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate); 731 return -EINVAL; 732 } 733 734 return 0; 735} 736 737static int rk_udphy_status_check(struct rk_udphy *udphy) 738{ 739 unsigned int val; 740 int ret; 741 742 /* LCPLL check */ 743 if (udphy->mode & UDPHY_MODE_USB) { 744 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET, 745 val, (val & CMN_ANA_LCPLL_AFC_DONE) && 746 (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000); 747 if (ret) { 748 dev_err(udphy->dev, "cmn ana lcpll lock timeout\n"); 749 /* 750 * If earlier software (U-Boot) enabled USB once already 751 * the PLL may have problems locking on the first try. 752 * It will be successful on the second try, so for the 753 * time being a -EPROBE_DEFER will solve the issue. 754 * 755 * This requires further investigation to understand the 756 * root cause, especially considering that the driver is 757 * asserting all reset lines at probe time. 758 */ 759 return -EPROBE_DEFER; 760 } 761 762 if (!udphy->flip) { 763 ret = regmap_read_poll_timeout(udphy->pma_regmap, 764 TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val, 765 val & TRSV_LN0_MON_RX_CDR_LOCK_DONE, 766 200, 100000); 767 if (ret) 768 dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n"); 769 } else { 770 ret = regmap_read_poll_timeout(udphy->pma_regmap, 771 TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val, 772 val & TRSV_LN2_MON_RX_CDR_LOCK_DONE, 773 200, 100000); 774 if (ret) 775 dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n"); 776 } 777 } 778 779 return 0; 780} 781 782static int rk_udphy_init(struct rk_udphy *udphy) 783{ 784 const struct rk_udphy_cfg *cfg = udphy->cfgs; 785 int ret; 786 787 rk_udphy_reset_assert_all(udphy); 788 usleep_range(10000, 11000); 789 790 /* enable rx lfps for usb */ 791 if (udphy->mode & UDPHY_MODE_USB) 792 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true); 793 794 /* Step 1: power on pma and deassert apb rstn */ 795 rk_udphy_grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true); 796 797 rk_udphy_reset_deassert(udphy, "pma_apb"); 798 rk_udphy_reset_deassert(udphy, "pcs_apb"); 799 800 /* Step 2: set init sequence and phy refclk */ 801 ret = regmap_multi_reg_write(udphy->pma_regmap, rk_udphy_init_sequence, 802 ARRAY_SIZE(rk_udphy_init_sequence)); 803 if (ret) { 804 dev_err(udphy->dev, "init sequence set error %d\n", ret); 805 goto assert_resets; 806 } 807 808 ret = rk_udphy_refclk_set(udphy); 809 if (ret) { 810 dev_err(udphy->dev, "refclk set error %d\n", ret); 811 goto assert_resets; 812 } 813 814 /* Step 3: configure lane mux */ 815 regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, 816 CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL, 817 FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) | 818 FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) | 819 FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) | 820 FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) | 821 FIELD_PREP(CMN_DP_LANE_EN_ALL, 0)); 822 823 /* Step 4: deassert init rstn and wait for 200ns from datasheet */ 824 if (udphy->mode & UDPHY_MODE_USB) 825 rk_udphy_reset_deassert(udphy, "init"); 826 827 if (udphy->mode & UDPHY_MODE_DP) { 828 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 829 CMN_DP_INIT_RSTN, 830 FIELD_PREP(CMN_DP_INIT_RSTN, 0x1)); 831 } 832 833 udelay(1); 834 835 /* Step 5: deassert cmn/lane rstn */ 836 if (udphy->mode & UDPHY_MODE_USB) { 837 rk_udphy_reset_deassert(udphy, "cmn"); 838 rk_udphy_reset_deassert(udphy, "lane"); 839 } 840 841 /* Step 6: wait for lock done of pll */ 842 ret = rk_udphy_status_check(udphy); 843 if (ret) 844 goto assert_resets; 845 846 return 0; 847 848assert_resets: 849 rk_udphy_reset_assert_all(udphy); 850 return ret; 851} 852 853static int rk_udphy_setup(struct rk_udphy *udphy) 854{ 855 int ret; 856 857 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); 858 if (ret) { 859 dev_err(udphy->dev, "failed to enable clk\n"); 860 return ret; 861 } 862 863 ret = rk_udphy_init(udphy); 864 if (ret) { 865 dev_err(udphy->dev, "failed to init combophy\n"); 866 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); 867 return ret; 868 } 869 870 return 0; 871} 872 873static void rk_udphy_disable(struct rk_udphy *udphy) 874{ 875 clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks); 876 rk_udphy_reset_assert_all(udphy); 877} 878 879static int rk_udphy_parse_lane_mux_data(struct rk_udphy *udphy) 880{ 881 int ret, i, num_lanes; 882 883 num_lanes = device_property_count_u32(udphy->dev, "rockchip,dp-lane-mux"); 884 if (num_lanes < 0) { 885 dev_dbg(udphy->dev, "no dp-lane-mux, following dp alt mode\n"); 886 udphy->mode = UDPHY_MODE_USB; 887 return 0; 888 } 889 890 if (num_lanes != 2 && num_lanes != 4) 891 return dev_err_probe(udphy->dev, -EINVAL, 892 "invalid number of lane mux\n"); 893 894 ret = device_property_read_u32_array(udphy->dev, "rockchip,dp-lane-mux", 895 udphy->dp_lane_sel, num_lanes); 896 if (ret) 897 return dev_err_probe(udphy->dev, ret, "get dp lane mux failed\n"); 898 899 for (i = 0; i < num_lanes; i++) { 900 int j; 901 902 if (udphy->dp_lane_sel[i] > 3) 903 return dev_err_probe(udphy->dev, -EINVAL, 904 "lane mux between 0 and 3, exceeding the range\n"); 905 906 udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP; 907 908 for (j = i + 1; j < num_lanes; j++) { 909 if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) 910 return dev_err_probe(udphy->dev, -EINVAL, 911 "set repeat lane mux value\n"); 912 } 913 } 914 915 udphy->mode = UDPHY_MODE_DP; 916 if (num_lanes == 2) { 917 udphy->mode |= UDPHY_MODE_USB; 918 udphy->flip = (udphy->lane_mux_sel[0] == PHY_LANE_MUX_DP); 919 } 920 921 return 0; 922} 923 924static int rk_udphy_get_initial_status(struct rk_udphy *udphy) 925{ 926 int ret; 927 u32 value; 928 929 ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks); 930 if (ret) { 931 dev_err(udphy->dev, "failed to enable clk\n"); 932 return ret; 933 } 934 935 rk_udphy_reset_deassert_all(udphy); 936 937 regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value); 938 if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value)) 939 udphy->status = UDPHY_MODE_DP; 940 else 941 rk_udphy_disable(udphy); 942 943 return 0; 944} 945 946static int rk_udphy_parse_dt(struct rk_udphy *udphy) 947{ 948 struct device *dev = udphy->dev; 949 struct device_node *np = dev_of_node(dev); 950 enum usb_device_speed maximum_speed; 951 int ret; 952 953 udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf"); 954 if (IS_ERR(udphy->u2phygrf)) 955 return dev_err_probe(dev, PTR_ERR(udphy->u2phygrf), "failed to get u2phy-grf\n"); 956 957 udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf"); 958 if (IS_ERR(udphy->udphygrf)) 959 return dev_err_probe(dev, PTR_ERR(udphy->udphygrf), "failed to get usbdpphy-grf\n"); 960 961 udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf"); 962 if (IS_ERR(udphy->usbgrf)) 963 return dev_err_probe(dev, PTR_ERR(udphy->usbgrf), "failed to get usb-grf\n"); 964 965 udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf"); 966 if (IS_ERR(udphy->vogrf)) 967 return dev_err_probe(dev, PTR_ERR(udphy->vogrf), "failed to get vo-grf\n"); 968 969 ret = rk_udphy_parse_lane_mux_data(udphy); 970 if (ret) 971 return ret; 972 973 udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW); 974 if (IS_ERR(udphy->sbu1_dc_gpio)) 975 return PTR_ERR(udphy->sbu1_dc_gpio); 976 977 udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW); 978 if (IS_ERR(udphy->sbu2_dc_gpio)) 979 return PTR_ERR(udphy->sbu2_dc_gpio); 980 981 if (device_property_present(dev, "maximum-speed")) { 982 maximum_speed = usb_get_maximum_speed(dev); 983 udphy->hs = maximum_speed <= USB_SPEED_HIGH; 984 } 985 986 ret = rk_udphy_clk_init(udphy, dev); 987 if (ret) 988 return ret; 989 990 return rk_udphy_reset_init(udphy, dev); 991} 992 993static int rk_udphy_power_on(struct rk_udphy *udphy, u8 mode) 994{ 995 int ret; 996 997 if (!(udphy->mode & mode)) { 998 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 999 return 0; 1000 } 1001 1002 if (udphy->status == UDPHY_MODE_NONE) { 1003 udphy->mode_change = false; 1004 ret = rk_udphy_setup(udphy); 1005 if (ret) 1006 return ret; 1007 1008 if (udphy->mode & UDPHY_MODE_USB) 1009 rk_udphy_u3_port_disable(udphy, false); 1010 } else if (udphy->mode_change) { 1011 udphy->mode_change = false; 1012 udphy->status = UDPHY_MODE_NONE; 1013 if (udphy->mode == UDPHY_MODE_DP) 1014 rk_udphy_u3_port_disable(udphy, true); 1015 1016 rk_udphy_disable(udphy); 1017 ret = rk_udphy_setup(udphy); 1018 if (ret) 1019 return ret; 1020 } 1021 1022 udphy->status |= mode; 1023 1024 return 0; 1025} 1026 1027static void rk_udphy_power_off(struct rk_udphy *udphy, u8 mode) 1028{ 1029 if (!(udphy->mode & mode)) { 1030 dev_info(udphy->dev, "mode 0x%02x is not support\n", mode); 1031 return; 1032 } 1033 1034 if (!udphy->status) 1035 return; 1036 1037 udphy->status &= ~mode; 1038 1039 if (udphy->status == UDPHY_MODE_NONE) 1040 rk_udphy_disable(udphy); 1041} 1042 1043static int rk_udphy_dp_phy_init(struct phy *phy) 1044{ 1045 struct rk_udphy *udphy = phy_get_drvdata(phy); 1046 1047 mutex_lock(&udphy->mutex); 1048 1049 udphy->dp_in_use = true; 1050 1051 mutex_unlock(&udphy->mutex); 1052 1053 return 0; 1054} 1055 1056static int rk_udphy_dp_phy_exit(struct phy *phy) 1057{ 1058 struct rk_udphy *udphy = phy_get_drvdata(phy); 1059 1060 mutex_lock(&udphy->mutex); 1061 udphy->dp_in_use = false; 1062 mutex_unlock(&udphy->mutex); 1063 return 0; 1064} 1065 1066static int rk_udphy_dp_phy_power_on(struct phy *phy) 1067{ 1068 struct rk_udphy *udphy = phy_get_drvdata(phy); 1069 int ret, dp_lanes; 1070 1071 mutex_lock(&udphy->mutex); 1072 1073 dp_lanes = rk_udphy_dplane_get(udphy); 1074 phy_set_bus_width(phy, dp_lanes); 1075 1076 ret = rk_udphy_power_on(udphy, UDPHY_MODE_DP); 1077 if (ret) 1078 goto unlock; 1079 1080 rk_udphy_dplane_enable(udphy, dp_lanes); 1081 1082 rk_udphy_dplane_select(udphy); 1083 1084unlock: 1085 mutex_unlock(&udphy->mutex); 1086 /* 1087 * If data send by aux channel too fast after phy power on, 1088 * the aux may be not ready which will cause aux error. Adding 1089 * delay to avoid this issue. 1090 */ 1091 usleep_range(10000, 11000); 1092 return ret; 1093} 1094 1095static int rk_udphy_dp_phy_power_off(struct phy *phy) 1096{ 1097 struct rk_udphy *udphy = phy_get_drvdata(phy); 1098 1099 mutex_lock(&udphy->mutex); 1100 rk_udphy_dplane_enable(udphy, 0); 1101 rk_udphy_power_off(udphy, UDPHY_MODE_DP); 1102 mutex_unlock(&udphy->mutex); 1103 1104 return 0; 1105} 1106 1107/* 1108 * Verify link rate 1109 */ 1110static int rk_udphy_dp_phy_verify_link_rate(struct rk_udphy *udphy, 1111 struct phy_configure_opts_dp *dp) 1112{ 1113 switch (dp->link_rate) { 1114 case 1620: 1115 case 2700: 1116 case 5400: 1117 case 8100: 1118 udphy->link_rate = dp->link_rate; 1119 break; 1120 default: 1121 return -EINVAL; 1122 } 1123 1124 return 0; 1125} 1126 1127static int rk_udphy_dp_phy_verify_lanes(struct rk_udphy *udphy, 1128 struct phy_configure_opts_dp *dp) 1129{ 1130 switch (dp->lanes) { 1131 case 1: 1132 case 2: 1133 case 4: 1134 /* valid lane count. */ 1135 udphy->lanes = dp->lanes; 1136 break; 1137 1138 default: 1139 return -EINVAL; 1140 } 1141 1142 return 0; 1143} 1144 1145/* 1146 * If changing voltages is required, check swing and pre-emphasis 1147 * levels, per-lane. 1148 */ 1149static int rk_udphy_dp_phy_verify_voltages(struct rk_udphy *udphy, 1150 struct phy_configure_opts_dp *dp) 1151{ 1152 int i; 1153 1154 /* Lane count verified previously. */ 1155 for (i = 0; i < udphy->lanes; i++) { 1156 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1157 return -EINVAL; 1158 1159 /* 1160 * Sum of voltage swing and pre-emphasis levels cannot 1161 * exceed 3. 1162 */ 1163 if (dp->voltage[i] + dp->pre[i] > 3) 1164 return -EINVAL; 1165 } 1166 1167 return 0; 1168} 1169 1170static void rk_udphy_dp_set_voltage(struct rk_udphy *udphy, u8 bw, 1171 u32 voltage, u32 pre, u32 lane) 1172{ 1173 const struct rk_udphy_cfg *cfg = udphy->cfgs; 1174 const struct rk_udphy_dp_tx_drv_ctrl (*dp_ctrl)[4]; 1175 u32 offset = 0x800 * lane; 1176 u32 val; 1177 1178 if (udphy->mux) 1179 dp_ctrl = cfg->dp_tx_ctrl_cfg_typec[bw]; 1180 else 1181 dp_ctrl = cfg->dp_tx_ctrl_cfg[bw]; 1182 1183 val = dp_ctrl[voltage][pre].trsv_reg0204; 1184 regmap_write(udphy->pma_regmap, 0x0810 + offset, val); 1185 1186 val = dp_ctrl[voltage][pre].trsv_reg0205; 1187 regmap_write(udphy->pma_regmap, 0x0814 + offset, val); 1188 1189 val = dp_ctrl[voltage][pre].trsv_reg0206; 1190 regmap_write(udphy->pma_regmap, 0x0818 + offset, val); 1191 1192 val = dp_ctrl[voltage][pre].trsv_reg0207; 1193 regmap_write(udphy->pma_regmap, 0x081c + offset, val); 1194} 1195 1196static int rk_udphy_dp_phy_configure(struct phy *phy, 1197 union phy_configure_opts *opts) 1198{ 1199 struct rk_udphy *udphy = phy_get_drvdata(phy); 1200 struct phy_configure_opts_dp *dp = &opts->dp; 1201 u32 i, val, lane; 1202 int ret; 1203 1204 if (dp->set_rate) { 1205 ret = rk_udphy_dp_phy_verify_link_rate(udphy, dp); 1206 if (ret) 1207 return ret; 1208 } 1209 1210 if (dp->set_lanes) { 1211 ret = rk_udphy_dp_phy_verify_lanes(udphy, dp); 1212 if (ret) 1213 return ret; 1214 } 1215 1216 if (dp->set_voltages) { 1217 ret = rk_udphy_dp_phy_verify_voltages(udphy, dp); 1218 if (ret) 1219 return ret; 1220 } 1221 1222 if (dp->set_rate) { 1223 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, 1224 CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0)); 1225 1226 switch (dp->link_rate) { 1227 case 1620: 1228 udphy->bw = DP_BW_RBR; 1229 break; 1230 1231 case 2700: 1232 udphy->bw = DP_BW_HBR; 1233 break; 1234 1235 case 5400: 1236 udphy->bw = DP_BW_HBR2; 1237 break; 1238 1239 case 8100: 1240 udphy->bw = DP_BW_HBR3; 1241 break; 1242 1243 default: 1244 return -EINVAL; 1245 } 1246 1247 regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW, 1248 FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw)); 1249 regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN, 1250 FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc)); 1251 regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN, 1252 FIELD_PREP(CMN_DP_CMN_RSTN, 0x1)); 1253 1254 ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val, 1255 FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) && 1256 FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val), 1257 0, 1000); 1258 if (ret) { 1259 dev_err(udphy->dev, "ROPLL is not lock, set_rate failed\n"); 1260 return ret; 1261 } 1262 } 1263 1264 if (dp->set_voltages) { 1265 for (i = 0; i < udphy->lanes; i++) { 1266 lane = udphy->dp_lane_sel[i]; 1267 switch (udphy->link_rate) { 1268 case 1620: 1269 case 2700: 1270 regmap_update_bits(udphy->pma_regmap, 1271 TRSV_ANA_TX_CLK_OFFSET_N(lane), 1272 LN_ANA_TX_SER_TXCLK_INV, 1273 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 1274 udphy->lane_mux_sel[lane])); 1275 break; 1276 1277 case 5400: 1278 case 8100: 1279 regmap_update_bits(udphy->pma_regmap, 1280 TRSV_ANA_TX_CLK_OFFSET_N(lane), 1281 LN_ANA_TX_SER_TXCLK_INV, 1282 FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0)); 1283 break; 1284 } 1285 1286 rk_udphy_dp_set_voltage(udphy, udphy->bw, dp->voltage[i], 1287 dp->pre[i], lane); 1288 } 1289 } 1290 1291 return 0; 1292} 1293 1294static const struct phy_ops rk_udphy_dp_phy_ops = { 1295 .init = rk_udphy_dp_phy_init, 1296 .exit = rk_udphy_dp_phy_exit, 1297 .power_on = rk_udphy_dp_phy_power_on, 1298 .power_off = rk_udphy_dp_phy_power_off, 1299 .configure = rk_udphy_dp_phy_configure, 1300 .owner = THIS_MODULE, 1301}; 1302 1303static int rk_udphy_usb3_phy_init(struct phy *phy) 1304{ 1305 struct rk_udphy *udphy = phy_get_drvdata(phy); 1306 int ret = 0; 1307 1308 mutex_lock(&udphy->mutex); 1309 /* DP only or high-speed, disable U3 port */ 1310 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) { 1311 rk_udphy_u3_port_disable(udphy, true); 1312 goto unlock; 1313 } 1314 1315 ret = rk_udphy_power_on(udphy, UDPHY_MODE_USB); 1316 1317unlock: 1318 mutex_unlock(&udphy->mutex); 1319 return ret; 1320} 1321 1322static int rk_udphy_usb3_phy_exit(struct phy *phy) 1323{ 1324 struct rk_udphy *udphy = phy_get_drvdata(phy); 1325 1326 mutex_lock(&udphy->mutex); 1327 /* DP only or high-speed */ 1328 if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) 1329 goto unlock; 1330 1331 rk_udphy_power_off(udphy, UDPHY_MODE_USB); 1332 1333unlock: 1334 mutex_unlock(&udphy->mutex); 1335 return 0; 1336} 1337 1338static const struct phy_ops rk_udphy_usb3_phy_ops = { 1339 .init = rk_udphy_usb3_phy_init, 1340 .exit = rk_udphy_usb3_phy_exit, 1341 .owner = THIS_MODULE, 1342}; 1343 1344static int rk_udphy_typec_mux_set(struct typec_mux_dev *mux, 1345 struct typec_mux_state *state) 1346{ 1347 struct rk_udphy *udphy = typec_mux_get_drvdata(mux); 1348 u8 mode; 1349 1350 mutex_lock(&udphy->mutex); 1351 1352 switch (state->mode) { 1353 case TYPEC_DP_STATE_C: 1354 case TYPEC_DP_STATE_E: 1355 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 1356 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 1357 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 1358 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 1359 mode = UDPHY_MODE_DP; 1360 break; 1361 1362 case TYPEC_DP_STATE_D: 1363 default: 1364 if (udphy->flip) { 1365 udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP; 1366 udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP; 1367 udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB; 1368 udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB; 1369 } else { 1370 udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB; 1371 udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB; 1372 udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP; 1373 udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP; 1374 } 1375 mode = UDPHY_MODE_DP_USB; 1376 break; 1377 } 1378 1379 if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) { 1380 struct typec_displayport_data *data = state->data; 1381 1382 if (!data) { 1383 rk_udphy_dp_hpd_event_trigger(udphy, false); 1384 } else if (data->status & DP_STATUS_IRQ_HPD) { 1385 rk_udphy_dp_hpd_event_trigger(udphy, false); 1386 usleep_range(750, 800); 1387 rk_udphy_dp_hpd_event_trigger(udphy, true); 1388 } else if (data->status & DP_STATUS_HPD_STATE) { 1389 if (udphy->mode != mode) { 1390 udphy->mode = mode; 1391 udphy->mode_change = true; 1392 } 1393 rk_udphy_dp_hpd_event_trigger(udphy, true); 1394 } else { 1395 rk_udphy_dp_hpd_event_trigger(udphy, false); 1396 } 1397 } 1398 1399 mutex_unlock(&udphy->mutex); 1400 return 0; 1401} 1402 1403static void rk_udphy_typec_mux_unregister(void *data) 1404{ 1405 struct rk_udphy *udphy = data; 1406 1407 typec_mux_unregister(udphy->mux); 1408} 1409 1410static int rk_udphy_setup_typec_mux(struct rk_udphy *udphy) 1411{ 1412 struct typec_mux_desc mux_desc = {}; 1413 1414 mux_desc.drvdata = udphy; 1415 mux_desc.fwnode = dev_fwnode(udphy->dev); 1416 mux_desc.set = rk_udphy_typec_mux_set; 1417 1418 udphy->mux = typec_mux_register(udphy->dev, &mux_desc); 1419 if (IS_ERR(udphy->mux)) { 1420 dev_err(udphy->dev, "Error register typec mux: %ld\n", 1421 PTR_ERR(udphy->mux)); 1422 return PTR_ERR(udphy->mux); 1423 } 1424 1425 return devm_add_action_or_reset(udphy->dev, rk_udphy_typec_mux_unregister, 1426 udphy); 1427} 1428 1429static const struct regmap_config rk_udphy_pma_regmap_cfg = { 1430 .reg_bits = 32, 1431 .reg_stride = 4, 1432 .val_bits = 32, 1433 .max_register = 0x20dc, 1434}; 1435 1436static struct phy *rk_udphy_phy_xlate(struct device *dev, const struct of_phandle_args *args) 1437{ 1438 struct rk_udphy *udphy = dev_get_drvdata(dev); 1439 1440 if (args->args_count == 0) 1441 return ERR_PTR(-EINVAL); 1442 1443 switch (args->args[0]) { 1444 case PHY_TYPE_USB3: 1445 return udphy->phy_u3; 1446 case PHY_TYPE_DP: 1447 return udphy->phy_dp; 1448 } 1449 1450 return ERR_PTR(-EINVAL); 1451} 1452 1453static int rk_udphy_probe(struct platform_device *pdev) 1454{ 1455 struct device *dev = &pdev->dev; 1456 struct phy_provider *phy_provider; 1457 struct resource *res; 1458 struct rk_udphy *udphy; 1459 void __iomem *base; 1460 int id, ret; 1461 1462 udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL); 1463 if (!udphy) 1464 return -ENOMEM; 1465 1466 udphy->cfgs = device_get_match_data(dev); 1467 if (!udphy->cfgs) 1468 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 1469 1470 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1471 if (IS_ERR(base)) 1472 return PTR_ERR(base); 1473 1474 /* find the phy-id from the io address */ 1475 udphy->id = -ENODEV; 1476 for (id = 0; id < udphy->cfgs->num_phys; id++) { 1477 if (res->start == udphy->cfgs->phy_ids[id]) { 1478 udphy->id = id; 1479 break; 1480 } 1481 } 1482 1483 if (udphy->id < 0) 1484 return dev_err_probe(dev, -ENODEV, "no matching device found\n"); 1485 1486 udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA, 1487 &rk_udphy_pma_regmap_cfg); 1488 if (IS_ERR(udphy->pma_regmap)) 1489 return PTR_ERR(udphy->pma_regmap); 1490 1491 udphy->dev = dev; 1492 ret = rk_udphy_parse_dt(udphy); 1493 if (ret) 1494 return ret; 1495 1496 ret = rk_udphy_get_initial_status(udphy); 1497 if (ret) 1498 return ret; 1499 1500 mutex_init(&udphy->mutex); 1501 platform_set_drvdata(pdev, udphy); 1502 1503 if (device_property_present(dev, "orientation-switch")) { 1504 ret = rk_udphy_setup_orien_switch(udphy); 1505 if (ret) 1506 return ret; 1507 } 1508 1509 if (device_property_present(dev, "mode-switch")) { 1510 ret = rk_udphy_setup_typec_mux(udphy); 1511 if (ret) 1512 return ret; 1513 } 1514 1515 udphy->phy_u3 = devm_phy_create(dev, dev->of_node, &rk_udphy_usb3_phy_ops); 1516 if (IS_ERR(udphy->phy_u3)) { 1517 ret = PTR_ERR(udphy->phy_u3); 1518 return dev_err_probe(dev, ret, "failed to create USB3 phy\n"); 1519 } 1520 phy_set_drvdata(udphy->phy_u3, udphy); 1521 1522 udphy->phy_dp = devm_phy_create(dev, dev->of_node, &rk_udphy_dp_phy_ops); 1523 if (IS_ERR(udphy->phy_dp)) { 1524 ret = PTR_ERR(udphy->phy_dp); 1525 return dev_err_probe(dev, ret, "failed to create DP phy\n"); 1526 } 1527 phy_set_bus_width(udphy->phy_dp, rk_udphy_dplane_get(udphy)); 1528 udphy->phy_dp->attrs.max_link_rate = 8100; 1529 phy_set_drvdata(udphy->phy_dp, udphy); 1530 1531 phy_provider = devm_of_phy_provider_register(dev, rk_udphy_phy_xlate); 1532 if (IS_ERR(phy_provider)) { 1533 ret = PTR_ERR(phy_provider); 1534 return dev_err_probe(dev, ret, "failed to register phy provider\n"); 1535 } 1536 1537 return 0; 1538} 1539 1540static int __maybe_unused rk_udphy_resume(struct device *dev) 1541{ 1542 struct rk_udphy *udphy = dev_get_drvdata(dev); 1543 1544 if (udphy->dp_sink_hpd_sel) 1545 rk_udphy_dp_hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg); 1546 1547 return 0; 1548} 1549 1550static const struct dev_pm_ops rk_udphy_pm_ops = { 1551 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, rk_udphy_resume) 1552}; 1553 1554static const char * const rk_udphy_rst_list[] = { 1555 "init", "cmn", "lane", "pcs_apb", "pma_apb" 1556}; 1557 1558static const struct rk_udphy_cfg rk3576_udphy_cfgs = { 1559 .num_phys = 1, 1560 .phy_ids = { 0x2b010000 }, 1561 .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), 1562 .rst_list = rk_udphy_rst_list, 1563 .grfcfg = { 1564 /* u2phy-grf */ 1565 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0010, 1, 0, 0x2, 0x3), 1566 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0000, 15, 14, 0x1, 0x3), 1567 1568 /* usb-grf */ 1569 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x0030, 15, 0, 0x1100, 0x0188), 1570 1571 /* usbdpphy-grf */ 1572 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), 1573 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), 1574 }, 1575 .vogrfcfg = { 1576 { 1577 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), 1578 .dp_lane_reg = 0x0000, 1579 }, 1580 }, 1581 .dp_tx_ctrl_cfg = { 1582 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1583 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1584 rk3588_dp_tx_drv_ctrl_hbr2, 1585 rk3588_dp_tx_drv_ctrl_hbr3, 1586 }, 1587 .dp_tx_ctrl_cfg_typec = { 1588 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1589 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1590 rk3588_dp_tx_drv_ctrl_hbr2, 1591 rk3588_dp_tx_drv_ctrl_hbr3, 1592 }, 1593}; 1594 1595static const struct rk_udphy_cfg rk3588_udphy_cfgs = { 1596 .num_phys = 2, 1597 .phy_ids = { 1598 0xfed80000, 1599 0xfed90000, 1600 }, 1601 .num_rsts = ARRAY_SIZE(rk_udphy_rst_list), 1602 .rst_list = rk_udphy_rst_list, 1603 .grfcfg = { 1604 /* u2phy-grf */ 1605 .bvalid_phy_con = RK_UDPHY_GEN_GRF_REG(0x0008, 1, 0, 0x2, 0x3), 1606 .bvalid_grf_con = RK_UDPHY_GEN_GRF_REG(0x0010, 3, 2, 0x2, 0x3), 1607 1608 /* usb-grf */ 1609 .usb3otg0_cfg = RK_UDPHY_GEN_GRF_REG(0x001c, 15, 0, 0x1100, 0x0188), 1610 .usb3otg1_cfg = RK_UDPHY_GEN_GRF_REG(0x0034, 15, 0, 0x1100, 0x0188), 1611 1612 /* usbdpphy-grf */ 1613 .low_pwrn = RK_UDPHY_GEN_GRF_REG(0x0004, 13, 13, 0, 1), 1614 .rx_lfps = RK_UDPHY_GEN_GRF_REG(0x0004, 14, 14, 0, 1), 1615 }, 1616 .vogrfcfg = { 1617 { 1618 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0000, 11, 10, 1, 3), 1619 .dp_lane_reg = 0x0000, 1620 }, 1621 { 1622 .hpd_trigger = RK_UDPHY_GEN_GRF_REG(0x0008, 11, 10, 1, 3), 1623 .dp_lane_reg = 0x0008, 1624 }, 1625 }, 1626 .dp_tx_ctrl_cfg = { 1627 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1628 rk3588_dp_tx_drv_ctrl_rbr_hbr, 1629 rk3588_dp_tx_drv_ctrl_hbr2, 1630 rk3588_dp_tx_drv_ctrl_hbr3, 1631 }, 1632 .dp_tx_ctrl_cfg_typec = { 1633 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1634 rk3588_dp_tx_drv_ctrl_rbr_hbr_typec, 1635 rk3588_dp_tx_drv_ctrl_hbr2, 1636 rk3588_dp_tx_drv_ctrl_hbr3, 1637 }, 1638}; 1639 1640static const struct of_device_id rk_udphy_dt_match[] = { 1641 { 1642 .compatible = "rockchip,rk3576-usbdp-phy", 1643 .data = &rk3576_udphy_cfgs 1644 }, 1645 { 1646 .compatible = "rockchip,rk3588-usbdp-phy", 1647 .data = &rk3588_udphy_cfgs 1648 }, 1649 { /* sentinel */ } 1650}; 1651MODULE_DEVICE_TABLE(of, rk_udphy_dt_match); 1652 1653static struct platform_driver rk_udphy_driver = { 1654 .probe = rk_udphy_probe, 1655 .driver = { 1656 .name = "rockchip-usbdp-phy", 1657 .of_match_table = rk_udphy_dt_match, 1658 .pm = &rk_udphy_pm_ops, 1659 }, 1660}; 1661module_platform_driver(rk_udphy_driver); 1662 1663MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>"); 1664MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>"); 1665MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver"); 1666MODULE_LICENSE("GPL");
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