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phy-rockchip-samsung-hdptx.c
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linux-6.19.14/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Algea Cao <algea.cao@rock-chips.com> 7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> 8 */ 9#include <linux/bitfield.h> 10#include <linux/clk.h> 11#include <linux/clk-provider.h> 12#include <linux/delay.h> 13#include <linux/mfd/syscon.h> 14#include <linux/module.h> 15#include <linux/of.h> 16#include <linux/of_platform.h> 17#include <linux/phy/phy.h> 18#include <linux/platform_device.h> 19#include <linux/pm_runtime.h> 20#include <linux/rational.h> 21#include <linux/regmap.h> 22#include <linux/reset.h> 23 24#define GRF_HDPTX_CON0 0x00 25#define HDPTX_I_PLL_EN BIT(7) 26#define HDPTX_I_BIAS_EN BIT(6) 27#define HDPTX_I_BGR_EN BIT(5) 28#define HDPTX_MODE_SEL BIT(0) 29#define GRF_HDPTX_STATUS 0x80 30#define HDPTX_O_PLL_LOCK_DONE BIT(3) 31#define HDPTX_O_PHY_CLK_RDY BIT(2) 32#define HDPTX_O_PHY_RDY BIT(1) 33#define HDPTX_O_SB_RDY BIT(0) 34 35#define HDTPX_REG(_n, _min, _max) \ 36 ( \ 37 BUILD_BUG_ON_ZERO((0x##_n) < (0x##_min)) + \ 38 BUILD_BUG_ON_ZERO((0x##_n) > (0x##_max)) + \ 39 ((0x##_n) * 4) \ 40 ) 41 42#define CMN_REG(n) HDTPX_REG(n, 0000, 00a7) 43#define SB_REG(n) HDTPX_REG(n, 0100, 0129) 44#define LNTOP_REG(n) HDTPX_REG(n, 0200, 0229) 45#define LANE_REG(n) HDTPX_REG(n, 0300, 062d) 46 47/* CMN_REG(0008) */ 48#define OVRD_LCPLL_EN_MASK BIT(7) 49#define LCPLL_EN_MASK BIT(6) 50#define LCPLL_LCVCO_MODE_EN_MASK BIT(4) 51/* CMN_REG(001e) */ 52#define LCPLL_PI_EN_MASK BIT(5) 53#define LCPLL_100M_CLK_EN_MASK BIT(0) 54/* CMN_REG(0025) */ 55#define LCPLL_PMS_IQDIV_RSTN_MASK BIT(4) 56/* CMN_REG(0028) */ 57#define LCPLL_SDC_FRAC_EN_MASK BIT(2) 58#define LCPLL_SDC_FRAC_RSTN_MASK BIT(0) 59/* CMN_REG(002d) */ 60#define LCPLL_SDC_N_MASK GENMASK(3, 1) 61/* CMN_REG(002e) */ 62#define LCPLL_SDC_NUMBERATOR_MASK GENMASK(5, 0) 63/* CMN_REG(002f) */ 64#define LCPLL_SDC_DENOMINATOR_MASK GENMASK(7, 2) 65#define LCPLL_SDC_NDIV_RSTN_MASK BIT(0) 66/* CMN_REG(003c) */ 67#define ANA_LCPLL_RESERVED7_MASK BIT(7) 68/* CMN_REG(003d) */ 69#define OVRD_ROPLL_EN_MASK BIT(7) 70#define ROPLL_EN_MASK BIT(6) 71#define ROPLL_LCVCO_EN_MASK BIT(4) 72/* CMN_REG(0046) */ 73#define ROPLL_ANA_CPP_CTRL_COARSE_MASK GENMASK(7, 4) 74#define ROPLL_ANA_CPP_CTRL_FINE_MASK GENMASK(3, 0) 75/* CMN_REG(0047) */ 76#define ROPLL_ANA_LPF_C_SEL_COARSE_MASK GENMASK(5, 3) 77#define ROPLL_ANA_LPF_C_SEL_FINE_MASK GENMASK(2, 0) 78/* CMN_REG(004e) */ 79#define ROPLL_PI_EN_MASK BIT(5) 80/* CMN_REG(0051) */ 81#define ROPLL_PMS_MDIV_MASK GENMASK(7, 0) 82/* CMN_REG(0055) */ 83#define ROPLL_PMS_MDIV_AFC_MASK GENMASK(7, 0) 84/* CMN_REG(0059) */ 85#define ANA_ROPLL_PMS_PDIV_MASK GENMASK(7, 4) 86#define ANA_ROPLL_PMS_REFDIV_MASK GENMASK(3, 0) 87/* CMN_REG(005a) */ 88#define ROPLL_PMS_SDIV_RBR_MASK GENMASK(7, 4) 89#define ROPLL_PMS_SDIV_HBR_MASK GENMASK(3, 0) 90/* CMN_REG(005b) */ 91#define ROPLL_PMS_SDIV_HBR2_MASK GENMASK(7, 4) 92/* CMN_REG(005c) */ 93#define ROPLL_PMS_IQDIV_RSTN_MASK BIT(5) 94/* CMN_REG(005e) */ 95#define ROPLL_SDM_EN_MASK BIT(6) 96#define OVRD_ROPLL_SDM_RSTN_MASK BIT(5) 97#define ROPLL_SDM_RSTN_MASK BIT(4) 98#define ROPLL_SDC_FRAC_EN_RBR_MASK BIT(3) 99#define ROPLL_SDC_FRAC_EN_HBR_MASK BIT(2) 100#define ROPLL_SDC_FRAC_EN_HBR2_MASK BIT(1) 101#define ROPLL_SDM_FRAC_EN_HBR3_MASK BIT(0) 102/* CMN_REG(005f) */ 103#define OVRD_ROPLL_SDC_RSTN_MASK BIT(5) 104#define ROPLL_SDC_RSTN_MASK BIT(4) 105/* CMN_REG(0060) */ 106#define ROPLL_SDM_DENOMINATOR_MASK GENMASK(7, 0) 107/* CMN_REG(0064) */ 108#define ROPLL_SDM_NUM_SIGN_RBR_MASK BIT(3) 109#define ROPLL_SDM_NUM_SIGN_HBR_MASK BIT(2) 110#define ROPLL_SDM_NUM_SIGN_HBR2_MASK BIT(1) 111/* CMN_REG(0065) */ 112#define ROPLL_SDM_NUM_MASK GENMASK(7, 0) 113/* CMN_REG(0069) */ 114#define ROPLL_SDC_N_RBR_MASK GENMASK(2, 0) 115/* CMN_REG(006a) */ 116#define ROPLL_SDC_N_HBR_MASK GENMASK(5, 3) 117#define ROPLL_SDC_N_HBR2_MASK GENMASK(2, 0) 118/* CMN_REG(006b) */ 119#define ROPLL_SDC_N_HBR3_MASK GENMASK(3, 1) 120/* CMN_REG(006c) */ 121#define ROPLL_SDC_NUM_MASK GENMASK(5, 0) 122/* cmn_reg0070 */ 123#define ROPLL_SDC_DENO_MASK GENMASK(5, 0) 124/* CMN_REG(0074) */ 125#define OVRD_ROPLL_SDC_NDIV_RSTN_MASK BIT(3) 126#define ROPLL_SDC_NDIV_RSTN_MASK BIT(2) 127#define OVRD_ROPLL_SSC_EN_MASK BIT(1) 128#define ROPLL_SSC_EN_MASK BIT(0) 129/* CMN_REG(0075) */ 130#define ANA_ROPLL_SSC_FM_DEVIATION_MASK GENMASK(5, 0) 131/* CMN_REG(0076) */ 132#define ANA_ROPLL_SSC_FM_FREQ_MASK GENMASK(6, 2) 133/* CMN_REG(0077) */ 134#define ANA_ROPLL_SSC_CLK_DIV_SEL_MASK GENMASK(6, 3) 135/* CMN_REG(0081) */ 136#define OVRD_PLL_CD_CLK_EN_MASK BIT(8) 137#define ANA_PLL_CD_TX_SER_RATE_SEL_MASK BIT(3) 138#define ANA_PLL_CD_HSCLK_WEST_EN_MASK BIT(1) 139#define ANA_PLL_CD_HSCLK_EAST_EN_MASK BIT(0) 140/* CMN_REG(0082) */ 141#define ANA_PLL_CD_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 142/* CMN_REG(0083) */ 143#define ANA_PLL_CD_VREG_ICTRL_MASK GENMASK(6, 5) 144/* CMN_REG(0084) */ 145#define PLL_LCRO_CLK_SEL_MASK BIT(5) 146/* CMN_REG(0085) */ 147#define ANA_PLL_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0) 148/* CMN_REG(0086) */ 149#define PLL_PCG_POSTDIV_SEL_MASK GENMASK(7, 4) 150#define PLL_PCG_CLK_SEL_MASK GENMASK(3, 1) 151#define PLL_PCG_CLK_EN_MASK BIT(0) 152/* CMN_REG(0087) */ 153#define ANA_PLL_FRL_MODE_EN_MASK BIT(3) 154#define ANA_PLL_TX_HS_CLK_EN_MASK BIT(2) 155/* CMN_REG(0089) */ 156#define LCPLL_ALONE_MODE_MASK BIT(1) 157/* CMN_REG(0095) */ 158#define DP_TX_LINK_BW_MASK GENMASK(1, 0) 159/* CMN_REG(0097) */ 160#define DIG_CLK_SEL_MASK BIT(1) 161#define LCPLL_REF BIT(1) 162#define ROPLL_REF 0 163/* CMN_REG(0099) */ 164#define SSC_EN_MASK GENMASK(7, 6) 165#define CMN_ROPLL_ALONE_MODE_MASK BIT(2) 166#define ROPLL_ALONE_MODE BIT(2) 167/* CMN_REG(009a) */ 168#define HS_SPEED_SEL_MASK BIT(0) 169#define DIV_10_CLOCK BIT(0) 170/* CMN_REG(009b) */ 171#define LS_SPEED_SEL_MASK BIT(4) 172#define LINK_SYMBOL_CLOCK BIT(4) 173#define LINK_SYMBOL_CLOCK1_2 0 174 175/* SB_REG(0102) */ 176#define OVRD_SB_RXTERM_EN_MASK BIT(5) 177#define SB_RXTERM_EN_MASK BIT(4) 178#define ANA_SB_RXTERM_OFFSP_MASK GENMASK(3, 0) 179/* SB_REG(0103) */ 180#define ANA_SB_RXTERM_OFFSN_MASK GENMASK(6, 3) 181#define OVRD_SB_RX_RESCAL_DONE_MASK BIT(1) 182#define SB_RX_RESCAL_DONE_MASK BIT(0) 183/* SB_REG(0104) */ 184#define OVRD_SB_EN_MASK BIT(5) 185#define SB_EN_MASK BIT(4) 186#define OVRD_SB_AUX_EN_MASK BIT(1) 187#define SB_AUX_EN_MASK BIT(0) 188/* SB_REG(0105) */ 189#define OVRD_SB_EARC_CMDC_EN_MASK BIT(6) 190#define SB_EARC_CMDC_EN_MASK BIT(5) 191#define ANA_SB_TX_HLVL_PROG_MASK GENMASK(2, 0) 192/* SB_REG(0106) */ 193#define ANA_SB_TX_LLVL_PROG_MASK GENMASK(6, 4) 194/* SB_REG(0109) */ 195#define ANA_SB_DMRX_AFC_DIV_RATIO_MASK GENMASK(2, 0) 196/* SB_REG(010d) */ 197#define ANA_SB_DMRX_LPBK_DATA_MASK BIT(4) 198/* SB_REG(010f) */ 199#define OVRD_SB_VREG_EN_MASK BIT(7) 200#define SB_VREG_EN_MASK BIT(6) 201#define OVRD_SB_VREG_LPF_BYPASS_MASK BIT(5) 202#define SB_VREG_LPF_BYPASS_MASK BIT(4) 203#define ANA_SB_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 204/* SB_REG(0110) */ 205#define ANA_SB_VREG_OUT_SEL_MASK BIT(1) 206#define ANA_SB_VREG_REF_SEL_MASK BIT(0) 207/* SB_REG(0113) */ 208#define SB_RX_RCAL_OPT_CODE_MASK GENMASK(5, 4) 209#define SB_RX_RTERM_CTRL_MASK GENMASK(3, 0) 210/* SB_REG(0114) */ 211#define SB_TG_SB_EN_DELAY_TIME_MASK GENMASK(5, 3) 212#define SB_TG_RXTERM_EN_DELAY_TIME_MASK GENMASK(2, 0) 213/* SB_REG(0115) */ 214#define SB_READY_DELAY_TIME_MASK GENMASK(5, 3) 215#define SB_TG_OSC_EN_DELAY_TIME_MASK GENMASK(2, 0) 216/* SB_REG(0116) */ 217#define AFC_RSTN_DELAY_TIME_MASK GENMASK(6, 4) 218/* SB_REG(0117) */ 219#define FAST_PULSE_TIME_MASK GENMASK(3, 0) 220/* SB_REG(0118) */ 221#define SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK GENMASK(7, 0) 222/* SB_REG(011a) */ 223#define SB_TG_CNT_RUN_NO_7_0_MASK GENMASK(7, 0) 224/* SB_REG(011b) */ 225#define SB_EARC_SIG_DET_BYPASS_MASK BIT(4) 226#define SB_AFC_TOL_MASK GENMASK(3, 0) 227/* SB_REG(011c) */ 228#define SB_AFC_STB_NUM_MASK GENMASK(3, 0) 229/* SB_REG(011d) */ 230#define SB_TG_OSC_CNT_MIN_MASK GENMASK(7, 0) 231/* SB_REG(011e) */ 232#define SB_TG_OSC_CNT_MAX_MASK GENMASK(7, 0) 233/* SB_REG(011f) */ 234#define SB_PWM_AFC_CTRL_MASK GENMASK(7, 2) 235#define SB_RCAL_RSTN_MASK BIT(1) 236/* SB_REG(0120) */ 237#define SB_AUX_EN_IN_MASK BIT(7) 238#define SB_EARC_EN_MASK BIT(1) 239#define SB_EARC_AFC_EN_MASK BIT(2) 240/* SB_REG(0123) */ 241#define OVRD_SB_READY_MASK BIT(5) 242#define SB_READY_MASK BIT(4) 243 244/* LNTOP_REG(0200) */ 245#define PROTOCOL_SEL_MASK BIT(2) 246#define HDMI_MODE BIT(2) 247#define HDMI_TMDS_FRL_SEL BIT(1) 248/* LNTOP_REG(0206) */ 249#define DATA_BUS_WIDTH_MASK GENMASK(2, 1) 250#define DATA_BUS_WIDTH_SEL_MASK BIT(0) 251#define DATA_BUS_36_40 BIT(0) 252/* LNTOP_REG(0207) */ 253#define LANE_EN_MASK 0xf 254#define ALL_LANE_EN 0xf 255 256/* LANE_REG(0301) */ 257#define OVRD_LN_TX_DRV_EI_EN_MASK BIT(7) 258#define LN_TX_DRV_EI_EN_MASK BIT(6) 259/* LANE_REG(0303) */ 260#define OVRD_LN_TX_DRV_LVL_CTRL_MASK BIT(5) 261#define LN_TX_DRV_LVL_CTRL_MASK GENMASK(4, 0) 262/* LANE_REG(0304) */ 263#define OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK BIT(4) 264#define LN_TX_DRV_POST_LVL_CTRL_MASK GENMASK(3, 0) 265/* LANE_REG(0305) */ 266#define OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK BIT(6) 267#define LN_TX_DRV_PRE_LVL_CTRL_MASK GENMASK(5, 2) 268/* LANE_REG(0306) */ 269#define LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK GENMASK(7, 5) 270#define LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK GENMASK(4, 2) 271#define LN_ANA_TX_DRV_ACCDRV_EN_MASK BIT(0) 272/* LANE_REG(0307) */ 273#define LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK BIT(6) 274#define LN_ANA_TX_DRV_ACCDRV_CTRL_MASK GENMASK(5, 3) 275/* LANE_REG(030a) */ 276#define LN_ANA_TX_JEQ_EN_MASK BIT(4) 277#define LN_TX_JEQ_EVEN_CTRL_RBR_MASK GENMASK(3, 0) 278/* LANE_REG(030b) */ 279#define LN_TX_JEQ_EVEN_CTRL_HBR_MASK GENMASK(7, 4) 280#define LN_TX_JEQ_EVEN_CTRL_HBR2_MASK GENMASK(3, 0) 281/* LANE_REG(030c) */ 282#define LN_TX_JEQ_ODD_CTRL_RBR_MASK GENMASK(3, 0) 283/* LANE_REG(030d) */ 284#define LN_TX_JEQ_ODD_CTRL_HBR_MASK GENMASK(7, 4) 285#define LN_TX_JEQ_ODD_CTRL_HBR2_MASK GENMASK(3, 0) 286/* LANE_REG(0310) */ 287#define LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK GENMASK(1, 0) 288/* LANE_REG(0311) */ 289#define LN_TX_SER_40BIT_EN_RBR_MASK BIT(3) 290#define LN_TX_SER_40BIT_EN_HBR_MASK BIT(2) 291#define LN_TX_SER_40BIT_EN_HBR2_MASK BIT(1) 292/* LANE_REG(0312) */ 293#define LN0_TX_SER_RATE_SEL_RBR_MASK BIT(5) 294#define LN0_TX_SER_RATE_SEL_HBR_MASK BIT(4) 295#define LN0_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 296#define LN0_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 297/* LANE_REG(0316) */ 298#define LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK GENMASK(3, 0) 299/* LANE_REG(031B) */ 300#define LN_ANA_TX_RESERVED_MASK GENMASK(7, 0) 301/* LANE_REG(031e) */ 302#define LN_POLARITY_INV_MASK BIT(2) 303#define LN_LANE_MODE_MASK BIT(1) 304 305/* LANE_REG(0412) */ 306#define LN1_TX_SER_RATE_SEL_RBR_MASK BIT(5) 307#define LN1_TX_SER_RATE_SEL_HBR_MASK BIT(4) 308#define LN1_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 309#define LN1_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 310 311/* LANE_REG(0512) */ 312#define LN2_TX_SER_RATE_SEL_RBR_MASK BIT(5) 313#define LN2_TX_SER_RATE_SEL_HBR_MASK BIT(4) 314#define LN2_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 315#define LN2_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 316 317/* LANE_REG(0612) */ 318#define LN3_TX_SER_RATE_SEL_RBR_MASK BIT(5) 319#define LN3_TX_SER_RATE_SEL_HBR_MASK BIT(4) 320#define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) 321#define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) 322 323#define HDMI14_MAX_RATE 340000000 324#define HDMI20_MAX_RATE 600000000 325 326enum dp_link_rate { 327 DP_BW_RBR, 328 DP_BW_HBR, 329 DP_BW_HBR2, 330}; 331 332struct ropll_config { 333 unsigned long long rate; 334 u8 pms_mdiv; 335 u8 pms_mdiv_afc; 336 u8 pms_pdiv; 337 u8 pms_refdiv; 338 u8 pms_sdiv; 339 u8 pms_iqdiv_rstn; 340 u8 ref_clk_sel; 341 u8 sdm_en; 342 u8 sdm_rstn; 343 u8 sdc_frac_en; 344 u8 sdc_rstn; 345 u8 sdm_clk_div; 346 u8 sdm_deno; 347 u8 sdm_num_sign; 348 u8 sdm_num; 349 u8 sdc_n; 350 u8 sdc_num; 351 u8 sdc_deno; 352 u8 sdc_ndiv_rstn; 353 u8 ssc_en; 354 u8 ssc_fm_dev; 355 u8 ssc_fm_freq; 356 u8 ssc_clk_div_sel; 357 u8 ana_cpp_ctrl; 358 u8 ana_lpf_c_sel; 359 u8 cd_tx_ser_rate_sel; 360}; 361 362struct tx_drv_ctrl { 363 u8 tx_drv_lvl_ctrl; 364 u8 tx_drv_post_lvl_ctrl; 365 u8 ana_tx_drv_idrv_idn_ctrl; 366 u8 ana_tx_drv_idrv_iup_ctrl; 367 u8 ana_tx_drv_accdrv_en; 368 u8 ana_tx_drv_accdrv_ctrl; 369 u8 tx_drv_pre_lvl_ctrl; 370 u8 ana_tx_jeq_en; 371 u8 tx_jeq_even_ctrl; 372 u8 tx_jeq_odd_ctrl; 373}; 374 375enum rk_hdptx_reset { 376 RST_APB = 0, 377 RST_INIT, 378 RST_CMN, 379 RST_LANE, 380 RST_MAX 381}; 382 383#define MAX_HDPTX_PHY_NUM 2 384 385struct rk_hdptx_phy_cfg { 386 unsigned int num_phys; 387 unsigned int phy_ids[MAX_HDPTX_PHY_NUM]; 388}; 389 390struct rk_hdptx_phy { 391 struct device *dev; 392 struct regmap *regmap; 393 struct regmap *grf; 394 395 int phy_id; 396 struct phy *phy; 397 struct phy_configure_opts_hdmi hdmi_cfg; 398 struct clk_bulk_data *clks; 399 int nr_clks; 400 struct reset_control_bulk_data rsts[RST_MAX]; 401 402 /* clk provider */ 403 struct clk_hw hw; 404 unsigned long hw_rate; 405 bool restrict_rate_change; 406 407 atomic_t usage_count; 408 409 /* used for dp mode */ 410 unsigned int link_rate; 411 unsigned int lanes; 412}; 413 414static const struct ropll_config ropll_tmds_cfg[] = { 415 { 594000000ULL, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 416 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 417 { 461101250ULL, 97, 97, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 71, 1, 53, 2, 6, 418 35, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 419 { 371250000ULL, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 420 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 421 { 297000000ULL, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 422 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 423 { 162000000ULL, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 424 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 425 { 185625000ULL, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 426 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 427 { 154000000ULL, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 428 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 429 { 148500000ULL, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 430 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 431 { 146250000ULL, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 432 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 433 { 119000000ULL, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 434 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 435 { 106500000ULL, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 436 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 437 { 108000000ULL, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 438 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 439 { 85500000ULL, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 440 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 441 { 83500000ULL, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 442 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 443 { 92812500ULL, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 444 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 445 { 74250000ULL, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 446 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 447 { 65000000ULL, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 448 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 449 { 50250000ULL, 84, 84, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 11, 1, 4, 5, 450 4, 11, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 451 { 33750000ULL, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 452 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 453 { 40000000ULL, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 454 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 455 { 27000000ULL, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 456 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 457 { 25175000ULL, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 458 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, 459}; 460 461static const struct reg_sequence rk_hdtpx_common_cmn_init_seq[] = { 462 REG_SEQ0(CMN_REG(0009), 0x0c), 463 REG_SEQ0(CMN_REG(000a), 0x83), 464 REG_SEQ0(CMN_REG(000b), 0x06), 465 REG_SEQ0(CMN_REG(000c), 0x20), 466 REG_SEQ0(CMN_REG(000d), 0xb8), 467 REG_SEQ0(CMN_REG(000e), 0x0f), 468 REG_SEQ0(CMN_REG(000f), 0x0f), 469 REG_SEQ0(CMN_REG(0010), 0x04), 470 REG_SEQ0(CMN_REG(0011), 0x00), 471 REG_SEQ0(CMN_REG(0012), 0x26), 472 REG_SEQ0(CMN_REG(0013), 0x22), 473 REG_SEQ0(CMN_REG(0014), 0x24), 474 REG_SEQ0(CMN_REG(0015), 0x77), 475 REG_SEQ0(CMN_REG(0016), 0x08), 476 REG_SEQ0(CMN_REG(0017), 0x00), 477 REG_SEQ0(CMN_REG(0018), 0x04), 478 REG_SEQ0(CMN_REG(0019), 0x48), 479 REG_SEQ0(CMN_REG(001a), 0x01), 480 REG_SEQ0(CMN_REG(001b), 0x00), 481 REG_SEQ0(CMN_REG(001c), 0x01), 482 REG_SEQ0(CMN_REG(001d), 0x64), 483 REG_SEQ0(CMN_REG(001f), 0x00), 484 REG_SEQ0(CMN_REG(0026), 0x53), 485 REG_SEQ0(CMN_REG(0029), 0x01), 486 REG_SEQ0(CMN_REG(0030), 0x00), 487 REG_SEQ0(CMN_REG(0031), 0x20), 488 REG_SEQ0(CMN_REG(0032), 0x30), 489 REG_SEQ0(CMN_REG(0033), 0x0b), 490 REG_SEQ0(CMN_REG(0034), 0x23), 491 REG_SEQ0(CMN_REG(0035), 0x00), 492 REG_SEQ0(CMN_REG(0038), 0x00), 493 REG_SEQ0(CMN_REG(0039), 0x00), 494 REG_SEQ0(CMN_REG(003a), 0x00), 495 REG_SEQ0(CMN_REG(003b), 0x00), 496 REG_SEQ0(CMN_REG(003c), 0x80), 497 REG_SEQ0(CMN_REG(003e), 0x0c), 498 REG_SEQ0(CMN_REG(003f), 0x83), 499 REG_SEQ0(CMN_REG(0040), 0x06), 500 REG_SEQ0(CMN_REG(0041), 0x20), 501 REG_SEQ0(CMN_REG(0042), 0xb8), 502 REG_SEQ0(CMN_REG(0043), 0x00), 503 REG_SEQ0(CMN_REG(0044), 0x46), 504 REG_SEQ0(CMN_REG(0045), 0x24), 505 REG_SEQ0(CMN_REG(0047), 0x00), 506 REG_SEQ0(CMN_REG(0049), 0xfa), 507 REG_SEQ0(CMN_REG(004a), 0x08), 508 REG_SEQ0(CMN_REG(004b), 0x00), 509 REG_SEQ0(CMN_REG(004c), 0x01), 510 REG_SEQ0(CMN_REG(004d), 0x64), 511 REG_SEQ0(CMN_REG(004e), 0x14), 512 REG_SEQ0(CMN_REG(004f), 0x00), 513 REG_SEQ0(CMN_REG(0050), 0x00), 514 REG_SEQ0(CMN_REG(005d), 0x0c), 515 REG_SEQ0(CMN_REG(005f), 0x01), 516 REG_SEQ0(CMN_REG(006b), 0x04), 517 REG_SEQ0(CMN_REG(0073), 0x30), 518 REG_SEQ0(CMN_REG(0074), 0x00), 519 REG_SEQ0(CMN_REG(0075), 0x20), 520 REG_SEQ0(CMN_REG(0076), 0x30), 521 REG_SEQ0(CMN_REG(0077), 0x08), 522 REG_SEQ0(CMN_REG(0078), 0x0c), 523 REG_SEQ0(CMN_REG(0079), 0x00), 524 REG_SEQ0(CMN_REG(007b), 0x00), 525 REG_SEQ0(CMN_REG(007c), 0x00), 526 REG_SEQ0(CMN_REG(007d), 0x00), 527 REG_SEQ0(CMN_REG(007e), 0x00), 528 REG_SEQ0(CMN_REG(007f), 0x00), 529 REG_SEQ0(CMN_REG(0080), 0x00), 530 REG_SEQ0(CMN_REG(0081), 0x09), 531 REG_SEQ0(CMN_REG(0082), 0x04), 532 REG_SEQ0(CMN_REG(0083), 0x24), 533 REG_SEQ0(CMN_REG(0084), 0x20), 534 REG_SEQ0(CMN_REG(0085), 0x03), 535 REG_SEQ0(CMN_REG(0086), 0x01), 536 REG_SEQ0(CMN_REG(0087), 0x0c), 537 REG_SEQ0(CMN_REG(008a), 0x55), 538 REG_SEQ0(CMN_REG(008b), 0x25), 539 REG_SEQ0(CMN_REG(008c), 0x2c), 540 REG_SEQ0(CMN_REG(008d), 0x22), 541 REG_SEQ0(CMN_REG(008e), 0x14), 542 REG_SEQ0(CMN_REG(008f), 0x20), 543 REG_SEQ0(CMN_REG(0090), 0x00), 544 REG_SEQ0(CMN_REG(0091), 0x00), 545 REG_SEQ0(CMN_REG(0092), 0x00), 546 REG_SEQ0(CMN_REG(0093), 0x00), 547 REG_SEQ0(CMN_REG(009a), 0x11), 548 REG_SEQ0(CMN_REG(009b), 0x10), 549}; 550 551static const struct reg_sequence rk_hdtpx_tmds_cmn_init_seq[] = { 552 REG_SEQ0(CMN_REG(0008), 0x00), 553 REG_SEQ0(CMN_REG(0011), 0x01), 554 REG_SEQ0(CMN_REG(0017), 0x20), 555 REG_SEQ0(CMN_REG(001e), 0x14), 556 REG_SEQ0(CMN_REG(0020), 0x00), 557 REG_SEQ0(CMN_REG(0021), 0x00), 558 REG_SEQ0(CMN_REG(0022), 0x11), 559 REG_SEQ0(CMN_REG(0023), 0x00), 560 REG_SEQ0(CMN_REG(0024), 0x00), 561 REG_SEQ0(CMN_REG(0025), 0x53), 562 REG_SEQ0(CMN_REG(0026), 0x00), 563 REG_SEQ0(CMN_REG(0027), 0x00), 564 REG_SEQ0(CMN_REG(0028), 0x01), 565 REG_SEQ0(CMN_REG(002a), 0x00), 566 REG_SEQ0(CMN_REG(002b), 0x00), 567 REG_SEQ0(CMN_REG(002c), 0x00), 568 REG_SEQ0(CMN_REG(002d), 0x00), 569 REG_SEQ0(CMN_REG(002e), 0x04), 570 REG_SEQ0(CMN_REG(002f), 0x00), 571 REG_SEQ0(CMN_REG(0030), 0x20), 572 REG_SEQ0(CMN_REG(0031), 0x30), 573 REG_SEQ0(CMN_REG(0032), 0x0b), 574 REG_SEQ0(CMN_REG(0033), 0x23), 575 REG_SEQ0(CMN_REG(0034), 0x00), 576 REG_SEQ0(CMN_REG(003d), 0x40), 577 REG_SEQ0(CMN_REG(0042), 0x78), 578 REG_SEQ0(CMN_REG(0046), 0xdd), 579 REG_SEQ0(CMN_REG(0048), 0x11), 580 REG_SEQ0(CMN_REG(004e), 0x34), 581 REG_SEQ0(CMN_REG(005c), 0x25), 582 REG_SEQ0(CMN_REG(005e), 0x4f), 583 REG_SEQ0(CMN_REG(0074), 0x04), 584 REG_SEQ0(CMN_REG(0081), 0x01), 585 REG_SEQ0(CMN_REG(0087), 0x04), 586 REG_SEQ0(CMN_REG(0089), 0x00), 587 REG_SEQ0(CMN_REG(0095), 0x00), 588 REG_SEQ0(CMN_REG(0097), 0x02), 589 REG_SEQ0(CMN_REG(0099), 0x04), 590 REG_SEQ0(CMN_REG(009b), 0x00), 591}; 592 593static const struct reg_sequence rk_hdtpx_common_sb_init_seq[] = { 594 REG_SEQ0(SB_REG(0114), 0x00), 595 REG_SEQ0(SB_REG(0115), 0x00), 596 REG_SEQ0(SB_REG(0116), 0x00), 597 REG_SEQ0(SB_REG(0117), 0x00), 598}; 599 600static const struct reg_sequence rk_hdtpx_tmds_lntop_highbr_seq[] = { 601 REG_SEQ0(LNTOP_REG(0201), 0x00), 602 REG_SEQ0(LNTOP_REG(0202), 0x00), 603 REG_SEQ0(LNTOP_REG(0203), 0x0f), 604 REG_SEQ0(LNTOP_REG(0204), 0xff), 605 REG_SEQ0(LNTOP_REG(0205), 0xff), 606}; 607 608static const struct reg_sequence rk_hdtpx_tmds_lntop_lowbr_seq[] = { 609 REG_SEQ0(LNTOP_REG(0201), 0x07), 610 REG_SEQ0(LNTOP_REG(0202), 0xc1), 611 REG_SEQ0(LNTOP_REG(0203), 0xf0), 612 REG_SEQ0(LNTOP_REG(0204), 0x7c), 613 REG_SEQ0(LNTOP_REG(0205), 0x1f), 614}; 615 616static const struct reg_sequence rk_hdtpx_common_lane_init_seq[] = { 617 REG_SEQ0(LANE_REG(0303), 0x0c), 618 REG_SEQ0(LANE_REG(0307), 0x20), 619 REG_SEQ0(LANE_REG(030a), 0x17), 620 REG_SEQ0(LANE_REG(030b), 0x77), 621 REG_SEQ0(LANE_REG(030c), 0x77), 622 REG_SEQ0(LANE_REG(030d), 0x77), 623 REG_SEQ0(LANE_REG(030e), 0x38), 624 REG_SEQ0(LANE_REG(0310), 0x03), 625 REG_SEQ0(LANE_REG(0311), 0x0f), 626 REG_SEQ0(LANE_REG(0316), 0x02), 627 REG_SEQ0(LANE_REG(031b), 0x01), 628 REG_SEQ0(LANE_REG(031f), 0x15), 629 REG_SEQ0(LANE_REG(0320), 0xa0), 630 REG_SEQ0(LANE_REG(0403), 0x0c), 631 REG_SEQ0(LANE_REG(0407), 0x20), 632 REG_SEQ0(LANE_REG(040a), 0x17), 633 REG_SEQ0(LANE_REG(040b), 0x77), 634 REG_SEQ0(LANE_REG(040c), 0x77), 635 REG_SEQ0(LANE_REG(040d), 0x77), 636 REG_SEQ0(LANE_REG(040e), 0x38), 637 REG_SEQ0(LANE_REG(0410), 0x03), 638 REG_SEQ0(LANE_REG(0411), 0x0f), 639 REG_SEQ0(LANE_REG(0416), 0x02), 640 REG_SEQ0(LANE_REG(041b), 0x01), 641 REG_SEQ0(LANE_REG(041f), 0x15), 642 REG_SEQ0(LANE_REG(0420), 0xa0), 643 REG_SEQ0(LANE_REG(0503), 0x0c), 644 REG_SEQ0(LANE_REG(0507), 0x20), 645 REG_SEQ0(LANE_REG(050a), 0x17), 646 REG_SEQ0(LANE_REG(050b), 0x77), 647 REG_SEQ0(LANE_REG(050c), 0x77), 648 REG_SEQ0(LANE_REG(050d), 0x77), 649 REG_SEQ0(LANE_REG(050e), 0x38), 650 REG_SEQ0(LANE_REG(0510), 0x03), 651 REG_SEQ0(LANE_REG(0511), 0x0f), 652 REG_SEQ0(LANE_REG(0516), 0x02), 653 REG_SEQ0(LANE_REG(051b), 0x01), 654 REG_SEQ0(LANE_REG(051f), 0x15), 655 REG_SEQ0(LANE_REG(0520), 0xa0), 656 REG_SEQ0(LANE_REG(0603), 0x0c), 657 REG_SEQ0(LANE_REG(0607), 0x20), 658 REG_SEQ0(LANE_REG(060a), 0x17), 659 REG_SEQ0(LANE_REG(060b), 0x77), 660 REG_SEQ0(LANE_REG(060c), 0x77), 661 REG_SEQ0(LANE_REG(060d), 0x77), 662 REG_SEQ0(LANE_REG(060e), 0x38), 663 REG_SEQ0(LANE_REG(0610), 0x03), 664 REG_SEQ0(LANE_REG(0611), 0x0f), 665 REG_SEQ0(LANE_REG(0616), 0x02), 666 REG_SEQ0(LANE_REG(061b), 0x01), 667 REG_SEQ0(LANE_REG(061f), 0x15), 668 REG_SEQ0(LANE_REG(0620), 0xa0), 669}; 670 671static const struct reg_sequence rk_hdtpx_tmds_lane_init_seq[] = { 672 REG_SEQ0(LANE_REG(0312), 0x00), 673 REG_SEQ0(LANE_REG(0412), 0x00), 674 REG_SEQ0(LANE_REG(0512), 0x00), 675 REG_SEQ0(LANE_REG(0612), 0x00), 676 REG_SEQ0(LANE_REG(0303), 0x2f), 677 REG_SEQ0(LANE_REG(0403), 0x2f), 678 REG_SEQ0(LANE_REG(0503), 0x2f), 679 REG_SEQ0(LANE_REG(0603), 0x2f), 680 REG_SEQ0(LANE_REG(0305), 0x03), 681 REG_SEQ0(LANE_REG(0405), 0x03), 682 REG_SEQ0(LANE_REG(0505), 0x03), 683 REG_SEQ0(LANE_REG(0605), 0x03), 684 REG_SEQ0(LANE_REG(0306), 0x1c), 685 REG_SEQ0(LANE_REG(0406), 0x1c), 686 REG_SEQ0(LANE_REG(0506), 0x1c), 687 REG_SEQ0(LANE_REG(0606), 0x1c), 688 /* Keep Inter-Pair Skew in the limits */ 689 REG_SEQ0(LANE_REG(031e), 0x02), 690 REG_SEQ0(LANE_REG(041e), 0x02), 691 REG_SEQ0(LANE_REG(051e), 0x02), 692 REG_SEQ0(LANE_REG(061e), 0x0a), 693}; 694 695static struct tx_drv_ctrl tx_drv_ctrl_rbr[4][4] = { 696 /* voltage swing 0, pre-emphasis 0->3 */ 697 { 698 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 699 { 0x4, 0x3, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 700 { 0x7, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 701 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 702 }, 703 704 /* voltage swing 1, pre-emphasis 0->2 */ 705 { 706 { 0x4, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 707 { 0x9, 0x5, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 708 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 709 }, 710 711 /* voltage swing 2, pre-emphasis 0->1 */ 712 { 713 { 0x8, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 714 { 0xc, 0x5, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 715 }, 716 717 /* voltage swing 3, pre-emphasis 0 */ 718 { 719 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 720 } 721}; 722 723static struct tx_drv_ctrl tx_drv_ctrl_hbr[4][4] = { 724 /* voltage swing 0, pre-emphasis 0->3 */ 725 { 726 { 0x2, 0x0, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 727 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 728 { 0x9, 0x8, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 729 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 730 }, 731 732 /* voltage swing 1, pre-emphasis 0->2 */ 733 { 734 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 735 { 0xa, 0x6, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 736 { 0xc, 0x8, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 737 }, 738 739 /* voltage swing 2, pre-emphasis 0->1 */ 740 { 741 { 0x9, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 742 { 0xd, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 743 }, 744 745 /* voltage swing 3, pre-emphasis 0 */ 746 { 747 { 0xc, 0x1, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 748 } 749}; 750 751static struct tx_drv_ctrl tx_drv_ctrl_hbr2[4][4] = { 752 /* voltage swing 0, pre-emphasis 0->3 */ 753 { 754 { 0x2, 0x1, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 755 { 0x5, 0x4, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 756 { 0x9, 0x8, 0x4, 0x6, 0x1, 0x4, 0x0, 0x1, 0x7, 0x7 }, 757 { 0xd, 0xc, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 758 }, 759 760 /* voltage swing 1, pre-emphasis 0->2 */ 761 { 762 { 0x6, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 763 { 0xb, 0x7, 0x4, 0x6, 0x0, 0x4, 0x0, 0x1, 0x7, 0x7 }, 764 { 0xd, 0x9, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 765 }, 766 767 /* voltage swing 2, pre-emphasis 0->1 */ 768 { 769 { 0x8, 0x1, 0x4, 0x6, 0x0, 0x4, 0x1, 0x1, 0x7, 0x7 }, 770 { 0xc, 0x6, 0x7, 0x7, 0x1, 0x7, 0x0, 0x1, 0x7, 0x7 }, 771 }, 772 773 /* voltage swing 3, pre-emphasis 0 */ 774 { 775 { 0xb, 0x0, 0x7, 0x7, 0x1, 0x4, 0x1, 0x1, 0x7, 0x7 }, 776 } 777}; 778 779static bool rk_hdptx_phy_is_rw_reg(struct device *dev, unsigned int reg) 780{ 781 switch (reg) { 782 case 0x0000 ... 0x029c: /* CMN Register */ 783 case 0x0400 ... 0x04a4: /* Sideband Register */ 784 case 0x0800 ... 0x08a4: /* Lane Top Register */ 785 case 0x0c00 ... 0x0cb4: /* Lane 0 Register */ 786 case 0x1000 ... 0x10b4: /* Lane 1 Register */ 787 case 0x1400 ... 0x14b4: /* Lane 2 Register */ 788 case 0x1800 ... 0x18b4: /* Lane 3 Register */ 789 return true; 790 } 791 792 return false; 793} 794 795static const struct regmap_config rk_hdptx_phy_regmap_config = { 796 .reg_bits = 32, 797 .reg_stride = 4, 798 .val_bits = 32, 799 .writeable_reg = rk_hdptx_phy_is_rw_reg, 800 .readable_reg = rk_hdptx_phy_is_rw_reg, 801 .max_register = 0x18b4, 802}; 803 804#define rk_hdptx_multi_reg_write(hdptx, seq) \ 805 regmap_multi_reg_write((hdptx)->regmap, seq, ARRAY_SIZE(seq)) 806 807static void rk_hdptx_pre_power_up(struct rk_hdptx_phy *hdptx) 808{ 809 u32 val; 810 811 reset_control_assert(hdptx->rsts[RST_APB].rstc); 812 usleep_range(20, 25); 813 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 814 815 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 816 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 817 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 818 819 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 820 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 821} 822 823static int rk_hdptx_post_enable_lane(struct rk_hdptx_phy *hdptx) 824{ 825 u32 val; 826 int ret; 827 828 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); 829 830 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | 831 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 832 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 833 834 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 835 (val & HDPTX_O_PHY_RDY) && 836 (val & HDPTX_O_PLL_LOCK_DONE), 837 100, 5000); 838 if (ret) { 839 dev_err(hdptx->dev, "Failed to get PHY lane lock: %d\n", ret); 840 return ret; 841 } 842 843 dev_dbg(hdptx->dev, "PHY lane locked\n"); 844 845 return 0; 846} 847 848static int rk_hdptx_post_enable_pll(struct rk_hdptx_phy *hdptx) 849{ 850 u32 val; 851 int ret; 852 853 val = (HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16 | 854 HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN; 855 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 856 857 usleep_range(10, 15); 858 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 859 860 usleep_range(10, 15); 861 val = HDPTX_I_PLL_EN << 16 | HDPTX_I_PLL_EN; 862 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 863 864 usleep_range(10, 15); 865 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 866 867 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, val, 868 val & HDPTX_O_PHY_CLK_RDY, 20, 400); 869 if (ret) { 870 dev_err(hdptx->dev, "Failed to get PHY clk ready: %d\n", ret); 871 return ret; 872 } 873 874 dev_dbg(hdptx->dev, "PHY clk ready\n"); 875 876 return 0; 877} 878 879static void rk_hdptx_phy_disable(struct rk_hdptx_phy *hdptx) 880{ 881 u32 val; 882 883 reset_control_assert(hdptx->rsts[RST_APB].rstc); 884 usleep_range(20, 30); 885 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 886 887 regmap_write(hdptx->regmap, LANE_REG(0300), 0x82); 888 regmap_write(hdptx->regmap, SB_REG(010f), 0xc1); 889 regmap_write(hdptx->regmap, SB_REG(0110), 0x1); 890 regmap_write(hdptx->regmap, LANE_REG(0301), 0x80); 891 regmap_write(hdptx->regmap, LANE_REG(0401), 0x80); 892 regmap_write(hdptx->regmap, LANE_REG(0501), 0x80); 893 regmap_write(hdptx->regmap, LANE_REG(0601), 0x80); 894 895 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 896 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 897 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 898 899 val = (HDPTX_I_PLL_EN | HDPTX_I_BIAS_EN | HDPTX_I_BGR_EN) << 16; 900 regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); 901} 902 903static bool rk_hdptx_phy_clk_pll_calc(unsigned long long rate, 904 struct ropll_config *cfg) 905{ 906 const unsigned int fout = div_u64(rate, 200), fref = 24000; 907 unsigned long k = 0, lc, k_sub, lc_sub; 908 unsigned int fvco, sdc; 909 u32 mdiv, sdiv, n = 8; 910 911 if (fout > 0xfffffff) 912 return false; 913 914 for (sdiv = 16; sdiv >= 1; sdiv--) { 915 if (sdiv % 2 && sdiv != 1) 916 continue; 917 918 fvco = fout * sdiv; 919 920 if (fvco < 2000000 || fvco > 4000000) 921 continue; 922 923 mdiv = DIV_ROUND_UP(fvco, fref); 924 if (mdiv < 20 || mdiv > 255) 925 continue; 926 927 if (fref * mdiv - fvco) { 928 for (sdc = 264000; sdc <= 750000; sdc += fref) 929 if (sdc * n > fref * mdiv) 930 break; 931 932 if (sdc > 750000) 933 continue; 934 935 rational_best_approximation(fref * mdiv - fvco, 936 sdc / 16, 937 GENMASK(6, 0), 938 GENMASK(7, 0), 939 &k, &lc); 940 941 rational_best_approximation(sdc * n - fref * mdiv, 942 sdc, 943 GENMASK(6, 0), 944 GENMASK(7, 0), 945 &k_sub, &lc_sub); 946 } 947 948 break; 949 } 950 951 if (sdiv < 1) 952 return false; 953 954 if (cfg) { 955 cfg->pms_mdiv = mdiv; 956 cfg->pms_mdiv_afc = mdiv; 957 cfg->pms_pdiv = 1; 958 cfg->pms_refdiv = 1; 959 cfg->pms_sdiv = sdiv - 1; 960 961 cfg->sdm_en = k > 0 ? 1 : 0; 962 if (cfg->sdm_en) { 963 cfg->sdm_deno = lc; 964 cfg->sdm_num_sign = 1; 965 cfg->sdm_num = k; 966 cfg->sdc_n = n - 3; 967 cfg->sdc_num = k_sub; 968 cfg->sdc_deno = lc_sub; 969 } 970 } 971 972 return true; 973} 974 975static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) 976{ 977 const struct ropll_config *cfg = NULL; 978 struct ropll_config rc = {0}; 979 int ret, i; 980 981 if (!hdptx->hdmi_cfg.tmds_char_rate) 982 return 0; 983 984 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 985 if (hdptx->hdmi_cfg.tmds_char_rate == ropll_tmds_cfg[i].rate) { 986 cfg = &ropll_tmds_cfg[i]; 987 break; 988 } 989 990 if (!cfg) { 991 if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) { 992 dev_err(hdptx->dev, "%s cannot find pll cfg for rate=%llu\n", 993 __func__, hdptx->hdmi_cfg.tmds_char_rate); 994 return -EINVAL; 995 } 996 997 cfg = &rc; 998 } 999 1000 dev_dbg(hdptx->dev, "%s rate=%llu mdiv=%u sdiv=%u sdm_en=%u k_sign=%u k=%u lc=%u\n", 1001 __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, 1002 cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); 1003 1004 rk_hdptx_pre_power_up(hdptx); 1005 1006 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_cmn_init_seq); 1007 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_cmn_init_seq); 1008 1009 regmap_write(hdptx->regmap, CMN_REG(0051), cfg->pms_mdiv); 1010 regmap_write(hdptx->regmap, CMN_REG(0055), cfg->pms_mdiv_afc); 1011 regmap_write(hdptx->regmap, CMN_REG(0059), 1012 (cfg->pms_pdiv << 4) | cfg->pms_refdiv); 1013 regmap_write(hdptx->regmap, CMN_REG(005a), cfg->pms_sdiv << 4); 1014 1015 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, 1016 FIELD_PREP(ROPLL_SDM_EN_MASK, cfg->sdm_en)); 1017 if (!cfg->sdm_en) 1018 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 0xf, 0); 1019 1020 regmap_update_bits(hdptx->regmap, CMN_REG(0064), ROPLL_SDM_NUM_SIGN_RBR_MASK, 1021 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, cfg->sdm_num_sign)); 1022 1023 regmap_write(hdptx->regmap, CMN_REG(0060), cfg->sdm_deno); 1024 regmap_write(hdptx->regmap, CMN_REG(0065), cfg->sdm_num); 1025 1026 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, 1027 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, cfg->sdc_n)); 1028 1029 regmap_write(hdptx->regmap, CMN_REG(006c), cfg->sdc_num); 1030 regmap_write(hdptx->regmap, CMN_REG(0070), cfg->sdc_deno); 1031 1032 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, 1033 FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); 1034 1035 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, 1036 FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); 1037 1038 regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, 1039 FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); 1040 1041 ret = rk_hdptx_post_enable_pll(hdptx); 1042 if (!ret) 1043 hdptx->hw_rate = DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, 1044 hdptx->hdmi_cfg.bpc); 1045 1046 return ret; 1047} 1048 1049static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) 1050{ 1051 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); 1052 1053 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); 1054 1055 if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { 1056 /* For 1/40 bitrate clk */ 1057 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); 1058 } else { 1059 /* For 1/10 bitrate clk */ 1060 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_lowbr_seq); 1061 } 1062 1063 regmap_write(hdptx->regmap, LNTOP_REG(0206), 0x07); 1064 regmap_write(hdptx->regmap, LNTOP_REG(0207), 0x0f); 1065 1066 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_lane_init_seq); 1067 rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lane_init_seq); 1068 1069 return rk_hdptx_post_enable_lane(hdptx); 1070} 1071 1072static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hdptx) 1073{ 1074 reset_control_assert(hdptx->rsts[RST_LANE].rstc); 1075 reset_control_assert(hdptx->rsts[RST_CMN].rstc); 1076 reset_control_assert(hdptx->rsts[RST_INIT].rstc); 1077 1078 reset_control_assert(hdptx->rsts[RST_APB].rstc); 1079 udelay(10); 1080 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 1081 1082 regmap_update_bits(hdptx->regmap, LANE_REG(0301), 1083 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1084 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1085 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1086 regmap_update_bits(hdptx->regmap, LANE_REG(0401), 1087 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1088 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1089 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1090 regmap_update_bits(hdptx->regmap, LANE_REG(0501), 1091 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1092 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1093 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1094 regmap_update_bits(hdptx->regmap, LANE_REG(0601), 1095 OVRD_LN_TX_DRV_EI_EN_MASK | LN_TX_DRV_EI_EN_MASK, 1096 FIELD_PREP(OVRD_LN_TX_DRV_EI_EN_MASK, 1) | 1097 FIELD_PREP(LN_TX_DRV_EI_EN_MASK, 0)); 1098 1099 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1100 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); 1101 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1102 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x0)); 1103 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1104 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); 1105} 1106 1107static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx) 1108{ 1109 enum phy_mode mode = phy_get_mode(hdptx->phy); 1110 u32 status; 1111 int ret; 1112 1113 if (atomic_inc_return(&hdptx->usage_count) > 1) 1114 return 0; 1115 1116 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); 1117 if (ret) 1118 goto dec_usage; 1119 1120 if (status & HDPTX_O_PLL_LOCK_DONE) 1121 dev_warn(hdptx->dev, "PLL locked by unknown consumer!\n"); 1122 1123 if (mode == PHY_MODE_DP) { 1124 rk_hdptx_dp_reset(hdptx); 1125 } else { 1126 ret = rk_hdptx_ropll_tmds_cmn_config(hdptx); 1127 if (ret) 1128 goto dec_usage; 1129 } 1130 1131 return 0; 1132 1133dec_usage: 1134 atomic_dec(&hdptx->usage_count); 1135 return ret; 1136} 1137 1138static int rk_hdptx_phy_consumer_put(struct rk_hdptx_phy *hdptx, bool force) 1139{ 1140 enum phy_mode mode = phy_get_mode(hdptx->phy); 1141 u32 status; 1142 int ret; 1143 1144 ret = atomic_dec_return(&hdptx->usage_count); 1145 if (ret > 0) 1146 return 0; 1147 1148 if (ret < 0) { 1149 dev_warn(hdptx->dev, "Usage count underflow!\n"); 1150 ret = -EINVAL; 1151 } else { 1152 ret = regmap_read(hdptx->grf, GRF_HDPTX_STATUS, &status); 1153 if (!ret) { 1154 if (status & HDPTX_O_PLL_LOCK_DONE) { 1155 if (mode == PHY_MODE_DP) 1156 rk_hdptx_dp_reset(hdptx); 1157 else 1158 rk_hdptx_phy_disable(hdptx); 1159 } 1160 return 0; 1161 } else if (force) { 1162 return 0; 1163 } 1164 } 1165 1166 atomic_inc(&hdptx->usage_count); 1167 return ret; 1168} 1169 1170static void rk_hdptx_dp_pll_init(struct rk_hdptx_phy *hdptx) 1171{ 1172 regmap_update_bits(hdptx->regmap, CMN_REG(003c), ANA_LCPLL_RESERVED7_MASK, 1173 FIELD_PREP(ANA_LCPLL_RESERVED7_MASK, 0x1)); 1174 1175 regmap_update_bits(hdptx->regmap, CMN_REG(0046), 1176 ROPLL_ANA_CPP_CTRL_COARSE_MASK | ROPLL_ANA_CPP_CTRL_FINE_MASK, 1177 FIELD_PREP(ROPLL_ANA_CPP_CTRL_COARSE_MASK, 0xe) | 1178 FIELD_PREP(ROPLL_ANA_CPP_CTRL_FINE_MASK, 0xe)); 1179 regmap_update_bits(hdptx->regmap, CMN_REG(0047), 1180 ROPLL_ANA_LPF_C_SEL_COARSE_MASK | 1181 ROPLL_ANA_LPF_C_SEL_FINE_MASK, 1182 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_COARSE_MASK, 0x4) | 1183 FIELD_PREP(ROPLL_ANA_LPF_C_SEL_FINE_MASK, 0x4)); 1184 1185 regmap_write(hdptx->regmap, CMN_REG(0051), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x87)); 1186 regmap_write(hdptx->regmap, CMN_REG(0052), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71)); 1187 regmap_write(hdptx->regmap, CMN_REG(0053), FIELD_PREP(ROPLL_PMS_MDIV_MASK, 0x71)); 1188 1189 regmap_write(hdptx->regmap, CMN_REG(0055), 1190 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x87)); 1191 regmap_write(hdptx->regmap, CMN_REG(0056), 1192 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71)); 1193 regmap_write(hdptx->regmap, CMN_REG(0057), 1194 FIELD_PREP(ROPLL_PMS_MDIV_AFC_MASK, 0x71)); 1195 1196 regmap_write(hdptx->regmap, CMN_REG(0059), 1197 FIELD_PREP(ANA_ROPLL_PMS_PDIV_MASK, 0x1) | 1198 FIELD_PREP(ANA_ROPLL_PMS_REFDIV_MASK, 0x1)); 1199 regmap_write(hdptx->regmap, CMN_REG(005a), 1200 FIELD_PREP(ROPLL_PMS_SDIV_RBR_MASK, 0x3) | 1201 FIELD_PREP(ROPLL_PMS_SDIV_HBR_MASK, 0x1)); 1202 regmap_update_bits(hdptx->regmap, CMN_REG(005b), ROPLL_PMS_SDIV_HBR2_MASK, 1203 FIELD_PREP(ROPLL_PMS_SDIV_HBR2_MASK, 0x0)); 1204 1205 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDM_EN_MASK, 1206 FIELD_PREP(ROPLL_SDM_EN_MASK, 0x1)); 1207 regmap_update_bits(hdptx->regmap, CMN_REG(005e), 1208 OVRD_ROPLL_SDM_RSTN_MASK | ROPLL_SDM_RSTN_MASK, 1209 FIELD_PREP(OVRD_ROPLL_SDM_RSTN_MASK, 0x1) | 1210 FIELD_PREP(ROPLL_SDM_RSTN_MASK, 0x1)); 1211 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_RBR_MASK, 1212 FIELD_PREP(ROPLL_SDC_FRAC_EN_RBR_MASK, 0x1)); 1213 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR_MASK, 1214 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR_MASK, 0x1)); 1215 regmap_update_bits(hdptx->regmap, CMN_REG(005e), ROPLL_SDC_FRAC_EN_HBR2_MASK, 1216 FIELD_PREP(ROPLL_SDC_FRAC_EN_HBR2_MASK, 0x1)); 1217 1218 regmap_update_bits(hdptx->regmap, CMN_REG(005f), 1219 OVRD_ROPLL_SDC_RSTN_MASK | ROPLL_SDC_RSTN_MASK, 1220 FIELD_PREP(OVRD_ROPLL_SDC_RSTN_MASK, 0x1) | 1221 FIELD_PREP(ROPLL_SDC_RSTN_MASK, 0x1)); 1222 regmap_write(hdptx->regmap, CMN_REG(0060), 1223 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x21)); 1224 regmap_write(hdptx->regmap, CMN_REG(0061), 1225 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27)); 1226 regmap_write(hdptx->regmap, CMN_REG(0062), 1227 FIELD_PREP(ROPLL_SDM_DENOMINATOR_MASK, 0x27)); 1228 1229 regmap_update_bits(hdptx->regmap, CMN_REG(0064), 1230 ROPLL_SDM_NUM_SIGN_RBR_MASK | 1231 ROPLL_SDM_NUM_SIGN_HBR_MASK | 1232 ROPLL_SDM_NUM_SIGN_HBR2_MASK, 1233 FIELD_PREP(ROPLL_SDM_NUM_SIGN_RBR_MASK, 0x0) | 1234 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR_MASK, 0x1) | 1235 FIELD_PREP(ROPLL_SDM_NUM_SIGN_HBR2_MASK, 0x1)); 1236 regmap_write(hdptx->regmap, CMN_REG(0065), 1237 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0x0)); 1238 regmap_write(hdptx->regmap, CMN_REG(0066), 1239 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd)); 1240 regmap_write(hdptx->regmap, CMN_REG(0067), 1241 FIELD_PREP(ROPLL_SDM_NUM_MASK, 0xd)); 1242 1243 regmap_update_bits(hdptx->regmap, CMN_REG(0069), ROPLL_SDC_N_RBR_MASK, 1244 FIELD_PREP(ROPLL_SDC_N_RBR_MASK, 0x2)); 1245 1246 regmap_update_bits(hdptx->regmap, CMN_REG(006a), 1247 ROPLL_SDC_N_HBR_MASK | ROPLL_SDC_N_HBR2_MASK, 1248 FIELD_PREP(ROPLL_SDC_N_HBR_MASK, 0x1) | 1249 FIELD_PREP(ROPLL_SDC_N_HBR2_MASK, 0x1)); 1250 1251 regmap_write(hdptx->regmap, CMN_REG(006c), 1252 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x3)); 1253 regmap_write(hdptx->regmap, CMN_REG(006d), 1254 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7)); 1255 regmap_write(hdptx->regmap, CMN_REG(006e), 1256 FIELD_PREP(ROPLL_SDC_NUM_MASK, 0x7)); 1257 1258 regmap_write(hdptx->regmap, CMN_REG(0070), 1259 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x8)); 1260 regmap_write(hdptx->regmap, CMN_REG(0071), 1261 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18)); 1262 regmap_write(hdptx->regmap, CMN_REG(0072), 1263 FIELD_PREP(ROPLL_SDC_DENO_MASK, 0x18)); 1264 1265 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1266 OVRD_ROPLL_SDC_NDIV_RSTN_MASK | ROPLL_SDC_NDIV_RSTN_MASK, 1267 FIELD_PREP(OVRD_ROPLL_SDC_NDIV_RSTN_MASK, 0x1) | 1268 FIELD_PREP(ROPLL_SDC_NDIV_RSTN_MASK, 0x1)); 1269 1270 regmap_update_bits(hdptx->regmap, CMN_REG(0077), ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 1271 FIELD_PREP(ANA_ROPLL_SSC_CLK_DIV_SEL_MASK, 0x1)); 1272 1273 regmap_update_bits(hdptx->regmap, CMN_REG(0081), ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 1274 FIELD_PREP(ANA_PLL_CD_TX_SER_RATE_SEL_MASK, 0x0)); 1275 regmap_update_bits(hdptx->regmap, CMN_REG(0081), 1276 ANA_PLL_CD_HSCLK_EAST_EN_MASK | ANA_PLL_CD_HSCLK_WEST_EN_MASK, 1277 FIELD_PREP(ANA_PLL_CD_HSCLK_EAST_EN_MASK, 0x1) | 1278 FIELD_PREP(ANA_PLL_CD_HSCLK_WEST_EN_MASK, 0x0)); 1279 1280 regmap_update_bits(hdptx->regmap, CMN_REG(0082), ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 1281 FIELD_PREP(ANA_PLL_CD_VREG_GAIN_CTRL_MASK, 0x4)); 1282 regmap_update_bits(hdptx->regmap, CMN_REG(0083), ANA_PLL_CD_VREG_ICTRL_MASK, 1283 FIELD_PREP(ANA_PLL_CD_VREG_ICTRL_MASK, 0x1)); 1284 regmap_update_bits(hdptx->regmap, CMN_REG(0084), PLL_LCRO_CLK_SEL_MASK, 1285 FIELD_PREP(PLL_LCRO_CLK_SEL_MASK, 0x1)); 1286 regmap_update_bits(hdptx->regmap, CMN_REG(0085), ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 1287 FIELD_PREP(ANA_PLL_SYNC_LOSS_DET_MODE_MASK, 0x3)); 1288 1289 regmap_update_bits(hdptx->regmap, CMN_REG(0087), ANA_PLL_TX_HS_CLK_EN_MASK, 1290 FIELD_PREP(ANA_PLL_TX_HS_CLK_EN_MASK, 0x1)); 1291 1292 regmap_update_bits(hdptx->regmap, CMN_REG(0097), DIG_CLK_SEL_MASK, 1293 FIELD_PREP(DIG_CLK_SEL_MASK, 0x1)); 1294 1295 regmap_update_bits(hdptx->regmap, CMN_REG(0099), CMN_ROPLL_ALONE_MODE_MASK, 1296 FIELD_PREP(CMN_ROPLL_ALONE_MODE_MASK, 0x1)); 1297 regmap_update_bits(hdptx->regmap, CMN_REG(009a), HS_SPEED_SEL_MASK, 1298 FIELD_PREP(HS_SPEED_SEL_MASK, 0x1)); 1299 regmap_update_bits(hdptx->regmap, CMN_REG(009b), LS_SPEED_SEL_MASK, 1300 FIELD_PREP(LS_SPEED_SEL_MASK, 0x1)); 1301} 1302 1303static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy *hdptx) 1304{ 1305 u32 status; 1306 int ret; 1307 1308 regmap_update_bits(hdptx->regmap, SB_REG(0102), ANA_SB_RXTERM_OFFSP_MASK, 1309 FIELD_PREP(ANA_SB_RXTERM_OFFSP_MASK, 0x3)); 1310 regmap_update_bits(hdptx->regmap, SB_REG(0103), ANA_SB_RXTERM_OFFSN_MASK, 1311 FIELD_PREP(ANA_SB_RXTERM_OFFSN_MASK, 0x3)); 1312 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK, 1313 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); 1314 regmap_update_bits(hdptx->regmap, SB_REG(0105), ANA_SB_TX_HLVL_PROG_MASK, 1315 FIELD_PREP(ANA_SB_TX_HLVL_PROG_MASK, 0x7)); 1316 regmap_update_bits(hdptx->regmap, SB_REG(0106), ANA_SB_TX_LLVL_PROG_MASK, 1317 FIELD_PREP(ANA_SB_TX_LLVL_PROG_MASK, 0x7)); 1318 1319 regmap_update_bits(hdptx->regmap, SB_REG(010d), ANA_SB_DMRX_LPBK_DATA_MASK, 1320 FIELD_PREP(ANA_SB_DMRX_LPBK_DATA_MASK, 0x1)); 1321 1322 regmap_update_bits(hdptx->regmap, SB_REG(010f), ANA_SB_VREG_GAIN_CTRL_MASK, 1323 FIELD_PREP(ANA_SB_VREG_GAIN_CTRL_MASK, 0x0)); 1324 regmap_update_bits(hdptx->regmap, SB_REG(0110), 1325 ANA_SB_VREG_OUT_SEL_MASK | ANA_SB_VREG_REF_SEL_MASK, 1326 FIELD_PREP(ANA_SB_VREG_OUT_SEL_MASK, 0x1) | 1327 FIELD_PREP(ANA_SB_VREG_REF_SEL_MASK, 0x1)); 1328 1329 regmap_update_bits(hdptx->regmap, SB_REG(0113), 1330 SB_RX_RCAL_OPT_CODE_MASK | SB_RX_RTERM_CTRL_MASK, 1331 FIELD_PREP(SB_RX_RCAL_OPT_CODE_MASK, 0x1) | 1332 FIELD_PREP(SB_RX_RTERM_CTRL_MASK, 0x3)); 1333 regmap_update_bits(hdptx->regmap, SB_REG(0114), 1334 SB_TG_SB_EN_DELAY_TIME_MASK | SB_TG_RXTERM_EN_DELAY_TIME_MASK, 1335 FIELD_PREP(SB_TG_SB_EN_DELAY_TIME_MASK, 0x2) | 1336 FIELD_PREP(SB_TG_RXTERM_EN_DELAY_TIME_MASK, 0x2)); 1337 regmap_update_bits(hdptx->regmap, SB_REG(0115), 1338 SB_READY_DELAY_TIME_MASK | SB_TG_OSC_EN_DELAY_TIME_MASK, 1339 FIELD_PREP(SB_READY_DELAY_TIME_MASK, 0x2) | 1340 FIELD_PREP(SB_TG_OSC_EN_DELAY_TIME_MASK, 0x2)); 1341 regmap_update_bits(hdptx->regmap, SB_REG(0116), 1342 AFC_RSTN_DELAY_TIME_MASK, 1343 FIELD_PREP(AFC_RSTN_DELAY_TIME_MASK, 0x2)); 1344 regmap_update_bits(hdptx->regmap, SB_REG(0117), 1345 FAST_PULSE_TIME_MASK, 1346 FIELD_PREP(FAST_PULSE_TIME_MASK, 0x4)); 1347 regmap_update_bits(hdptx->regmap, SB_REG(0118), 1348 SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 1349 FIELD_PREP(SB_TG_EARC_DMRX_RECVRD_CLK_CNT_MASK, 0xa)); 1350 1351 regmap_update_bits(hdptx->regmap, SB_REG(011a), SB_TG_CNT_RUN_NO_7_0_MASK, 1352 FIELD_PREP(SB_TG_CNT_RUN_NO_7_0_MASK, 0x3)); 1353 regmap_update_bits(hdptx->regmap, SB_REG(011b), 1354 SB_EARC_SIG_DET_BYPASS_MASK | SB_AFC_TOL_MASK, 1355 FIELD_PREP(SB_EARC_SIG_DET_BYPASS_MASK, 0x1) | 1356 FIELD_PREP(SB_AFC_TOL_MASK, 0x3)); 1357 regmap_update_bits(hdptx->regmap, SB_REG(011c), SB_AFC_STB_NUM_MASK, 1358 FIELD_PREP(SB_AFC_STB_NUM_MASK, 0x4)); 1359 regmap_update_bits(hdptx->regmap, SB_REG(011d), SB_TG_OSC_CNT_MIN_MASK, 1360 FIELD_PREP(SB_TG_OSC_CNT_MIN_MASK, 0x67)); 1361 regmap_update_bits(hdptx->regmap, SB_REG(011e), SB_TG_OSC_CNT_MAX_MASK, 1362 FIELD_PREP(SB_TG_OSC_CNT_MAX_MASK, 0x6a)); 1363 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_PWM_AFC_CTRL_MASK, 1364 FIELD_PREP(SB_PWM_AFC_CTRL_MASK, 0x5)); 1365 regmap_update_bits(hdptx->regmap, SB_REG(011f), SB_RCAL_RSTN_MASK, 1366 FIELD_PREP(SB_RCAL_RSTN_MASK, 0x1)); 1367 regmap_update_bits(hdptx->regmap, SB_REG(0120), SB_AUX_EN_IN_MASK, 1368 FIELD_PREP(SB_AUX_EN_IN_MASK, 0x1)); 1369 1370 regmap_update_bits(hdptx->regmap, SB_REG(0102), OVRD_SB_RXTERM_EN_MASK, 1371 FIELD_PREP(OVRD_SB_RXTERM_EN_MASK, 0x1)); 1372 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, 1373 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1)); 1374 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_EN_MASK, 1375 FIELD_PREP(OVRD_SB_EN_MASK, 0x1)); 1376 regmap_update_bits(hdptx->regmap, SB_REG(0104), OVRD_SB_AUX_EN_MASK, 1377 FIELD_PREP(OVRD_SB_AUX_EN_MASK, 0x1)); 1378 1379 regmap_update_bits(hdptx->regmap, SB_REG(010f), OVRD_SB_VREG_EN_MASK, 1380 FIELD_PREP(OVRD_SB_VREG_EN_MASK, 0x1)); 1381 1382 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1383 HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x1)); 1384 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1385 HDPTX_I_BIAS_EN << 16 | FIELD_PREP(HDPTX_I_BIAS_EN, 0x1)); 1386 usleep_range(20, 25); 1387 1388 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 1389 usleep_range(20, 25); 1390 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 1391 usleep_range(20, 25); 1392 1393 regmap_update_bits(hdptx->regmap, SB_REG(0103), OVRD_SB_RX_RESCAL_DONE_MASK, 1394 FIELD_PREP(OVRD_SB_RX_RESCAL_DONE_MASK, 0x1)); 1395 usleep_range(100, 110); 1396 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_EN_MASK, 1397 FIELD_PREP(SB_EN_MASK, 0x1)); 1398 usleep_range(100, 110); 1399 regmap_update_bits(hdptx->regmap, SB_REG(0102), SB_RXTERM_EN_MASK, 1400 FIELD_PREP(SB_RXTERM_EN_MASK, 0x1)); 1401 usleep_range(20, 25); 1402 regmap_update_bits(hdptx->regmap, SB_REG(010f), SB_VREG_EN_MASK, 1403 FIELD_PREP(SB_VREG_EN_MASK, 0x1)); 1404 usleep_range(20, 25); 1405 regmap_update_bits(hdptx->regmap, SB_REG(0104), SB_AUX_EN_MASK, 1406 FIELD_PREP(SB_AUX_EN_MASK, 0x1)); 1407 usleep_range(100, 110); 1408 1409 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1410 status, FIELD_GET(HDPTX_O_SB_RDY, status), 1411 50, 1000); 1412 if (ret) { 1413 dev_err(hdptx->dev, "Failed to get phy sb ready: %d\n", ret); 1414 return ret; 1415 } 1416 1417 return 0; 1418} 1419 1420static int rk_hdptx_phy_power_on(struct phy *phy) 1421{ 1422 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1423 enum phy_mode mode = phy_get_mode(phy); 1424 int ret, lane; 1425 1426 if (mode != PHY_MODE_DP) { 1427 if (!hdptx->hdmi_cfg.tmds_char_rate) { 1428 /* 1429 * FIXME: Temporary workaround to setup TMDS char rate 1430 * from the RK DW HDMI QP bridge driver. 1431 * Will be removed as soon the switch to the HDMI PHY 1432 * configuration API has been completed on both ends. 1433 */ 1434 hdptx->hdmi_cfg.tmds_char_rate = phy_get_bus_width(hdptx->phy) & 0xfffffff; 1435 hdptx->hdmi_cfg.tmds_char_rate *= 100; 1436 } 1437 1438 dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__, 1439 hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); 1440 } 1441 1442 ret = rk_hdptx_phy_consumer_get(hdptx); 1443 if (ret) 1444 return ret; 1445 1446 if (mode == PHY_MODE_DP) { 1447 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1448 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x1)); 1449 1450 for (lane = 0; lane < 4; lane++) { 1451 regmap_update_bits(hdptx->regmap, LANE_REG(031e) + 0x400 * lane, 1452 LN_POLARITY_INV_MASK | LN_LANE_MODE_MASK, 1453 FIELD_PREP(LN_POLARITY_INV_MASK, 0) | 1454 FIELD_PREP(LN_LANE_MODE_MASK, 1)); 1455 } 1456 1457 regmap_update_bits(hdptx->regmap, LNTOP_REG(0200), PROTOCOL_SEL_MASK, 1458 FIELD_PREP(PROTOCOL_SEL_MASK, 0x0)); 1459 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_MASK, 1460 FIELD_PREP(DATA_BUS_WIDTH_MASK, 0x1)); 1461 regmap_update_bits(hdptx->regmap, LNTOP_REG(0206), DATA_BUS_WIDTH_SEL_MASK, 1462 FIELD_PREP(DATA_BUS_WIDTH_SEL_MASK, 0x0)); 1463 1464 rk_hdptx_dp_pll_init(hdptx); 1465 1466 ret = rk_hdptx_dp_aux_init(hdptx); 1467 if (ret) 1468 rk_hdptx_phy_consumer_put(hdptx, true); 1469 } else { 1470 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1471 HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); 1472 1473 ret = rk_hdptx_ropll_tmds_mode_config(hdptx); 1474 if (ret) 1475 rk_hdptx_phy_consumer_put(hdptx, true); 1476 } 1477 1478 return ret; 1479} 1480 1481static int rk_hdptx_phy_power_off(struct phy *phy) 1482{ 1483 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1484 1485 return rk_hdptx_phy_consumer_put(hdptx, false); 1486} 1487 1488static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, 1489 struct phy_configure_opts_hdmi *hdmi) 1490{ 1491 int i; 1492 1493 if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) 1494 return -EINVAL; 1495 1496 for (i = 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) 1497 if (hdmi->tmds_char_rate == ropll_tmds_cfg[i].rate) 1498 break; 1499 1500 if (i == ARRAY_SIZE(ropll_tmds_cfg) && 1501 !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) 1502 return -EINVAL; 1503 1504 if (!hdmi->bpc) 1505 hdmi->bpc = 8; 1506 1507 switch (hdmi->bpc) { 1508 case 8: 1509 case 10: 1510 case 12: 1511 case 16: 1512 break; 1513 default: 1514 return -EINVAL; 1515 } 1516 1517 return 0; 1518} 1519 1520static int rk_hdptx_phy_verify_dp_config(struct rk_hdptx_phy *hdptx, 1521 struct phy_configure_opts_dp *dp) 1522{ 1523 int i; 1524 1525 if (dp->set_rate) { 1526 switch (dp->link_rate) { 1527 case 1620: 1528 case 2700: 1529 case 5400: 1530 break; 1531 default: 1532 return -EINVAL; 1533 } 1534 } 1535 1536 if (dp->set_lanes) { 1537 switch (dp->lanes) { 1538 case 1: 1539 case 2: 1540 case 4: 1541 break; 1542 default: 1543 return -EINVAL; 1544 } 1545 } 1546 1547 if (dp->set_voltages) { 1548 for (i = 0; i < hdptx->lanes; i++) { 1549 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1550 return -EINVAL; 1551 1552 if (dp->voltage[i] + dp->pre[i] > 3) 1553 return -EINVAL; 1554 } 1555 } 1556 1557 return 0; 1558} 1559 1560static int rk_hdptx_phy_set_rate(struct rk_hdptx_phy *hdptx, 1561 struct phy_configure_opts_dp *dp) 1562{ 1563 u32 bw, status; 1564 int ret; 1565 1566 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1567 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x0)); 1568 1569 switch (dp->link_rate) { 1570 case 1620: 1571 bw = DP_BW_RBR; 1572 break; 1573 case 2700: 1574 bw = DP_BW_HBR; 1575 break; 1576 case 5400: 1577 bw = DP_BW_HBR2; 1578 break; 1579 default: 1580 return -EINVAL; 1581 } 1582 hdptx->link_rate = dp->link_rate; 1583 1584 regmap_update_bits(hdptx->regmap, CMN_REG(0008), OVRD_LCPLL_EN_MASK | LCPLL_EN_MASK, 1585 FIELD_PREP(OVRD_LCPLL_EN_MASK, 0x1) | 1586 FIELD_PREP(LCPLL_EN_MASK, 0x0)); 1587 1588 regmap_update_bits(hdptx->regmap, CMN_REG(003d), OVRD_ROPLL_EN_MASK | ROPLL_EN_MASK, 1589 FIELD_PREP(OVRD_ROPLL_EN_MASK, 0x1) | 1590 FIELD_PREP(ROPLL_EN_MASK, 0x1)); 1591 1592 if (dp->ssc) { 1593 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1594 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK, 1595 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) | 1596 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x1)); 1597 regmap_write(hdptx->regmap, CMN_REG(0075), 1598 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0xc)); 1599 regmap_update_bits(hdptx->regmap, CMN_REG(0076), 1600 ANA_ROPLL_SSC_FM_FREQ_MASK, 1601 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0x1f)); 1602 1603 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK, 1604 FIELD_PREP(SSC_EN_MASK, 0x2)); 1605 } else { 1606 regmap_update_bits(hdptx->regmap, CMN_REG(0074), 1607 OVRD_ROPLL_SSC_EN_MASK | ROPLL_SSC_EN_MASK, 1608 FIELD_PREP(OVRD_ROPLL_SSC_EN_MASK, 0x1) | 1609 FIELD_PREP(ROPLL_SSC_EN_MASK, 0x0)); 1610 regmap_write(hdptx->regmap, CMN_REG(0075), 1611 FIELD_PREP(ANA_ROPLL_SSC_FM_DEVIATION_MASK, 0x20)); 1612 regmap_update_bits(hdptx->regmap, CMN_REG(0076), 1613 ANA_ROPLL_SSC_FM_FREQ_MASK, 1614 FIELD_PREP(ANA_ROPLL_SSC_FM_FREQ_MASK, 0xc)); 1615 1616 regmap_update_bits(hdptx->regmap, CMN_REG(0099), SSC_EN_MASK, 1617 FIELD_PREP(SSC_EN_MASK, 0x0)); 1618 } 1619 1620 regmap_update_bits(hdptx->regmap, CMN_REG(0095), DP_TX_LINK_BW_MASK, 1621 FIELD_PREP(DP_TX_LINK_BW_MASK, bw)); 1622 1623 regmap_write(hdptx->grf, GRF_HDPTX_CON0, 1624 HDPTX_I_PLL_EN << 16 | FIELD_PREP(HDPTX_I_PLL_EN, 0x1)); 1625 1626 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1627 status, FIELD_GET(HDPTX_O_PLL_LOCK_DONE, status), 1628 50, 1000); 1629 if (ret) { 1630 dev_err(hdptx->dev, "Failed to get phy pll lock: %d\n", ret); 1631 return ret; 1632 } 1633 1634 return 0; 1635} 1636 1637static int rk_hdptx_phy_set_lanes(struct rk_hdptx_phy *hdptx, 1638 struct phy_configure_opts_dp *dp) 1639{ 1640 hdptx->lanes = dp->lanes; 1641 1642 regmap_update_bits(hdptx->regmap, LNTOP_REG(0207), LANE_EN_MASK, 1643 FIELD_PREP(LANE_EN_MASK, GENMASK(hdptx->lanes - 1, 0))); 1644 1645 return 0; 1646} 1647 1648static void rk_hdptx_phy_set_voltage(struct rk_hdptx_phy *hdptx, 1649 struct phy_configure_opts_dp *dp, 1650 u8 lane) 1651{ 1652 const struct tx_drv_ctrl *ctrl; 1653 u32 offset = lane * 0x400; 1654 1655 switch (hdptx->link_rate) { 1656 case 1620: 1657 ctrl = &tx_drv_ctrl_rbr[dp->voltage[lane]][dp->pre[lane]]; 1658 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, 1659 LN_TX_JEQ_EVEN_CTRL_RBR_MASK, 1660 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_RBR_MASK, 1661 ctrl->tx_jeq_even_ctrl)); 1662 regmap_update_bits(hdptx->regmap, LANE_REG(030c) + offset, 1663 LN_TX_JEQ_ODD_CTRL_RBR_MASK, 1664 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_RBR_MASK, 1665 ctrl->tx_jeq_odd_ctrl)); 1666 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1667 LN_TX_SER_40BIT_EN_RBR_MASK, 1668 FIELD_PREP(LN_TX_SER_40BIT_EN_RBR_MASK, 0x1)); 1669 break; 1670 case 2700: 1671 ctrl = &tx_drv_ctrl_hbr[dp->voltage[lane]][dp->pre[lane]]; 1672 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, 1673 LN_TX_JEQ_EVEN_CTRL_HBR_MASK, 1674 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR_MASK, 1675 ctrl->tx_jeq_even_ctrl)); 1676 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, 1677 LN_TX_JEQ_ODD_CTRL_HBR_MASK, 1678 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR_MASK, 1679 ctrl->tx_jeq_odd_ctrl)); 1680 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1681 LN_TX_SER_40BIT_EN_HBR_MASK, 1682 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR_MASK, 0x1)); 1683 break; 1684 case 5400: 1685 default: 1686 ctrl = &tx_drv_ctrl_hbr2[dp->voltage[lane]][dp->pre[lane]]; 1687 regmap_update_bits(hdptx->regmap, LANE_REG(030b) + offset, 1688 LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, 1689 FIELD_PREP(LN_TX_JEQ_EVEN_CTRL_HBR2_MASK, 1690 ctrl->tx_jeq_even_ctrl)); 1691 regmap_update_bits(hdptx->regmap, LANE_REG(030d) + offset, 1692 LN_TX_JEQ_ODD_CTRL_HBR2_MASK, 1693 FIELD_PREP(LN_TX_JEQ_ODD_CTRL_HBR2_MASK, 1694 ctrl->tx_jeq_odd_ctrl)); 1695 regmap_update_bits(hdptx->regmap, LANE_REG(0311) + offset, 1696 LN_TX_SER_40BIT_EN_HBR2_MASK, 1697 FIELD_PREP(LN_TX_SER_40BIT_EN_HBR2_MASK, 0x1)); 1698 break; 1699 } 1700 1701 regmap_update_bits(hdptx->regmap, LANE_REG(0303) + offset, 1702 OVRD_LN_TX_DRV_LVL_CTRL_MASK | LN_TX_DRV_LVL_CTRL_MASK, 1703 FIELD_PREP(OVRD_LN_TX_DRV_LVL_CTRL_MASK, 0x1) | 1704 FIELD_PREP(LN_TX_DRV_LVL_CTRL_MASK, 1705 ctrl->tx_drv_lvl_ctrl)); 1706 regmap_update_bits(hdptx->regmap, LANE_REG(0304) + offset, 1707 OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK | 1708 LN_TX_DRV_POST_LVL_CTRL_MASK, 1709 FIELD_PREP(OVRD_LN_TX_DRV_POST_LVL_CTRL_MASK, 0x1) | 1710 FIELD_PREP(LN_TX_DRV_POST_LVL_CTRL_MASK, 1711 ctrl->tx_drv_post_lvl_ctrl)); 1712 regmap_update_bits(hdptx->regmap, LANE_REG(0305) + offset, 1713 OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK | 1714 LN_TX_DRV_PRE_LVL_CTRL_MASK, 1715 FIELD_PREP(OVRD_LN_TX_DRV_PRE_LVL_CTRL_MASK, 0x1) | 1716 FIELD_PREP(LN_TX_DRV_PRE_LVL_CTRL_MASK, 1717 ctrl->tx_drv_pre_lvl_ctrl)); 1718 regmap_update_bits(hdptx->regmap, LANE_REG(0306) + offset, 1719 LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK | 1720 LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK | 1721 LN_ANA_TX_DRV_ACCDRV_EN_MASK, 1722 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IDN_CTRL_MASK, 1723 ctrl->ana_tx_drv_idrv_idn_ctrl) | 1724 FIELD_PREP(LN_ANA_TX_DRV_IDRV_IUP_CTRL_MASK, 1725 ctrl->ana_tx_drv_idrv_iup_ctrl) | 1726 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_EN_MASK, 1727 ctrl->ana_tx_drv_accdrv_en)); 1728 regmap_update_bits(hdptx->regmap, LANE_REG(0307) + offset, 1729 LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK | 1730 LN_ANA_TX_DRV_ACCDRV_CTRL_MASK, 1731 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_POL_SEL_MASK, 0x1) | 1732 FIELD_PREP(LN_ANA_TX_DRV_ACCDRV_CTRL_MASK, 1733 ctrl->ana_tx_drv_accdrv_ctrl)); 1734 1735 regmap_update_bits(hdptx->regmap, LANE_REG(030a) + offset, 1736 LN_ANA_TX_JEQ_EN_MASK, 1737 FIELD_PREP(LN_ANA_TX_JEQ_EN_MASK, ctrl->ana_tx_jeq_en)); 1738 1739 regmap_update_bits(hdptx->regmap, LANE_REG(0310) + offset, 1740 LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 1741 FIELD_PREP(LN_ANA_TX_SYNC_LOSS_DET_MODE_MASK, 0x3)); 1742 1743 regmap_update_bits(hdptx->regmap, LANE_REG(0316) + offset, 1744 LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 1745 FIELD_PREP(LN_ANA_TX_SER_VREG_GAIN_CTRL_MASK, 0x2)); 1746 1747 regmap_update_bits(hdptx->regmap, LANE_REG(031b) + offset, 1748 LN_ANA_TX_RESERVED_MASK, 1749 FIELD_PREP(LN_ANA_TX_RESERVED_MASK, 0x1)); 1750} 1751 1752static int rk_hdptx_phy_set_voltages(struct rk_hdptx_phy *hdptx, 1753 struct phy_configure_opts_dp *dp) 1754{ 1755 u8 lane; 1756 u32 status; 1757 int ret; 1758 1759 for (lane = 0; lane < hdptx->lanes; lane++) 1760 rk_hdptx_phy_set_voltage(hdptx, dp, lane); 1761 1762 reset_control_deassert(hdptx->rsts[RST_LANE].rstc); 1763 1764 ret = regmap_read_poll_timeout(hdptx->grf, GRF_HDPTX_STATUS, 1765 status, FIELD_GET(HDPTX_O_PHY_RDY, status), 1766 50, 5000); 1767 if (ret) { 1768 dev_err(hdptx->dev, "Failed to get phy ready: %d\n", ret); 1769 return ret; 1770 } 1771 1772 return 0; 1773} 1774 1775static int rk_hdptx_phy_configure(struct phy *phy, union phy_configure_opts *opts) 1776{ 1777 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1778 enum phy_mode mode = phy_get_mode(phy); 1779 int ret; 1780 1781 if (mode != PHY_MODE_DP) { 1782 ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); 1783 if (ret) { 1784 dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); 1785 } else { 1786 hdptx->hdmi_cfg = opts->hdmi; 1787 hdptx->restrict_rate_change = true; 1788 } 1789 1790 dev_dbg(hdptx->dev, "%s rate=%llu bpc=%u\n", __func__, 1791 hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); 1792 return ret; 1793 } 1794 1795 ret = rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); 1796 if (ret) { 1797 dev_err(hdptx->dev, "invalid dp params for phy configure\n"); 1798 return ret; 1799 } 1800 1801 if (opts->dp.set_rate) { 1802 ret = rk_hdptx_phy_set_rate(hdptx, &opts->dp); 1803 if (ret) { 1804 dev_err(hdptx->dev, "failed to set rate: %d\n", ret); 1805 return ret; 1806 } 1807 } 1808 1809 if (opts->dp.set_lanes) { 1810 ret = rk_hdptx_phy_set_lanes(hdptx, &opts->dp); 1811 if (ret) { 1812 dev_err(hdptx->dev, "failed to set lanes: %d\n", ret); 1813 return ret; 1814 } 1815 } 1816 1817 if (opts->dp.set_voltages) { 1818 ret = rk_hdptx_phy_set_voltages(hdptx, &opts->dp); 1819 if (ret) { 1820 dev_err(hdptx->dev, "failed to set voltages: %d\n", 1821 ret); 1822 return ret; 1823 } 1824 } 1825 1826 return 0; 1827} 1828 1829static int rk_hdptx_phy_validate(struct phy *phy, enum phy_mode mode, 1830 int submode, union phy_configure_opts *opts) 1831{ 1832 struct rk_hdptx_phy *hdptx = phy_get_drvdata(phy); 1833 1834 if (mode != PHY_MODE_DP) 1835 return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); 1836 1837 return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); 1838} 1839 1840static const struct phy_ops rk_hdptx_phy_ops = { 1841 .power_on = rk_hdptx_phy_power_on, 1842 .power_off = rk_hdptx_phy_power_off, 1843 .configure = rk_hdptx_phy_configure, 1844 .validate = rk_hdptx_phy_validate, 1845 .owner = THIS_MODULE, 1846}; 1847 1848static struct rk_hdptx_phy *to_rk_hdptx_phy(struct clk_hw *hw) 1849{ 1850 return container_of(hw, struct rk_hdptx_phy, hw); 1851} 1852 1853static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) 1854{ 1855 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1856 1857 return rk_hdptx_phy_consumer_get(hdptx); 1858} 1859 1860static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) 1861{ 1862 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1863 1864 rk_hdptx_phy_consumer_put(hdptx, true); 1865} 1866 1867static unsigned long rk_hdptx_phy_clk_recalc_rate(struct clk_hw *hw, 1868 unsigned long parent_rate) 1869{ 1870 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1871 1872 return hdptx->hw_rate; 1873} 1874 1875static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate, 1876 unsigned long *parent_rate) 1877{ 1878 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1879 1880 /* 1881 * FIXME: Temporarily allow altering TMDS char rate via CCF. 1882 * To be dropped as soon as the RK DW HDMI QP bridge driver 1883 * switches to make use of phy_configure(). 1884 */ 1885 if (!hdptx->restrict_rate_change && rate != hdptx->hdmi_cfg.tmds_char_rate) { 1886 struct phy_configure_opts_hdmi hdmi = { 1887 .tmds_char_rate = rate, 1888 }; 1889 int ret = rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi); 1890 1891 if (ret) 1892 return ret; 1893 1894 hdptx->hdmi_cfg = hdmi; 1895 } 1896 1897 /* 1898 * The TMDS char rate shall be adjusted via phy_configure() only, 1899 * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with 1900 * a different rate argument. 1901 */ 1902 return DIV_ROUND_CLOSEST_ULL(hdptx->hdmi_cfg.tmds_char_rate * 8, hdptx->hdmi_cfg.bpc); 1903} 1904 1905static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, 1906 unsigned long parent_rate) 1907{ 1908 struct rk_hdptx_phy *hdptx = to_rk_hdptx_phy(hw); 1909 unsigned long long tmds_rate = DIV_ROUND_CLOSEST_ULL(rate * hdptx->hdmi_cfg.bpc, 8); 1910 1911 /* Revert any unlikely TMDS char rate change since round_rate() */ 1912 if (hdptx->hdmi_cfg.tmds_char_rate != tmds_rate) { 1913 dev_warn(hdptx->dev, "Reverting unexpected rate change from %llu to %llu\n", 1914 tmds_rate, hdptx->hdmi_cfg.tmds_char_rate); 1915 hdptx->hdmi_cfg.tmds_char_rate = tmds_rate; 1916 } 1917 1918 /* 1919 * The TMDS char rate would be normally programmed in HW during 1920 * phy_ops.power_on() or clk_ops.prepare() callbacks, but it might 1921 * happen that the former gets fired too late, i.e. after this call, 1922 * while the latter being executed only once, i.e. when clock remains 1923 * in the prepared state during rate changes. 1924 */ 1925 return rk_hdptx_ropll_tmds_cmn_config(hdptx); 1926} 1927 1928static const struct clk_ops hdptx_phy_clk_ops = { 1929 .prepare = rk_hdptx_phy_clk_prepare, 1930 .unprepare = rk_hdptx_phy_clk_unprepare, 1931 .recalc_rate = rk_hdptx_phy_clk_recalc_rate, 1932 .round_rate = rk_hdptx_phy_clk_round_rate, 1933 .set_rate = rk_hdptx_phy_clk_set_rate, 1934}; 1935 1936static int rk_hdptx_phy_clk_register(struct rk_hdptx_phy *hdptx) 1937{ 1938 struct device *dev = hdptx->dev; 1939 const char *name, *pname; 1940 struct clk *refclk; 1941 int ret; 1942 1943 refclk = devm_clk_get(dev, "ref"); 1944 if (IS_ERR(refclk)) 1945 return dev_err_probe(dev, PTR_ERR(refclk), 1946 "Failed to get ref clock\n"); 1947 1948 name = hdptx->phy_id > 0 ? "clk_hdmiphy_pixel1" : "clk_hdmiphy_pixel0"; 1949 pname = __clk_get_name(refclk); 1950 1951 hdptx->hw.init = CLK_HW_INIT(name, pname, &hdptx_phy_clk_ops, 1952 CLK_GET_RATE_NOCACHE); 1953 1954 ret = devm_clk_hw_register(dev, &hdptx->hw); 1955 if (ret) 1956 return dev_err_probe(dev, ret, "Failed to register clock\n"); 1957 1958 ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &hdptx->hw); 1959 if (ret) 1960 return dev_err_probe(dev, ret, 1961 "Failed to register clk provider\n"); 1962 return 0; 1963} 1964 1965static int rk_hdptx_phy_runtime_suspend(struct device *dev) 1966{ 1967 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); 1968 1969 clk_bulk_disable_unprepare(hdptx->nr_clks, hdptx->clks); 1970 1971 return 0; 1972} 1973 1974static int rk_hdptx_phy_runtime_resume(struct device *dev) 1975{ 1976 struct rk_hdptx_phy *hdptx = dev_get_drvdata(dev); 1977 int ret; 1978 1979 ret = clk_bulk_prepare_enable(hdptx->nr_clks, hdptx->clks); 1980 if (ret) 1981 dev_err(hdptx->dev, "Failed to enable clocks: %d\n", ret); 1982 1983 return ret; 1984} 1985 1986static int rk_hdptx_phy_probe(struct platform_device *pdev) 1987{ 1988 const struct rk_hdptx_phy_cfg *cfgs; 1989 struct phy_provider *phy_provider; 1990 struct device *dev = &pdev->dev; 1991 struct rk_hdptx_phy *hdptx; 1992 struct resource *res; 1993 void __iomem *regs; 1994 int ret, id; 1995 1996 hdptx = devm_kzalloc(dev, sizeof(*hdptx), GFP_KERNEL); 1997 if (!hdptx) 1998 return -ENOMEM; 1999 2000 hdptx->dev = dev; 2001 hdptx->hdmi_cfg.bpc = 8; 2002 2003 regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 2004 if (IS_ERR(regs)) 2005 return dev_err_probe(dev, PTR_ERR(regs), 2006 "Failed to ioremap resource\n"); 2007 2008 cfgs = device_get_match_data(dev); 2009 if (!cfgs) 2010 return dev_err_probe(dev, -EINVAL, "missing match data\n"); 2011 2012 /* find the phy-id from the io address */ 2013 hdptx->phy_id = -ENODEV; 2014 for (id = 0; id < cfgs->num_phys; id++) { 2015 if (res->start == cfgs->phy_ids[id]) { 2016 hdptx->phy_id = id; 2017 break; 2018 } 2019 } 2020 2021 if (hdptx->phy_id < 0) 2022 return dev_err_probe(dev, -ENODEV, "no matching device found\n"); 2023 2024 ret = devm_clk_bulk_get_all(dev, &hdptx->clks); 2025 if (ret < 0) 2026 return dev_err_probe(dev, ret, "Failed to get clocks\n"); 2027 if (ret == 0) 2028 return dev_err_probe(dev, -EINVAL, "Missing clocks\n"); 2029 2030 hdptx->nr_clks = ret; 2031 2032 hdptx->regmap = devm_regmap_init_mmio(dev, regs, 2033 &rk_hdptx_phy_regmap_config); 2034 if (IS_ERR(hdptx->regmap)) 2035 return dev_err_probe(dev, PTR_ERR(hdptx->regmap), 2036 "Failed to init regmap\n"); 2037 2038 hdptx->rsts[RST_APB].id = "apb"; 2039 hdptx->rsts[RST_INIT].id = "init"; 2040 hdptx->rsts[RST_CMN].id = "cmn"; 2041 hdptx->rsts[RST_LANE].id = "lane"; 2042 2043 ret = devm_reset_control_bulk_get_exclusive(dev, RST_MAX, hdptx->rsts); 2044 if (ret) 2045 return dev_err_probe(dev, ret, "Failed to get resets\n"); 2046 2047 hdptx->grf = syscon_regmap_lookup_by_phandle(dev->of_node, 2048 "rockchip,grf"); 2049 if (IS_ERR(hdptx->grf)) 2050 return dev_err_probe(dev, PTR_ERR(hdptx->grf), 2051 "Could not get GRF syscon\n"); 2052 2053 platform_set_drvdata(pdev, hdptx); 2054 2055 ret = devm_pm_runtime_enable(dev); 2056 if (ret) 2057 return dev_err_probe(dev, ret, "Failed to enable runtime PM\n"); 2058 2059 hdptx->phy = devm_phy_create(dev, NULL, &rk_hdptx_phy_ops); 2060 if (IS_ERR(hdptx->phy)) 2061 return dev_err_probe(dev, PTR_ERR(hdptx->phy), 2062 "Failed to create HDMI PHY\n"); 2063 2064 phy_set_drvdata(hdptx->phy, hdptx); 2065 phy_set_bus_width(hdptx->phy, 8); 2066 2067 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2068 if (IS_ERR(phy_provider)) 2069 return dev_err_probe(dev, PTR_ERR(phy_provider), 2070 "Failed to register PHY provider\n"); 2071 2072 reset_control_deassert(hdptx->rsts[RST_APB].rstc); 2073 reset_control_deassert(hdptx->rsts[RST_CMN].rstc); 2074 reset_control_deassert(hdptx->rsts[RST_INIT].rstc); 2075 2076 return rk_hdptx_phy_clk_register(hdptx); 2077} 2078 2079static const struct dev_pm_ops rk_hdptx_phy_pm_ops = { 2080 RUNTIME_PM_OPS(rk_hdptx_phy_runtime_suspend, 2081 rk_hdptx_phy_runtime_resume, NULL) 2082}; 2083 2084static const struct rk_hdptx_phy_cfg rk3576_hdptx_phy_cfgs = { 2085 .num_phys = 1, 2086 .phy_ids = { 2087 0x2b000000, 2088 }, 2089}; 2090 2091static const struct rk_hdptx_phy_cfg rk3588_hdptx_phy_cfgs = { 2092 .num_phys = 2, 2093 .phy_ids = { 2094 0xfed60000, 2095 0xfed70000, 2096 }, 2097}; 2098 2099static const struct of_device_id rk_hdptx_phy_of_match[] = { 2100 { 2101 .compatible = "rockchip,rk3576-hdptx-phy", 2102 .data = &rk3576_hdptx_phy_cfgs 2103 }, 2104 { 2105 .compatible = "rockchip,rk3588-hdptx-phy", 2106 .data = &rk3588_hdptx_phy_cfgs 2107 }, 2108 {} 2109}; 2110MODULE_DEVICE_TABLE(of, rk_hdptx_phy_of_match); 2111 2112static struct platform_driver rk_hdptx_phy_driver = { 2113 .probe = rk_hdptx_phy_probe, 2114 .driver = { 2115 .name = "rockchip-hdptx-phy", 2116 .pm = &rk_hdptx_phy_pm_ops, 2117 .of_match_table = rk_hdptx_phy_of_match, 2118 }, 2119}; 2120module_platform_driver(rk_hdptx_phy_driver); 2121 2122MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>"); 2123MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>"); 2124MODULE_AUTHOR("Damon Ding <damon.ding@rock-chips.com>"); 2125MODULE_DESCRIPTION("Samsung HDMI/eDP Transmitter Combo PHY Driver"); 2126MODULE_LICENSE("GPL");
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