phy-rcar-gen3-usb2.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Renesas R-Car Gen3 for USB2.0 PHY driver
  4 *
  5 * Copyright (C) 2015-2017 Renesas Electronics Corporation
  6 *
  7 * This is based on the phy-rcar-gen2 driver:
  8 * Copyright (C) 2014 Renesas Solutions Corp.
  9 * Copyright (C) 2014 Cogent Embedded, Inc.
 10 */
 11
 12#include <linux/bitfield.h>
 13#include <linux/bits.h>
 14#include <linux/cleanup.h>
 15#include <linux/extcon-provider.h>
 16#include <linux/interrupt.h>
 17#include <linux/io.h>
 18#include <linux/module.h>
 19#include <linux/mutex.h>
 20#include <linux/of.h>
 21#include <linux/phy/phy.h>
 22#include <linux/platform_device.h>
 23#include <linux/pm_runtime.h>
 24#include <linux/regulator/consumer.h>
 25#include <linux/reset.h>
 26#include <linux/string.h>
 27#include <linux/usb/of.h>
 28#include <linux/workqueue.h>
 29
 30/******* USB2.0 Host registers (original offset is +0x200) *******/
 31#define USB2_INT_ENABLE		0x000
 32#define USB2_AHB_BUS_CTR	0x008
 33#define USB2_USBCTR		0x00c
 34#define USB2_REGEN_CG_CTRL	0x104	/* RZ/V2H(P) only */
 35#define USB2_SPD_RSM_TIMSET	0x10c
 36#define USB2_OC_TIMSET		0x110
 37#define USB2_UTMI_CTRL		0x118	/* RZ/V2H(P) only */
 38#define USB2_COMMCTRL		0x600
 39#define USB2_OBINTSTA		0x604
 40#define USB2_OBINTEN		0x608
 41#define USB2_VBCTRL		0x60c
 42#define USB2_LINECTRL1		0x610
 43#define USB2_ADPCTRL		0x630
 44
 45/* INT_ENABLE */
 46#define USB2_INT_ENABLE_UCOM_INTEN	BIT(3)
 47#define USB2_INT_ENABLE_USBH_INTB_EN	BIT(2)	/* For EHCI */
 48#define USB2_INT_ENABLE_USBH_INTA_EN	BIT(1)	/* For OHCI */
 49
 50/* AHB_BUS_CTR */
 51#define USB2_AHB_BUS_CTR_MBL_MASK	GENMASK(1, 0)
 52#define USB2_AHB_BUS_CTR_MBL_INCR4	2
 53
 54/* USBCTR */
 55#define USB2_USBCTR_DIRPD	BIT(2)
 56#define USB2_USBCTR_PLL_RST	BIT(1)
 57
 58/* REGEN_CG_CTRL*/
 59#define USB2_REGEN_CG_CTRL_UPHY_WEN	BIT(0)
 60
 61/* SPD_RSM_TIMSET */
 62#define USB2_SPD_RSM_TIMSET_INIT	0x014e029b
 63
 64/* OC_TIMSET */
 65#define USB2_OC_TIMSET_INIT		0x000209ab
 66
 67/* UTMI_CTRL */
 68#define USB2_UTMI_CTRL_INIT		0x8000018f
 69
 70/* COMMCTRL */
 71#define USB2_COMMCTRL_OTG_PERI		BIT(31)	/* 1 = Peripheral mode */
 72
 73/* OBINTSTA and OBINTEN */
 74#define USB2_OBINTSTA_CLEAR		GENMASK(31, 0)
 75#define USB2_OBINT_SESSVLDCHG		BIT(12)
 76#define USB2_OBINT_IDDIGCHG		BIT(11)
 77#define USB2_OBINT_VBSTAINT		BIT(3)
 78#define USB2_OBINT_IDCHG_EN		BIT(0) /*  RZ/G2L specific */
 79
 80/* VBCTRL */
 81#define USB2_VBCTRL_VBSTA_MASK		GENMASK(31, 28)
 82#define USB2_VBCTRL_VBSTA_DEFAULT	2
 83#define USB2_VBCTRL_VBLVL_MASK		GENMASK(23, 20)
 84#define USB2_VBCTRL_VBLVL(m)		FIELD_PREP_CONST(USB2_VBCTRL_VBLVL_MASK, (m))
 85#define USB2_VBCTRL_OCCLREN		BIT(16)
 86#define USB2_VBCTRL_DRVVBUSSEL		BIT(8)
 87#define USB2_VBCTRL_SIDDQREL		BIT(2)
 88#define USB2_VBCTRL_VBOUT		BIT(0)
 89
 90/* LINECTRL1 */
 91#define USB2_LINECTRL1_DPRPD_EN		BIT(19)
 92#define USB2_LINECTRL1_DP_RPD		BIT(18)
 93#define USB2_LINECTRL1_DMRPD_EN		BIT(17)
 94#define USB2_LINECTRL1_DM_RPD		BIT(16)
 95#define USB2_LINECTRL1_OPMODE_NODRV	BIT(6)
 96
 97/* ADPCTRL */
 98#define USB2_ADPCTRL_OTGSESSVLD		BIT(20)
 99#define USB2_ADPCTRL_IDDIG		BIT(19)
100#define USB2_ADPCTRL_VBUSVALID		BIT(18)
101#define USB2_ADPCTRL_IDPULLUP		BIT(5)	/* 1 = ID sampling is enabled */
102#define USB2_ADPCTRL_DRVVBUS		BIT(4)
103
104/*  RZ/G2L specific */
105#define USB2_LINECTRL1_USB2_IDMON	BIT(0)
106
107#define NUM_OF_PHYS			4
108enum rcar_gen3_phy_index {
109	PHY_INDEX_BOTH_HC,
110	PHY_INDEX_OHCI,
111	PHY_INDEX_EHCI,
112	PHY_INDEX_HSUSB
113};
114
115static const u32 rcar_gen3_int_enable[NUM_OF_PHYS] = {
116	USB2_INT_ENABLE_USBH_INTB_EN | USB2_INT_ENABLE_USBH_INTA_EN,
117	USB2_INT_ENABLE_USBH_INTA_EN,
118	USB2_INT_ENABLE_USBH_INTB_EN,
119	0
120};
121
122struct rcar_gen3_phy {
123	struct phy *phy;
124	struct rcar_gen3_chan *ch;
125	u32 int_enable_bits;
126	bool initialized;
127	bool powered;
128};
129
130struct rcar_gen3_chan {
131	void __iomem *base;
132	struct device *dev;	/* platform_device's device */
133	const struct rcar_gen3_phy_drv_data *phy_data;
134	struct extcon_dev *extcon;
135	struct reset_control *rstc;
136	struct rcar_gen3_phy rphys[NUM_OF_PHYS];
137	struct regulator *vbus;
138	struct work_struct work;
139	spinlock_t lock;	/* protects access to hardware and driver data structure. */
140	enum usb_dr_mode dr_mode;
141	bool extcon_host;
142	bool is_otg_channel;
143	bool uses_otg_pins;
144};
145
146struct rcar_gen3_phy_drv_data {
147	const struct phy_ops *phy_usb2_ops;
148	bool no_adp_ctrl;
149	bool init_bus;
150	bool utmi_ctrl;
151	bool vblvl_ctrl;
152	u32 obint_enable_bits;
153};
154
155/*
156 * Combination about is_otg_channel and uses_otg_pins:
157 *
158 * Parameters				|| Behaviors
159 * is_otg_channel	| uses_otg_pins	|| irqs		| role sysfs
160 * ---------------------+---------------++--------------+------------
161 * true			| true		|| enabled	| enabled
162 * true                 | false		|| disabled	| enabled
163 * false                | any		|| disabled	| disabled
164 */
165
166static void rcar_gen3_phy_usb2_work(struct work_struct *work)
167{
168	struct rcar_gen3_chan *ch = container_of(work, struct rcar_gen3_chan,
169						 work);
170
171	if (ch->extcon_host) {
172		extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, true);
173		extcon_set_state_sync(ch->extcon, EXTCON_USB, false);
174	} else {
175		extcon_set_state_sync(ch->extcon, EXTCON_USB_HOST, false);
176		extcon_set_state_sync(ch->extcon, EXTCON_USB, true);
177	}
178}
179
180static void rcar_gen3_set_host_mode(struct rcar_gen3_chan *ch, int host)
181{
182	void __iomem *usb2_base = ch->base;
183	u32 val = readl(usb2_base + USB2_COMMCTRL);
184
185	dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, host);
186	if (host)
187		val &= ~USB2_COMMCTRL_OTG_PERI;
188	else
189		val |= USB2_COMMCTRL_OTG_PERI;
190	writel(val, usb2_base + USB2_COMMCTRL);
191}
192
193static void rcar_gen3_set_linectrl(struct rcar_gen3_chan *ch, int dp, int dm)
194{
195	void __iomem *usb2_base = ch->base;
196	u32 val = readl(usb2_base + USB2_LINECTRL1);
197
198	dev_vdbg(ch->dev, "%s: %08x, %d, %d\n", __func__, val, dp, dm);
199	val &= ~(USB2_LINECTRL1_DP_RPD | USB2_LINECTRL1_DM_RPD);
200	if (dp)
201		val |= USB2_LINECTRL1_DP_RPD;
202	if (dm)
203		val |= USB2_LINECTRL1_DM_RPD;
204	writel(val, usb2_base + USB2_LINECTRL1);
205}
206
207static void rcar_gen3_enable_vbus_ctrl(struct rcar_gen3_chan *ch, int vbus)
208{
209	void __iomem *usb2_base = ch->base;
210	u32 vbus_ctrl_reg = USB2_ADPCTRL;
211	u32 vbus_ctrl_val = USB2_ADPCTRL_DRVVBUS;
212	u32 val;
213
214	if (ch->phy_data->no_adp_ctrl || ch->phy_data->vblvl_ctrl) {
215		if (ch->vbus)
216			regulator_hardware_enable(ch->vbus, vbus);
217
218		vbus_ctrl_reg = USB2_VBCTRL;
219		vbus_ctrl_val = USB2_VBCTRL_VBOUT;
220	}
221
222	val = readl(usb2_base + vbus_ctrl_reg);
223	if (vbus)
224		val |= vbus_ctrl_val;
225	else
226		val &= ~vbus_ctrl_val;
227	dev_vdbg(ch->dev, "%s: %08x, %d\n", __func__, val, vbus);
228	writel(val, usb2_base + vbus_ctrl_reg);
229}
230
231static void rcar_gen3_control_otg_irq(struct rcar_gen3_chan *ch, int enable)
232{
233	void __iomem *usb2_base = ch->base;
234	u32 val = readl(usb2_base + USB2_OBINTEN);
235
236	if (ch->uses_otg_pins && enable)
237		val |= ch->phy_data->obint_enable_bits;
238	else
239		val &= ~ch->phy_data->obint_enable_bits;
240	writel(val, usb2_base + USB2_OBINTEN);
241}
242
243static void rcar_gen3_init_for_host(struct rcar_gen3_chan *ch)
244{
245	rcar_gen3_set_linectrl(ch, 1, 1);
246	rcar_gen3_set_host_mode(ch, 1);
247	rcar_gen3_enable_vbus_ctrl(ch, 1);
248
249	ch->extcon_host = true;
250	schedule_work(&ch->work);
251}
252
253static void rcar_gen3_init_for_peri(struct rcar_gen3_chan *ch)
254{
255	rcar_gen3_set_linectrl(ch, 0, 1);
256	rcar_gen3_set_host_mode(ch, 0);
257	rcar_gen3_enable_vbus_ctrl(ch, 0);
258
259	ch->extcon_host = false;
260	schedule_work(&ch->work);
261}
262
263static void rcar_gen3_init_for_b_host(struct rcar_gen3_chan *ch)
264{
265	void __iomem *usb2_base = ch->base;
266	u32 val;
267
268	val = readl(usb2_base + USB2_LINECTRL1);
269	writel(val | USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
270
271	rcar_gen3_set_linectrl(ch, 1, 1);
272	rcar_gen3_set_host_mode(ch, 1);
273	rcar_gen3_enable_vbus_ctrl(ch, 0);
274
275	val = readl(usb2_base + USB2_LINECTRL1);
276	writel(val & ~USB2_LINECTRL1_OPMODE_NODRV, usb2_base + USB2_LINECTRL1);
277}
278
279static void rcar_gen3_init_for_a_peri(struct rcar_gen3_chan *ch)
280{
281	rcar_gen3_set_linectrl(ch, 0, 1);
282	rcar_gen3_set_host_mode(ch, 0);
283	rcar_gen3_enable_vbus_ctrl(ch, 1);
284}
285
286static void rcar_gen3_init_from_a_peri_to_a_host(struct rcar_gen3_chan *ch)
287{
288	rcar_gen3_control_otg_irq(ch, 0);
289
290	rcar_gen3_enable_vbus_ctrl(ch, 1);
291	rcar_gen3_init_for_host(ch);
292
293	rcar_gen3_control_otg_irq(ch, 1);
294}
295
296static bool rcar_gen3_check_id(struct rcar_gen3_chan *ch)
297{
298	if (ch->phy_data->vblvl_ctrl) {
299		bool vbus_valid;
300		bool device;
301
302		device = !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
303		vbus_valid = !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_VBUSVALID);
304
305		return vbus_valid ? device : !device;
306	}
307
308	if (!ch->uses_otg_pins)
309		return ch->dr_mode != USB_DR_MODE_HOST;
310
311	if (ch->phy_data->no_adp_ctrl)
312		return !!(readl(ch->base + USB2_LINECTRL1) & USB2_LINECTRL1_USB2_IDMON);
313
314	return !!(readl(ch->base + USB2_ADPCTRL) & USB2_ADPCTRL_IDDIG);
315}
316
317static void rcar_gen3_device_recognition(struct rcar_gen3_chan *ch)
318{
319	if (!rcar_gen3_check_id(ch))
320		rcar_gen3_init_for_host(ch);
321	else
322		rcar_gen3_init_for_peri(ch);
323}
324
325static bool rcar_gen3_is_host(struct rcar_gen3_chan *ch)
326{
327	return !(readl(ch->base + USB2_COMMCTRL) & USB2_COMMCTRL_OTG_PERI);
328}
329
330static enum phy_mode rcar_gen3_get_phy_mode(struct rcar_gen3_chan *ch)
331{
332	if (rcar_gen3_is_host(ch))
333		return PHY_MODE_USB_HOST;
334
335	return PHY_MODE_USB_DEVICE;
336}
337
338static bool rcar_gen3_is_any_rphy_initialized(struct rcar_gen3_chan *ch)
339{
340	int i;
341
342	for (i = 0; i < NUM_OF_PHYS; i++) {
343		if (ch->rphys[i].initialized)
344			return true;
345	}
346
347	return false;
348}
349
350static bool rcar_gen3_is_any_otg_rphy_initialized(struct rcar_gen3_chan *ch)
351{
352	for (enum rcar_gen3_phy_index i = PHY_INDEX_BOTH_HC; i <= PHY_INDEX_EHCI;
353	     i++) {
354		if (ch->rphys[i].initialized)
355			return true;
356	}
357
358	return false;
359}
360
361static bool rcar_gen3_are_all_rphys_power_off(struct rcar_gen3_chan *ch)
362{
363	int i;
364
365	for (i = 0; i < NUM_OF_PHYS; i++) {
366		if (ch->rphys[i].powered)
367			return false;
368	}
369
370	return true;
371}
372
373static ssize_t role_store(struct device *dev, struct device_attribute *attr,
374			  const char *buf, size_t count)
375{
376	struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
377	bool is_b_device;
378	enum phy_mode cur_mode, new_mode;
379
380	guard(spinlock_irqsave)(&ch->lock);
381
382	if (!ch->is_otg_channel || !rcar_gen3_is_any_otg_rphy_initialized(ch))
383		return -EIO;
384
385	if (sysfs_streq(buf, "host"))
386		new_mode = PHY_MODE_USB_HOST;
387	else if (sysfs_streq(buf, "peripheral"))
388		new_mode = PHY_MODE_USB_DEVICE;
389	else
390		return -EINVAL;
391
392	/* is_b_device: true is B-Device. false is A-Device. */
393	is_b_device = rcar_gen3_check_id(ch);
394	cur_mode = rcar_gen3_get_phy_mode(ch);
395
396	/* If current and new mode is the same, this returns the error */
397	if (cur_mode == new_mode)
398		return -EINVAL;
399
400	if (new_mode == PHY_MODE_USB_HOST) { /* And is_host must be false */
401		if (!is_b_device)	/* A-Peripheral */
402			rcar_gen3_init_from_a_peri_to_a_host(ch);
403		else			/* B-Peripheral */
404			rcar_gen3_init_for_b_host(ch);
405	} else {			/* And is_host must be true */
406		if (!is_b_device)	/* A-Host */
407			rcar_gen3_init_for_a_peri(ch);
408		else			/* B-Host */
409			rcar_gen3_init_for_peri(ch);
410	}
411
412	return count;
413}
414
415static ssize_t role_show(struct device *dev, struct device_attribute *attr,
416			 char *buf)
417{
418	struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
419
420	if (!ch->is_otg_channel || !rcar_gen3_is_any_otg_rphy_initialized(ch))
421		return -EIO;
422
423	return sprintf(buf, "%s\n", rcar_gen3_is_host(ch) ? "host" :
424							    "peripheral");
425}
426static DEVICE_ATTR_RW(role);
427
428static void rcar_gen3_init_otg(struct rcar_gen3_chan *ch)
429{
430	void __iomem *usb2_base = ch->base;
431	u32 val;
432
433	if (!ch->is_otg_channel || rcar_gen3_is_any_otg_rphy_initialized(ch))
434		return;
435
436	/* Should not use functions of read-modify-write a register */
437	val = readl(usb2_base + USB2_LINECTRL1);
438	val = (val & ~USB2_LINECTRL1_DP_RPD) | USB2_LINECTRL1_DPRPD_EN |
439	      USB2_LINECTRL1_DMRPD_EN | USB2_LINECTRL1_DM_RPD;
440	writel(val, usb2_base + USB2_LINECTRL1);
441
442	if (!ch->phy_data->no_adp_ctrl) {
443		if (ch->phy_data->vblvl_ctrl) {
444			val = readl(usb2_base + USB2_VBCTRL);
445			val = (val & ~USB2_VBCTRL_VBLVL_MASK) | USB2_VBCTRL_VBLVL(2);
446			writel(val, usb2_base + USB2_VBCTRL);
447			val = readl(usb2_base + USB2_ADPCTRL);
448			writel(val | USB2_ADPCTRL_IDPULLUP | USB2_ADPCTRL_DRVVBUS,
449			       usb2_base + USB2_ADPCTRL);
450		} else {
451			val = readl(usb2_base + USB2_VBCTRL);
452			val &= ~USB2_VBCTRL_OCCLREN;
453			writel(val | USB2_VBCTRL_DRVVBUSSEL, usb2_base + USB2_VBCTRL);
454			val = readl(usb2_base + USB2_ADPCTRL);
455			writel(val | USB2_ADPCTRL_IDPULLUP, usb2_base + USB2_ADPCTRL);
456		}
457	}
458	mdelay(20);
459
460	writel(0xffffffff, usb2_base + USB2_OBINTSTA);
461	writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTEN);
462
463	rcar_gen3_device_recognition(ch);
464}
465
466static void rcar_gen3_configure_vblvl_ctrl(struct rcar_gen3_chan *ch)
467{
468	void __iomem *usb2_base = ch->base;
469	u32 val;
470
471	if (!ch->phy_data->vblvl_ctrl)
472		return;
473
474	val = readl(usb2_base + USB2_VBCTRL);
475	if ((val & USB2_VBCTRL_VBSTA_MASK) ==
476	    FIELD_PREP_CONST(USB2_VBCTRL_VBSTA_MASK, USB2_VBCTRL_VBSTA_DEFAULT))
477		val &= ~USB2_VBCTRL_VBLVL_MASK;
478	else
479		val |= USB2_VBCTRL_VBLVL(USB2_VBCTRL_VBSTA_DEFAULT);
480	writel(val, usb2_base + USB2_VBCTRL);
481}
482
483static irqreturn_t rcar_gen3_phy_usb2_irq(int irq, void *_ch)
484{
485	struct rcar_gen3_chan *ch = _ch;
486	void __iomem *usb2_base = ch->base;
487	struct device *dev = ch->dev;
488	irqreturn_t ret = IRQ_NONE;
489	u32 status;
490
491	pm_runtime_get_noresume(dev);
492
493	if (pm_runtime_suspended(dev))
494		goto rpm_put;
495
496	scoped_guard(spinlock, &ch->lock) {
497		status = readl(usb2_base + USB2_OBINTSTA);
498		if (status & ch->phy_data->obint_enable_bits) {
499			dev_vdbg(dev, "%s: %08x\n", __func__, status);
500			if (ch->phy_data->vblvl_ctrl)
501				writel(USB2_OBINTSTA_CLEAR, usb2_base + USB2_OBINTSTA);
502			else
503				writel(ch->phy_data->obint_enable_bits, usb2_base + USB2_OBINTSTA);
504			rcar_gen3_device_recognition(ch);
505			rcar_gen3_configure_vblvl_ctrl(ch);
506			ret = IRQ_HANDLED;
507		}
508	}
509
510rpm_put:
511	pm_runtime_put_noidle(dev);
512	return ret;
513}
514
515static int rcar_gen3_phy_usb2_init(struct phy *p)
516{
517	struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
518	struct rcar_gen3_chan *channel = rphy->ch;
519	void __iomem *usb2_base = channel->base;
520	u32 val;
521
522	guard(spinlock_irqsave)(&channel->lock);
523
524	/* Initialize USB2 part */
525	val = readl(usb2_base + USB2_INT_ENABLE);
526	val |= USB2_INT_ENABLE_UCOM_INTEN | rphy->int_enable_bits;
527	writel(val, usb2_base + USB2_INT_ENABLE);
528
529	if (!rcar_gen3_is_any_rphy_initialized(channel)) {
530		writel(USB2_SPD_RSM_TIMSET_INIT, usb2_base + USB2_SPD_RSM_TIMSET);
531		writel(USB2_OC_TIMSET_INIT, usb2_base + USB2_OC_TIMSET);
532	}
533
534	/* Initialize otg part (only if we initialize a PHY with IRQs). */
535	if (rphy->int_enable_bits)
536		rcar_gen3_init_otg(channel);
537
538	if (channel->phy_data->vblvl_ctrl) {
539		/* SIDDQ mode release */
540		writel(readl(usb2_base + USB2_VBCTRL) | USB2_VBCTRL_SIDDQREL,
541		       usb2_base + USB2_VBCTRL);
542		udelay(250);
543	}
544
545	if (channel->phy_data->utmi_ctrl) {
546		val = readl(usb2_base + USB2_REGEN_CG_CTRL) | USB2_REGEN_CG_CTRL_UPHY_WEN;
547		writel(val, usb2_base + USB2_REGEN_CG_CTRL);
548
549		writel(USB2_UTMI_CTRL_INIT, usb2_base + USB2_UTMI_CTRL);
550		writel(val & ~USB2_REGEN_CG_CTRL_UPHY_WEN, usb2_base + USB2_REGEN_CG_CTRL);
551	}
552
553	rphy->initialized = true;
554
555	return 0;
556}
557
558static int rcar_gen3_phy_usb2_exit(struct phy *p)
559{
560	struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
561	struct rcar_gen3_chan *channel = rphy->ch;
562	void __iomem *usb2_base = channel->base;
563	u32 val;
564
565	guard(spinlock_irqsave)(&channel->lock);
566
567	rphy->initialized = false;
568
569	val = readl(usb2_base + USB2_INT_ENABLE);
570	val &= ~rphy->int_enable_bits;
571	if (!rcar_gen3_is_any_rphy_initialized(channel))
572		val &= ~USB2_INT_ENABLE_UCOM_INTEN;
573	writel(val, usb2_base + USB2_INT_ENABLE);
574
575	return 0;
576}
577
578static int rcar_gen3_phy_usb2_power_on(struct phy *p)
579{
580	struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
581	struct rcar_gen3_chan *channel = rphy->ch;
582	void __iomem *usb2_base = channel->base;
583	u32 val;
584	int ret = 0;
585
586	if (channel->vbus) {
587		ret = regulator_enable(channel->vbus);
588		if (ret)
589			return ret;
590	}
591
592	guard(spinlock_irqsave)(&channel->lock);
593
594	if (!rcar_gen3_are_all_rphys_power_off(channel))
595		goto out;
596
597	val = readl(usb2_base + USB2_USBCTR);
598	val |= USB2_USBCTR_PLL_RST;
599	writel(val, usb2_base + USB2_USBCTR);
600	val &= ~USB2_USBCTR_PLL_RST;
601	writel(val, usb2_base + USB2_USBCTR);
602
603out:
604	/* The powered flag should be set for any other phys anyway */
605	rphy->powered = true;
606
607	return 0;
608}
609
610static int rcar_gen3_phy_usb2_power_off(struct phy *p)
611{
612	struct rcar_gen3_phy *rphy = phy_get_drvdata(p);
613	struct rcar_gen3_chan *channel = rphy->ch;
614	int ret = 0;
615
616	scoped_guard(spinlock_irqsave, &channel->lock) {
617		rphy->powered = false;
618
619		if (rcar_gen3_are_all_rphys_power_off(channel)) {
620			u32 val = readl(channel->base + USB2_USBCTR);
621
622			val |= USB2_USBCTR_PLL_RST;
623			writel(val, channel->base + USB2_USBCTR);
624		}
625	}
626
627	if (channel->vbus)
628		ret = regulator_disable(channel->vbus);
629
630	return ret;
631}
632
633static const struct phy_ops rcar_gen3_phy_usb2_ops = {
634	.init		= rcar_gen3_phy_usb2_init,
635	.exit		= rcar_gen3_phy_usb2_exit,
636	.power_on	= rcar_gen3_phy_usb2_power_on,
637	.power_off	= rcar_gen3_phy_usb2_power_off,
638	.owner		= THIS_MODULE,
639};
640
641static const struct phy_ops rz_g1c_phy_usb2_ops = {
642	.init		= rcar_gen3_phy_usb2_init,
643	.exit		= rcar_gen3_phy_usb2_exit,
644	.owner		= THIS_MODULE,
645};
646
647static const struct rcar_gen3_phy_drv_data rcar_gen3_phy_usb2_data = {
648	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
649	.no_adp_ctrl = false,
650	.obint_enable_bits = USB2_OBINT_SESSVLDCHG |
651			     USB2_OBINT_IDDIGCHG,
652};
653
654static const struct rcar_gen3_phy_drv_data rz_g1c_phy_usb2_data = {
655	.phy_usb2_ops = &rz_g1c_phy_usb2_ops,
656	.no_adp_ctrl = false,
657	.obint_enable_bits = USB2_OBINT_SESSVLDCHG |
658			     USB2_OBINT_IDDIGCHG,
659};
660
661static const struct rcar_gen3_phy_drv_data rz_g2l_phy_usb2_data = {
662	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
663	.no_adp_ctrl = true,
664	.obint_enable_bits = USB2_OBINT_IDCHG_EN,
665};
666
667static const struct rcar_gen3_phy_drv_data rz_g3s_phy_usb2_data = {
668	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
669	.no_adp_ctrl = true,
670	.init_bus = true,
671	.obint_enable_bits = USB2_OBINT_IDCHG_EN,
672};
673
674static const struct rcar_gen3_phy_drv_data rz_t2h_phy_usb2_data = {
675	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
676	.vblvl_ctrl = true,
677	.obint_enable_bits = USB2_OBINT_IDCHG_EN | USB2_OBINT_VBSTAINT,
678};
679
680static const struct rcar_gen3_phy_drv_data rz_v2h_phy_usb2_data = {
681	.phy_usb2_ops = &rcar_gen3_phy_usb2_ops,
682	.no_adp_ctrl = true,
683	.utmi_ctrl = true,
684	.obint_enable_bits = USB2_OBINT_IDCHG_EN,
685};
686
687static const struct of_device_id rcar_gen3_phy_usb2_match_table[] = {
688	{
689		.compatible = "renesas,usb2-phy-r8a77470",
690		.data = &rz_g1c_phy_usb2_data,
691	},
692	{
693		.compatible = "renesas,usb2-phy-r8a7795",
694		.data = &rcar_gen3_phy_usb2_data,
695	},
696	{
697		.compatible = "renesas,usb2-phy-r8a7796",
698		.data = &rcar_gen3_phy_usb2_data,
699	},
700	{
701		.compatible = "renesas,usb2-phy-r8a77965",
702		.data = &rcar_gen3_phy_usb2_data,
703	},
704	{
705		.compatible = "renesas,usb2-phy-r9a08g045",
706		.data = &rz_g3s_phy_usb2_data,
707	},
708	{
709		.compatible = "renesas,usb2-phy-r9a09g057",
710		.data = &rz_v2h_phy_usb2_data,
711	},
712	{
713		.compatible = "renesas,usb2-phy-r9a09g077",
714		.data = &rz_t2h_phy_usb2_data,
715	},
716	{
717		.compatible = "renesas,rzg2l-usb2-phy",
718		.data = &rz_g2l_phy_usb2_data,
719	},
720	{
721		.compatible = "renesas,rcar-gen3-usb2-phy",
722		.data = &rcar_gen3_phy_usb2_data,
723	},
724	{ /* sentinel */ },
725};
726MODULE_DEVICE_TABLE(of, rcar_gen3_phy_usb2_match_table);
727
728static const unsigned int rcar_gen3_phy_cable[] = {
729	EXTCON_USB,
730	EXTCON_USB_HOST,
731	EXTCON_NONE,
732};
733
734static struct phy *rcar_gen3_phy_usb2_xlate(struct device *dev,
735					    const struct of_phandle_args *args)
736{
737	struct rcar_gen3_chan *ch = dev_get_drvdata(dev);
738
739	if (args->args_count == 0)	/* For old version dts */
740		return ch->rphys[PHY_INDEX_BOTH_HC].phy;
741	else if (args->args_count > 1)	/* Prevent invalid args count */
742		return ERR_PTR(-ENODEV);
743
744	if (args->args[0] >= NUM_OF_PHYS)
745		return ERR_PTR(-ENODEV);
746
747	return ch->rphys[args->args[0]].phy;
748}
749
750static enum usb_dr_mode rcar_gen3_get_dr_mode(struct device_node *np)
751{
752	enum usb_dr_mode candidate = USB_DR_MODE_UNKNOWN;
753	int i;
754
755	/*
756	 * If one of device nodes has other dr_mode except UNKNOWN,
757	 * this function returns UNKNOWN. To achieve backward compatibility,
758	 * this loop starts the index as 0.
759	 */
760	for (i = 0; i < NUM_OF_PHYS; i++) {
761		enum usb_dr_mode mode = of_usb_get_dr_mode_by_phy(np, i);
762
763		if (mode != USB_DR_MODE_UNKNOWN) {
764			if (candidate == USB_DR_MODE_UNKNOWN)
765				candidate = mode;
766			else if (candidate != mode)
767				return USB_DR_MODE_UNKNOWN;
768		}
769	}
770
771	return candidate;
772}
773
774static void rcar_gen3_reset_assert(void *data)
775{
776	reset_control_assert(data);
777}
778
779static int rcar_gen3_phy_usb2_init_bus(struct rcar_gen3_chan *channel)
780{
781	struct device *dev = channel->dev;
782	int ret;
783	u32 val;
784
785	if (!channel->phy_data->init_bus)
786		return 0;
787
788	ret = pm_runtime_resume_and_get(dev);
789	if (ret)
790		return ret;
791
792	val = readl(channel->base + USB2_AHB_BUS_CTR);
793	val &= ~USB2_AHB_BUS_CTR_MBL_MASK;
794	val |= USB2_AHB_BUS_CTR_MBL_INCR4;
795	writel(val, channel->base + USB2_AHB_BUS_CTR);
796
797	pm_runtime_put(dev);
798
799	return 0;
800}
801
802static int rcar_gen3_phy_usb2_probe(struct platform_device *pdev)
803{
804	struct device *dev = &pdev->dev;
805	struct rcar_gen3_chan *channel;
806	struct phy_provider *provider;
807	int ret = 0, i, irq;
808
809	if (!dev->of_node) {
810		dev_err(dev, "This driver needs device tree\n");
811		return -EINVAL;
812	}
813
814	channel = devm_kzalloc(dev, sizeof(*channel), GFP_KERNEL);
815	if (!channel)
816		return -ENOMEM;
817
818	channel->base = devm_platform_ioremap_resource(pdev, 0);
819	if (IS_ERR(channel->base))
820		return PTR_ERR(channel->base);
821
822	channel->dr_mode = rcar_gen3_get_dr_mode(dev->of_node);
823	if (channel->dr_mode != USB_DR_MODE_UNKNOWN) {
824		channel->is_otg_channel = true;
825		channel->uses_otg_pins = !of_property_read_bool(dev->of_node,
826							"renesas,no-otg-pins");
827		channel->extcon = devm_extcon_dev_allocate(dev,
828							rcar_gen3_phy_cable);
829		if (IS_ERR(channel->extcon))
830			return PTR_ERR(channel->extcon);
831
832		ret = devm_extcon_dev_register(dev, channel->extcon);
833		if (ret < 0) {
834			dev_err(dev, "Failed to register extcon\n");
835			return ret;
836		}
837	}
838
839	channel->rstc = devm_reset_control_array_get_optional_shared(dev);
840	if (IS_ERR(channel->rstc))
841		return PTR_ERR(channel->rstc);
842
843	ret = reset_control_deassert(channel->rstc);
844	if (ret)
845		return ret;
846
847	ret = devm_add_action_or_reset(dev, rcar_gen3_reset_assert, channel->rstc);
848	if (ret)
849		return ret;
850
851	/*
852	 * devm_phy_create() will call pm_runtime_enable(&phy->dev);
853	 * And then, phy-core will manage runtime pm for this device.
854	 */
855	pm_runtime_enable(dev);
856
857	channel->phy_data = of_device_get_match_data(dev);
858	if (!channel->phy_data) {
859		ret = -EINVAL;
860		goto error;
861	}
862
863	platform_set_drvdata(pdev, channel);
864	channel->dev = dev;
865
866	ret = rcar_gen3_phy_usb2_init_bus(channel);
867	if (ret)
868		goto error;
869
870	spin_lock_init(&channel->lock);
871	for (i = 0; i < NUM_OF_PHYS; i++) {
872		channel->rphys[i].phy = devm_phy_create(dev, NULL,
873							channel->phy_data->phy_usb2_ops);
874		if (IS_ERR(channel->rphys[i].phy)) {
875			dev_err(dev, "Failed to create USB2 PHY\n");
876			ret = PTR_ERR(channel->rphys[i].phy);
877			goto error;
878		}
879		channel->rphys[i].ch = channel;
880		channel->rphys[i].int_enable_bits = rcar_gen3_int_enable[i];
881		phy_set_drvdata(channel->rphys[i].phy, &channel->rphys[i]);
882	}
883
884	if (channel->phy_data->no_adp_ctrl && channel->is_otg_channel)
885		channel->vbus = devm_regulator_get_exclusive(dev, "vbus");
886	else
887		channel->vbus = devm_regulator_get_optional(dev, "vbus");
888	if (IS_ERR(channel->vbus)) {
889		if (PTR_ERR(channel->vbus) == -EPROBE_DEFER) {
890			ret = PTR_ERR(channel->vbus);
891			goto error;
892		}
893		channel->vbus = NULL;
894	}
895
896	irq = platform_get_irq_optional(pdev, 0);
897	if (irq < 0 && irq != -ENXIO) {
898		ret = irq;
899		goto error;
900	} else if (irq > 0) {
901		INIT_WORK(&channel->work, rcar_gen3_phy_usb2_work);
902		ret = devm_request_irq(dev, irq, rcar_gen3_phy_usb2_irq,
903				       IRQF_SHARED, dev_name(dev), channel);
904		if (ret < 0) {
905			dev_err(dev, "Failed to request irq (%d)\n", irq);
906			goto error;
907		}
908	}
909
910	provider = devm_of_phy_provider_register(dev, rcar_gen3_phy_usb2_xlate);
911	if (IS_ERR(provider)) {
912		dev_err(dev, "Failed to register PHY provider\n");
913		ret = PTR_ERR(provider);
914		goto error;
915	} else if (channel->is_otg_channel) {
916		ret = device_create_file(dev, &dev_attr_role);
917		if (ret < 0)
918			goto error;
919	}
920
921	return 0;
922
923error:
924	pm_runtime_disable(dev);
925
926	return ret;
927}
928
929static void rcar_gen3_phy_usb2_remove(struct platform_device *pdev)
930{
931	struct rcar_gen3_chan *channel = platform_get_drvdata(pdev);
932
933	if (channel->is_otg_channel)
934		device_remove_file(&pdev->dev, &dev_attr_role);
935
936	pm_runtime_disable(&pdev->dev);
937}
938
939static int rcar_gen3_phy_usb2_suspend(struct device *dev)
940{
941	struct rcar_gen3_chan *channel = dev_get_drvdata(dev);
942
943	return reset_control_assert(channel->rstc);
944}
945
946static int rcar_gen3_phy_usb2_resume(struct device *dev)
947{
948	struct rcar_gen3_chan *channel = dev_get_drvdata(dev);
949	int ret;
950
951	ret = reset_control_deassert(channel->rstc);
952	if (ret)
953		return ret;
954
955	ret = rcar_gen3_phy_usb2_init_bus(channel);
956	if (ret)
957		reset_control_assert(channel->rstc);
958
959	return ret;
960}
961
962static DEFINE_SIMPLE_DEV_PM_OPS(rcar_gen3_phy_usb2_pm_ops,
963				rcar_gen3_phy_usb2_suspend,
964				rcar_gen3_phy_usb2_resume);
965
966static struct platform_driver rcar_gen3_phy_usb2_driver = {
967	.driver = {
968		.name		= "phy_rcar_gen3_usb2",
969		.of_match_table	= rcar_gen3_phy_usb2_match_table,
970		.pm		= pm_ptr(&rcar_gen3_phy_usb2_pm_ops),
971	},
972	.probe	= rcar_gen3_phy_usb2_probe,
973	.remove = rcar_gen3_phy_usb2_remove,
974};
975module_platform_driver(rcar_gen3_phy_usb2_driver);
976
977MODULE_LICENSE("GPL v2");
978MODULE_DESCRIPTION("Renesas R-Car Gen3 USB 2.0 PHY");
979MODULE_AUTHOR("Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>");