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phy-qcom-qmp-ufs.c
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linux-6.19.14/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#include <linux/clk.h> 7#include <linux/clk-provider.h> 8#include <linux/delay.h> 9#include <linux/err.h> 10#include <linux/io.h> 11#include <linux/iopoll.h> 12#include <linux/kernel.h> 13#include <linux/module.h> 14#include <linux/of.h> 15#include <linux/of_address.h> 16#include <linux/phy/phy.h> 17#include <linux/platform_device.h> 18#include <linux/regulator/consumer.h> 19#include <linux/reset.h> 20#include <linux/slab.h> 21 22#include <ufs/unipro.h> 23 24#include "phy-qcom-qmp-common.h" 25 26#include "phy-qcom-qmp.h" 27#include "phy-qcom-qmp-pcs-ufs-v2.h" 28#include "phy-qcom-qmp-pcs-ufs-v3.h" 29#include "phy-qcom-qmp-pcs-ufs-v4.h" 30#include "phy-qcom-qmp-pcs-ufs-v5.h" 31#include "phy-qcom-qmp-pcs-ufs-v6.h" 32 33#include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h" 34#include "phy-qcom-qmp-qserdes-txrx-ufs-v7.h" 35 36/* QPHY_PCS_READY_STATUS bit */ 37#define PCS_READY BIT(0) 38 39#define PHY_INIT_COMPLETE_TIMEOUT 10000 40 41#define NUM_OVERLAY 2 42 43/* set of registers with offsets different per-PHY */ 44enum qphy_reg_layout { 45 /* PCS registers */ 46 QPHY_SW_RESET, 47 QPHY_START_CTRL, 48 QPHY_PCS_READY_STATUS, 49 QPHY_PCS_POWER_DOWN_CONTROL, 50 /* Keep last to ensure regs_layout arrays are properly initialized */ 51 QPHY_LAYOUT_SIZE 52}; 53 54static const unsigned int ufsphy_v2_regs_layout[QPHY_LAYOUT_SIZE] = { 55 [QPHY_START_CTRL] = QPHY_V2_PCS_UFS_PHY_START, 56 [QPHY_PCS_READY_STATUS] = QPHY_V2_PCS_UFS_READY_STATUS, 57 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL, 58}; 59 60static const unsigned int ufsphy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { 61 [QPHY_START_CTRL] = QPHY_V3_PCS_UFS_PHY_START, 62 [QPHY_PCS_READY_STATUS] = QPHY_V3_PCS_UFS_READY_STATUS, 63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL, 64}; 65 66static const unsigned int ufsphy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { 67 [QPHY_START_CTRL] = QPHY_V4_PCS_UFS_PHY_START, 68 [QPHY_PCS_READY_STATUS] = QPHY_V4_PCS_UFS_READY_STATUS, 69 [QPHY_SW_RESET] = QPHY_V4_PCS_UFS_SW_RESET, 70 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL, 71}; 72 73static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { 74 [QPHY_START_CTRL] = QPHY_V5_PCS_UFS_PHY_START, 75 [QPHY_PCS_READY_STATUS] = QPHY_V5_PCS_UFS_READY_STATUS, 76 [QPHY_SW_RESET] = QPHY_V5_PCS_UFS_SW_RESET, 77 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, 78}; 79 80static const unsigned int ufsphy_v6_regs_layout[QPHY_LAYOUT_SIZE] = { 81 [QPHY_START_CTRL] = QPHY_V6_PCS_UFS_PHY_START, 82 [QPHY_PCS_READY_STATUS] = QPHY_V6_PCS_UFS_READY_STATUS, 83 [QPHY_SW_RESET] = QPHY_V6_PCS_UFS_SW_RESET, 84 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL, 85}; 86 87static const struct qmp_phy_init_tbl msm8996_ufsphy_serdes[] = { 88 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 89 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), 90 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 91 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 92 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 93 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 94 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x05), 95 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 96 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 97 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 98 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x10), 99 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 100 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 101 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 102 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 103 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 104 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x54), 105 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 106 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 107 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 108 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 109 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 110 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 111 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 112 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 113 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 114 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 115 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 116 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 117 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 118 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 119 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 120 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 121 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 122 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 123 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 124 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 125 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 126 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 127 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 128 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 129 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 130 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 131 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 132 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 133 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 134}; 135 136static const struct qmp_phy_init_tbl msm8996_ufsphy_tx[] = { 137 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 138 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), 139}; 140 141static const struct qmp_phy_init_tbl msm8996_ufsphy_rx[] = { 142 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 143 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), 144 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), 145 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x18), 146 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 147 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5b), 148 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xff), 149 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3f), 150 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xff), 151 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x0f), 152 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), 153}; 154 155static const struct qmp_phy_init_tbl sc7280_ufsphy_tx[] = { 156 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 157 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 158 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 159 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 160 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x35), 161 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 162}; 163 164static const struct qmp_phy_init_tbl sc7280_ufsphy_rx[] = { 165 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 166 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 167 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 168 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 169 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 170 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 171 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 172 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 173 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 174 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 175 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 176 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 177 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 178 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 179 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 180 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 181 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 182 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 183 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 184 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x6d), 185 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x6d), 186 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xed), 187 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 188 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3c), 189 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 190 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 191 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 192 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 193 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 194 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 195 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 196 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 197 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 198 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 199 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 200}; 201 202static const struct qmp_phy_init_tbl sc7280_ufsphy_pcs[] = { 203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 204 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 210 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x03), 211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x16), 212 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xd8), 213 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xaa), 214 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x06), 215 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x03), 216 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x03), 217}; 218 219static const struct qmp_phy_init_tbl sc7280_ufsphy_hs_g4_rx[] = { 220 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 221 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 222 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 223 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 224 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 225 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 226 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 227 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 228 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 229 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 230 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 231 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 232 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 233 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 234 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 235 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 236 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 237 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 239 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 240 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 241 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 242 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 243 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 244 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 245 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 246 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 247 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 248 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 249 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 250 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 251 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 252 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 253 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 254 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 255 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 256 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 257 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x0f), 258}; 259 260static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = { 261 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), 262 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 263 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 264 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02), 265 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 266 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 267 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 268 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 269 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV_MODE1, 0x0a), 270 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x01), 271 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 272 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x20), 273 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 274 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 275 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff), 276 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x3f), 277 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x04), 278 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x05), 279 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 280 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x00), 281 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x00), 282 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x00), 283 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 284 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 285 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 286 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 287 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 288 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE0, 0x28), 289 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE0, 0x02), 290 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xff), 291 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x0c), 292 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 293 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE1, 0x98), 294 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE1, 0x00), 295 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE1, 0x00), 296 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE1, 0x00), 297 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE1, 0x0b), 298 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE1, 0x16), 299 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE1, 0x28), 300 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE1, 0x80), 301 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 302 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE1_MODE1, 0xd6), 303 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE2_MODE1, 0x00), 304 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE1, 0x32), 305 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE1, 0x0f), 306 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), 307 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 308 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 309 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL1, 0xff), 310 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_INITVAL2, 0x00), 311}; 312 313static const struct qmp_phy_init_tbl sm6115_ufsphy_hs_b_serdes[] = { 314 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), 315}; 316 317static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = { 318 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 319 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 320}; 321 322static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = { 323 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), 324 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), 325 QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), 326 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x1E), 327 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0B), 328 QMP_PHY_INIT_CFG(QSERDES_RX_RX_TERM_BW, 0x5B), 329 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_LSB, 0xFF), 330 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN1_MSB, 0x3F), 331 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_LSB, 0xFF), 332 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_GAIN2_MSB, 0x3F), 333 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0D), 334 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 335 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 336 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SVS_SO_GAIN, 0x04), 337 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), 338}; 339 340static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = { 341 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), 342 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 343 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 344 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 345 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP, 0x28), 346 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 347 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL, 0x12), 348 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL, 0x0f), 349 QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ 350}; 351 352static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = { 353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 357 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 358 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0xd5), 359 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL, 0x20), 360 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 361 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00), 362 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x01), 363 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00), 364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x04), 366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x05), 367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL1, 0xff), 368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_INITVAL2, 0x00), 369 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xda), 376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0xff), 378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0c), 379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE1, 0x98), 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE1, 0x06), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE1, 0x16), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE1, 0x36), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1, 0x3f), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1, 0x00), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE1, 0xc1), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE1, 0x00), 387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE1, 0x32), 388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE1, 0x0f), 389}; 390 391static const struct qmp_phy_init_tbl sdm845_ufsphy_hs_b_serdes[] = { 392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), 393}; 394 395static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = { 396 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), 397 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), 398 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), 399}; 400 401static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = { 402 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 403 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 404 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 405 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 406 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 407 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 408 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 409 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 410 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 418}; 419 420static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = { 421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), 422 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), 428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 429}; 430 431static const struct qmp_phy_init_tbl sm7150_ufsphy_rx[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), 433 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), 434 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 435 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_INTERFACE_MODE, 0x40), 436 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 437 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_TERM_BW, 0x5b), 438 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 439 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1b), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF, 0x04), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER, 0x04), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SVS_SO_GAIN, 0x04), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5b), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x81), 446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), 448}; 449 450static const struct qmp_phy_init_tbl sm7150_ufsphy_pcs[] = { 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6f), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL, 0x03), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1, 0x0f), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 459}; 460 461static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = { 462 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), 463 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), 464 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), 465 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x01), 466 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 467 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f), 468 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_INITVAL2, 0x00), 469 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 470 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 471 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 472 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 473 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 474 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0xff), 475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0c), 476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x98), 479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x32), 483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x0f), 484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 486}; 487 488static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_b_serdes[] = { 489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), 490}; 491 492static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = { 493 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 494 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 495 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 496 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 497 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x05), 498 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), 499}; 500 501static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_tx[] = { 502 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x75), 503}; 504 505static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = { 506 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), 507 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), 508 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 509 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_BAND, 0x18), 510 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 511 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b), 512 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0xf1), 513 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 514 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x80), 515 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0c), 516 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 517 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x1b), 518 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 519 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 520 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1d), 521 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 522 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x10), 523 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 524 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x36), 526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x36), 527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xf6), 528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x3b), 529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x3d), 530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xe0), 531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xc8), 532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xc8), 533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x3b), 534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb1), 535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_LOW, 0xe0), 536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH, 0xc8), 537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH2, 0xc8), 538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH3, 0x3b), 539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_10_HIGH4, 0xb1), 540}; 541 542static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_rx[] = { 543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x6c), 555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 559}; 560 561static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { 562 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 563 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 569}; 570 571static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { 572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), 573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 574}; 575 576static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_tx[] = { 577 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xe5), 578}; 579 580static const struct qmp_phy_init_tbl sm8250_ufsphy_hs_g4_rx[] = { 581 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 582 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CTRL2, 0x81), 583 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0e), 584 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_TERM_BW, 0x6f), 585 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 586 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 587 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x09), 588 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x07), 589 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 590 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_MEASURE_TIME, 0x20), 591 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0x80), 592 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 593 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x3f), 594 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff), 595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xff), 596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x2c), 598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0x6d), 599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0x6d), 600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0xed), 601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0x3c), 602}; 603 604static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = { 605 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), 606 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), 607 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), 608 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x42), 609 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 610 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0x0f), 611 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00), 612 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 613 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 614 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x14), 615 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x18), 616 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x18), 617 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0xff), 618 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x19), 619 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xac), 620 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 621 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x98), 622 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x14), 623 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x18), 624 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x18), 625 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x65), 626 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x1e), 627 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xdd), 628 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 629}; 630 631static const struct qmp_phy_init_tbl sm8350_ufsphy_hs_b_serdes[] = { 632 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), 633}; 634 635static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = { 636 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), 637 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), 638 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), 639 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1, 0x00), 640 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xf5), 641 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 642 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x09), 643 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 644 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), 645}; 646 647static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = { 648 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), 649 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), 650 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), 651 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_BAND, 0x18), 652 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x0a), 653 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5a), 654 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0xf1), 655 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0x80), 656 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x80), 657 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0e), 658 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x04), 659 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x1b), 660 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1, 0x04), 661 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x06), 662 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x04), 663 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x1a), 664 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x17), 665 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x00), 666 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x10), 667 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 668 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 669 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x6d), 670 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x6d), 671 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xed), 672 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3b), 673 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x3c), 674 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0xe0), 675 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0xc8), 676 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xc8), 677 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x3b), 678 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xb7), 679 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_LOW, 0xe0), 680 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH, 0xc8), 681 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH2, 0xc8), 682 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH3, 0x3b), 683 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_10_HIGH4, 0xb7), 684 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 685}; 686 687static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = { 688 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), 689 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), 690 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), 691 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 692 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL, 0x1f), 693 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME, 0xff), 694 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1, 0x0e), 695 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 696}; 697 698static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_tx[] = { 699 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xe5), 700}; 701 702static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_rx[] = { 703 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CTRL2, 0x81), 704 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_TERM_BW, 0x6f), 705 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x00), 706 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 707 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 708 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_MEASURE_TIME, 0x20), 709 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0x80), 710 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x01), 711 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbf), 712 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0xbf), 713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f), 714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x7f), 715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0x2d), 716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x6d), 717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x6d), 718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xed), 719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0x3c), 720}; 721 722static const struct qmp_phy_init_tbl sm8350_ufsphy_g4_pcs[] = { 723 QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), 724}; 725 726static const struct qmp_phy_init_tbl sm8475_ufsphy_serdes[] = { 727 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 728 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 729 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 730 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 731 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 732 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 733 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82), 734 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 735 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x18), 736 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0xff), 737 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0c), 738}; 739 740static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_serdes[] = { 741 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 742 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 743 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x14), 744 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x98), 745 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x14), 746 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x18), 748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x32), 749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x0f), 750}; 751 752static const struct qmp_phy_init_tbl sm8475_ufsphy_g4_pcs[] = { 753 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x0b), 754 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 755 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 756}; 757 758static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { 759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 770}; 771 772static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { 773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), 774}; 775 776static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_serdes[] = { 777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f), 779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), 780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), 782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 786}; 787 788static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_serdes[] = { 789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x1b), 791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x1c), 792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 793}; 794 795static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { 796 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), 797 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 798}; 799 800static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_tx[] = { 801 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), 802}; 803 804static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { 805 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 806 807 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), 808 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xc2), 809 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 810 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 811 812 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 813 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 814 815 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 816 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 817 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 818 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 819}; 820 821static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_rx[] = { 822 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), 823}; 824 825static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_rx[] = { 826 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 827 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 828 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 829 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 830 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 831 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 832 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 833 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 834 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x08), 835 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 836 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 837 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B6, 0xff), 838 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 839}; 840 841static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { 842 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x69), 843 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 844 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 845 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 846}; 847 848static const struct qmp_phy_init_tbl sm8550_ufsphy_g4_pcs[] = { 849 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), 850 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 851 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 852}; 853 854static const struct qmp_phy_init_tbl sm8550_ufsphy_g5_pcs[] = { 855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4f), 857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 858}; 859 860static const struct qmp_phy_init_tbl sm8650_ufsphy_serdes[] = { 861 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 862 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 863 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 864 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 865 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 866 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 867 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 868 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x0a), 869 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x17), 870 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 871 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00), 872 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 873 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 874 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 875 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 876 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 877 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 878 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 879 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 880 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 881 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 882 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 883 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 884}; 885 886static const struct qmp_phy_init_tbl sm8650_ufsphy_tx[] = { 887 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x01), 888 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 889 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 890}; 891 892static const struct qmp_phy_init_tbl sm8650_ufsphy_rx[] = { 893 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), 894 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE4, 0x0c), 895 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_GAIN_RATE4, 0x04), 896 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 897 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CONTROLS, 0x07), 898 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 899 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 900 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 901 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 902 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x3e), 903 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 904 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xce), 905 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1, 0xce), 906 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B2, 0x18), 907 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3, 0x1a), 908 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B4, 0x0f), 909 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6, 0x60), 910 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B3, 0x9e), 911 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE2_B6, 0x60), 912 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B3, 0x9e), 913 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B4, 0x0e), 914 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B5, 0x36), 915 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE3_B8, 0x02), 916 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B0, 0x24), 917 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B1, 0x24), 918 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B2, 0x20), 919 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B3, 0xb9), 920 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE4_B4, 0x4f), 921 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_SO_SATURATION, 0x1f), 922 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_PI_CTRL1, 0x94), 923 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_RX_TERM_BW_CTRL0, 0xfa), 924 QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_DLL0_FTUNE_CTRL, 0x30), 925}; 926 927static const struct qmp_phy_init_tbl sm8650_ufsphy_pcs[] = { 928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 929 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 930 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0xc1), 931 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x33), 932 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 933 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 934 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 935 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 936 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 937 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 938}; 939 940static const struct qmp_phy_init_tbl sm8650_ufsphy_g4_pcs[] = { 941 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 942 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 943}; 944 945static const struct qmp_phy_init_tbl sm8650_ufsphy_g5_pcs[] = { 946 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x05), 947 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x05), 948 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HS_G5_SYNC_LENGTH_CAPABILITY, 0x4d), 949 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSG5_SYNC_WAIT_TIME, 0x9e), 950}; 951 952static const struct qmp_phy_init_tbl sm8750_ufsphy_serdes[] = { 953 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0xd9), 954 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16), 955 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x11), 956 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00), 957 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x01), 958 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x60), 959 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x1f), 960 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x1f), 961 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IETRIM, 0x07), 962 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_IPTRIM, 0x20), 963 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04), 964 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x40), 965 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADAPTIVE_ANALOG_CONFIG, 0x06), 966 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41), 967 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06), 968 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), 969 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), 970 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE0, 0x06), 971 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE0, 0x18), 972 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE0, 0x14), 973 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), 974 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), 975 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x92), 976 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 977 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), 978 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x06), 979 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), 980 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), 981 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_ADAPTIVE_MODE1, 0x06), 982 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCCTRL_ADAPTIVE_MODE1, 0x18), 983 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_ADAPTIVE_MODE1, 0x14), 984 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), 985 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), 986 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xbe), 987 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x23), 988}; 989 990static const struct qmp_phy_init_tbl sm8750_ufsphy_tx[] = { 991 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_LANE_MODE_1, 0x00), 992 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x07), 993 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x17), 994}; 995 996static const struct qmp_phy_init_tbl sm8750_ufsphy_rx[] = { 997 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE2, 0x0c), 998 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FO_GAIN_RATE4, 0x0c), 999 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_GAIN_RATE4, 0x04), 1000 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x14), 1001 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CONTROLS, 0x07), 1002 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_OFFSET_ADAPTOR_CNTRL3, 0x0e), 1003 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_COUNT_HIGH_RATE4, 0x02), 1004 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x1c), 1005 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_FASTLOCK_SO_GAIN_RATE4, 0x06), 1006 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_VGA_CAL_MAN_VAL, 0x8e), 1007 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_EQU_ADAPTOR_CNTRL4, 0x0f), 1008 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B0, 0xce), 1009 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B1, 0xce), 1010 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B2, 0x18), 1011 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B3, 0x1a), 1012 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B4, 0x0f), 1013 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B6, 0x60), 1014 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE_0_1_B7, 0x62), 1015 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B3, 0x9a), 1016 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B6, 0xe2), 1017 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE2_B7, 0x06), 1018 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B0, 0x1b), 1019 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B1, 0x1b), 1020 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B2, 0x98), 1021 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B3, 0x9b), 1022 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B4, 0x2a), 1023 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B5, 0x12), 1024 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B7, 0x06), 1025 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE3_B8, 0x01), 1026 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B0, 0x93), 1027 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B1, 0x93), 1028 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B2, 0x60), 1029 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B3, 0x99), 1030 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B4, 0x5f), 1031 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B5, 0x92), 1032 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B6, 0xe3), 1033 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SA_B7, 0x06), 1034 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B0, 0x9b), 1035 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B1, 0x9b), 1036 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B2, 0x60), 1037 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B3, 0x99), 1038 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B4, 0x5f), 1039 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B5, 0x92), 1040 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B6, 0xfb), 1041 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_MODE_RATE4_SB_B7, 0x06), 1042 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_SO_SATURATION, 0x1f), 1043 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_UCDR_PI_CTRL1, 0x94), 1044 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_TERM_BW_CTRL0, 0xfa), 1045 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_DLL0_FTUNE_CTRL, 0x30), 1046 QMP_PHY_INIT_CFG(QSERDES_UFS_V7_RX_SIGDET_CAL_TRIM, 0x77), 1047}; 1048 1049static const struct qmp_phy_init_tbl sm8750_ufsphy_pcs[] = { 1050 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), 1051 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), 1052 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x40), 1053 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), 1054 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2, 0x68), 1055 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S4, 0x0e), 1056 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S5, 0x12), 1057 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S6, 0x15), 1058 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_POST_EMP_LVL_S7, 0x19), 1059}; 1060 1061static const struct qmp_phy_init_tbl sm8750_ufsphy_g4_pcs[] = { 1062 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), 1063 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), 1064}; 1065 1066static const struct qmp_phy_init_tbl sm8750_ufsphy_hs_b_pcs[] = { 1067 QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PCS_CTRL1, 0x41), 1068}; 1069 1070struct qmp_ufs_offsets { 1071 u16 serdes; 1072 u16 pcs; 1073 u16 tx; 1074 u16 rx; 1075 u16 tx2; 1076 u16 rx2; 1077}; 1078 1079struct qmp_phy_cfg_tbls { 1080 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1081 const struct qmp_phy_init_tbl *serdes; 1082 int serdes_num; 1083 const struct qmp_phy_init_tbl *tx; 1084 int tx_num; 1085 const struct qmp_phy_init_tbl *rx; 1086 int rx_num; 1087 const struct qmp_phy_init_tbl *pcs; 1088 int pcs_num; 1089 /* Maximum supported Gear of this tbls */ 1090 u32 max_gear; 1091}; 1092 1093/* struct qmp_phy_cfg - per-PHY initialization config */ 1094struct qmp_phy_cfg { 1095 int lanes; 1096 1097 const struct qmp_ufs_offsets *offsets; 1098 /* Maximum supported Gear of this config */ 1099 u32 max_supported_gear; 1100 1101 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */ 1102 const struct qmp_phy_cfg_tbls tbls; 1103 /* Additional sequence for HS Series B */ 1104 const struct qmp_phy_cfg_tbls tbls_hs_b; 1105 /* Additional sequence for different HS Gears */ 1106 const struct qmp_phy_cfg_tbls tbls_hs_overlay[NUM_OVERLAY]; 1107 1108 /* regulators to be requested */ 1109 const struct regulator_bulk_data *vreg_list; 1110 int num_vregs; 1111 1112 /* array of registers with different offsets */ 1113 const unsigned int *regs; 1114 1115 /* true, if PCS block has no separate SW_RESET register */ 1116 bool no_pcs_sw_reset; 1117}; 1118 1119struct qmp_ufs { 1120 struct device *dev; 1121 1122 const struct qmp_phy_cfg *cfg; 1123 1124 void __iomem *serdes; 1125 void __iomem *pcs; 1126 void __iomem *pcs_misc; 1127 void __iomem *tx; 1128 void __iomem *rx; 1129 void __iomem *tx2; 1130 void __iomem *rx2; 1131 1132 struct clk_bulk_data *clks; 1133 int num_clks; 1134 struct regulator_bulk_data *vregs; 1135 struct reset_control *ufs_reset; 1136 1137 struct phy *phy; 1138 u32 mode; 1139 u32 submode; 1140}; 1141 1142static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1143{ 1144 u32 reg; 1145 1146 reg = readl(base + offset); 1147 reg |= val; 1148 writel(reg, base + offset); 1149 1150 /* ensure that above write is through */ 1151 readl(base + offset); 1152} 1153 1154static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1155{ 1156 u32 reg; 1157 1158 reg = readl(base + offset); 1159 reg &= ~val; 1160 writel(reg, base + offset); 1161 1162 /* ensure that above write is through */ 1163 readl(base + offset); 1164} 1165 1166/* Regulator bulk data with load values for specific configurations */ 1167static const struct regulator_bulk_data msm8996_ufsphy_vreg_l[] = { 1168 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1169 { .supply = "vdda-pll", .init_load_uA = 14600 }, 1170}; 1171 1172static const struct regulator_bulk_data sa8775p_ufsphy_vreg_l[] = { 1173 { .supply = "vdda-phy", .init_load_uA = 137000 }, 1174 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1175}; 1176 1177static const struct regulator_bulk_data sc7280_ufsphy_vreg_l[] = { 1178 { .supply = "vdda-phy", .init_load_uA = 97500 }, 1179 { .supply = "vdda-pll", .init_load_uA = 18400 }, 1180}; 1181 1182static const struct regulator_bulk_data sc8280xp_ufsphy_vreg_l[] = { 1183 { .supply = "vdda-phy", .init_load_uA = 85700 }, 1184 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1185}; 1186 1187static const struct regulator_bulk_data sdm845_ufsphy_vreg_l[] = { 1188 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1189 { .supply = "vdda-pll", .init_load_uA = 14600 }, 1190}; 1191 1192static const struct regulator_bulk_data sm6115_ufsphy_vreg_l[] = { 1193 { .supply = "vdda-phy", .init_load_uA = 51400 }, 1194 { .supply = "vdda-pll", .init_load_uA = 14200 }, 1195}; 1196 1197static const struct regulator_bulk_data sm7150_ufsphy_vreg_l[] = { 1198 { .supply = "vdda-phy", .init_load_uA = 62900 }, 1199 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1200}; 1201 1202static const struct regulator_bulk_data sm8150_ufsphy_vreg_l[] = { 1203 { .supply = "vdda-phy", .init_load_uA = 90200 }, 1204 { .supply = "vdda-pll", .init_load_uA = 19000 }, 1205}; 1206 1207static const struct regulator_bulk_data sm8250_ufsphy_vreg_l[] = { 1208 { .supply = "vdda-phy", .init_load_uA = 89900 }, 1209 { .supply = "vdda-pll", .init_load_uA = 18800 }, 1210}; 1211 1212static const struct regulator_bulk_data sm8350_ufsphy_vreg_l[] = { 1213 { .supply = "vdda-phy", .init_load_uA = 91600 }, 1214 { .supply = "vdda-pll", .init_load_uA = 19000 }, 1215}; 1216 1217static const struct regulator_bulk_data sm8450_ufsphy_vreg_l[] = { 1218 { .supply = "vdda-phy", .init_load_uA = 173000 }, 1219 { .supply = "vdda-pll", .init_load_uA = 24900 }, 1220}; 1221 1222static const struct regulator_bulk_data sm8475_ufsphy_vreg_l[] = { 1223 { .supply = "vdda-phy", .init_load_uA = 213030 }, 1224 { .supply = "vdda-pll", .init_load_uA = 18340 }, 1225}; 1226 1227static const struct regulator_bulk_data sm8550_ufsphy_vreg_l[] = { 1228 { .supply = "vdda-phy", .init_load_uA = 188000 }, 1229 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1230}; 1231 1232static const struct regulator_bulk_data sm8650_ufsphy_vreg_l[] = { 1233 { .supply = "vdda-phy", .init_load_uA = 205000 }, 1234 { .supply = "vdda-pll", .init_load_uA = 17500 }, 1235}; 1236 1237static const struct regulator_bulk_data sm8750_ufsphy_vreg_l[] = { 1238 { .supply = "vdda-phy", .init_load_uA = 213000 }, 1239 { .supply = "vdda-pll", .init_load_uA = 18300 }, 1240}; 1241 1242static const struct qmp_ufs_offsets qmp_ufs_offsets = { 1243 .serdes = 0, 1244 .pcs = 0xc00, 1245 .tx = 0x400, 1246 .rx = 0x600, 1247 .tx2 = 0x800, 1248 .rx2 = 0xa00, 1249}; 1250 1251static const struct qmp_ufs_offsets qmp_ufs_offsets_v6 = { 1252 .serdes = 0, 1253 .pcs = 0x0400, 1254 .tx = 0x1000, 1255 .rx = 0x1200, 1256 .tx2 = 0x1800, 1257 .rx2 = 0x1a00, 1258}; 1259 1260static const struct qmp_phy_cfg msm8996_ufsphy_cfg = { 1261 .lanes = 1, 1262 1263 .offsets = &qmp_ufs_offsets, 1264 .max_supported_gear = UFS_HS_G3, 1265 1266 .tbls = { 1267 .serdes = msm8996_ufsphy_serdes, 1268 .serdes_num = ARRAY_SIZE(msm8996_ufsphy_serdes), 1269 .tx = msm8996_ufsphy_tx, 1270 .tx_num = ARRAY_SIZE(msm8996_ufsphy_tx), 1271 .rx = msm8996_ufsphy_rx, 1272 .rx_num = ARRAY_SIZE(msm8996_ufsphy_rx), 1273 }, 1274 1275 .vreg_list = msm8996_ufsphy_vreg_l, 1276 .num_vregs = ARRAY_SIZE(msm8996_ufsphy_vreg_l), 1277 1278 .regs = ufsphy_v2_regs_layout, 1279 1280 .no_pcs_sw_reset = true, 1281}; 1282 1283static const struct qmp_phy_cfg sa8775p_ufsphy_cfg = { 1284 .lanes = 2, 1285 1286 .offsets = &qmp_ufs_offsets, 1287 .max_supported_gear = UFS_HS_G4, 1288 1289 .tbls = { 1290 .serdes = sm8350_ufsphy_serdes, 1291 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1292 .tx = sm8350_ufsphy_tx, 1293 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1294 .rx = sm8350_ufsphy_rx, 1295 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1296 .pcs = sm8350_ufsphy_pcs, 1297 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1298 }, 1299 .tbls_hs_b = { 1300 .serdes = sm8350_ufsphy_hs_b_serdes, 1301 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1302 }, 1303 .tbls_hs_overlay[0] = { 1304 .tx = sm8350_ufsphy_g4_tx, 1305 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1306 .rx = sm8350_ufsphy_g4_rx, 1307 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1308 .pcs = sm8350_ufsphy_g4_pcs, 1309 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1310 .max_gear = UFS_HS_G4, 1311 }, 1312 .vreg_list = sa8775p_ufsphy_vreg_l, 1313 .num_vregs = ARRAY_SIZE(sa8775p_ufsphy_vreg_l), 1314 .regs = ufsphy_v5_regs_layout, 1315}; 1316 1317static const struct qmp_phy_cfg sc7280_ufsphy_cfg = { 1318 .lanes = 2, 1319 1320 .offsets = &qmp_ufs_offsets, 1321 .max_supported_gear = UFS_HS_G4, 1322 1323 .tbls = { 1324 .serdes = sm8150_ufsphy_serdes, 1325 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1326 .tx = sc7280_ufsphy_tx, 1327 .tx_num = ARRAY_SIZE(sc7280_ufsphy_tx), 1328 .rx = sc7280_ufsphy_rx, 1329 .rx_num = ARRAY_SIZE(sc7280_ufsphy_rx), 1330 .pcs = sc7280_ufsphy_pcs, 1331 .pcs_num = ARRAY_SIZE(sc7280_ufsphy_pcs), 1332 }, 1333 .tbls_hs_b = { 1334 .serdes = sm8150_ufsphy_hs_b_serdes, 1335 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1336 }, 1337 .tbls_hs_overlay[0] = { 1338 .tx = sm8250_ufsphy_hs_g4_tx, 1339 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1340 .rx = sc7280_ufsphy_hs_g4_rx, 1341 .rx_num = ARRAY_SIZE(sc7280_ufsphy_hs_g4_rx), 1342 .pcs = sm8150_ufsphy_hs_g4_pcs, 1343 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1344 .max_gear = UFS_HS_G4, 1345 }, 1346 .vreg_list = sc7280_ufsphy_vreg_l, 1347 .num_vregs = ARRAY_SIZE(sc7280_ufsphy_vreg_l), 1348 .regs = ufsphy_v4_regs_layout, 1349}; 1350 1351static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { 1352 .lanes = 2, 1353 1354 .offsets = &qmp_ufs_offsets, 1355 .max_supported_gear = UFS_HS_G4, 1356 1357 .tbls = { 1358 .serdes = sm8350_ufsphy_serdes, 1359 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1360 .tx = sm8350_ufsphy_tx, 1361 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1362 .rx = sm8350_ufsphy_rx, 1363 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1364 .pcs = sm8350_ufsphy_pcs, 1365 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1366 }, 1367 .tbls_hs_b = { 1368 .serdes = sm8350_ufsphy_hs_b_serdes, 1369 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1370 }, 1371 .tbls_hs_overlay[0] = { 1372 .tx = sm8350_ufsphy_g4_tx, 1373 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1374 .rx = sm8350_ufsphy_g4_rx, 1375 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1376 .pcs = sm8350_ufsphy_g4_pcs, 1377 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1378 .max_gear = UFS_HS_G4, 1379 }, 1380 .vreg_list = sc8280xp_ufsphy_vreg_l, 1381 .num_vregs = ARRAY_SIZE(sc8280xp_ufsphy_vreg_l), 1382 .regs = ufsphy_v5_regs_layout, 1383}; 1384 1385static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { 1386 .lanes = 2, 1387 1388 .offsets = &qmp_ufs_offsets, 1389 .max_supported_gear = UFS_HS_G3, 1390 1391 .tbls = { 1392 .serdes = sdm845_ufsphy_serdes, 1393 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1394 .tx = sdm845_ufsphy_tx, 1395 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1396 .rx = sdm845_ufsphy_rx, 1397 .rx_num = ARRAY_SIZE(sdm845_ufsphy_rx), 1398 .pcs = sdm845_ufsphy_pcs, 1399 .pcs_num = ARRAY_SIZE(sdm845_ufsphy_pcs), 1400 }, 1401 .tbls_hs_b = { 1402 .serdes = sdm845_ufsphy_hs_b_serdes, 1403 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1404 }, 1405 .vreg_list = sdm845_ufsphy_vreg_l, 1406 .num_vregs = ARRAY_SIZE(sdm845_ufsphy_vreg_l), 1407 .regs = ufsphy_v3_regs_layout, 1408 1409 .no_pcs_sw_reset = true, 1410}; 1411 1412static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { 1413 .lanes = 1, 1414 1415 .offsets = &qmp_ufs_offsets, 1416 .max_supported_gear = UFS_HS_G3, 1417 1418 .tbls = { 1419 .serdes = sm6115_ufsphy_serdes, 1420 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_serdes), 1421 .tx = sm6115_ufsphy_tx, 1422 .tx_num = ARRAY_SIZE(sm6115_ufsphy_tx), 1423 .rx = sm6115_ufsphy_rx, 1424 .rx_num = ARRAY_SIZE(sm6115_ufsphy_rx), 1425 .pcs = sm6115_ufsphy_pcs, 1426 .pcs_num = ARRAY_SIZE(sm6115_ufsphy_pcs), 1427 }, 1428 .tbls_hs_b = { 1429 .serdes = sm6115_ufsphy_hs_b_serdes, 1430 .serdes_num = ARRAY_SIZE(sm6115_ufsphy_hs_b_serdes), 1431 }, 1432 .vreg_list = sm6115_ufsphy_vreg_l, 1433 .num_vregs = ARRAY_SIZE(sm6115_ufsphy_vreg_l), 1434 .regs = ufsphy_v2_regs_layout, 1435 1436 .no_pcs_sw_reset = true, 1437}; 1438 1439static const struct qmp_phy_cfg sm7150_ufsphy_cfg = { 1440 .lanes = 1, 1441 1442 .offsets = &qmp_ufs_offsets, 1443 .max_supported_gear = UFS_HS_G3, 1444 1445 .tbls = { 1446 .serdes = sdm845_ufsphy_serdes, 1447 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_serdes), 1448 .tx = sdm845_ufsphy_tx, 1449 .tx_num = ARRAY_SIZE(sdm845_ufsphy_tx), 1450 .rx = sm7150_ufsphy_rx, 1451 .rx_num = ARRAY_SIZE(sm7150_ufsphy_rx), 1452 .pcs = sm7150_ufsphy_pcs, 1453 .pcs_num = ARRAY_SIZE(sm7150_ufsphy_pcs), 1454 }, 1455 .tbls_hs_b = { 1456 .serdes = sdm845_ufsphy_hs_b_serdes, 1457 .serdes_num = ARRAY_SIZE(sdm845_ufsphy_hs_b_serdes), 1458 }, 1459 .vreg_list = sm7150_ufsphy_vreg_l, 1460 .num_vregs = ARRAY_SIZE(sm7150_ufsphy_vreg_l), 1461 .regs = ufsphy_v3_regs_layout, 1462 1463 .no_pcs_sw_reset = true, 1464}; 1465 1466static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { 1467 .lanes = 2, 1468 1469 .offsets = &qmp_ufs_offsets, 1470 .max_supported_gear = UFS_HS_G4, 1471 1472 .tbls = { 1473 .serdes = sm8150_ufsphy_serdes, 1474 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1475 .tx = sm8150_ufsphy_tx, 1476 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1477 .rx = sm8150_ufsphy_rx, 1478 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1479 .pcs = sm8150_ufsphy_pcs, 1480 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1481 }, 1482 .tbls_hs_b = { 1483 .serdes = sm8150_ufsphy_hs_b_serdes, 1484 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1485 }, 1486 .tbls_hs_overlay[0] = { 1487 .tx = sm8150_ufsphy_hs_g4_tx, 1488 .tx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_tx), 1489 .rx = sm8150_ufsphy_hs_g4_rx, 1490 .rx_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_rx), 1491 .pcs = sm8150_ufsphy_hs_g4_pcs, 1492 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1493 .max_gear = UFS_HS_G4, 1494 }, 1495 .vreg_list = sm8150_ufsphy_vreg_l, 1496 .num_vregs = ARRAY_SIZE(sm8150_ufsphy_vreg_l), 1497 .regs = ufsphy_v4_regs_layout, 1498}; 1499 1500static const struct qmp_phy_cfg sm8250_ufsphy_cfg = { 1501 .lanes = 2, 1502 1503 .offsets = &qmp_ufs_offsets, 1504 .max_supported_gear = UFS_HS_G4, 1505 1506 .tbls = { 1507 .serdes = sm8150_ufsphy_serdes, 1508 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_serdes), 1509 .tx = sm8150_ufsphy_tx, 1510 .tx_num = ARRAY_SIZE(sm8150_ufsphy_tx), 1511 .rx = sm8150_ufsphy_rx, 1512 .rx_num = ARRAY_SIZE(sm8150_ufsphy_rx), 1513 .pcs = sm8150_ufsphy_pcs, 1514 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_pcs), 1515 }, 1516 .tbls_hs_b = { 1517 .serdes = sm8150_ufsphy_hs_b_serdes, 1518 .serdes_num = ARRAY_SIZE(sm8150_ufsphy_hs_b_serdes), 1519 }, 1520 .tbls_hs_overlay[0] = { 1521 .tx = sm8250_ufsphy_hs_g4_tx, 1522 .tx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_tx), 1523 .rx = sm8250_ufsphy_hs_g4_rx, 1524 .rx_num = ARRAY_SIZE(sm8250_ufsphy_hs_g4_rx), 1525 .pcs = sm8150_ufsphy_hs_g4_pcs, 1526 .pcs_num = ARRAY_SIZE(sm8150_ufsphy_hs_g4_pcs), 1527 .max_gear = UFS_HS_G4, 1528 }, 1529 .vreg_list = sm8250_ufsphy_vreg_l, 1530 .num_vregs = ARRAY_SIZE(sm8250_ufsphy_vreg_l), 1531 .regs = ufsphy_v4_regs_layout, 1532}; 1533 1534static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { 1535 .lanes = 2, 1536 1537 .offsets = &qmp_ufs_offsets, 1538 .max_supported_gear = UFS_HS_G4, 1539 1540 .tbls = { 1541 .serdes = sm8350_ufsphy_serdes, 1542 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1543 .tx = sm8350_ufsphy_tx, 1544 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1545 .rx = sm8350_ufsphy_rx, 1546 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1547 .pcs = sm8350_ufsphy_pcs, 1548 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1549 }, 1550 .tbls_hs_b = { 1551 .serdes = sm8350_ufsphy_hs_b_serdes, 1552 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1553 }, 1554 .tbls_hs_overlay[0] = { 1555 .tx = sm8350_ufsphy_g4_tx, 1556 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1557 .rx = sm8350_ufsphy_g4_rx, 1558 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1559 .pcs = sm8350_ufsphy_g4_pcs, 1560 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1561 .max_gear = UFS_HS_G4, 1562 }, 1563 .vreg_list = sm8350_ufsphy_vreg_l, 1564 .num_vregs = ARRAY_SIZE(sm8350_ufsphy_vreg_l), 1565 .regs = ufsphy_v5_regs_layout, 1566}; 1567 1568static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { 1569 .lanes = 2, 1570 1571 .offsets = &qmp_ufs_offsets, 1572 .max_supported_gear = UFS_HS_G4, 1573 1574 .tbls = { 1575 .serdes = sm8350_ufsphy_serdes, 1576 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_serdes), 1577 .tx = sm8350_ufsphy_tx, 1578 .tx_num = ARRAY_SIZE(sm8350_ufsphy_tx), 1579 .rx = sm8350_ufsphy_rx, 1580 .rx_num = ARRAY_SIZE(sm8350_ufsphy_rx), 1581 .pcs = sm8350_ufsphy_pcs, 1582 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_pcs), 1583 }, 1584 .tbls_hs_b = { 1585 .serdes = sm8350_ufsphy_hs_b_serdes, 1586 .serdes_num = ARRAY_SIZE(sm8350_ufsphy_hs_b_serdes), 1587 }, 1588 .tbls_hs_overlay[0] = { 1589 .tx = sm8350_ufsphy_g4_tx, 1590 .tx_num = ARRAY_SIZE(sm8350_ufsphy_g4_tx), 1591 .rx = sm8350_ufsphy_g4_rx, 1592 .rx_num = ARRAY_SIZE(sm8350_ufsphy_g4_rx), 1593 .pcs = sm8350_ufsphy_g4_pcs, 1594 .pcs_num = ARRAY_SIZE(sm8350_ufsphy_g4_pcs), 1595 .max_gear = UFS_HS_G4, 1596 }, 1597 .vreg_list = sm8450_ufsphy_vreg_l, 1598 .num_vregs = ARRAY_SIZE(sm8450_ufsphy_vreg_l), 1599 .regs = ufsphy_v5_regs_layout, 1600}; 1601 1602static const struct qmp_phy_cfg sm8475_ufsphy_cfg = { 1603 .lanes = 2, 1604 1605 .offsets = &qmp_ufs_offsets_v6, 1606 .max_supported_gear = UFS_HS_G4, 1607 1608 .tbls = { 1609 .serdes = sm8475_ufsphy_serdes, 1610 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_serdes), 1611 .tx = sm8550_ufsphy_tx, 1612 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1613 .rx = sm8550_ufsphy_rx, 1614 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1615 .pcs = sm8550_ufsphy_pcs, 1616 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1617 }, 1618 .tbls_hs_b = { 1619 .serdes = sm8550_ufsphy_hs_b_serdes, 1620 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1621 }, 1622 .tbls_hs_overlay[0] = { 1623 .serdes = sm8475_ufsphy_g4_serdes, 1624 .serdes_num = ARRAY_SIZE(sm8475_ufsphy_g4_serdes), 1625 .tx = sm8550_ufsphy_g4_tx, 1626 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1627 .rx = sm8550_ufsphy_g4_rx, 1628 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1629 .pcs = sm8475_ufsphy_g4_pcs, 1630 .pcs_num = ARRAY_SIZE(sm8475_ufsphy_g4_pcs), 1631 .max_gear = UFS_HS_G4, 1632 }, 1633 .vreg_list = sm8475_ufsphy_vreg_l, 1634 .num_vregs = ARRAY_SIZE(sm8475_ufsphy_vreg_l), 1635 .regs = ufsphy_v6_regs_layout, 1636}; 1637 1638static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { 1639 .lanes = 2, 1640 1641 .offsets = &qmp_ufs_offsets_v6, 1642 .max_supported_gear = UFS_HS_G5, 1643 1644 .tbls = { 1645 .serdes = sm8550_ufsphy_serdes, 1646 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_serdes), 1647 .tx = sm8550_ufsphy_tx, 1648 .tx_num = ARRAY_SIZE(sm8550_ufsphy_tx), 1649 .rx = sm8550_ufsphy_rx, 1650 .rx_num = ARRAY_SIZE(sm8550_ufsphy_rx), 1651 .pcs = sm8550_ufsphy_pcs, 1652 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), 1653 }, 1654 .tbls_hs_b = { 1655 .serdes = sm8550_ufsphy_hs_b_serdes, 1656 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), 1657 }, 1658 .tbls_hs_overlay[0] = { 1659 .serdes = sm8550_ufsphy_g4_serdes, 1660 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g4_serdes), 1661 .tx = sm8550_ufsphy_g4_tx, 1662 .tx_num = ARRAY_SIZE(sm8550_ufsphy_g4_tx), 1663 .rx = sm8550_ufsphy_g4_rx, 1664 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g4_rx), 1665 .pcs = sm8550_ufsphy_g4_pcs, 1666 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g4_pcs), 1667 .max_gear = UFS_HS_G4, 1668 }, 1669 .tbls_hs_overlay[1] = { 1670 .serdes = sm8550_ufsphy_g5_serdes, 1671 .serdes_num = ARRAY_SIZE(sm8550_ufsphy_g5_serdes), 1672 .rx = sm8550_ufsphy_g5_rx, 1673 .rx_num = ARRAY_SIZE(sm8550_ufsphy_g5_rx), 1674 .pcs = sm8550_ufsphy_g5_pcs, 1675 .pcs_num = ARRAY_SIZE(sm8550_ufsphy_g5_pcs), 1676 .max_gear = UFS_HS_G5, 1677 }, 1678 .vreg_list = sm8550_ufsphy_vreg_l, 1679 .num_vregs = ARRAY_SIZE(sm8550_ufsphy_vreg_l), 1680 .regs = ufsphy_v6_regs_layout, 1681}; 1682 1683static const struct qmp_phy_cfg sm8650_ufsphy_cfg = { 1684 .lanes = 2, 1685 1686 .offsets = &qmp_ufs_offsets_v6, 1687 .max_supported_gear = UFS_HS_G5, 1688 1689 .tbls = { 1690 .serdes = sm8650_ufsphy_serdes, 1691 .serdes_num = ARRAY_SIZE(sm8650_ufsphy_serdes), 1692 .tx = sm8650_ufsphy_tx, 1693 .tx_num = ARRAY_SIZE(sm8650_ufsphy_tx), 1694 .rx = sm8650_ufsphy_rx, 1695 .rx_num = ARRAY_SIZE(sm8650_ufsphy_rx), 1696 .pcs = sm8650_ufsphy_pcs, 1697 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_pcs), 1698 }, 1699 .tbls_hs_overlay[0] = { 1700 .pcs = sm8650_ufsphy_g4_pcs, 1701 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g4_pcs), 1702 .max_gear = UFS_HS_G4, 1703 }, 1704 .tbls_hs_overlay[1] = { 1705 .pcs = sm8650_ufsphy_g5_pcs, 1706 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1707 .max_gear = UFS_HS_G5, 1708 }, 1709 1710 .vreg_list = sm8650_ufsphy_vreg_l, 1711 .num_vregs = ARRAY_SIZE(sm8650_ufsphy_vreg_l), 1712 .regs = ufsphy_v6_regs_layout, 1713}; 1714 1715static const struct qmp_phy_cfg sm8750_ufsphy_cfg = { 1716 .lanes = 2, 1717 1718 .offsets = &qmp_ufs_offsets_v6, 1719 .max_supported_gear = UFS_HS_G5, 1720 1721 .tbls = { 1722 .serdes = sm8750_ufsphy_serdes, 1723 .serdes_num = ARRAY_SIZE(sm8750_ufsphy_serdes), 1724 .tx = sm8750_ufsphy_tx, 1725 .tx_num = ARRAY_SIZE(sm8750_ufsphy_tx), 1726 .rx = sm8750_ufsphy_rx, 1727 .rx_num = ARRAY_SIZE(sm8750_ufsphy_rx), 1728 .pcs = sm8750_ufsphy_pcs, 1729 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_pcs), 1730 }, 1731 1732 .tbls_hs_b = { 1733 .pcs = sm8750_ufsphy_hs_b_pcs, 1734 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_hs_b_pcs), 1735 }, 1736 1737 .tbls_hs_overlay[0] = { 1738 .pcs = sm8750_ufsphy_g4_pcs, 1739 .pcs_num = ARRAY_SIZE(sm8750_ufsphy_g4_pcs), 1740 .max_gear = UFS_HS_G4, 1741 }, 1742 .tbls_hs_overlay[1] = { 1743 .pcs = sm8650_ufsphy_g5_pcs, 1744 .pcs_num = ARRAY_SIZE(sm8650_ufsphy_g5_pcs), 1745 .max_gear = UFS_HS_G5, 1746 }, 1747 1748 .vreg_list = sm8750_ufsphy_vreg_l, 1749 .num_vregs = ARRAY_SIZE(sm8750_ufsphy_vreg_l), 1750 .regs = ufsphy_v6_regs_layout, 1751 1752}; 1753 1754static void qmp_ufs_serdes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1755{ 1756 void __iomem *serdes = qmp->serdes; 1757 1758 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); 1759} 1760 1761static void qmp_ufs_lanes_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1762{ 1763 const struct qmp_phy_cfg *cfg = qmp->cfg; 1764 void __iomem *tx = qmp->tx; 1765 void __iomem *rx = qmp->rx; 1766 1767 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); 1768 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); 1769 1770 if (cfg->lanes >= 2) { 1771 qmp_configure_lane(qmp->dev, qmp->tx2, tbls->tx, tbls->tx_num, 2); 1772 qmp_configure_lane(qmp->dev, qmp->rx2, tbls->rx, tbls->rx_num, 2); 1773 } 1774} 1775 1776static void qmp_ufs_pcs_init(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1777{ 1778 void __iomem *pcs = qmp->pcs; 1779 1780 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); 1781} 1782 1783static int qmp_ufs_get_gear_overlay(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1784{ 1785 u32 max_gear, floor_max_gear = cfg->max_supported_gear; 1786 int idx, ret = -EINVAL; 1787 1788 for (idx = NUM_OVERLAY - 1; idx >= 0; idx--) { 1789 max_gear = cfg->tbls_hs_overlay[idx].max_gear; 1790 1791 /* Skip if the table is not available */ 1792 if (max_gear == 0) 1793 continue; 1794 1795 /* Direct matching, bail */ 1796 if (qmp->submode == max_gear) 1797 return idx; 1798 1799 /* If no direct matching, the lowest gear is the best matching */ 1800 if (max_gear < floor_max_gear) { 1801 ret = idx; 1802 floor_max_gear = max_gear; 1803 } 1804 } 1805 1806 return ret; 1807} 1808 1809static void qmp_ufs_init_all(struct qmp_ufs *qmp, const struct qmp_phy_cfg_tbls *tbls) 1810{ 1811 qmp_ufs_serdes_init(qmp, tbls); 1812 qmp_ufs_lanes_init(qmp, tbls); 1813 qmp_ufs_pcs_init(qmp, tbls); 1814} 1815 1816static void qmp_ufs_init_registers(struct qmp_ufs *qmp, const struct qmp_phy_cfg *cfg) 1817{ 1818 int i; 1819 1820 qmp_ufs_init_all(qmp, &cfg->tbls); 1821 1822 i = qmp_ufs_get_gear_overlay(qmp, cfg); 1823 if (i >= 0) { 1824 qmp_ufs_init_all(qmp, &cfg->tbls_hs_overlay[i]); 1825 } 1826 1827 if (qmp->mode == PHY_MODE_UFS_HS_B) 1828 qmp_ufs_init_all(qmp, &cfg->tbls_hs_b); 1829} 1830 1831static int qmp_ufs_power_on(struct phy *phy) 1832{ 1833 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1834 const struct qmp_phy_cfg *cfg = qmp->cfg; 1835 void __iomem *pcs = qmp->pcs; 1836 int ret; 1837 1838 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1839 if (ret) { 1840 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1841 return ret; 1842 } 1843 1844 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks); 1845 if (ret) 1846 goto err_disable_regulators; 1847 1848 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1849 return 0; 1850 1851err_disable_regulators: 1852 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1853 return ret; 1854} 1855 1856static int qmp_ufs_phy_calibrate(struct phy *phy) 1857{ 1858 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1859 const struct qmp_phy_cfg *cfg = qmp->cfg; 1860 void __iomem *pcs = qmp->pcs; 1861 void __iomem *status; 1862 unsigned int val; 1863 int ret; 1864 1865 ret = reset_control_assert(qmp->ufs_reset); 1866 if (ret) 1867 return ret; 1868 1869 qmp_ufs_init_registers(qmp, cfg); 1870 1871 ret = reset_control_deassert(qmp->ufs_reset); 1872 if (ret) 1873 return ret; 1874 1875 /* Pull PHY out of reset state */ 1876 if (!cfg->no_pcs_sw_reset) 1877 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1878 1879 /* start SerDes */ 1880 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START); 1881 1882 status = pcs + cfg->regs[QPHY_PCS_READY_STATUS]; 1883 ret = readl_poll_timeout(status, val, (val & PCS_READY), 200, 1884 PHY_INIT_COMPLETE_TIMEOUT); 1885 if (ret) { 1886 dev_err(qmp->dev, "phy initialization timed-out\n"); 1887 return ret; 1888 } 1889 1890 return 0; 1891} 1892 1893static int qmp_ufs_power_off(struct phy *phy) 1894{ 1895 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1896 const struct qmp_phy_cfg *cfg = qmp->cfg; 1897 1898 /* Put PHY into POWER DOWN state: active low */ 1899 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1900 SW_PWRDN); 1901 1902 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks); 1903 1904 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1905 1906 return 0; 1907} 1908 1909static int qmp_ufs_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1910{ 1911 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1912 const struct qmp_phy_cfg *cfg = qmp->cfg; 1913 1914 if (submode > cfg->max_supported_gear || submode == 0) { 1915 dev_err(qmp->dev, "Invalid PHY submode %d\n", submode); 1916 return -EINVAL; 1917 } 1918 1919 qmp->mode = mode; 1920 qmp->submode = submode; 1921 1922 return 0; 1923} 1924 1925static int qmp_ufs_phy_init(struct phy *phy) 1926{ 1927 struct qmp_ufs *qmp = phy_get_drvdata(phy); 1928 const struct qmp_phy_cfg *cfg = qmp->cfg; 1929 int ret; 1930 1931 if (!cfg->no_pcs_sw_reset) 1932 return 0; 1933 1934 /* 1935 * Get UFS reset, which is delayed until now to avoid a 1936 * circular dependency where UFS needs its PHY, but the PHY 1937 * needs this UFS reset. 1938 */ 1939 if (!qmp->ufs_reset) { 1940 qmp->ufs_reset = 1941 devm_reset_control_get_exclusive(qmp->dev, "ufsphy"); 1942 1943 if (IS_ERR(qmp->ufs_reset)) { 1944 ret = PTR_ERR(qmp->ufs_reset); 1945 dev_err(qmp->dev, "failed to get PHY reset: %d\n", ret); 1946 qmp->ufs_reset = NULL; 1947 return ret; 1948 } 1949 } 1950 1951 return 0; 1952} 1953 1954static const struct phy_ops qcom_qmp_ufs_phy_ops = { 1955 .init = qmp_ufs_phy_init, 1956 .power_on = qmp_ufs_power_on, 1957 .power_off = qmp_ufs_power_off, 1958 .calibrate = qmp_ufs_phy_calibrate, 1959 .set_mode = qmp_ufs_set_mode, 1960 .owner = THIS_MODULE, 1961}; 1962 1963 1964static int qmp_ufs_clk_init(struct qmp_ufs *qmp) 1965{ 1966 struct device *dev = qmp->dev; 1967 1968 qmp->num_clks = devm_clk_bulk_get_all(dev, &qmp->clks); 1969 if (qmp->num_clks < 0) 1970 return qmp->num_clks; 1971 1972 return 0; 1973} 1974 1975static void qmp_ufs_clk_release_provider(void *res) 1976{ 1977 of_clk_del_provider(res); 1978} 1979 1980#define UFS_SYMBOL_CLOCKS 3 1981 1982static int qmp_ufs_register_clocks(struct qmp_ufs *qmp, struct device_node *np) 1983{ 1984 struct clk_hw_onecell_data *clk_data; 1985 struct clk_hw *hw; 1986 char name[64]; 1987 int ret; 1988 1989 clk_data = devm_kzalloc(qmp->dev, 1990 struct_size(clk_data, hws, UFS_SYMBOL_CLOCKS), 1991 GFP_KERNEL); 1992 if (!clk_data) 1993 return -ENOMEM; 1994 1995 clk_data->num = UFS_SYMBOL_CLOCKS; 1996 1997 snprintf(name, sizeof(name), "%s::rx_symbol_0", dev_name(qmp->dev)); 1998 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 1999 if (IS_ERR(hw)) 2000 return PTR_ERR(hw); 2001 2002 clk_data->hws[0] = hw; 2003 2004 snprintf(name, sizeof(name), "%s::rx_symbol_1", dev_name(qmp->dev)); 2005 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2006 if (IS_ERR(hw)) 2007 return PTR_ERR(hw); 2008 2009 clk_data->hws[1] = hw; 2010 2011 snprintf(name, sizeof(name), "%s::tx_symbol_0", dev_name(qmp->dev)); 2012 hw = devm_clk_hw_register_fixed_rate(qmp->dev, name, NULL, 0, 0); 2013 if (IS_ERR(hw)) 2014 return PTR_ERR(hw); 2015 2016 clk_data->hws[2] = hw; 2017 2018 ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data); 2019 if (ret) 2020 return ret; 2021 2022 /* 2023 * Roll a devm action because the clock provider can be a child node. 2024 */ 2025 return devm_add_action_or_reset(qmp->dev, qmp_ufs_clk_release_provider, np); 2026} 2027 2028static int qmp_ufs_parse_dt_legacy(struct qmp_ufs *qmp, struct device_node *np) 2029{ 2030 struct platform_device *pdev = to_platform_device(qmp->dev); 2031 const struct qmp_phy_cfg *cfg = qmp->cfg; 2032 struct device *dev = qmp->dev; 2033 2034 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2035 if (IS_ERR(qmp->serdes)) 2036 return PTR_ERR(qmp->serdes); 2037 2038 /* 2039 * Get memory resources for the PHY: 2040 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2041 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2042 * For single lane PHYs: pcs_misc (optional) -> 3. 2043 */ 2044 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2045 if (IS_ERR(qmp->tx)) 2046 return PTR_ERR(qmp->tx); 2047 2048 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2049 if (IS_ERR(qmp->rx)) 2050 return PTR_ERR(qmp->rx); 2051 2052 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); 2053 if (IS_ERR(qmp->pcs)) 2054 return PTR_ERR(qmp->pcs); 2055 2056 if (cfg->lanes >= 2) { 2057 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2058 if (IS_ERR(qmp->tx2)) 2059 return PTR_ERR(qmp->tx2); 2060 2061 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2062 if (IS_ERR(qmp->rx2)) 2063 return PTR_ERR(qmp->rx2); 2064 2065 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2066 } else { 2067 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2068 } 2069 2070 if (IS_ERR(qmp->pcs_misc)) 2071 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2072 2073 return 0; 2074} 2075 2076static int qmp_ufs_parse_dt(struct qmp_ufs *qmp) 2077{ 2078 struct platform_device *pdev = to_platform_device(qmp->dev); 2079 const struct qmp_phy_cfg *cfg = qmp->cfg; 2080 const struct qmp_ufs_offsets *offs = cfg->offsets; 2081 void __iomem *base; 2082 2083 if (!offs) 2084 return -EINVAL; 2085 2086 base = devm_platform_ioremap_resource(pdev, 0); 2087 if (IS_ERR(base)) 2088 return PTR_ERR(base); 2089 2090 qmp->serdes = base + offs->serdes; 2091 qmp->pcs = base + offs->pcs; 2092 qmp->tx = base + offs->tx; 2093 qmp->rx = base + offs->rx; 2094 2095 if (cfg->lanes >= 2) { 2096 qmp->tx2 = base + offs->tx2; 2097 qmp->rx2 = base + offs->rx2; 2098 } 2099 2100 return 0; 2101} 2102 2103static int qmp_ufs_probe(struct platform_device *pdev) 2104{ 2105 struct device *dev = &pdev->dev; 2106 struct phy_provider *phy_provider; 2107 struct device_node *np; 2108 struct qmp_ufs *qmp; 2109 int ret; 2110 2111 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2112 if (!qmp) 2113 return -ENOMEM; 2114 2115 qmp->dev = dev; 2116 2117 qmp->cfg = of_device_get_match_data(dev); 2118 if (!qmp->cfg) 2119 return -EINVAL; 2120 2121 ret = qmp_ufs_clk_init(qmp); 2122 if (ret) 2123 return ret; 2124 2125 ret = devm_regulator_bulk_get_const(dev, qmp->cfg->num_vregs, 2126 qmp->cfg->vreg_list, 2127 &qmp->vregs); 2128 if (ret) 2129 return ret; 2130 2131 /* Check for legacy binding with child node. */ 2132 np = of_get_next_available_child(dev->of_node, NULL); 2133 if (np) { 2134 ret = qmp_ufs_parse_dt_legacy(qmp, np); 2135 } else { 2136 np = of_node_get(dev->of_node); 2137 ret = qmp_ufs_parse_dt(qmp); 2138 } 2139 if (ret) 2140 goto err_node_put; 2141 2142 ret = qmp_ufs_register_clocks(qmp, np); 2143 if (ret) 2144 goto err_node_put; 2145 2146 qmp->phy = devm_phy_create(dev, np, &qcom_qmp_ufs_phy_ops); 2147 if (IS_ERR(qmp->phy)) { 2148 ret = PTR_ERR(qmp->phy); 2149 dev_err(dev, "failed to create PHY: %d\n", ret); 2150 goto err_node_put; 2151 } 2152 2153 phy_set_drvdata(qmp->phy, qmp); 2154 2155 of_node_put(np); 2156 2157 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2158 2159 return PTR_ERR_OR_ZERO(phy_provider); 2160 2161err_node_put: 2162 of_node_put(np); 2163 return ret; 2164} 2165 2166static const struct of_device_id qmp_ufs_of_match_table[] = { 2167 { 2168 .compatible = "qcom,msm8996-qmp-ufs-phy", 2169 .data = &msm8996_ufsphy_cfg, 2170 }, { 2171 .compatible = "qcom,msm8998-qmp-ufs-phy", 2172 .data = &sdm845_ufsphy_cfg, 2173 }, { 2174 .compatible = "qcom,sa8775p-qmp-ufs-phy", 2175 .data = &sa8775p_ufsphy_cfg, 2176 }, { 2177 .compatible = "qcom,sc7180-qmp-ufs-phy", 2178 .data = &sm7150_ufsphy_cfg, 2179 }, { 2180 .compatible = "qcom,sc7280-qmp-ufs-phy", 2181 .data = &sc7280_ufsphy_cfg, 2182 }, { 2183 .compatible = "qcom,sc8180x-qmp-ufs-phy", 2184 .data = &sm8150_ufsphy_cfg, 2185 }, { 2186 .compatible = "qcom,sc8280xp-qmp-ufs-phy", 2187 .data = &sc8280xp_ufsphy_cfg, 2188 }, { 2189 .compatible = "qcom,sdm845-qmp-ufs-phy", 2190 .data = &sdm845_ufsphy_cfg, 2191 }, { 2192 .compatible = "qcom,sm6115-qmp-ufs-phy", 2193 .data = &sm6115_ufsphy_cfg, 2194 }, { 2195 .compatible = "qcom,sm6125-qmp-ufs-phy", 2196 .data = &sm6115_ufsphy_cfg, 2197 }, { 2198 .compatible = "qcom,sm6350-qmp-ufs-phy", 2199 .data = &sdm845_ufsphy_cfg, 2200 }, { 2201 .compatible = "qcom,sm7150-qmp-ufs-phy", 2202 .data = &sm7150_ufsphy_cfg, 2203 }, { 2204 .compatible = "qcom,sm8150-qmp-ufs-phy", 2205 .data = &sm8150_ufsphy_cfg, 2206 }, { 2207 .compatible = "qcom,sm8250-qmp-ufs-phy", 2208 .data = &sm8250_ufsphy_cfg, 2209 }, { 2210 .compatible = "qcom,sm8350-qmp-ufs-phy", 2211 .data = &sm8350_ufsphy_cfg, 2212 }, { 2213 .compatible = "qcom,sm8450-qmp-ufs-phy", 2214 .data = &sm8450_ufsphy_cfg, 2215 }, { 2216 .compatible = "qcom,sm8475-qmp-ufs-phy", 2217 .data = &sm8475_ufsphy_cfg, 2218 }, { 2219 .compatible = "qcom,sm8550-qmp-ufs-phy", 2220 .data = &sm8550_ufsphy_cfg, 2221 }, { 2222 .compatible = "qcom,sm8650-qmp-ufs-phy", 2223 .data = &sm8650_ufsphy_cfg, 2224 }, { 2225 .compatible = "qcom,sm8750-qmp-ufs-phy", 2226 .data = &sm8750_ufsphy_cfg, 2227 }, 2228 2229 { }, 2230}; 2231MODULE_DEVICE_TABLE(of, qmp_ufs_of_match_table); 2232 2233static struct platform_driver qmp_ufs_driver = { 2234 .probe = qmp_ufs_probe, 2235 .driver = { 2236 .name = "qcom-qmp-ufs-phy", 2237 .of_match_table = qmp_ufs_of_match_table, 2238 }, 2239}; 2240 2241module_platform_driver(qmp_ufs_driver); 2242 2243MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2244MODULE_DESCRIPTION("Qualcomm QMP UFS PHY driver"); 2245MODULE_LICENSE("GPL v2");
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