phy-qcom-qmp-qserdes-txrx-v6_n4.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2023, Linaro Limited
 4 */
 5
 6#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
 7#define QCOM_PHY_QMP_QSERDES_TXRX_V6_N4_H_
 8
 9#define QSERDES_V6_N4_TX_CLKBUF_ENABLE			0x08
10#define QSERDES_V6_N4_TX_TX_EMP_POST1_LVL		0x0c
11#define QSERDES_V6_N4_TX_TX_DRV_LVL			0x14
12#define QSERDES_V6_N4_TX_RESET_TSYNC_EN			0x1c
13#define QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN		0x20
14#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX	0x30
15#define QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX	0x34
16#define QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN		0x48
17#define QSERDES_V6_N4_TX_HIGHZ_DRVR_EN			0x4c
18#define QSERDES_V6_N4_TX_TX_POL_INV			0x50
19#define QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN	0x54
20#define QSERDES_V6_N4_TX_LANE_MODE_1			0x78
21#define QSERDES_V6_N4_TX_LANE_MODE_2			0x7c
22#define QSERDES_V6_N4_TX_LANE_MODE_3			0x80
23#define QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN		0xac
24#define QSERDES_V6_N4_TX_TX_BAND			0xd8
25#define QSERDES_V6_N4_TX_INTERFACE_SELECT		0xe4
26#define QSERDES_V6_N4_TX_VMODE_CTRL1			0xb0
27
28#define QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2		0x8
29#define QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2		0x18
30#define QSERDES_V6_N4_RX_UCDR_PI_CONTROLS		0x20
31#define QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE		0x94
32#define QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2		0x9c
33#define QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET		0xa0
34#define QSERDES_V6_N4_RX_DFE_3				0xb4
35#define QSERDES_V6_N4_RX_VGA_CAL_CNTRL1			0xe0
36#define QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL		0xe8
37#define QSERDES_V6_N4_RX_GM_CAL				0x10c
38#define QSERDES_V6_N4_RX_SIGDET_ENABLES			0x148
39#define QSERDES_V6_N4_RX_SIGDET_CNTRL			0x14c
40#define QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL		0x154
41#define QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET	0x194
42#define QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32	0x1dc
43#define QSERDES_V6_N4_RX_UCDR_PI_CTRL1			0x23c
44#define QSERDES_V6_N4_RX_UCDR_PI_CTRL2			0x240
45#define QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2		0x27c
46#define QSERDES_V6_N4_RX_DFE_DAC_ENABLE1		0x298
47#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B0		0x2b8
48#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B1		0x2bc
49#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B2		0x2c0
50#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B3		0x2c4
51#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B4		0x2c8
52#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B5		0x2cc
53#define QSERDES_V6_N4_RX_MODE_RATE_0_1_B6		0x2d0
54#define QSERDES_V6_N4_RX_MODE_RATE2_B0			0x2d4
55#define QSERDES_V6_N4_RX_MODE_RATE2_B1			0x2d8
56#define QSERDES_V6_N4_RX_MODE_RATE2_B2			0x2dc
57#define QSERDES_V6_N4_RX_MODE_RATE2_B3			0x2e0
58#define QSERDES_V6_N4_RX_MODE_RATE2_B4			0x2e4
59#define QSERDES_V6_N4_RX_MODE_RATE2_B5			0x2e8
60#define QSERDES_V6_N4_RX_MODE_RATE2_B6			0x2ec
61#define QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE		0x30c
62#define QSERDES_V6_N4_RX_RX_BKUP_CTRL1			0x310
63
64#endif