phy-qcom-qmp-qserdes-com-v8.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 4 */
 5
 6#ifndef QCOM_PHY_QMP_QSERDES_COM_V8_H_
 7#define QCOM_PHY_QMP_QSERDES_COM_V8_H_
 8
 9/* Only for QMP V8 PHY - QSERDES COM registers */
10#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1		0x000
11#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1		0x004
12#define QSERDES_V8_COM_SSC_STEP_SIZE3_MODE1		0x008
13#define QSERDES_V8_COM_CP_CTRL_MODE1			0x010
14#define QSERDES_V8_COM_PLL_RCTRL_MODE1			0x014
15#define QSERDES_V8_COM_PLL_CCTRL_MODE1			0x018
16#define QSERDES_V8_COM_CORECLK_DIV_MODE1		0x01c
17#define QSERDES_V8_COM_LOCK_CMP1_MODE1			0x020
18#define QSERDES_V8_COM_LOCK_CMP2_MODE1			0x024
19#define QSERDES_V8_COM_DEC_START_MODE1			0x028
20#define QSERDES_V8_COM_DEC_START_MSB_MODE1		0x02c
21#define QSERDES_V8_COM_DIV_FRAC_START1_MODE1		0x030
22#define QSERDES_V8_COM_DIV_FRAC_START2_MODE1		0x034
23#define QSERDES_V8_COM_DIV_FRAC_START3_MODE1		0x038
24#define QSERDES_V8_COM_HSCLK_SEL_1			0x03c
25#define QSERDES_V8_COM_VCO_TUNE1_MODE1			0x048
26#define QSERDES_V8_COM_VCO_TUNE2_MODE1			0x04c
27#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1	0x050
28#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1	0x054
29#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0	0x058
30#define QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0	0x05c
31#define QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0		0x060
32#define QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0		0x064
33#define QSERDES_V8_COM_CP_CTRL_MODE0			0x070
34#define QSERDES_V8_COM_PLL_RCTRL_MODE0			0x074
35#define QSERDES_V8_COM_PLL_CCTRL_MODE0			0x078
36#define QSERDES_V8_COM_LOCK_CMP1_MODE0			0x080
37#define QSERDES_V8_COM_LOCK_CMP2_MODE0			0x084
38#define QSERDES_V8_COM_DEC_START_MODE0			0x088
39#define QSERDES_V8_COM_DEC_START_MSB_MODE0		0x08c
40#define QSERDES_V8_COM_DIV_FRAC_START1_MODE0		0x090
41#define QSERDES_V8_COM_DIV_FRAC_START2_MODE0		0x094
42#define QSERDES_V8_COM_DIV_FRAC_START3_MODE0		0x098
43#define QSERDES_V8_COM_VCO_TUNE1_MODE0			0x0a8
44#define QSERDES_V8_COM_VCO_TUNE2_MODE0			0x0ac
45#define QSERDES_V8_COM_BG_TIMER				0x0bc
46#define QSERDES_V8_COM_SSC_EN_CENTER			0x0c0
47#define QSERDES_V8_COM_SSC_PER1				0x0cc
48#define QSERDES_V8_COM_SSC_PER2				0x0d0
49#define QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN		0x0dc
50#define QSERDES_V8_COM_SYSCLK_BUF_ENABLE		0x0e8
51#define QSERDES_V8_COM_SYSCLK_EN_SEL			0x110
52#define QSERDES_V8_COM_RESETSM_CNTRL			0x118
53#define QSERDES_V8_COM_LOCK_CMP_CFG			0x124
54#define QSERDES_V8_COM_VCO_TUNE_MAP			0x140
55#define QSERDES_V8_COM_CORE_CLK_EN			0x170
56#define QSERDES_V8_COM_CMN_CONFIG_1			0x174
57#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1		0x1a4
58#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2		0x1a8
59#define QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3		0x1ac
60#define QSERDES_V8_COM_ADDITIONAL_MISC			0x1b4
61#define QSERDES_V8_COM_CMN_STATUS			0x2c8
62#define QSERDES_V8_COM_C_READY_STATUS			0x2f0
63
64#endif