phy-qcom-qmp-pcs-v8.h

 1/* SPDX-License-Identifier: GPL-2.0 */
 2/*
 3 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved.
 4 */
 5
 6#ifndef QCOM_PHY_QMP_PCS_V8_H_
 7#define QCOM_PHY_QMP_PCS_V8_H_
 8
 9/* Only for QMP V8 PHY - USB/PCIe PCS registers */
10#define QPHY_V8_PCS_SW_RESET			0x000
11#define QPHY_V8_PCS_PCS_STATUS1			0x014
12#define QPHY_V8_PCS_POWER_DOWN_CONTROL		0x040
13#define QPHY_V8_PCS_START_CONTROL		0x044
14#define QPHY_V8_PCS_POWER_STATE_CONFIG1		0x090
15#define QPHY_V8_PCS_LOCK_DETECT_CONFIG1		0x0c4
16#define QPHY_V8_PCS_LOCK_DETECT_CONFIG2		0x0c8
17#define QPHY_V8_PCS_LOCK_DETECT_CONFIG3		0x0cc
18#define QPHY_V8_PCS_LOCK_DETECT_CONFIG6		0x0d8
19#define QPHY_V8_PCS_REFGEN_REQ_CONFIG1		0x0dc
20#define QPHY_V8_PCS_RX_SIGDET_LVL		0x188
21#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L	0x190
22#define QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H	0x194
23#define QPHY_V8_PCS_RATE_SLEW_CNTRL1		0x198
24#define QPHY_V8_PCS_CDR_RESET_TIME		0x1b0
25#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG1	0x1c0
26#define QPHY_V8_PCS_ALIGN_DETECT_CONFIG2	0x1c4
27#define QPHY_V8_PCS_PCS_TX_RX_CONFIG		0x1d0
28#define QPHY_V8_PCS_EQ_CONFIG1			0x1dc
29#define QPHY_V8_PCS_EQ_CONFIG2			0x1e0
30#define QPHY_V8_PCS_EQ_CONFIG5			0x1ec
31
32#endif