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phy-mtk-tphy.c
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linux-6.19.14/drivers/phy/mediatek/phy-mtk-tphy.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> 5 * 6 */ 7 8#include <dt-bindings/phy/phy.h> 9#include <linux/clk.h> 10#include <linux/debugfs.h> 11#include <linux/delay.h> 12#include <linux/iopoll.h> 13#include <linux/mfd/syscon.h> 14#include <linux/module.h> 15#include <linux/nvmem-consumer.h> 16#include <linux/of.h> 17#include <linux/of_address.h> 18#include <linux/phy/phy.h> 19#include <linux/platform_device.h> 20#include <linux/regmap.h> 21 22#include "phy-mtk-io.h" 23 24/* version V1 sub-banks offset base address */ 25/* banks shared by multiple phys */ 26#define SSUSB_SIFSLV_V1_SPLLC 0x000 /* shared by u3 phys */ 27#define SSUSB_SIFSLV_V1_U2FREQ 0x100 /* shared by u2 phys */ 28#define SSUSB_SIFSLV_V1_CHIP 0x300 /* shared by u3 phys */ 29/* u2 phy bank */ 30#define SSUSB_SIFSLV_V1_U2PHY_COM 0x000 31/* u3/pcie/sata phy banks */ 32#define SSUSB_SIFSLV_V1_U3PHYD 0x000 33#define SSUSB_SIFSLV_V1_U3PHYA 0x200 34 35/* version V2/V3 sub-banks offset base address */ 36/* V3: U2FREQ is not used anymore, but reserved */ 37/* u2 phy banks */ 38#define SSUSB_SIFSLV_V2_MISC 0x000 39#define SSUSB_SIFSLV_V2_U2FREQ 0x100 40#define SSUSB_SIFSLV_V2_U2PHY_COM 0x300 41/* u3/pcie/sata phy banks */ 42#define SSUSB_SIFSLV_V2_SPLLC 0x000 43#define SSUSB_SIFSLV_V2_CHIP 0x100 44#define SSUSB_SIFSLV_V2_U3PHYD 0x200 45#define SSUSB_SIFSLV_V2_U3PHYA 0x400 46 47#define U3P_MISC_REG1 0x04 48#define MR1_EFUSE_AUTO_LOAD_DIS BIT(6) 49 50#define U3P_USBPHYACR0 0x000 51#define PA0_RG_U2PLL_FORCE_ON BIT(15) 52#define PA0_USB20_PLL_PREDIV GENMASK(7, 6) 53#define PA0_RG_USB20_INTR_EN BIT(5) 54 55#define U3P_USBPHYACR1 0x004 56#define PA1_RG_INTR_CAL GENMASK(23, 19) 57#define PA1_RG_VRT_SEL GENMASK(14, 12) 58#define PA1_RG_TERM_SEL GENMASK(10, 8) 59 60#define U3P_USBPHYACR2 0x008 61#define PA2_RG_U2PLL_BW GENMASK(21, 19) 62#define PA2_RG_SIF_U2PLL_FORCE_EN BIT(18) 63 64#define U3P_USBPHYACR5 0x014 65#define PA5_RG_U2_HSTX_SRCAL_EN BIT(15) 66#define PA5_RG_U2_HSTX_SRCTRL GENMASK(14, 12) 67#define PA5_RG_U2_HS_100U_U3_EN BIT(11) 68 69#define U3P_USBPHYACR6 0x018 70#define PA6_RG_U2_PRE_EMP GENMASK(31, 30) 71#define PA6_RG_U2_BC11_SW_EN BIT(23) 72#define PA6_RG_U2_OTG_VBUSCMP_EN BIT(20) 73#define PA6_RG_U2_DISCTH GENMASK(7, 4) 74#define PA6_RG_U2_SQTH GENMASK(3, 0) 75 76#define U3P_U2PHYACR4 0x020 77#define P2C_RG_USB20_GPIO_CTL BIT(9) 78#define P2C_USB20_GPIO_MODE BIT(8) 79#define P2C_U2_GPIO_CTR_MSK (P2C_RG_USB20_GPIO_CTL | P2C_USB20_GPIO_MODE) 80 81#define U3P_U2PHYA_RESV 0x030 82#define P2R_RG_U2PLL_FBDIV_26M 0x1bb13b 83#define P2R_RG_U2PLL_FBDIV_48M 0x3c0000 84 85#define U3P_U2PHYA_RESV1 0x044 86#define P2R_RG_U2PLL_REFCLK_SEL BIT(5) 87#define P2R_RG_U2PLL_FRA_EN BIT(3) 88 89#define U3D_U2PHYDCR0 0x060 90#define P2C_RG_SIF_U2PLL_FORCE_ON BIT(24) 91 92#define U3P_U2PHYDTM0 0x068 93#define P2C_FORCE_UART_EN BIT(26) 94#define P2C_FORCE_DATAIN BIT(23) 95#define P2C_FORCE_DM_PULLDOWN BIT(21) 96#define P2C_FORCE_DP_PULLDOWN BIT(20) 97#define P2C_FORCE_XCVRSEL BIT(19) 98#define P2C_FORCE_SUSPENDM BIT(18) 99#define P2C_FORCE_TERMSEL BIT(17) 100#define P2C_RG_DATAIN GENMASK(13, 10) 101#define P2C_RG_DMPULLDOWN BIT(7) 102#define P2C_RG_DPPULLDOWN BIT(6) 103#define P2C_RG_XCVRSEL GENMASK(5, 4) 104#define P2C_RG_SUSPENDM BIT(3) 105#define P2C_RG_TERMSEL BIT(2) 106#define P2C_DTM0_PART_MASK \ 107 (P2C_FORCE_DATAIN | P2C_FORCE_DM_PULLDOWN | \ 108 P2C_FORCE_DP_PULLDOWN | P2C_FORCE_XCVRSEL | \ 109 P2C_FORCE_TERMSEL | P2C_RG_DMPULLDOWN | \ 110 P2C_RG_DPPULLDOWN | P2C_RG_TERMSEL) 111 112#define U3P_U2PHYDTM1 0x06C 113#define P2C_RG_UART_EN BIT(16) 114#define P2C_FORCE_IDDIG BIT(9) 115#define P2C_RG_VBUSVALID BIT(5) 116#define P2C_RG_SESSEND BIT(4) 117#define P2C_RG_AVALID BIT(2) 118#define P2C_RG_IDDIG BIT(1) 119 120#define U3P_U2PHYBC12C 0x080 121#define P2C_RG_CHGDT_EN BIT(0) 122 123#define U3P_U3_CHIP_GPIO_CTLD 0x0c 124#define P3C_REG_IP_SW_RST BIT(31) 125#define P3C_MCU_BUS_CK_GATE_EN BIT(30) 126#define P3C_FORCE_IP_SW_RST BIT(29) 127 128#define U3P_U3_CHIP_GPIO_CTLE 0x10 129#define P3C_RG_SWRST_U3_PHYD BIT(25) 130#define P3C_RG_SWRST_U3_PHYD_FORCE_EN BIT(24) 131 132#define U3P_U3_PHYA_REG0 0x000 133#define P3A_RG_IEXT_INTR GENMASK(15, 10) 134#define P3A_RG_CLKDRV_OFF GENMASK(3, 2) 135 136#define U3P_U3_PHYA_REG1 0x004 137#define P3A_RG_CLKDRV_AMP GENMASK(31, 29) 138 139#define U3P_U3_PHYA_REG6 0x018 140#define P3A_RG_TX_EIDLE_CM GENMASK(31, 28) 141 142#define U3P_U3_PHYA_REG9 0x024 143#define P3A_RG_RX_DAC_MUX GENMASK(5, 1) 144 145#define U3P_U3_PHYA_DA_REG0 0x100 146#define P3A_RG_XTAL_EXT_PE2H GENMASK(17, 16) 147#define P3A_RG_XTAL_EXT_PE1H GENMASK(13, 12) 148#define P3A_RG_XTAL_EXT_EN_U3 GENMASK(11, 10) 149 150#define U3P_U3_PHYA_DA_REG4 0x108 151#define P3A_RG_PLL_DIVEN_PE2H GENMASK(21, 19) 152#define P3A_RG_PLL_BC_PE2H GENMASK(7, 6) 153 154#define U3P_U3_PHYA_DA_REG5 0x10c 155#define P3A_RG_PLL_BR_PE2H GENMASK(29, 28) 156#define P3A_RG_PLL_IC_PE2H GENMASK(15, 12) 157 158#define U3P_U3_PHYA_DA_REG6 0x110 159#define P3A_RG_PLL_IR_PE2H GENMASK(19, 16) 160 161#define U3P_U3_PHYA_DA_REG7 0x114 162#define P3A_RG_PLL_BP_PE2H GENMASK(19, 16) 163 164#define U3P_U3_PHYA_DA_REG20 0x13c 165#define P3A_RG_PLL_DELTA1_PE2H GENMASK(31, 16) 166 167#define U3P_U3_PHYA_DA_REG25 0x148 168#define P3A_RG_PLL_DELTA_PE2H GENMASK(15, 0) 169 170#define U3P_U3_PHYD_LFPS1 0x00c 171#define P3D_RG_FWAKE_TH GENMASK(21, 16) 172 173#define U3P_U3_PHYD_IMPCAL0 0x010 174#define P3D_RG_FORCE_TX_IMPEL BIT(31) 175#define P3D_RG_TX_IMPEL GENMASK(28, 24) 176 177#define U3P_U3_PHYD_IMPCAL1 0x014 178#define P3D_RG_FORCE_RX_IMPEL BIT(31) 179#define P3D_RG_RX_IMPEL GENMASK(28, 24) 180 181#define U3P_U3_PHYD_RSV 0x054 182#define P3D_RG_EFUSE_AUTO_LOAD_DIS BIT(12) 183 184#define U3P_U3_PHYD_CDR1 0x05c 185#define P3D_RG_CDR_BIR_LTD1 GENMASK(28, 24) 186#define P3D_RG_CDR_BIR_LTD0 GENMASK(12, 8) 187 188#define U3P_U3_PHYD_TOP1 0x100 189#define P3D_RG_PHY_MODE GENMASK(2, 1) 190#define P3D_RG_FORCE_PHY_MODE BIT(0) 191 192#define U3P_U3_PHYD_RXDET1 0x128 193#define P3D_RG_RXDET_STB2_SET GENMASK(17, 9) 194 195#define U3P_U3_PHYD_RXDET2 0x12c 196#define P3D_RG_RXDET_STB2_SET_P3 GENMASK(8, 0) 197 198#define U3P_SPLLC_XTALCTL3 0x018 199#define XC3_RG_U3_XTAL_RX_PWD BIT(9) 200#define XC3_RG_U3_FRC_XTAL_RX_PWD BIT(8) 201 202#define U3P_U2FREQ_FMCR0 0x00 203#define P2F_RG_MONCLK_SEL GENMASK(27, 26) 204#define P2F_RG_FREQDET_EN BIT(24) 205#define P2F_RG_CYCLECNT GENMASK(23, 0) 206 207#define U3P_U2FREQ_VALUE 0x0c 208 209#define U3P_U2FREQ_FMMONR1 0x10 210#define P2F_USB_FM_VALID BIT(0) 211#define P2F_RG_FRCK_EN BIT(8) 212 213#define U3P_SR_COEF_DIVISOR 1000 214#define U3P_FM_DET_CYCLE_CNT 1024 215 216/* SATA register setting */ 217#define PHYD_CTRL_SIGNAL_MODE4 0x1c 218/* CDR Charge Pump P-path current adjustment */ 219#define RG_CDR_BICLTD1_GEN1_MSK GENMASK(23, 20) 220#define RG_CDR_BICLTD0_GEN1_MSK GENMASK(11, 8) 221 222#define PHYD_DESIGN_OPTION2 0x24 223/* Symbol lock count selection */ 224#define RG_LOCK_CNT_SEL_MSK GENMASK(5, 4) 225 226#define PHYD_DESIGN_OPTION9 0x40 227/* COMWAK GAP width window */ 228#define RG_TG_MAX_MSK GENMASK(20, 16) 229/* COMINIT GAP width window */ 230#define RG_T2_MAX_MSK GENMASK(13, 8) 231/* COMWAK GAP width window */ 232#define RG_TG_MIN_MSK GENMASK(7, 5) 233/* COMINIT GAP width window */ 234#define RG_T2_MIN_MSK GENMASK(4, 0) 235 236#define ANA_RG_CTRL_SIGNAL1 0x4c 237/* TX driver tail current control for 0dB de-empahsis mdoe for Gen1 speed */ 238#define RG_IDRV_0DB_GEN1_MSK GENMASK(13, 8) 239 240#define ANA_RG_CTRL_SIGNAL4 0x58 241#define RG_CDR_BICLTR_GEN1_MSK GENMASK(23, 20) 242/* Loop filter R1 resistance adjustment for Gen1 speed */ 243#define RG_CDR_BR_GEN2_MSK GENMASK(10, 8) 244 245#define ANA_RG_CTRL_SIGNAL6 0x60 246/* I-path capacitance adjustment for Gen1 */ 247#define RG_CDR_BC_GEN1_MSK GENMASK(28, 24) 248#define RG_CDR_BIRLTR_GEN1_MSK GENMASK(4, 0) 249 250#define ANA_EQ_EYE_CTRL_SIGNAL1 0x6c 251/* RX Gen1 LEQ tuning step */ 252#define RG_EQ_DLEQ_LFI_GEN1_MSK GENMASK(11, 8) 253 254#define ANA_EQ_EYE_CTRL_SIGNAL4 0xd8 255#define RG_CDR_BIRLTD0_GEN1_MSK GENMASK(20, 16) 256 257#define ANA_EQ_EYE_CTRL_SIGNAL5 0xdc 258#define RG_CDR_BIRLTD0_GEN3_MSK GENMASK(4, 0) 259 260/* PHY switch between pcie/usb3/sgmii/sata */ 261#define USB_PHY_SWITCH_CTRL 0x0 262#define RG_PHY_SW_TYPE GENMASK(3, 0) 263#define RG_PHY_SW_PCIE 0x0 264#define RG_PHY_SW_USB3 0x1 265#define RG_PHY_SW_SGMII 0x2 266#define RG_PHY_SW_SATA 0x3 267 268#define TPHY_CLKS_CNT 2 269 270#define USER_BUF_LEN(count) min_t(size_t, 8, (count)) 271 272enum mtk_phy_version { 273 MTK_PHY_V1 = 1, 274 MTK_PHY_V2, 275 MTK_PHY_V3, 276}; 277 278/** 279 * mtk_phy_pdata - SoC specific platform data 280 * @avoid_rx_sen_degradation: Avoid TX Sensitivity level degradation (MT6795/8173 only) 281 * @sw_pll_48m_to_26m: Workaround for V3 IP (MT8195) - switch the 48MHz PLL from 282 * fractional mode to integer to output 26MHz for U2PHY 283 * @sw_efuse_supported: Switches off eFuse auto-load from PHY and applies values 284 * read from different nvmem (usually different eFuse array) 285 * that is pointed at in the device tree node for this PHY 286 * @slew_ref_clk_mhz: Default reference clock (in MHz) for slew rate calibration 287 * @slew_rate_coefficient: Coefficient for slew rate calibration 288 * @version: PHY IP Version 289 */ 290struct mtk_phy_pdata { 291 bool avoid_rx_sen_degradation; 292 bool sw_pll_48m_to_26m; 293 bool sw_efuse_supported; 294 u8 slew_ref_clock_mhz; 295 u8 slew_rate_coefficient; 296 enum mtk_phy_version version; 297}; 298 299struct u2phy_banks { 300 void __iomem *misc; 301 void __iomem *fmreg; 302 void __iomem *com; 303}; 304 305struct u3phy_banks { 306 void __iomem *spllc; 307 void __iomem *chip; 308 void __iomem *phyd; /* include u3phyd_bank2 */ 309 void __iomem *phya; /* include u3phya_da */ 310}; 311 312struct mtk_phy_instance { 313 struct phy *phy; 314 void __iomem *port_base; 315 union { 316 struct u2phy_banks u2_banks; 317 struct u3phy_banks u3_banks; 318 }; 319 struct clk_bulk_data clks[TPHY_CLKS_CNT]; 320 u32 index; 321 u32 type; 322 struct regmap *type_sw; 323 u32 type_sw_reg; 324 u32 type_sw_index; 325 u32 efuse_sw_en; 326 u32 efuse_intr; 327 u32 efuse_tx_imp; 328 u32 efuse_rx_imp; 329 int eye_src; 330 int eye_vrt; 331 int eye_term; 332 int intr; 333 int discth; 334 int pre_emphasis; 335 bool bc12_en; 336 bool type_force_mode; 337}; 338 339struct mtk_tphy { 340 struct device *dev; 341 void __iomem *sif_base; /* only shared sif */ 342 const struct mtk_phy_pdata *pdata; 343 struct mtk_phy_instance **phys; 344 int nphys; 345 int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */ 346 int src_coef; /* coefficient for slew rate calibrate */ 347}; 348 349#if IS_ENABLED(CONFIG_DEBUG_FS) 350 351enum u2_phy_params { 352 U2P_EYE_VRT = 0, 353 U2P_EYE_TERM, 354 U2P_EFUSE_EN, 355 U2P_EFUSE_INTR, 356 U2P_DISCTH, 357 U2P_PRE_EMPHASIS, 358}; 359 360enum u3_phy_params { 361 U3P_EFUSE_EN = 0, 362 U3P_EFUSE_INTR, 363 U3P_EFUSE_TX_IMP, 364 U3P_EFUSE_RX_IMP, 365}; 366 367static const char *const u2_phy_files[] = { 368 [U2P_EYE_VRT] = "vrt", 369 [U2P_EYE_TERM] = "term", 370 [U2P_EFUSE_EN] = "efuse", 371 [U2P_EFUSE_INTR] = "intr", 372 [U2P_DISCTH] = "discth", 373 [U2P_PRE_EMPHASIS] = "preemph", 374}; 375 376static const char *const u3_phy_files[] = { 377 [U3P_EFUSE_EN] = "efuse", 378 [U3P_EFUSE_INTR] = "intr", 379 [U3P_EFUSE_TX_IMP] = "tx-imp", 380 [U3P_EFUSE_RX_IMP] = "rx-imp", 381}; 382 383static int u2_phy_params_show(struct seq_file *sf, void *unused) 384{ 385 struct mtk_phy_instance *inst = sf->private; 386 struct u2phy_banks *u2_banks = &inst->u2_banks; 387 void __iomem *com = u2_banks->com; 388 u32 max = 0; 389 u32 tmp = 0; 390 u32 val = 0; 391 int ret = debugfs_get_aux_num(sf->file); 392 393 switch (ret) { 394 case U2P_EYE_VRT: 395 tmp = readl(com + U3P_USBPHYACR1); 396 val = FIELD_GET(PA1_RG_VRT_SEL, tmp); 397 max = FIELD_MAX(PA1_RG_VRT_SEL); 398 break; 399 400 case U2P_EYE_TERM: 401 tmp = readl(com + U3P_USBPHYACR1); 402 val = FIELD_GET(PA1_RG_TERM_SEL, tmp); 403 max = FIELD_MAX(PA1_RG_TERM_SEL); 404 break; 405 406 case U2P_EFUSE_EN: 407 if (u2_banks->misc) { 408 tmp = readl(u2_banks->misc + U3P_MISC_REG1); 409 max = 1; 410 } 411 412 val = !!(tmp & MR1_EFUSE_AUTO_LOAD_DIS); 413 break; 414 415 case U2P_EFUSE_INTR: 416 tmp = readl(com + U3P_USBPHYACR1); 417 val = FIELD_GET(PA1_RG_INTR_CAL, tmp); 418 max = FIELD_MAX(PA1_RG_INTR_CAL); 419 break; 420 421 case U2P_DISCTH: 422 tmp = readl(com + U3P_USBPHYACR6); 423 val = FIELD_GET(PA6_RG_U2_DISCTH, tmp); 424 max = FIELD_MAX(PA6_RG_U2_DISCTH); 425 break; 426 427 case U2P_PRE_EMPHASIS: 428 tmp = readl(com + U3P_USBPHYACR6); 429 val = FIELD_GET(PA6_RG_U2_PRE_EMP, tmp); 430 max = FIELD_MAX(PA6_RG_U2_PRE_EMP); 431 break; 432 433 default: 434 seq_printf(sf, "invalid, %d\n", ret); 435 break; 436 } 437 438 seq_printf(sf, "%s : %d [0, %d]\n", u2_phy_files[ret], val, max); 439 440 return 0; 441} 442 443static int u2_phy_params_open(struct inode *inode, struct file *file) 444{ 445 return single_open(file, u2_phy_params_show, inode->i_private); 446} 447 448static ssize_t u2_phy_params_write(struct file *file, const char __user *ubuf, 449 size_t count, loff_t *ppos) 450{ 451 struct seq_file *sf = file->private_data; 452 struct mtk_phy_instance *inst = sf->private; 453 struct u2phy_banks *u2_banks = &inst->u2_banks; 454 void __iomem *com = u2_banks->com; 455 ssize_t rc; 456 u32 val; 457 int ret = debugfs_get_aux_num(file); 458 459 rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val); 460 if (rc) 461 return rc; 462 463 switch (ret) { 464 case U2P_EYE_VRT: 465 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, val); 466 break; 467 468 case U2P_EYE_TERM: 469 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, val); 470 break; 471 472 case U2P_EFUSE_EN: 473 if (u2_banks->misc) 474 mtk_phy_update_field(u2_banks->misc + U3P_MISC_REG1, 475 MR1_EFUSE_AUTO_LOAD_DIS, !!val); 476 break; 477 478 case U2P_EFUSE_INTR: 479 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, val); 480 break; 481 482 case U2P_DISCTH: 483 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, val); 484 break; 485 486 case U2P_PRE_EMPHASIS: 487 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, val); 488 break; 489 490 default: 491 break; 492 } 493 494 return count; 495} 496 497static const struct file_operations u2_phy_fops = { 498 .open = u2_phy_params_open, 499 .write = u2_phy_params_write, 500 .read = seq_read, 501 .llseek = seq_lseek, 502 .release = single_release, 503}; 504 505static void u2_phy_dbgfs_files_create(struct mtk_phy_instance *inst) 506{ 507 u32 count = ARRAY_SIZE(u2_phy_files); 508 int i; 509 510 for (i = 0; i < count; i++) 511 debugfs_create_file_aux_num(u2_phy_files[i], 0644, inst->phy->debugfs, 512 inst, i, &u2_phy_fops); 513} 514 515static int u3_phy_params_show(struct seq_file *sf, void *unused) 516{ 517 struct mtk_phy_instance *inst = sf->private; 518 struct u3phy_banks *u3_banks = &inst->u3_banks; 519 u32 val = 0; 520 u32 max = 0; 521 u32 tmp; 522 int ret = debugfs_get_aux_num(sf->file); 523 524 switch (ret) { 525 case U3P_EFUSE_EN: 526 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV); 527 val = !!(tmp & P3D_RG_EFUSE_AUTO_LOAD_DIS); 528 max = 1; 529 break; 530 531 case U3P_EFUSE_INTR: 532 tmp = readl(u3_banks->phya + U3P_U3_PHYA_REG0); 533 val = FIELD_GET(P3A_RG_IEXT_INTR, tmp); 534 max = FIELD_MAX(P3A_RG_IEXT_INTR); 535 break; 536 537 case U3P_EFUSE_TX_IMP: 538 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0); 539 val = FIELD_GET(P3D_RG_TX_IMPEL, tmp); 540 max = FIELD_MAX(P3D_RG_TX_IMPEL); 541 break; 542 543 case U3P_EFUSE_RX_IMP: 544 tmp = readl(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1); 545 val = FIELD_GET(P3D_RG_RX_IMPEL, tmp); 546 max = FIELD_MAX(P3D_RG_RX_IMPEL); 547 break; 548 549 default: 550 seq_printf(sf, "invalid, %d\n", ret); 551 break; 552 } 553 554 seq_printf(sf, "%s : %d [0, %d]\n", u3_phy_files[ret], val, max); 555 556 return 0; 557} 558 559static int u3_phy_params_open(struct inode *inode, struct file *file) 560{ 561 return single_open(file, u3_phy_params_show, inode->i_private); 562} 563 564static ssize_t u3_phy_params_write(struct file *file, const char __user *ubuf, 565 size_t count, loff_t *ppos) 566{ 567 struct seq_file *sf = file->private_data; 568 struct mtk_phy_instance *inst = sf->private; 569 struct u3phy_banks *u3_banks = &inst->u3_banks; 570 void __iomem *phyd = u3_banks->phyd; 571 ssize_t rc; 572 u32 val; 573 int ret = debugfs_get_aux_num(sf->file); 574 575 rc = kstrtouint_from_user(ubuf, USER_BUF_LEN(count), 0, &val); 576 if (rc) 577 return rc; 578 579 switch (ret) { 580 case U3P_EFUSE_EN: 581 mtk_phy_update_field(phyd + U3P_U3_PHYD_RSV, 582 P3D_RG_EFUSE_AUTO_LOAD_DIS, !!val); 583 break; 584 585 case U3P_EFUSE_INTR: 586 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, 587 P3A_RG_IEXT_INTR, val); 588 break; 589 590 case U3P_EFUSE_TX_IMP: 591 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, val); 592 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); 593 break; 594 595 case U3P_EFUSE_RX_IMP: 596 mtk_phy_update_field(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, val); 597 mtk_phy_set_bits(phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); 598 break; 599 600 default: 601 break; 602 } 603 604 return count; 605} 606 607static const struct file_operations u3_phy_fops = { 608 .open = u3_phy_params_open, 609 .write = u3_phy_params_write, 610 .read = seq_read, 611 .llseek = seq_lseek, 612 .release = single_release, 613}; 614 615static void u3_phy_dbgfs_files_create(struct mtk_phy_instance *inst) 616{ 617 u32 count = ARRAY_SIZE(u3_phy_files); 618 int i; 619 620 for (i = 0; i < count; i++) 621 debugfs_create_file_aux_num(u3_phy_files[i], 0644, inst->phy->debugfs, 622 inst, i, &u3_phy_fops); 623} 624 625static int phy_type_show(struct seq_file *sf, void *unused) 626{ 627 struct mtk_phy_instance *inst = sf->private; 628 const char *type; 629 630 switch (inst->type) { 631 case PHY_TYPE_USB2: 632 type = "USB2"; 633 break; 634 case PHY_TYPE_USB3: 635 type = "USB3"; 636 break; 637 case PHY_TYPE_PCIE: 638 type = "PCIe"; 639 break; 640 case PHY_TYPE_SGMII: 641 type = "SGMII"; 642 break; 643 case PHY_TYPE_SATA: 644 type = "SATA"; 645 break; 646 default: 647 type = ""; 648 } 649 650 seq_printf(sf, "%s\n", type); 651 652 return 0; 653} 654DEFINE_SHOW_ATTRIBUTE(phy_type); 655 656/* these files will be removed when phy is released by phy core */ 657static void phy_debugfs_init(struct mtk_phy_instance *inst) 658{ 659 debugfs_create_file("type", 0444, inst->phy->debugfs, inst, &phy_type_fops); 660 661 switch (inst->type) { 662 case PHY_TYPE_USB2: 663 u2_phy_dbgfs_files_create(inst); 664 break; 665 case PHY_TYPE_USB3: 666 case PHY_TYPE_PCIE: 667 u3_phy_dbgfs_files_create(inst); 668 break; 669 default: 670 break; 671 } 672} 673 674#else 675 676static void phy_debugfs_init(struct mtk_phy_instance *inst) 677{} 678 679#endif 680 681static void hs_slew_rate_calibrate(struct mtk_tphy *tphy, 682 struct mtk_phy_instance *instance) 683{ 684 struct u2phy_banks *u2_banks = &instance->u2_banks; 685 void __iomem *fmreg = u2_banks->fmreg; 686 void __iomem *com = u2_banks->com; 687 int calibration_val; 688 int fm_out; 689 u32 tmp; 690 691 /* 692 * If a fixed HS slew rate (EYE) value was supplied, don't run the 693 * calibration sequence and prefer using that value instead; also, 694 * if there is no reference clock for slew calibration or there is 695 * no slew coefficient, this means that the slew rate calibration 696 * sequence is not supported. 697 */ 698 if (instance->eye_src || !tphy->src_ref_clk || !tphy->src_coef) 699 return; 700 701 /* enable USB ring oscillator */ 702 mtk_phy_set_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); 703 udelay(1); 704 705 /*enable free run clock */ 706 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); 707 708 /* set cycle count as 1024, and select u2 channel */ 709 tmp = readl(fmreg + U3P_U2FREQ_FMCR0); 710 tmp &= ~(P2F_RG_CYCLECNT | P2F_RG_MONCLK_SEL); 711 tmp |= FIELD_PREP(P2F_RG_CYCLECNT, U3P_FM_DET_CYCLE_CNT); 712 if (tphy->pdata->version == MTK_PHY_V1) 713 tmp |= FIELD_PREP(P2F_RG_MONCLK_SEL, instance->index >> 1); 714 715 writel(tmp, fmreg + U3P_U2FREQ_FMCR0); 716 717 /* enable frequency meter */ 718 mtk_phy_set_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); 719 720 /* ignore return value */ 721 readl_poll_timeout(fmreg + U3P_U2FREQ_FMMONR1, tmp, 722 (tmp & P2F_USB_FM_VALID), 10, 200); 723 724 fm_out = readl(fmreg + U3P_U2FREQ_VALUE); 725 726 /* disable frequency meter */ 727 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMCR0, P2F_RG_FREQDET_EN); 728 729 /*disable free run clock */ 730 mtk_phy_clear_bits(fmreg + U3P_U2FREQ_FMMONR1, P2F_RG_FRCK_EN); 731 732 if (fm_out) { 733 /* ( 1024 / FM_OUT ) x reference clock frequency x coef */ 734 tmp = tphy->src_ref_clk * tphy->src_coef; 735 tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out; 736 calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR); 737 } else { 738 /* if FM detection fail, set default value */ 739 calibration_val = 4; 740 } 741 dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n", 742 instance->index, fm_out, calibration_val, 743 tphy->src_ref_clk, tphy->src_coef); 744 745 /* set HS slew rate */ 746 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 747 calibration_val); 748 749 /* disable USB ring oscillator */ 750 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCAL_EN); 751} 752 753static void u3_phy_instance_init(struct mtk_tphy *tphy, 754 struct mtk_phy_instance *instance) 755{ 756 struct u3phy_banks *u3_banks = &instance->u3_banks; 757 void __iomem *phya = u3_banks->phya; 758 void __iomem *phyd = u3_banks->phyd; 759 760 if (instance->type_force_mode) { 761 /* force phy as usb mode, default is pcie rc mode */ 762 mtk_phy_update_field(phyd + U3P_U3_PHYD_TOP1, P3D_RG_PHY_MODE, 1); 763 mtk_phy_set_bits(phyd + U3P_U3_PHYD_TOP1, P3D_RG_FORCE_PHY_MODE); 764 /* power down phy by ip and pipe reset */ 765 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, 766 P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN); 767 mtk_phy_set_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, 768 P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN); 769 udelay(10); 770 /* power on phy again */ 771 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLD, 772 P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN); 773 mtk_phy_clear_bits(u3_banks->chip + U3P_U3_CHIP_GPIO_CTLE, 774 P3C_RG_SWRST_U3_PHYD | P3C_RG_SWRST_U3_PHYD_FORCE_EN); 775 } 776 777 /* gating PCIe Analog XTAL clock */ 778 mtk_phy_set_bits(u3_banks->spllc + U3P_SPLLC_XTALCTL3, 779 XC3_RG_U3_XTAL_RX_PWD | XC3_RG_U3_FRC_XTAL_RX_PWD); 780 781 /* gating XSQ */ 782 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG0, P3A_RG_XTAL_EXT_EN_U3, 2); 783 784 mtk_phy_update_field(phya + U3P_U3_PHYA_REG9, P3A_RG_RX_DAC_MUX, 4); 785 786 mtk_phy_update_field(phya + U3P_U3_PHYA_REG6, P3A_RG_TX_EIDLE_CM, 0xe); 787 788 mtk_phy_update_bits(u3_banks->phyd + U3P_U3_PHYD_CDR1, 789 P3D_RG_CDR_BIR_LTD0 | P3D_RG_CDR_BIR_LTD1, 790 FIELD_PREP(P3D_RG_CDR_BIR_LTD0, 0xc) | 791 FIELD_PREP(P3D_RG_CDR_BIR_LTD1, 0x3)); 792 793 mtk_phy_update_field(phyd + U3P_U3_PHYD_LFPS1, P3D_RG_FWAKE_TH, 0x34); 794 795 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET1, P3D_RG_RXDET_STB2_SET, 0x10); 796 797 mtk_phy_update_field(phyd + U3P_U3_PHYD_RXDET2, P3D_RG_RXDET_STB2_SET_P3, 0x10); 798 799 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 800} 801 802static void u2_phy_pll_26m_set(struct mtk_tphy *tphy, 803 struct mtk_phy_instance *instance) 804{ 805 struct u2phy_banks *u2_banks = &instance->u2_banks; 806 void __iomem *com = u2_banks->com; 807 808 if (!tphy->pdata->sw_pll_48m_to_26m) 809 return; 810 811 mtk_phy_update_field(com + U3P_USBPHYACR0, PA0_USB20_PLL_PREDIV, 0); 812 813 mtk_phy_update_field(com + U3P_USBPHYACR2, PA2_RG_U2PLL_BW, 3); 814 815 writel(P2R_RG_U2PLL_FBDIV_26M, com + U3P_U2PHYA_RESV); 816 817 mtk_phy_set_bits(com + U3P_U2PHYA_RESV1, 818 P2R_RG_U2PLL_FRA_EN | P2R_RG_U2PLL_REFCLK_SEL); 819} 820 821static void u2_phy_instance_init(struct mtk_tphy *tphy, 822 struct mtk_phy_instance *instance) 823{ 824 struct u2phy_banks *u2_banks = &instance->u2_banks; 825 void __iomem *com = u2_banks->com; 826 u32 index = instance->index; 827 828 /* switch to USB function, and enable usb pll */ 829 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_UART_EN | P2C_FORCE_SUSPENDM); 830 831 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, 832 P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); 833 834 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_UART_EN); 835 836 mtk_phy_set_bits(com + U3P_USBPHYACR0, PA0_RG_USB20_INTR_EN); 837 838 /* disable switch 100uA current to SSUSB */ 839 mtk_phy_clear_bits(com + U3P_USBPHYACR5, PA5_RG_U2_HS_100U_U3_EN); 840 841 mtk_phy_clear_bits(com + U3P_U2PHYACR4, P2C_U2_GPIO_CTR_MSK); 842 843 if (tphy->pdata->avoid_rx_sen_degradation) { 844 if (!index) { 845 mtk_phy_set_bits(com + U3P_USBPHYACR2, PA2_RG_SIF_U2PLL_FORCE_EN); 846 847 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 848 } else { 849 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 850 851 mtk_phy_set_bits(com + U3P_U2PHYDTM0, 852 P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 853 } 854 } 855 856 /* DP/DM BC1.1 path Disable */ 857 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_BC11_SW_EN); 858 859 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_SQTH, 2); 860 861 /* Workaround only for mt8195, HW fix it for others (V3) */ 862 u2_phy_pll_26m_set(tphy, instance); 863 864 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 865} 866 867static void u2_phy_instance_power_on(struct mtk_tphy *tphy, 868 struct mtk_phy_instance *instance) 869{ 870 struct u2phy_banks *u2_banks = &instance->u2_banks; 871 void __iomem *com = u2_banks->com; 872 u32 index = instance->index; 873 874 /* OTG Enable */ 875 mtk_phy_set_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); 876 877 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); 878 879 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); 880 881 if (tphy->pdata->avoid_rx_sen_degradation && index) { 882 mtk_phy_set_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 883 884 mtk_phy_set_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 885 } 886 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 887} 888 889static void u2_phy_instance_power_off(struct mtk_tphy *tphy, 890 struct mtk_phy_instance *instance) 891{ 892 struct u2phy_banks *u2_banks = &instance->u2_banks; 893 void __iomem *com = u2_banks->com; 894 u32 index = instance->index; 895 896 /* OTG Disable */ 897 mtk_phy_clear_bits(com + U3P_USBPHYACR6, PA6_RG_U2_OTG_VBUSCMP_EN); 898 899 mtk_phy_clear_bits(com + U3P_U2PHYDTM1, P2C_RG_VBUSVALID | P2C_RG_AVALID); 900 901 mtk_phy_set_bits(com + U3P_U2PHYDTM1, P2C_RG_SESSEND); 902 903 if (tphy->pdata->avoid_rx_sen_degradation && index) { 904 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_RG_SUSPENDM | P2C_FORCE_SUSPENDM); 905 906 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 907 } 908 909 dev_dbg(tphy->dev, "%s(%d)\n", __func__, index); 910} 911 912static void u2_phy_instance_exit(struct mtk_tphy *tphy, 913 struct mtk_phy_instance *instance) 914{ 915 struct u2phy_banks *u2_banks = &instance->u2_banks; 916 void __iomem *com = u2_banks->com; 917 u32 index = instance->index; 918 919 if (tphy->pdata->avoid_rx_sen_degradation && index) { 920 mtk_phy_clear_bits(com + U3D_U2PHYDCR0, P2C_RG_SIF_U2PLL_FORCE_ON); 921 922 mtk_phy_clear_bits(com + U3P_U2PHYDTM0, P2C_FORCE_SUSPENDM); 923 } 924} 925 926static void u2_phy_instance_set_mode(struct mtk_tphy *tphy, 927 struct mtk_phy_instance *instance, 928 enum phy_mode mode) 929{ 930 struct u2phy_banks *u2_banks = &instance->u2_banks; 931 u32 tmp; 932 933 tmp = readl(u2_banks->com + U3P_U2PHYDTM1); 934 switch (mode) { 935 case PHY_MODE_USB_DEVICE: 936 tmp |= P2C_FORCE_IDDIG | P2C_RG_IDDIG; 937 break; 938 case PHY_MODE_USB_HOST: 939 tmp |= P2C_FORCE_IDDIG; 940 tmp &= ~P2C_RG_IDDIG; 941 break; 942 case PHY_MODE_USB_OTG: 943 tmp &= ~(P2C_FORCE_IDDIG | P2C_RG_IDDIG); 944 break; 945 default: 946 return; 947 } 948 writel(tmp, u2_banks->com + U3P_U2PHYDTM1); 949} 950 951static void pcie_phy_instance_init(struct mtk_tphy *tphy, 952 struct mtk_phy_instance *instance) 953{ 954 struct u3phy_banks *u3_banks = &instance->u3_banks; 955 void __iomem *phya = u3_banks->phya; 956 957 if (tphy->pdata->version != MTK_PHY_V1) 958 return; 959 960 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG0, 961 P3A_RG_XTAL_EXT_PE1H | P3A_RG_XTAL_EXT_PE2H, 962 FIELD_PREP(P3A_RG_XTAL_EXT_PE1H, 0x2) | 963 FIELD_PREP(P3A_RG_XTAL_EXT_PE2H, 0x2)); 964 965 /* ref clk drive */ 966 mtk_phy_update_field(phya + U3P_U3_PHYA_REG1, P3A_RG_CLKDRV_AMP, 0x4); 967 968 mtk_phy_update_field(phya + U3P_U3_PHYA_REG0, P3A_RG_CLKDRV_OFF, 0x1); 969 970 /* SSC delta -5000ppm */ 971 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG20, P3A_RG_PLL_DELTA1_PE2H, 0x3c); 972 973 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG25, P3A_RG_PLL_DELTA_PE2H, 0x36); 974 975 /* change pll BW 0.6M */ 976 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG5, 977 P3A_RG_PLL_BR_PE2H | P3A_RG_PLL_IC_PE2H, 978 FIELD_PREP(P3A_RG_PLL_BR_PE2H, 0x1) | 979 FIELD_PREP(P3A_RG_PLL_IC_PE2H, 0x1)); 980 981 mtk_phy_update_bits(phya + U3P_U3_PHYA_DA_REG4, 982 P3A_RG_PLL_DIVEN_PE2H | P3A_RG_PLL_BC_PE2H, 983 FIELD_PREP(P3A_RG_PLL_BC_PE2H, 0x3)); 984 985 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG6, P3A_RG_PLL_IR_PE2H, 0x2); 986 987 mtk_phy_update_field(phya + U3P_U3_PHYA_DA_REG7, P3A_RG_PLL_BP_PE2H, 0xa); 988 989 /* Tx Detect Rx Timing: 10us -> 5us */ 990 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET1, 991 P3D_RG_RXDET_STB2_SET, 0x10); 992 993 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_RXDET2, 994 P3D_RG_RXDET_STB2_SET_P3, 0x10); 995 996 /* wait for PCIe subsys register to active */ 997 usleep_range(2500, 3000); 998 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 999} 1000 1001static void pcie_phy_instance_power_on(struct mtk_tphy *tphy, 1002 struct mtk_phy_instance *instance) 1003{ 1004 struct u3phy_banks *bank = &instance->u3_banks; 1005 1006 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, 1007 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); 1008 1009 mtk_phy_clear_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, 1010 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 1011} 1012 1013static void pcie_phy_instance_power_off(struct mtk_tphy *tphy, 1014 struct mtk_phy_instance *instance) 1015 1016{ 1017 struct u3phy_banks *bank = &instance->u3_banks; 1018 1019 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLD, 1020 P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST); 1021 1022 mtk_phy_set_bits(bank->chip + U3P_U3_CHIP_GPIO_CTLE, 1023 P3C_RG_SWRST_U3_PHYD_FORCE_EN | P3C_RG_SWRST_U3_PHYD); 1024} 1025 1026static void sata_phy_instance_init(struct mtk_tphy *tphy, 1027 struct mtk_phy_instance *instance) 1028{ 1029 struct u3phy_banks *u3_banks = &instance->u3_banks; 1030 void __iomem *phyd = u3_banks->phyd; 1031 1032 /* charge current adjustment */ 1033 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL6, 1034 RG_CDR_BIRLTR_GEN1_MSK | RG_CDR_BC_GEN1_MSK, 1035 FIELD_PREP(RG_CDR_BIRLTR_GEN1_MSK, 0x6) | 1036 FIELD_PREP(RG_CDR_BC_GEN1_MSK, 0x1a)); 1037 1038 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL4, RG_CDR_BIRLTD0_GEN1_MSK, 0x18); 1039 1040 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL5, RG_CDR_BIRLTD0_GEN3_MSK, 0x06); 1041 1042 mtk_phy_update_bits(phyd + ANA_RG_CTRL_SIGNAL4, 1043 RG_CDR_BICLTR_GEN1_MSK | RG_CDR_BR_GEN2_MSK, 1044 FIELD_PREP(RG_CDR_BICLTR_GEN1_MSK, 0x0c) | 1045 FIELD_PREP(RG_CDR_BR_GEN2_MSK, 0x07)); 1046 1047 mtk_phy_update_bits(phyd + PHYD_CTRL_SIGNAL_MODE4, 1048 RG_CDR_BICLTD0_GEN1_MSK | RG_CDR_BICLTD1_GEN1_MSK, 1049 FIELD_PREP(RG_CDR_BICLTD0_GEN1_MSK, 0x08) | 1050 FIELD_PREP(RG_CDR_BICLTD1_GEN1_MSK, 0x02)); 1051 1052 mtk_phy_update_field(phyd + PHYD_DESIGN_OPTION2, RG_LOCK_CNT_SEL_MSK, 0x02); 1053 1054 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, 1055 RG_T2_MIN_MSK | RG_TG_MIN_MSK, 1056 FIELD_PREP(RG_T2_MIN_MSK, 0x12) | 1057 FIELD_PREP(RG_TG_MIN_MSK, 0x04)); 1058 1059 mtk_phy_update_bits(phyd + PHYD_DESIGN_OPTION9, 1060 RG_T2_MAX_MSK | RG_TG_MAX_MSK, 1061 FIELD_PREP(RG_T2_MAX_MSK, 0x31) | 1062 FIELD_PREP(RG_TG_MAX_MSK, 0x0e)); 1063 1064 mtk_phy_update_field(phyd + ANA_RG_CTRL_SIGNAL1, RG_IDRV_0DB_GEN1_MSK, 0x20); 1065 1066 mtk_phy_update_field(phyd + ANA_EQ_EYE_CTRL_SIGNAL1, RG_EQ_DLEQ_LFI_GEN1_MSK, 0x03); 1067 1068 dev_dbg(tphy->dev, "%s(%d)\n", __func__, instance->index); 1069} 1070 1071static void phy_v1_banks_init(struct mtk_tphy *tphy, 1072 struct mtk_phy_instance *instance) 1073{ 1074 struct u2phy_banks *u2_banks = &instance->u2_banks; 1075 struct u3phy_banks *u3_banks = &instance->u3_banks; 1076 1077 switch (instance->type) { 1078 case PHY_TYPE_USB2: 1079 u2_banks->misc = NULL; 1080 u2_banks->fmreg = tphy->sif_base + SSUSB_SIFSLV_V1_U2FREQ; 1081 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V1_U2PHY_COM; 1082 break; 1083 case PHY_TYPE_USB3: 1084 case PHY_TYPE_PCIE: 1085 u3_banks->spllc = tphy->sif_base + SSUSB_SIFSLV_V1_SPLLC; 1086 u3_banks->chip = tphy->sif_base + SSUSB_SIFSLV_V1_CHIP; 1087 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 1088 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V1_U3PHYA; 1089 break; 1090 case PHY_TYPE_SATA: 1091 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V1_U3PHYD; 1092 break; 1093 default: 1094 dev_err(tphy->dev, "incompatible PHY type\n"); 1095 return; 1096 } 1097} 1098 1099static void phy_v2_banks_init(struct mtk_tphy *tphy, 1100 struct mtk_phy_instance *instance) 1101{ 1102 struct u2phy_banks *u2_banks = &instance->u2_banks; 1103 struct u3phy_banks *u3_banks = &instance->u3_banks; 1104 1105 switch (instance->type) { 1106 case PHY_TYPE_USB2: 1107 u2_banks->misc = instance->port_base + SSUSB_SIFSLV_V2_MISC; 1108 u2_banks->fmreg = instance->port_base + SSUSB_SIFSLV_V2_U2FREQ; 1109 u2_banks->com = instance->port_base + SSUSB_SIFSLV_V2_U2PHY_COM; 1110 break; 1111 case PHY_TYPE_USB3: 1112 case PHY_TYPE_PCIE: 1113 u3_banks->spllc = instance->port_base + SSUSB_SIFSLV_V2_SPLLC; 1114 u3_banks->chip = instance->port_base + SSUSB_SIFSLV_V2_CHIP; 1115 u3_banks->phyd = instance->port_base + SSUSB_SIFSLV_V2_U3PHYD; 1116 u3_banks->phya = instance->port_base + SSUSB_SIFSLV_V2_U3PHYA; 1117 break; 1118 default: 1119 dev_err(tphy->dev, "incompatible PHY type\n"); 1120 return; 1121 } 1122} 1123 1124static void phy_parse_property(struct mtk_tphy *tphy, 1125 struct mtk_phy_instance *instance) 1126{ 1127 struct device *dev = &instance->phy->dev; 1128 1129 if (instance->type == PHY_TYPE_USB3) 1130 instance->type_force_mode = device_property_read_bool(dev, "mediatek,force-mode"); 1131 1132 if (instance->type != PHY_TYPE_USB2) 1133 return; 1134 1135 instance->bc12_en = device_property_read_bool(dev, "mediatek,bc12"); 1136 device_property_read_u32(dev, "mediatek,eye-src", 1137 &instance->eye_src); 1138 device_property_read_u32(dev, "mediatek,eye-vrt", 1139 &instance->eye_vrt); 1140 device_property_read_u32(dev, "mediatek,eye-term", 1141 &instance->eye_term); 1142 device_property_read_u32(dev, "mediatek,intr", 1143 &instance->intr); 1144 device_property_read_u32(dev, "mediatek,discth", 1145 &instance->discth); 1146 device_property_read_u32(dev, "mediatek,pre-emphasis", 1147 &instance->pre_emphasis); 1148 dev_dbg(dev, "bc12:%d, src:%d, vrt:%d, term:%d, intr:%d, disc:%d\n", 1149 instance->bc12_en, instance->eye_src, 1150 instance->eye_vrt, instance->eye_term, 1151 instance->intr, instance->discth); 1152 dev_dbg(dev, "pre-emp:%d\n", instance->pre_emphasis); 1153} 1154 1155static void u2_phy_props_set(struct mtk_tphy *tphy, 1156 struct mtk_phy_instance *instance) 1157{ 1158 struct u2phy_banks *u2_banks = &instance->u2_banks; 1159 void __iomem *com = u2_banks->com; 1160 1161 if (instance->bc12_en) /* BC1.2 path Enable */ 1162 mtk_phy_set_bits(com + U3P_U2PHYBC12C, P2C_RG_CHGDT_EN); 1163 1164 if (tphy->pdata->version < MTK_PHY_V3 && instance->eye_src) 1165 mtk_phy_update_field(com + U3P_USBPHYACR5, PA5_RG_U2_HSTX_SRCTRL, 1166 instance->eye_src); 1167 1168 if (instance->eye_vrt) 1169 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_VRT_SEL, 1170 instance->eye_vrt); 1171 1172 if (instance->eye_term) 1173 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_TERM_SEL, 1174 instance->eye_term); 1175 1176 if (instance->intr) { 1177 if (u2_banks->misc) 1178 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, 1179 MR1_EFUSE_AUTO_LOAD_DIS); 1180 1181 mtk_phy_update_field(com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 1182 instance->intr); 1183 } 1184 1185 if (instance->discth) 1186 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_DISCTH, 1187 instance->discth); 1188 1189 if (instance->pre_emphasis) 1190 mtk_phy_update_field(com + U3P_USBPHYACR6, PA6_RG_U2_PRE_EMP, 1191 instance->pre_emphasis); 1192} 1193 1194/* type switch for usb3/pcie/sgmii/sata */ 1195static int phy_type_syscon_get(struct mtk_phy_instance *instance, 1196 struct device_node *dn) 1197{ 1198 struct of_phandle_args args; 1199 int ret; 1200 1201 /* type switch function is optional */ 1202 if (!of_property_present(dn, "mediatek,syscon-type")) 1203 return 0; 1204 1205 ret = of_parse_phandle_with_fixed_args(dn, "mediatek,syscon-type", 1206 2, 0, &args); 1207 if (ret) 1208 return ret; 1209 1210 instance->type_sw_reg = args.args[0]; 1211 instance->type_sw_index = args.args[1] & 0x3; /* <=3 */ 1212 instance->type_sw = syscon_node_to_regmap(args.np); 1213 of_node_put(args.np); 1214 dev_info(&instance->phy->dev, "type_sw - reg %#x, index %d\n", 1215 instance->type_sw_reg, instance->type_sw_index); 1216 1217 return PTR_ERR_OR_ZERO(instance->type_sw); 1218} 1219 1220static int phy_type_set(struct mtk_phy_instance *instance) 1221{ 1222 int type; 1223 u32 offset; 1224 1225 if (!instance->type_sw) 1226 return 0; 1227 1228 switch (instance->type) { 1229 case PHY_TYPE_USB3: 1230 type = RG_PHY_SW_USB3; 1231 break; 1232 case PHY_TYPE_PCIE: 1233 type = RG_PHY_SW_PCIE; 1234 break; 1235 case PHY_TYPE_SGMII: 1236 type = RG_PHY_SW_SGMII; 1237 break; 1238 case PHY_TYPE_SATA: 1239 type = RG_PHY_SW_SATA; 1240 break; 1241 case PHY_TYPE_USB2: 1242 default: 1243 return 0; 1244 } 1245 1246 offset = instance->type_sw_index * BITS_PER_BYTE; 1247 regmap_update_bits(instance->type_sw, instance->type_sw_reg, 1248 RG_PHY_SW_TYPE << offset, type << offset); 1249 1250 return 0; 1251} 1252 1253static int phy_efuse_get(struct mtk_tphy *tphy, struct mtk_phy_instance *instance) 1254{ 1255 struct device *dev = &instance->phy->dev; 1256 int ret = 0; 1257 1258 /* tphy v1 doesn't support sw efuse, skip it */ 1259 if (!tphy->pdata->sw_efuse_supported) { 1260 instance->efuse_sw_en = 0; 1261 return 0; 1262 } 1263 1264 /* software efuse is optional */ 1265 instance->efuse_sw_en = device_property_present(dev, "nvmem-cells"); 1266 if (!instance->efuse_sw_en) 1267 return 0; 1268 1269 switch (instance->type) { 1270 case PHY_TYPE_USB2: 1271 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); 1272 if (ret) { 1273 dev_err(dev, "fail to get u2 intr efuse, %d\n", ret); 1274 break; 1275 } 1276 1277 /* no efuse, ignore it */ 1278 if (!instance->efuse_intr) { 1279 dev_warn(dev, "no u2 intr efuse, but dts enable it\n"); 1280 instance->efuse_sw_en = 0; 1281 break; 1282 } 1283 1284 dev_dbg(dev, "u2 efuse - intr %x\n", instance->efuse_intr); 1285 break; 1286 1287 case PHY_TYPE_USB3: 1288 case PHY_TYPE_PCIE: 1289 ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr); 1290 if (ret) { 1291 dev_err(dev, "fail to get u3 intr efuse, %d\n", ret); 1292 break; 1293 } 1294 1295 ret = nvmem_cell_read_variable_le_u32(dev, "rx_imp", &instance->efuse_rx_imp); 1296 if (ret) { 1297 dev_err(dev, "fail to get u3 rx_imp efuse, %d\n", ret); 1298 break; 1299 } 1300 1301 ret = nvmem_cell_read_variable_le_u32(dev, "tx_imp", &instance->efuse_tx_imp); 1302 if (ret) { 1303 dev_err(dev, "fail to get u3 tx_imp efuse, %d\n", ret); 1304 break; 1305 } 1306 1307 /* no efuse, ignore it */ 1308 if (!instance->efuse_intr && 1309 !instance->efuse_rx_imp && 1310 !instance->efuse_tx_imp) { 1311 dev_warn(dev, "no u3 intr efuse, but dts enable it\n"); 1312 instance->efuse_sw_en = 0; 1313 break; 1314 } 1315 1316 dev_dbg(dev, "u3 efuse - intr %x, rx_imp %x, tx_imp %x\n", 1317 instance->efuse_intr, instance->efuse_rx_imp,instance->efuse_tx_imp); 1318 break; 1319 default: 1320 dev_err(dev, "no sw efuse for type %d\n", instance->type); 1321 ret = -EINVAL; 1322 } 1323 1324 return ret; 1325} 1326 1327static void phy_efuse_set(struct mtk_phy_instance *instance) 1328{ 1329 struct device *dev = &instance->phy->dev; 1330 struct u2phy_banks *u2_banks = &instance->u2_banks; 1331 struct u3phy_banks *u3_banks = &instance->u3_banks; 1332 1333 if (!instance->efuse_sw_en) 1334 return; 1335 1336 switch (instance->type) { 1337 case PHY_TYPE_USB2: 1338 mtk_phy_set_bits(u2_banks->misc + U3P_MISC_REG1, MR1_EFUSE_AUTO_LOAD_DIS); 1339 1340 mtk_phy_update_field(u2_banks->com + U3P_USBPHYACR1, PA1_RG_INTR_CAL, 1341 instance->efuse_intr); 1342 break; 1343 case PHY_TYPE_USB3: 1344 case PHY_TYPE_PCIE: 1345 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_RSV, P3D_RG_EFUSE_AUTO_LOAD_DIS); 1346 1347 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_TX_IMPEL, 1348 instance->efuse_tx_imp); 1349 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL0, P3D_RG_FORCE_TX_IMPEL); 1350 1351 mtk_phy_update_field(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_RX_IMPEL, 1352 instance->efuse_rx_imp); 1353 mtk_phy_set_bits(u3_banks->phyd + U3P_U3_PHYD_IMPCAL1, P3D_RG_FORCE_RX_IMPEL); 1354 1355 mtk_phy_update_field(u3_banks->phya + U3P_U3_PHYA_REG0, P3A_RG_IEXT_INTR, 1356 instance->efuse_intr); 1357 break; 1358 default: 1359 dev_warn(dev, "no sw efuse for type %d\n", instance->type); 1360 break; 1361 } 1362} 1363 1364static int mtk_phy_init(struct phy *phy) 1365{ 1366 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1367 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1368 int ret; 1369 1370 ret = clk_bulk_prepare_enable(TPHY_CLKS_CNT, instance->clks); 1371 if (ret) 1372 return ret; 1373 1374 phy_efuse_set(instance); 1375 1376 switch (instance->type) { 1377 case PHY_TYPE_USB2: 1378 u2_phy_instance_init(tphy, instance); 1379 u2_phy_props_set(tphy, instance); 1380 break; 1381 case PHY_TYPE_USB3: 1382 u3_phy_instance_init(tphy, instance); 1383 break; 1384 case PHY_TYPE_PCIE: 1385 pcie_phy_instance_init(tphy, instance); 1386 break; 1387 case PHY_TYPE_SATA: 1388 sata_phy_instance_init(tphy, instance); 1389 break; 1390 case PHY_TYPE_SGMII: 1391 /* nothing to do, only used to set type */ 1392 break; 1393 default: 1394 dev_err(tphy->dev, "incompatible PHY type\n"); 1395 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); 1396 return -EINVAL; 1397 } 1398 1399 return 0; 1400} 1401 1402static int mtk_phy_power_on(struct phy *phy) 1403{ 1404 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1405 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1406 1407 if (instance->type == PHY_TYPE_USB2) { 1408 u2_phy_instance_power_on(tphy, instance); 1409 hs_slew_rate_calibrate(tphy, instance); 1410 } else if (instance->type == PHY_TYPE_PCIE) { 1411 pcie_phy_instance_power_on(tphy, instance); 1412 } 1413 1414 return 0; 1415} 1416 1417static int mtk_phy_power_off(struct phy *phy) 1418{ 1419 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1420 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1421 1422 if (instance->type == PHY_TYPE_USB2) 1423 u2_phy_instance_power_off(tphy, instance); 1424 else if (instance->type == PHY_TYPE_PCIE) 1425 pcie_phy_instance_power_off(tphy, instance); 1426 1427 return 0; 1428} 1429 1430static int mtk_phy_exit(struct phy *phy) 1431{ 1432 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1433 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1434 1435 if (instance->type == PHY_TYPE_USB2) 1436 u2_phy_instance_exit(tphy, instance); 1437 1438 clk_bulk_disable_unprepare(TPHY_CLKS_CNT, instance->clks); 1439 return 0; 1440} 1441 1442static int mtk_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1443{ 1444 struct mtk_phy_instance *instance = phy_get_drvdata(phy); 1445 struct mtk_tphy *tphy = dev_get_drvdata(phy->dev.parent); 1446 1447 if (instance->type == PHY_TYPE_USB2) 1448 u2_phy_instance_set_mode(tphy, instance, mode); 1449 1450 return 0; 1451} 1452 1453static struct phy *mtk_phy_xlate(struct device *dev, 1454 const struct of_phandle_args *args) 1455{ 1456 struct mtk_tphy *tphy = dev_get_drvdata(dev); 1457 struct mtk_phy_instance *instance = NULL; 1458 struct device_node *phy_np = args->np; 1459 int index; 1460 int ret; 1461 1462 if (args->args_count != 1) { 1463 dev_err(dev, "invalid number of cells in 'phy' property\n"); 1464 return ERR_PTR(-EINVAL); 1465 } 1466 1467 for (index = 0; index < tphy->nphys; index++) 1468 if (phy_np == tphy->phys[index]->phy->dev.of_node) { 1469 instance = tphy->phys[index]; 1470 break; 1471 } 1472 1473 if (!instance) { 1474 dev_err(dev, "failed to find appropriate phy\n"); 1475 return ERR_PTR(-EINVAL); 1476 } 1477 1478 instance->type = args->args[0]; 1479 if (!(instance->type == PHY_TYPE_USB2 || 1480 instance->type == PHY_TYPE_USB3 || 1481 instance->type == PHY_TYPE_PCIE || 1482 instance->type == PHY_TYPE_SATA || 1483 instance->type == PHY_TYPE_SGMII)) { 1484 dev_err(dev, "unsupported device type: %d\n", instance->type); 1485 return ERR_PTR(-EINVAL); 1486 } 1487 1488 switch (tphy->pdata->version) { 1489 case MTK_PHY_V1: 1490 phy_v1_banks_init(tphy, instance); 1491 break; 1492 case MTK_PHY_V2: 1493 case MTK_PHY_V3: 1494 phy_v2_banks_init(tphy, instance); 1495 break; 1496 default: 1497 dev_err(dev, "phy version is not supported\n"); 1498 return ERR_PTR(-EINVAL); 1499 } 1500 1501 ret = phy_efuse_get(tphy, instance); 1502 if (ret) 1503 return ERR_PTR(ret); 1504 1505 phy_parse_property(tphy, instance); 1506 phy_type_set(instance); 1507 phy_debugfs_init(instance); 1508 1509 return instance->phy; 1510} 1511 1512static const struct phy_ops mtk_tphy_ops = { 1513 .init = mtk_phy_init, 1514 .exit = mtk_phy_exit, 1515 .power_on = mtk_phy_power_on, 1516 .power_off = mtk_phy_power_off, 1517 .set_mode = mtk_phy_set_mode, 1518 .owner = THIS_MODULE, 1519}; 1520 1521static const struct mtk_phy_pdata tphy_v1_pdata = { 1522 .avoid_rx_sen_degradation = false, 1523 .slew_ref_clock_mhz = 26, 1524 .slew_rate_coefficient = 28, 1525 .version = MTK_PHY_V1, 1526}; 1527 1528static const struct mtk_phy_pdata tphy_v2_pdata = { 1529 .avoid_rx_sen_degradation = false, 1530 .sw_efuse_supported = true, 1531 .slew_ref_clock_mhz = 26, 1532 .slew_rate_coefficient = 28, 1533 .version = MTK_PHY_V2, 1534}; 1535 1536static const struct mtk_phy_pdata tphy_v3_pdata = { 1537 .sw_efuse_supported = true, 1538 .version = MTK_PHY_V3, 1539}; 1540 1541static const struct mtk_phy_pdata mt8173_pdata = { 1542 .avoid_rx_sen_degradation = true, 1543 .slew_ref_clock_mhz = 26, 1544 .slew_rate_coefficient = 28, 1545 .version = MTK_PHY_V1, 1546}; 1547 1548static const struct mtk_phy_pdata mt8195_pdata = { 1549 .sw_pll_48m_to_26m = true, 1550 .sw_efuse_supported = true, 1551 .version = MTK_PHY_V3, 1552}; 1553 1554static const struct of_device_id mtk_tphy_id_table[] = { 1555 { .compatible = "mediatek,mt2701-u3phy", .data = &tphy_v1_pdata }, 1556 { .compatible = "mediatek,mt2712-u3phy", .data = &tphy_v2_pdata }, 1557 { .compatible = "mediatek,mt8173-u3phy", .data = &mt8173_pdata }, 1558 { .compatible = "mediatek,mt8195-tphy", .data = &mt8195_pdata }, 1559 { .compatible = "mediatek,generic-tphy-v1", .data = &tphy_v1_pdata }, 1560 { .compatible = "mediatek,generic-tphy-v2", .data = &tphy_v2_pdata }, 1561 { .compatible = "mediatek,generic-tphy-v3", .data = &tphy_v3_pdata }, 1562 { }, 1563}; 1564MODULE_DEVICE_TABLE(of, mtk_tphy_id_table); 1565 1566static int mtk_tphy_probe(struct platform_device *pdev) 1567{ 1568 struct device *dev = &pdev->dev; 1569 struct device_node *np = dev->of_node; 1570 struct phy_provider *provider; 1571 struct resource *sif_res; 1572 struct mtk_tphy *tphy; 1573 struct resource res; 1574 int port, ret; 1575 1576 tphy = devm_kzalloc(dev, sizeof(*tphy), GFP_KERNEL); 1577 if (!tphy) 1578 return -ENOMEM; 1579 1580 tphy->pdata = of_device_get_match_data(dev); 1581 if (!tphy->pdata) 1582 return -EINVAL; 1583 1584 tphy->nphys = of_get_child_count(np); 1585 tphy->phys = devm_kcalloc(dev, tphy->nphys, 1586 sizeof(*tphy->phys), GFP_KERNEL); 1587 if (!tphy->phys) 1588 return -ENOMEM; 1589 1590 tphy->dev = dev; 1591 platform_set_drvdata(pdev, tphy); 1592 1593 sif_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1594 /* SATA phy of V1 needn't it if not shared with PCIe or USB */ 1595 if (sif_res && tphy->pdata->version == MTK_PHY_V1) { 1596 /* get banks shared by multiple phys */ 1597 tphy->sif_base = devm_ioremap_resource(dev, sif_res); 1598 if (IS_ERR(tphy->sif_base)) { 1599 dev_err(dev, "failed to remap sif regs\n"); 1600 return PTR_ERR(tphy->sif_base); 1601 } 1602 } 1603 1604 /* Optional properties for slew calibration variation */ 1605 ret = device_property_read_u32(dev, "mediatek,src-ref-clk-mhz", &tphy->src_ref_clk); 1606 if (ret) 1607 tphy->src_ref_clk = tphy->pdata->slew_ref_clock_mhz; 1608 1609 ret = device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef); 1610 if (ret) 1611 tphy->src_coef = tphy->pdata->slew_rate_coefficient; 1612 1613 port = 0; 1614 for_each_child_of_node_scoped(np, child_np) { 1615 struct mtk_phy_instance *instance; 1616 struct clk_bulk_data *clks; 1617 struct device *subdev; 1618 struct phy *phy; 1619 int retval; 1620 1621 instance = devm_kzalloc(dev, sizeof(*instance), GFP_KERNEL); 1622 if (!instance) 1623 return -ENOMEM; 1624 1625 tphy->phys[port] = instance; 1626 1627 phy = devm_phy_create(dev, child_np, &mtk_tphy_ops); 1628 if (IS_ERR(phy)) { 1629 dev_err(dev, "failed to create phy\n"); 1630 return PTR_ERR(phy); 1631 } 1632 1633 subdev = &phy->dev; 1634 retval = of_address_to_resource(child_np, 0, &res); 1635 if (retval) { 1636 dev_err(subdev, "failed to get address resource(id-%d)\n", 1637 port); 1638 return retval; 1639 } 1640 1641 instance->port_base = devm_ioremap_resource(subdev, &res); 1642 if (IS_ERR(instance->port_base)) 1643 return PTR_ERR(instance->port_base); 1644 1645 instance->phy = phy; 1646 instance->index = port; 1647 phy_set_drvdata(phy, instance); 1648 port++; 1649 1650 clks = instance->clks; 1651 clks[0].id = "ref"; /* digital (& analog) clock */ 1652 clks[1].id = "da_ref"; /* analog clock */ 1653 retval = devm_clk_bulk_get_optional(subdev, TPHY_CLKS_CNT, clks); 1654 if (retval) 1655 return retval; 1656 1657 retval = phy_type_syscon_get(instance, child_np); 1658 if (retval) 1659 return retval; 1660 } 1661 1662 provider = devm_of_phy_provider_register(dev, mtk_phy_xlate); 1663 1664 return PTR_ERR_OR_ZERO(provider); 1665} 1666 1667static struct platform_driver mtk_tphy_driver = { 1668 .probe = mtk_tphy_probe, 1669 .driver = { 1670 .name = "mtk-tphy", 1671 .of_match_table = mtk_tphy_id_table, 1672 }, 1673}; 1674 1675module_platform_driver(mtk_tphy_driver); 1676 1677MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); 1678MODULE_DESCRIPTION("MediaTek T-PHY driver"); 1679MODULE_LICENSE("GPL v2");
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