phy-hi3670-pcie.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * PCIe phy driver for Kirin 970
  4 *
  5 * Copyright (C) 2017 HiSilicon Electronics Co., Ltd.
  6 *		https://www.huawei.com
  7 * Copyright (C) 2021 Huawei Technologies Co., Ltd.
  8 *		https://www.huawei.com
  9 *
 10 * Authors:
 11 *	Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
 12 *	Manivannan Sadhasivam <mani@kernel.org>
 13 *
 14 * Based on:
 15 *	https://lore.kernel.org/lkml/4c9d6581478aa966698758c0420933f5defab4dd.1612335031.git.mchehab+huawei@kernel.org/
 16 */
 17
 18#include <linux/bitfield.h>
 19#include <linux/bits.h>
 20#include <linux/clk.h>
 21#include <linux/delay.h>
 22#include <linux/device.h>
 23#include <linux/err.h>
 24#include <linux/io.h>
 25#include <linux/mfd/syscon.h>
 26#include <linux/mod_devicetable.h>
 27#include <linux/module.h>
 28#include <linux/of.h>
 29#include <linux/phy/phy.h>
 30#include <linux/platform_device.h>
 31#include <linux/regmap.h>
 32#include <linux/types.h>
 33
 34#define AXI_CLK_FREQ				207500000
 35#define REF_CLK_FREQ				100000000
 36
 37/* PCIe CTRL registers */
 38#define SOC_PCIECTRL_CTRL7_ADDR			0x01c
 39#define SOC_PCIECTRL_CTRL12_ADDR		0x030
 40#define SOC_PCIECTRL_CTRL20_ADDR		0x050
 41#define SOC_PCIECTRL_CTRL21_ADDR		0x054
 42
 43#define PCIE_OUTPUT_PULL_BITS			GENMASK(3, 0)
 44#define SOC_PCIECTRL_CTRL20_2P_MEM_CTRL		0x02605550
 45#define SOC_PCIECTRL_CTRL21_DEFAULT		0x20000070
 46#define PCIE_PULL_UP_SYS_AUX_PWR_DET		BIT(10)
 47#define PCIE_OUTPUT_PULL_DOWN			BIT(1)
 48
 49/* PCIe PHY registers */
 50#define SOC_PCIEPHY_CTRL0_ADDR			0x000
 51#define SOC_PCIEPHY_CTRL1_ADDR			0x004
 52#define SOC_PCIEPHY_CTRL38_ADDR			0x0098
 53#define SOC_PCIEPHY_STATE0_ADDR			0x400
 54
 55#define RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1	0xc004
 56#define SUP_DIG_LVL_OVRD_IN			0x003c
 57#define LANEN_DIG_ASIC_TX_OVRD_IN_1		0x4008
 58#define LANEN_DIG_ASIC_TX_OVRD_IN_2		0x400c
 59
 60#define PCIEPHY_RESET_BIT			BIT(17)
 61#define PCIEPHY_PIPE_LINE0_RESET_BIT		BIT(19)
 62#define PCIE_TXDETECT_RX_FAIL			BIT(2)
 63#define PCIE_CLK_SOURCE				BIT(8)
 64#define PCIE_IS_CLOCK_STABLE			BIT(19)
 65#define PCIE_PULL_DOWN_PHY_TEST_POWERDOWN	BIT(22)
 66#define PCIE_DEASSERT_CONTROLLER_PERST		BIT(2)
 67
 68#define EYEPARAM_NOCFG				0xffffffff
 69#define EYE_PARM0_MASK				GENMASK(8, 6)
 70#define EYE_PARM1_MASK				GENMASK(11, 8)
 71#define EYE_PARM2_MASK				GENMASK(5, 0)
 72#define EYE_PARM3_MASK				GENMASK(12, 7)
 73#define EYE_PARM4_MASK				GENMASK(14, 9)
 74#define EYE_PARM0_EN				BIT(9)
 75#define EYE_PARM1_EN				BIT(12)
 76#define EYE_PARM2_EN				BIT(6)
 77#define EYE_PARM3_EN				BIT(13)
 78#define EYE_PARM4_EN				BIT(15)
 79
 80/* hi3670 pciephy register */
 81#define APB_PHY_START_ADDR			0x40000
 82#define SOC_PCIEPHY_MMC1PLL_CTRL1		0xc04
 83#define SOC_PCIEPHY_MMC1PLL_CTRL16		0xC40
 84#define SOC_PCIEPHY_MMC1PLL_CTRL17		0xC44
 85#define SOC_PCIEPHY_MMC1PLL_CTRL20		0xC50
 86#define SOC_PCIEPHY_MMC1PLL_CTRL21		0xC54
 87#define SOC_PCIEPHY_MMC1PLL_STAT0		0xE00
 88
 89#define CRGPERIPH_PEREN12			0x470
 90#define CRGPERIPH_PERDIS12			0x474
 91#define CRGPERIPH_PCIECTRL0			0x800
 92
 93#define PCIE_FNPLL_FBDIV_MASK			GENMASK(27, 16)
 94#define PCIE_FNPLL_FRACDIV_MASK			GENMASK(23, 0)
 95#define PCIE_FNPLL_POSTDIV1_MASK		GENMASK(10, 8)
 96#define PCIE_FNPLL_POSTDIV2_MASK		GENMASK(14, 12)
 97#define PCIE_FNPLL_PLL_MODE_MASK		BIT(25)
 98
 99#define PCIE_FNPLL_DLL_EN			BIT(27)
100#define PCIE_FNPLL_FBDIV			0xd0
101#define PCIE_FNPLL_FRACDIV			0x555555
102#define PCIE_FNPLL_POSTDIV1			0x5
103#define PCIE_FNPLL_POSTDIV2			0x4
104#define PCIE_FNPLL_PLL_MODE			0x0
105
106#define PCIE_PHY_MMC1PLL			0x20
107#define PCIE_PHY_CHOOSE_FNPLL			BIT(27)
108#define PCIE_PHY_MMC1PLL_DISABLE		BIT(0)
109#define PCIE_PHY_PCIEPL_BP			BIT(16)
110
111/* define ie,oe cfg */
112#define IO_OE_HARD_GT_MODE			BIT(1)
113#define IO_IE_EN_HARD_BYPASS			BIT(27)
114#define IO_OE_EN_HARD_BYPASS			BIT(11)
115#define IO_HARD_CTRL_DEBOUNCE_BYPASS		BIT(10)
116#define IO_OE_GT_MODE				BIT(8)
117#define DEBOUNCE_WAITCFG_IN			GENMASK(23, 20)
118#define DEBOUNCE_WAITCFG_OUT			GENMASK(16, 13)
119
120#define IO_HP_DEBOUNCE_GT			(BIT(12) | BIT(15))
121#define IO_PHYREF_SOFT_GT_MODE			BIT(14)
122#define IO_REF_SOFT_GT_MODE			BIT(13)
123#define IO_REF_HARD_GT_MODE			BIT(0)
124
125/* noc power domain */
126#define NOC_POWER_IDLEREQ_1			0x38c
127#define NOC_POWER_IDLE_1			0x394
128#define NOC_PW_MASK				0x10000
129#define NOC_PW_SET_BIT				0x1
130
131#define NUM_EYEPARAM				5
132
133/* info located in sysctrl */
134#define SCTRL_PCIE_CMOS_OFFSET			0x60
135#define SCTRL_PCIE_CMOS_BIT			0x10
136#define SCTRL_PCIE_ISO_OFFSET			0x44
137#define SCTRL_PCIE_ISO_BIT			0x30
138#define SCTRL_PCIE_HPCLK_OFFSET			0x190
139#define SCTRL_PCIE_HPCLK_BIT			0x184000
140#define SCTRL_PCIE_OE_OFFSET			0x14a
141#define PCIE_DEBOUNCE_PARAM			0xf0f400
142#define PCIE_OE_BYPASS				GENMASK(29, 28)
143
144/* peri_crg ctrl */
145#define CRGCTRL_PCIE_ASSERT_OFFSET		0x88
146#define CRGCTRL_PCIE_ASSERT_BIT			0x8c000000
147
148#define FNPLL_HAS_LOCKED			BIT(4)
149
150/* Time for delay */
151#define TIME_CMOS_MIN		100
152#define TIME_CMOS_MAX		105
153#define PIPE_CLK_STABLE_TIME	100
154#define PLL_CTRL_WAIT_TIME	200
155#define NOC_POWER_TIME		100
156
157struct hi3670_pcie_phy {
158	struct device	*dev;
159	void __iomem	*base;
160	struct regmap	*apb;
161	struct regmap	*crgctrl;
162	struct regmap	*sysctrl;
163	struct regmap	*pmctrl;
164	struct clk	*apb_sys_clk;
165	struct clk	*apb_phy_clk;
166	struct clk	*phy_ref_clk;
167	struct clk	*aclk;
168	struct clk	*aux_clk;
169	u32		eye_param[NUM_EYEPARAM];
170};
171
172/* Registers in PCIePHY */
173static inline void hi3670_apb_phy_writel(struct hi3670_pcie_phy *phy, u32 val,
174					 u32 reg)
175{
176	writel(val, phy->base + APB_PHY_START_ADDR + reg);
177}
178
179static inline u32 hi3670_apb_phy_readl(struct hi3670_pcie_phy *phy, u32 reg)
180{
181	return readl(phy->base + APB_PHY_START_ADDR + reg);
182}
183
184static inline void hi3670_apb_phy_updatel(struct hi3670_pcie_phy *phy,
185					  u32 val, u32 mask, u32 reg)
186{
187	u32 regval;
188
189	regval = hi3670_apb_phy_readl(phy, reg);
190	regval &= ~mask;
191	regval |= val;
192	hi3670_apb_phy_writel(phy, regval, reg);
193}
194
195static inline void kirin_apb_natural_phy_writel(struct hi3670_pcie_phy *phy,
196						u32 val, u32 reg)
197{
198	writel(val, phy->base + reg);
199}
200
201static inline u32 kirin_apb_natural_phy_readl(struct hi3670_pcie_phy *phy,
202					      u32 reg)
203{
204	return readl(phy->base + reg);
205}
206
207static void hi3670_pcie_phy_oe_enable(struct hi3670_pcie_phy *phy, bool enable)
208{
209	u32 val;
210
211	regmap_read(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
212	val |= PCIE_DEBOUNCE_PARAM;
213	if (enable)
214		val &= ~PCIE_OE_BYPASS;
215	else
216		val |= PCIE_OE_BYPASS;
217	regmap_write(phy->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
218}
219
220static void hi3670_pcie_get_eyeparam(struct hi3670_pcie_phy *phy)
221{
222	struct device *dev = phy->dev;
223	struct device_node *np;
224	int ret, i;
225
226	np = dev->of_node;
227
228	ret = of_property_read_u32_array(np, "hisilicon,eye-diagram-param",
229					 phy->eye_param, NUM_EYEPARAM);
230	if (!ret)
231		return;
232
233	/* There's no optional eye_param property. Set array to default */
234	for (i = 0; i < NUM_EYEPARAM; i++)
235		phy->eye_param[i] = EYEPARAM_NOCFG;
236}
237
238static void hi3670_pcie_set_eyeparam(struct hi3670_pcie_phy *phy)
239{
240	u32 val;
241
242	val = kirin_apb_natural_phy_readl(phy, RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
243
244	if (phy->eye_param[1] != EYEPARAM_NOCFG) {
245		val &= ~EYE_PARM1_MASK;
246		val |= FIELD_PREP(EYE_PARM1_MASK, phy->eye_param[1]);
247		val |= EYE_PARM1_EN;
248	}
249	kirin_apb_natural_phy_writel(phy, val,
250				     RAWLANEN_DIG_PCS_XF_TX_OVRD_IN_1);
251
252	val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_2);
253	val &= ~(EYE_PARM2_MASK | EYE_PARM3_MASK);
254	if (phy->eye_param[2] != EYEPARAM_NOCFG) {
255		val |= FIELD_PREP(EYE_PARM2_MASK, phy->eye_param[2]);
256		val |= EYE_PARM2_EN;
257	}
258
259	if (phy->eye_param[3] != EYEPARAM_NOCFG) {
260		val |= FIELD_PREP(EYE_PARM3_MASK, phy->eye_param[3]);
261		val |= EYE_PARM3_EN;
262	}
263
264	kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_2);
265
266	val = kirin_apb_natural_phy_readl(phy, SUP_DIG_LVL_OVRD_IN);
267	if (phy->eye_param[0] != EYEPARAM_NOCFG) {
268		val &= ~EYE_PARM0_MASK;
269		val |= FIELD_PREP(EYE_PARM0_MASK, phy->eye_param[0]);
270		val |= EYE_PARM0_EN;
271	}
272	kirin_apb_natural_phy_writel(phy, val, SUP_DIG_LVL_OVRD_IN);
273
274	val = kirin_apb_natural_phy_readl(phy, LANEN_DIG_ASIC_TX_OVRD_IN_1);
275	if (phy->eye_param[4] != EYEPARAM_NOCFG) {
276		val &= ~EYE_PARM4_MASK;
277		val |= FIELD_PREP(EYE_PARM4_MASK, phy->eye_param[4]);
278		val |= EYE_PARM4_EN;
279	}
280	kirin_apb_natural_phy_writel(phy, val, LANEN_DIG_ASIC_TX_OVRD_IN_1);
281}
282
283static void hi3670_pcie_natural_cfg(struct hi3670_pcie_phy *phy)
284{
285	u32 val;
286
287	/* change 2p mem_ctrl */
288	regmap_write(phy->apb, SOC_PCIECTRL_CTRL20_ADDR,
289		     SOC_PCIECTRL_CTRL20_2P_MEM_CTRL);
290
291	regmap_read(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, &val);
292	val |= PCIE_PULL_UP_SYS_AUX_PWR_DET;
293	regmap_write(phy->apb, SOC_PCIECTRL_CTRL7_ADDR, val);
294
295	/* output, pull down */
296	regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
297	val &= ~PCIE_OUTPUT_PULL_BITS;
298	val |= PCIE_OUTPUT_PULL_DOWN;
299	regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
300
301	/* Handle phy_reset and lane0_reset to HW */
302	hi3670_apb_phy_updatel(phy, PCIEPHY_RESET_BIT,
303			       PCIEPHY_PIPE_LINE0_RESET_BIT | PCIEPHY_RESET_BIT,
304			       SOC_PCIEPHY_CTRL1_ADDR);
305
306	/* fix chip bug: TxDetectRx fail */
307	hi3670_apb_phy_updatel(phy, PCIE_TXDETECT_RX_FAIL, PCIE_TXDETECT_RX_FAIL,
308			       SOC_PCIEPHY_CTRL38_ADDR);
309}
310
311static void hi3670_pcie_pll_init(struct hi3670_pcie_phy *phy)
312{
313	hi3670_apb_phy_updatel(phy, PCIE_PHY_CHOOSE_FNPLL, PCIE_PHY_CHOOSE_FNPLL,
314			       SOC_PCIEPHY_MMC1PLL_CTRL1);
315
316	hi3670_apb_phy_updatel(phy,
317			       FIELD_PREP(PCIE_FNPLL_FBDIV_MASK, PCIE_FNPLL_FBDIV),
318			       PCIE_FNPLL_FBDIV_MASK,
319			       SOC_PCIEPHY_MMC1PLL_CTRL16);
320
321	hi3670_apb_phy_updatel(phy,
322			       FIELD_PREP(PCIE_FNPLL_FRACDIV_MASK, PCIE_FNPLL_FRACDIV),
323			       PCIE_FNPLL_FRACDIV_MASK, SOC_PCIEPHY_MMC1PLL_CTRL17);
324
325	hi3670_apb_phy_updatel(phy,
326			       PCIE_FNPLL_DLL_EN |
327			       FIELD_PREP(PCIE_FNPLL_POSTDIV1_MASK, PCIE_FNPLL_POSTDIV1) |
328			       FIELD_PREP(PCIE_FNPLL_POSTDIV2_MASK, PCIE_FNPLL_POSTDIV2) |
329			       FIELD_PREP(PCIE_FNPLL_PLL_MODE_MASK, PCIE_FNPLL_PLL_MODE),
330			       PCIE_FNPLL_POSTDIV1_MASK |
331			       PCIE_FNPLL_POSTDIV2_MASK |
332			       PCIE_FNPLL_PLL_MODE_MASK | PCIE_FNPLL_DLL_EN,
333			       SOC_PCIEPHY_MMC1PLL_CTRL20);
334
335	hi3670_apb_phy_writel(phy, PCIE_PHY_MMC1PLL,
336			      SOC_PCIEPHY_MMC1PLL_CTRL21);
337}
338
339static int hi3670_pcie_pll_ctrl(struct hi3670_pcie_phy *phy, bool enable)
340{
341	struct device *dev = phy->dev;
342	u32 val;
343	int time = PLL_CTRL_WAIT_TIME;
344
345	if (enable) {
346		/* pd = 0 */
347		hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_MMC1PLL_DISABLE,
348				       SOC_PCIEPHY_MMC1PLL_CTRL16);
349
350		/* choose FNPLL */
351		val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
352		while (!(val & FNPLL_HAS_LOCKED)) {
353			if (!time) {
354				dev_err(dev, "wait for pll_lock timeout\n");
355				return -EINVAL;
356			}
357			time--;
358			udelay(1);
359			val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_MMC1PLL_STAT0);
360		}
361
362		hi3670_apb_phy_updatel(phy, 0, PCIE_PHY_PCIEPL_BP,
363				       SOC_PCIEPHY_MMC1PLL_CTRL20);
364
365	} else {
366		hi3670_apb_phy_updatel(phy,
367				       PCIE_PHY_MMC1PLL_DISABLE,
368				       PCIE_PHY_MMC1PLL_DISABLE,
369				       SOC_PCIEPHY_MMC1PLL_CTRL16);
370
371		hi3670_apb_phy_updatel(phy, PCIE_PHY_PCIEPL_BP,
372				       PCIE_PHY_PCIEPL_BP,
373				       SOC_PCIEPHY_MMC1PLL_CTRL20);
374	}
375
376	return 0;
377}
378
379static void hi3670_pcie_hp_debounce_gt(struct hi3670_pcie_phy *phy, bool open)
380{
381	if (open)
382		/* gt_clk_pcie_hp/gt_clk_pcie_debounce open */
383		regmap_write(phy->crgctrl, CRGPERIPH_PEREN12,
384			     IO_HP_DEBOUNCE_GT);
385	else
386		/* gt_clk_pcie_hp/gt_clk_pcie_debounce close */
387		regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
388			     IO_HP_DEBOUNCE_GT);
389}
390
391static void hi3670_pcie_phyref_gt(struct hi3670_pcie_phy *phy, bool open)
392{
393	unsigned int val;
394
395	regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
396
397	if (open)
398		val &= ~IO_OE_HARD_GT_MODE; /* enable hard gt mode */
399	else
400		val |= IO_OE_HARD_GT_MODE; /* disable hard gt mode */
401
402	regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
403
404	/* disable soft gt mode */
405	regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12, IO_PHYREF_SOFT_GT_MODE);
406}
407
408static void hi3670_pcie_oe_ctrl(struct hi3670_pcie_phy *phy, bool en_flag)
409{
410	unsigned int val;
411
412	regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
413
414	/* set ie cfg */
415	val |= IO_IE_EN_HARD_BYPASS;
416
417	/* set oe cfg */
418	val &= ~IO_HARD_CTRL_DEBOUNCE_BYPASS;
419
420	/* set phy_debounce in&out time */
421	val |= (DEBOUNCE_WAITCFG_IN | DEBOUNCE_WAITCFG_OUT);
422
423	/* select oe_gt_mode */
424	val |= IO_OE_GT_MODE;
425
426	if (en_flag)
427		val &= ~IO_OE_EN_HARD_BYPASS;
428	else
429		val |= IO_OE_EN_HARD_BYPASS;
430
431	regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
432}
433
434static void hi3670_pcie_ioref_gt(struct hi3670_pcie_phy *phy, bool open)
435{
436	unsigned int val;
437
438	if (open) {
439		regmap_write(phy->apb, SOC_PCIECTRL_CTRL21_ADDR,
440			     SOC_PCIECTRL_CTRL21_DEFAULT);
441
442		hi3670_pcie_oe_ctrl(phy, true);
443
444		/* en hard gt mode */
445		regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
446		val &= ~IO_REF_HARD_GT_MODE;
447		regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
448
449		/* disable soft gt mode */
450		regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
451			     IO_REF_SOFT_GT_MODE);
452
453	} else {
454		/* disable hard gt mode */
455		regmap_read(phy->crgctrl, CRGPERIPH_PCIECTRL0, &val);
456		val |= IO_REF_HARD_GT_MODE;
457		regmap_write(phy->crgctrl, CRGPERIPH_PCIECTRL0, val);
458
459		/* disable soft gt mode */
460		regmap_write(phy->crgctrl, CRGPERIPH_PERDIS12,
461			     IO_REF_SOFT_GT_MODE);
462
463		hi3670_pcie_oe_ctrl(phy, false);
464	}
465}
466
467static int hi3670_pcie_allclk_ctrl(struct hi3670_pcie_phy *phy, bool clk_on)
468{
469	struct device *dev = phy->dev;
470	int ret = 0;
471
472	if (!clk_on)
473		goto close_clocks;
474
475	/* choose 100MHz clk src: Bit[8]==1 pad, Bit[8]==0 pll */
476	hi3670_apb_phy_updatel(phy, 0, PCIE_CLK_SOURCE,
477			       SOC_PCIEPHY_CTRL1_ADDR);
478
479	hi3670_pcie_pll_init(phy);
480
481	ret = hi3670_pcie_pll_ctrl(phy, true);
482	if (ret) {
483		dev_err(dev, "Failed to enable pll\n");
484		return -EINVAL;
485	}
486	hi3670_pcie_hp_debounce_gt(phy, true);
487	hi3670_pcie_phyref_gt(phy, true);
488	hi3670_pcie_ioref_gt(phy, true);
489
490	ret = clk_set_rate(phy->aclk, AXI_CLK_FREQ);
491	if (ret) {
492		dev_err(dev, "Failed to set rate\n");
493		goto close_clocks;
494	}
495
496	return 0;
497
498close_clocks:
499	hi3670_pcie_ioref_gt(phy, false);
500	hi3670_pcie_phyref_gt(phy, false);
501	hi3670_pcie_hp_debounce_gt(phy, false);
502
503	hi3670_pcie_pll_ctrl(phy, false);
504
505	return ret;
506}
507
508static bool is_pipe_clk_stable(struct hi3670_pcie_phy *phy)
509{
510	struct device *dev = phy->dev;
511	u32 val;
512	u32 time = PIPE_CLK_STABLE_TIME;
513	u32 pipe_clk_stable = PCIE_IS_CLOCK_STABLE;
514
515	val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
516	while (val & pipe_clk_stable) {
517		mdelay(1);
518		if (!time) {
519			dev_err(dev, "PIPE clk is not stable\n");
520			return false;
521		}
522		time--;
523		val = hi3670_apb_phy_readl(phy, SOC_PCIEPHY_STATE0_ADDR);
524	}
525
526	return true;
527}
528
529static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
530{
531	struct device *dev = phy->dev;
532	u32 time = NOC_POWER_TIME;
533	unsigned int val = NOC_PW_MASK;
534	int rst;
535
536	if (enable)
537		val = NOC_PW_MASK | NOC_PW_SET_BIT;
538	else
539		val = NOC_PW_MASK;
540	rst = enable ? 1 : 0;
541
542	regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
543
544	time = NOC_POWER_TIME;
545	regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
546	while ((val & NOC_PW_SET_BIT) != rst) {
547		udelay(10);
548		if (!time) {
549			dev_err(dev, "Failed to reverse noc power-status\n");
550			return -EINVAL;
551		}
552		time--;
553		regmap_read(phy->pmctrl, NOC_POWER_IDLE_1, &val);
554	}
555
556	return 0;
557}
558
559static int hi3670_pcie_get_resources_from_pcie(struct hi3670_pcie_phy *phy)
560{
561	struct device_node *pcie_port;
562	struct device *dev = phy->dev;
563	struct device *pcie_dev;
564
565	pcie_port = of_get_child_by_name(dev->parent->of_node, "pcie");
566	if (!pcie_port) {
567		dev_err(dev, "no pcie node found in %s\n",
568			dev->parent->of_node->full_name);
569		return -ENODEV;
570	}
571
572	pcie_dev = bus_find_device_by_of_node(&platform_bus_type, pcie_port);
573	if (!pcie_dev) {
574		dev_err(dev, "Didn't find pcie device\n");
575		return -ENODEV;
576	}
577
578	/*
579	 * We might just use NULL instead of the APB name, as the
580	 * pcie-kirin currently registers directly just one regmap (although
581	 * the DWC driver register other regmaps).
582	 *
583	 * Yet, it sounds safer to warrant that it will be accessing the
584	 * right regmap. So, let's use the named version.
585	 */
586	phy->apb = dev_get_regmap(pcie_dev, "kirin_pcie_apb");
587	if (!phy->apb) {
588		dev_err(dev, "Failed to get APB regmap\n");
589		return -ENODEV;
590	}
591
592	return 0;
593}
594
595static int kirin_pcie_clk_ctrl(struct hi3670_pcie_phy *phy, bool enable)
596{
597	int ret = 0;
598
599	if (!enable)
600		goto close_clk;
601
602	ret = clk_set_rate(phy->phy_ref_clk, REF_CLK_FREQ);
603	if (ret)
604		return ret;
605
606	ret = clk_prepare_enable(phy->phy_ref_clk);
607	if (ret)
608		return ret;
609
610	ret = clk_prepare_enable(phy->apb_sys_clk);
611	if (ret)
612		goto apb_sys_fail;
613
614	ret = clk_prepare_enable(phy->apb_phy_clk);
615	if (ret)
616		goto apb_phy_fail;
617
618	ret = clk_prepare_enable(phy->aclk);
619	if (ret)
620		goto aclk_fail;
621
622	ret = clk_prepare_enable(phy->aux_clk);
623	if (ret)
624		goto aux_clk_fail;
625
626	return 0;
627
628close_clk:
629	clk_disable_unprepare(phy->aux_clk);
630aux_clk_fail:
631	clk_disable_unprepare(phy->aclk);
632aclk_fail:
633	clk_disable_unprepare(phy->apb_phy_clk);
634apb_phy_fail:
635	clk_disable_unprepare(phy->apb_sys_clk);
636apb_sys_fail:
637	clk_disable_unprepare(phy->phy_ref_clk);
638
639	return ret;
640}
641
642static int hi3670_pcie_phy_init(struct phy *generic_phy)
643{
644	struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
645	int ret;
646
647	/*
648	 * The code under hi3670_pcie_get_resources_from_pcie() need to
649	 * access the reset-gpios and the APB registers, both from the
650	 * pcie-kirin driver.
651	 *
652	 * The APB is obtained via the pcie driver's regmap
653	 * Such kind of resource can only be obtained during the PCIe
654	 * power_on sequence, as the code inside pcie-kirin needs to
655	 * be already probed, as it needs to register the APB regmap.
656	 */
657
658	ret = hi3670_pcie_get_resources_from_pcie(phy);
659	if (ret)
660		return ret;
661
662	return 0;
663}
664
665static int hi3670_pcie_phy_power_on(struct phy *generic_phy)
666{
667	struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
668	int val, ret;
669
670	/* Power supply for Host */
671	regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
672	usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
673
674	hi3670_pcie_phy_oe_enable(phy, true);
675
676	ret = kirin_pcie_clk_ctrl(phy, true);
677	if (ret)
678		return ret;
679
680	/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
681	regmap_write(phy->sysctrl, SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
682	regmap_write(phy->crgctrl, CRGCTRL_PCIE_ASSERT_OFFSET,
683		     CRGCTRL_PCIE_ASSERT_BIT);
684	regmap_write(phy->sysctrl, SCTRL_PCIE_HPCLK_OFFSET,
685		     SCTRL_PCIE_HPCLK_BIT);
686
687	hi3670_pcie_natural_cfg(phy);
688
689	ret = hi3670_pcie_allclk_ctrl(phy, true);
690	if (ret)
691		goto disable_clks;
692
693	/* pull down phy_test_powerdown signal */
694	hi3670_apb_phy_updatel(phy, 0, PCIE_PULL_DOWN_PHY_TEST_POWERDOWN,
695			       SOC_PCIEPHY_CTRL0_ADDR);
696
697	/* deassert controller perst_n */
698	regmap_read(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, &val);
699	val |= PCIE_DEASSERT_CONTROLLER_PERST;
700	regmap_write(phy->apb, SOC_PCIECTRL_CTRL12_ADDR, val);
701	udelay(10);
702
703	ret = is_pipe_clk_stable(phy);
704	if (!ret)
705		goto disable_clks;
706
707	hi3670_pcie_set_eyeparam(phy);
708
709	ret = hi3670_pcie_noc_power(phy, false);
710	if (ret)
711		goto disable_clks;
712
713	return 0;
714
715disable_clks:
716	kirin_pcie_clk_ctrl(phy, false);
717	return ret;
718}
719
720static int hi3670_pcie_phy_power_off(struct phy *generic_phy)
721{
722	struct hi3670_pcie_phy *phy = phy_get_drvdata(generic_phy);
723
724	hi3670_pcie_phy_oe_enable(phy, false);
725
726	hi3670_pcie_allclk_ctrl(phy, false);
727
728	/* Drop power supply for Host */
729	regmap_write(phy->sysctrl, SCTRL_PCIE_CMOS_OFFSET, 0);
730
731	/*
732	 * FIXME: The enabled clocks should be disabled here by calling
733	 * kirin_pcie_clk_ctrl(phy, false);
734	 * However, some clocks used at Kirin 970 should be marked as
735	 * CLK_IS_CRITICAL at clk-hi3670 driver, as powering such clocks off
736	 * cause an Asynchronous SError interrupt, which produces panic().
737	 * While clk-hi3670 is not fixed, we cannot risk disabling clocks here.
738	 */
739
740	return 0;
741}
742
743static const struct phy_ops hi3670_phy_ops = {
744	.init		= hi3670_pcie_phy_init,
745	.power_on	= hi3670_pcie_phy_power_on,
746	.power_off	= hi3670_pcie_phy_power_off,
747	.owner		= THIS_MODULE,
748};
749
750static int hi3670_pcie_phy_get_resources(struct hi3670_pcie_phy *phy,
751					 struct platform_device *pdev)
752{
753	struct device *dev = &pdev->dev;
754
755	/* syscon */
756	phy->crgctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-crgctrl");
757	if (IS_ERR(phy->crgctrl))
758		return PTR_ERR(phy->crgctrl);
759
760	phy->sysctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-sctrl");
761	if (IS_ERR(phy->sysctrl))
762		return PTR_ERR(phy->sysctrl);
763
764	phy->pmctrl = syscon_regmap_lookup_by_compatible("hisilicon,hi3670-pmctrl");
765	if (IS_ERR(phy->pmctrl))
766		return PTR_ERR(phy->pmctrl);
767
768	/* clocks */
769	phy->phy_ref_clk = devm_clk_get(dev, "phy_ref");
770	if (IS_ERR(phy->phy_ref_clk))
771		return PTR_ERR(phy->phy_ref_clk);
772
773	phy->aux_clk = devm_clk_get(dev, "aux");
774	if (IS_ERR(phy->aux_clk))
775		return PTR_ERR(phy->aux_clk);
776
777	phy->apb_phy_clk = devm_clk_get(dev, "apb_phy");
778	if (IS_ERR(phy->apb_phy_clk))
779		return PTR_ERR(phy->apb_phy_clk);
780
781	phy->apb_sys_clk = devm_clk_get(dev, "apb_sys");
782	if (IS_ERR(phy->apb_sys_clk))
783		return PTR_ERR(phy->apb_sys_clk);
784
785	phy->aclk = devm_clk_get(dev, "aclk");
786	if (IS_ERR(phy->aclk))
787		return PTR_ERR(phy->aclk);
788
789	/* registers */
790	phy->base = devm_platform_ioremap_resource(pdev, 0);
791	if (IS_ERR(phy->base))
792		return PTR_ERR(phy->base);
793
794	hi3670_pcie_get_eyeparam(phy);
795
796	return 0;
797}
798
799static int hi3670_pcie_phy_probe(struct platform_device *pdev)
800{
801	struct phy_provider *phy_provider;
802	struct device *dev = &pdev->dev;
803	struct hi3670_pcie_phy *phy;
804	struct phy *generic_phy;
805	int ret;
806
807	phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
808	if (!phy)
809		return -ENOMEM;
810
811	phy->dev = dev;
812
813	ret = hi3670_pcie_phy_get_resources(phy, pdev);
814	if (ret)
815		return ret;
816
817	generic_phy = devm_phy_create(dev, dev->of_node, &hi3670_phy_ops);
818	if (IS_ERR(generic_phy)) {
819		dev_err(dev, "failed to create PHY\n");
820		return PTR_ERR(generic_phy);
821	}
822
823	phy_set_drvdata(generic_phy, phy);
824	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
825
826	return PTR_ERR_OR_ZERO(phy_provider);
827}
828
829static const struct of_device_id hi3670_pcie_phy_match[] = {
830	{
831		.compatible = "hisilicon,hi970-pcie-phy",
832	},
833	{},
834};
835
836static struct platform_driver hi3670_pcie_phy_driver = {
837	.probe	= hi3670_pcie_phy_probe,
838	.driver = {
839		.of_match_table	= hi3670_pcie_phy_match,
840		.name		= "hi3670_pcie_phy",
841		.suppress_bind_attrs = true,
842	}
843};
844builtin_platform_driver(hi3670_pcie_phy_driver);
845
846MODULE_DEVICE_TABLE(of, hi3670_pcie_phy_match);
847MODULE_DESCRIPTION("PCIe phy driver for Kirin 970");
848MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@kernel.org>");
849MODULE_AUTHOR("Manivannan Sadhasivam <mani@kernel.org>");
850MODULE_LICENSE("GPL v2");