phy-fsl-imx8m-pcie.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright 2021 NXP
  4 */
  5
  6#include <linux/bitfield.h>
  7#include <linux/clk.h>
  8#include <linux/delay.h>
  9#include <linux/io.h>
 10#include <linux/iopoll.h>
 11#include <linux/mfd/syscon.h>
 12#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
 13#include <linux/module.h>
 14#include <linux/of.h>
 15#include <linux/phy/phy.h>
 16#include <linux/platform_device.h>
 17#include <linux/regmap.h>
 18#include <linux/reset.h>
 19
 20#include <dt-bindings/phy/phy-imx8-pcie.h>
 21
 22#define IMX8MM_PCIE_PHY_CMN_REG061	0x184
 23#define  ANA_PLL_CLK_OUT_TO_EXT_IO_EN	BIT(0)
 24#define IMX8MM_PCIE_PHY_CMN_REG062	0x188
 25#define  ANA_PLL_CLK_OUT_TO_EXT_IO_SEL	BIT(3)
 26#define IMX8MM_PCIE_PHY_CMN_REG063	0x18C
 27#define  AUX_PLL_REFCLK_SEL_SYS_PLL	GENMASK(7, 6)
 28#define IMX8MM_PCIE_PHY_CMN_REG064	0x190
 29#define  ANA_AUX_RX_TX_SEL_TX		BIT(7)
 30#define  ANA_AUX_RX_TERM_GND_EN		BIT(3)
 31#define  ANA_AUX_TX_TERM		BIT(2)
 32#define IMX8MM_PCIE_PHY_CMN_REG065	0x194
 33#define  ANA_AUX_RX_TERM		(BIT(7) | BIT(4))
 34#define  ANA_AUX_TX_LVL			GENMASK(3, 0)
 35#define IMX8MM_PCIE_PHY_CMN_REG075	0x1D4
 36#define  ANA_PLL_DONE			0x3
 37#define PCIE_PHY_TRSV_REG5		0x414
 38#define PCIE_PHY_TRSV_REG6		0x418
 39
 40#define IMX8MM_GPR_PCIE_REF_CLK_SEL	GENMASK(25, 24)
 41#define IMX8MM_GPR_PCIE_REF_CLK_PLL	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x3)
 42#define IMX8MM_GPR_PCIE_REF_CLK_EXT	FIELD_PREP(IMX8MM_GPR_PCIE_REF_CLK_SEL, 0x2)
 43#define IMX8MM_GPR_PCIE_AUX_EN		BIT(19)
 44#define IMX8MM_GPR_PCIE_CMN_RST		BIT(18)
 45#define IMX8MM_GPR_PCIE_POWER_OFF	BIT(17)
 46#define IMX8MM_GPR_PCIE_SSC_EN		BIT(16)
 47#define IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE	BIT(9)
 48
 49enum imx8_pcie_phy_type {
 50	IMX8MM,
 51	IMX8MP,
 52};
 53
 54struct imx8_pcie_phy_drvdata {
 55	const	char			*gpr;
 56	enum	imx8_pcie_phy_type	variant;
 57};
 58
 59struct imx8_pcie_phy {
 60	void __iomem		*base;
 61	struct clk		*clk;
 62	struct phy		*phy;
 63	struct regmap		*iomuxc_gpr;
 64	struct reset_control	*perst;
 65	struct reset_control	*reset;
 66	u32			refclk_pad_mode;
 67	u32			tx_deemph_gen1;
 68	u32			tx_deemph_gen2;
 69	bool			clkreq_unused;
 70	const struct imx8_pcie_phy_drvdata	*drvdata;
 71};
 72
 73static int imx8_pcie_phy_power_on(struct phy *phy)
 74{
 75	int ret;
 76	u32 val, pad_mode;
 77	struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
 78
 79	pad_mode = imx8_phy->refclk_pad_mode;
 80	switch (imx8_phy->drvdata->variant) {
 81	case IMX8MM:
 82		reset_control_assert(imx8_phy->reset);
 83
 84		/* Tune PHY de-emphasis setting to pass PCIe compliance. */
 85		if (imx8_phy->tx_deemph_gen1)
 86			writel(imx8_phy->tx_deemph_gen1,
 87			       imx8_phy->base + PCIE_PHY_TRSV_REG5);
 88		if (imx8_phy->tx_deemph_gen2)
 89			writel(imx8_phy->tx_deemph_gen2,
 90			       imx8_phy->base + PCIE_PHY_TRSV_REG6);
 91		break;
 92	case IMX8MP:
 93		reset_control_assert(imx8_phy->reset);
 94		break;
 95	}
 96
 97	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
 98	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
 99		/* Configure the pad as input */
100		val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
101		writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
102		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
103	} else {
104		/* Configure the PHY to output the refclock via pad */
105		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
106		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
107	}
108
109	if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
110	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
111		/* Source clock from SoC internal PLL */
112		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
113		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
114		if (imx8_phy->drvdata->variant != IMX8MM) {
115			writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
116			       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG063);
117		}
118		val = ANA_AUX_RX_TX_SEL_TX | ANA_AUX_TX_TERM;
119		writel(val | ANA_AUX_RX_TERM_GND_EN,
120		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG064);
121		writel(ANA_AUX_RX_TERM | ANA_AUX_TX_LVL,
122		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG065);
123	}
124
125	/* Set AUX_EN_OVERRIDE 1'b0, when the CLKREQ# isn't hooked */
126	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
127			   IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE,
128			   imx8_phy->clkreq_unused ?
129			   0 : IMX8MM_GPR_PCIE_AUX_EN_OVERRIDE);
130	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
131			   IMX8MM_GPR_PCIE_AUX_EN,
132			   IMX8MM_GPR_PCIE_AUX_EN);
133	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
134			   IMX8MM_GPR_PCIE_POWER_OFF, 0);
135	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
136			   IMX8MM_GPR_PCIE_SSC_EN, 0);
137
138	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
139			   IMX8MM_GPR_PCIE_REF_CLK_SEL,
140			   pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ?
141			   IMX8MM_GPR_PCIE_REF_CLK_EXT :
142			   IMX8MM_GPR_PCIE_REF_CLK_PLL);
143	usleep_range(100, 200);
144
145	reset_control_deassert(imx8_phy->perst);
146	reset_control_deassert(imx8_phy->reset);
147	usleep_range(200, 500);
148
149	/* Do the PHY common block reset */
150	regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14,
151			   IMX8MM_GPR_PCIE_CMN_RST,
152			   IMX8MM_GPR_PCIE_CMN_RST);
153
154	/* Polling to check the phy is ready or not. */
155	ret = readl_poll_timeout(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG075,
156				 val, val == ANA_PLL_DONE, 10, 20000);
157	return ret;
158}
159
160static int imx8_pcie_phy_power_off(struct phy *phy)
161{
162	struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
163
164	reset_control_assert(imx8_phy->reset);
165	reset_control_assert(imx8_phy->perst);
166
167	return 0;
168}
169
170static int imx8_pcie_phy_init(struct phy *phy)
171{
172	struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
173
174	return clk_prepare_enable(imx8_phy->clk);
175}
176
177static int imx8_pcie_phy_exit(struct phy *phy)
178{
179	struct imx8_pcie_phy *imx8_phy = phy_get_drvdata(phy);
180
181	clk_disable_unprepare(imx8_phy->clk);
182
183	return 0;
184}
185
186static const struct phy_ops imx8_pcie_phy_ops = {
187	.init		= imx8_pcie_phy_init,
188	.exit		= imx8_pcie_phy_exit,
189	.power_on	= imx8_pcie_phy_power_on,
190	.power_off	= imx8_pcie_phy_power_off,
191	.owner		= THIS_MODULE,
192};
193
194static const struct imx8_pcie_phy_drvdata imx8mm_drvdata = {
195	.gpr = "fsl,imx8mm-iomuxc-gpr",
196	.variant = IMX8MM,
197};
198
199static const struct imx8_pcie_phy_drvdata imx8mp_drvdata = {
200	.gpr = "fsl,imx8mp-iomuxc-gpr",
201	.variant = IMX8MP,
202};
203
204static const struct of_device_id imx8_pcie_phy_of_match[] = {
205	{.compatible = "fsl,imx8mm-pcie-phy", .data = &imx8mm_drvdata, },
206	{.compatible = "fsl,imx8mp-pcie-phy", .data = &imx8mp_drvdata, },
207	{ },
208};
209MODULE_DEVICE_TABLE(of, imx8_pcie_phy_of_match);
210
211static int imx8_pcie_phy_probe(struct platform_device *pdev)
212{
213	struct phy_provider *phy_provider;
214	struct device *dev = &pdev->dev;
215	struct device_node *np = dev->of_node;
216	struct imx8_pcie_phy *imx8_phy;
217
218	imx8_phy = devm_kzalloc(dev, sizeof(*imx8_phy), GFP_KERNEL);
219	if (!imx8_phy)
220		return -ENOMEM;
221
222	imx8_phy->drvdata = of_device_get_match_data(dev);
223
224	/* get PHY refclk pad mode */
225	of_property_read_u32(np, "fsl,refclk-pad-mode",
226			     &imx8_phy->refclk_pad_mode);
227
228	if (of_property_read_u32(np, "fsl,tx-deemph-gen1",
229				 &imx8_phy->tx_deemph_gen1))
230		imx8_phy->tx_deemph_gen1 = 0;
231
232	if (of_property_read_u32(np, "fsl,tx-deemph-gen2",
233				 &imx8_phy->tx_deemph_gen2))
234		imx8_phy->tx_deemph_gen2 = 0;
235
236	if (of_property_read_bool(np, "fsl,clkreq-unsupported"))
237		imx8_phy->clkreq_unused = true;
238	else
239		imx8_phy->clkreq_unused = false;
240
241	imx8_phy->clk = devm_clk_get(dev, "ref");
242	if (IS_ERR(imx8_phy->clk))
243		return dev_err_probe(dev, PTR_ERR(imx8_phy->clk),
244				     "failed to get imx pcie phy clock\n");
245
246	/* Grab GPR config register range */
247	imx8_phy->iomuxc_gpr =
248		 syscon_regmap_lookup_by_compatible(imx8_phy->drvdata->gpr);
249	if (IS_ERR(imx8_phy->iomuxc_gpr))
250		return dev_err_probe(dev, PTR_ERR(imx8_phy->iomuxc_gpr),
251				     "unable to find iomuxc registers\n");
252
253	imx8_phy->reset = devm_reset_control_get_exclusive(dev, "pciephy");
254	if (IS_ERR(imx8_phy->reset))
255		return dev_err_probe(dev, PTR_ERR(imx8_phy->reset),
256				     "Failed to get PCIEPHY reset control\n");
257
258	if (imx8_phy->drvdata->variant == IMX8MP) {
259		imx8_phy->perst =
260			devm_reset_control_get_exclusive(dev, "perst");
261		if (IS_ERR(imx8_phy->perst))
262			return dev_err_probe(dev, PTR_ERR(imx8_phy->perst),
263				      "Failed to get PCIE PHY PERST control\n");
264	}
265
266	imx8_phy->base = devm_platform_ioremap_resource(pdev, 0);
267	if (IS_ERR(imx8_phy->base))
268		return PTR_ERR(imx8_phy->base);
269
270	imx8_phy->phy = devm_phy_create(dev, NULL, &imx8_pcie_phy_ops);
271	if (IS_ERR(imx8_phy->phy))
272		return PTR_ERR(imx8_phy->phy);
273
274	phy_set_drvdata(imx8_phy->phy, imx8_phy);
275
276	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
277
278	return PTR_ERR_OR_ZERO(phy_provider);
279}
280
281static struct platform_driver imx8_pcie_phy_driver = {
282	.probe	= imx8_pcie_phy_probe,
283	.driver = {
284		.name	= "imx8-pcie-phy",
285		.of_match_table	= imx8_pcie_phy_of_match,
286	}
287};
288module_platform_driver(imx8_pcie_phy_driver);
289
290MODULE_DESCRIPTION("FSL IMX8 PCIE PHY driver");
291MODULE_LICENSE("GPL v2");