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phy-cadence-torrent.c
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linux-6.19.14/drivers/phy/cadence/phy-cadence-torrent.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Cadence Torrent SD0801 PHY driver. 4 * 5 * Copyright 2018 Cadence Design Systems, Inc. 6 * 7 */ 8 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/phy/phy-cadence.h> 11#include <linux/clk.h> 12#include <linux/clk-provider.h> 13#include <linux/delay.h> 14#include <linux/err.h> 15#include <linux/io.h> 16#include <linux/iopoll.h> 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/of.h> 20#include <linux/phy/phy.h> 21#include <linux/platform_device.h> 22#include <linux/reset.h> 23#include <linux/regmap.h> 24 25#define REF_CLK_19_2MHZ 19200000 26#define REF_CLK_25MHZ 25000000 27#define REF_CLK_100MHZ 100000000 28#define REF_CLK_156_25MHZ 156250000 29 30#define MAX_NUM_LANES 4 31#define DEFAULT_MAX_BIT_RATE 8100 /* in Mbps */ 32 33#define POLL_TIMEOUT_US 5000 34#define PLL_LOCK_TIMEOUT 100000 35 36#define DP_PLL0 BIT(0) 37#define DP_PLL1 BIT(1) 38 39#define TORRENT_COMMON_CDB_OFFSET 0x0 40 41#define TORRENT_TX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 42 ((0x4000 << (block_offset)) + \ 43 (((ln) << 9) << (reg_offset))) 44 45#define TORRENT_RX_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 46 ((0x8000 << (block_offset)) + \ 47 (((ln) << 9) << (reg_offset))) 48 49#define TORRENT_PHY_PCS_COMMON_OFFSET(block_offset) \ 50 (0xC000 << (block_offset)) 51 52#define TORRENT_PHY_PCS_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ 53 ((0xD000 << (block_offset)) + \ 54 (((ln) << 8) << (reg_offset))) 55 56#define TORRENT_PHY_PMA_COMMON_OFFSET(block_offset) \ 57 (0xE000 << (block_offset)) 58 59#define TORRENT_DPTX_PHY_OFFSET 0x0 60 61/* 62 * register offsets from DPTX PHY register block base (i.e MHDP 63 * register base + 0x30a00) 64 */ 65#define PHY_AUX_CTRL 0x04 66#define PHY_RESET 0x20 67#define PMA_TX_ELEC_IDLE_SHIFT 4 68#define PHY_PMA_XCVR_PLLCLK_EN 0x24 69#define PHY_PMA_XCVR_PLLCLK_EN_ACK 0x28 70#define PHY_PMA_XCVR_POWER_STATE_REQ 0x2c 71#define PHY_POWER_STATE_LN(ln) ((ln) * 8) 72#define PMA_XCVR_POWER_STATE_REQ_LN_MASK 0x3FU 73#define PHY_PMA_XCVR_POWER_STATE_ACK 0x30 74#define PHY_PMA_CMN_READY 0x34 75 76/* 77 * register offsets from SD0801 PHY register block base (i.e MHDP 78 * register base + 0x500000) 79 */ 80#define CMN_SSM_BANDGAP_TMR 0x0021U 81#define CMN_SSM_BIAS_TMR 0x0022U 82#define CMN_PLLSM0_PLLPRE_TMR 0x002AU 83#define CMN_PLLSM0_PLLLOCK_TMR 0x002CU 84#define CMN_PLLSM1_PLLPRE_TMR 0x0032U 85#define CMN_PLLSM1_PLLLOCK_TMR 0x0034U 86#define CMN_CDIAG_CDB_PWRI_OVRD 0x0041U 87#define CMN_CDIAG_XCVRC_PWRI_OVRD 0x0047U 88#define CMN_CDIAG_REFCLK_OVRD 0x004CU 89#define CMN_CDIAG_REFCLK_DRV0_CTRL 0x0050U 90#define CMN_BGCAL_INIT_TMR 0x0064U 91#define CMN_BGCAL_ITER_TMR 0x0065U 92#define CMN_IBCAL_INIT_TMR 0x0074U 93#define CMN_PLL0_VCOCAL_TCTRL 0x0082U 94#define CMN_PLL0_VCOCAL_INIT_TMR 0x0084U 95#define CMN_PLL0_VCOCAL_ITER_TMR 0x0085U 96#define CMN_PLL0_VCOCAL_REFTIM_START 0x0086U 97#define CMN_PLL0_VCOCAL_PLLCNT_START 0x0088U 98#define CMN_PLL0_INTDIV_M0 0x0090U 99#define CMN_PLL0_FRACDIVL_M0 0x0091U 100#define CMN_PLL0_FRACDIVH_M0 0x0092U 101#define CMN_PLL0_HIGH_THR_M0 0x0093U 102#define CMN_PLL0_DSM_DIAG_M0 0x0094U 103#define CMN_PLL0_DSM_FBH_OVRD_M0 0x0095U 104#define CMN_PLL0_DSM_FBL_OVRD_M0 0x0096U 105#define CMN_PLL0_SS_CTRL1_M0 0x0098U 106#define CMN_PLL0_SS_CTRL2_M0 0x0099U 107#define CMN_PLL0_SS_CTRL3_M0 0x009AU 108#define CMN_PLL0_SS_CTRL4_M0 0x009BU 109#define CMN_PLL0_LOCK_REFCNT_START 0x009CU 110#define CMN_PLL0_LOCK_PLLCNT_START 0x009EU 111#define CMN_PLL0_LOCK_PLLCNT_THR 0x009FU 112#define CMN_PLL0_INTDIV_M1 0x00A0U 113#define CMN_PLL0_FRACDIVH_M1 0x00A2U 114#define CMN_PLL0_HIGH_THR_M1 0x00A3U 115#define CMN_PLL0_DSM_DIAG_M1 0x00A4U 116#define CMN_PLL0_SS_CTRL1_M1 0x00A8U 117#define CMN_PLL0_SS_CTRL2_M1 0x00A9U 118#define CMN_PLL0_SS_CTRL3_M1 0x00AAU 119#define CMN_PLL0_SS_CTRL4_M1 0x00ABU 120#define CMN_PLL1_VCOCAL_TCTRL 0x00C2U 121#define CMN_PLL1_VCOCAL_INIT_TMR 0x00C4U 122#define CMN_PLL1_VCOCAL_ITER_TMR 0x00C5U 123#define CMN_PLL1_VCOCAL_REFTIM_START 0x00C6U 124#define CMN_PLL1_VCOCAL_PLLCNT_START 0x00C8U 125#define CMN_PLL1_INTDIV_M0 0x00D0U 126#define CMN_PLL1_FRACDIVL_M0 0x00D1U 127#define CMN_PLL1_FRACDIVH_M0 0x00D2U 128#define CMN_PLL1_HIGH_THR_M0 0x00D3U 129#define CMN_PLL1_DSM_DIAG_M0 0x00D4U 130#define CMN_PLL1_DSM_FBH_OVRD_M0 0x00D5U 131#define CMN_PLL1_DSM_FBL_OVRD_M0 0x00D6U 132#define CMN_PLL1_SS_CTRL1_M0 0x00D8U 133#define CMN_PLL1_SS_CTRL2_M0 0x00D9U 134#define CMN_PLL1_SS_CTRL3_M0 0x00DAU 135#define CMN_PLL1_SS_CTRL4_M0 0x00DBU 136#define CMN_PLL1_LOCK_REFCNT_START 0x00DCU 137#define CMN_PLL1_LOCK_PLLCNT_START 0x00DEU 138#define CMN_PLL1_LOCK_PLLCNT_THR 0x00DFU 139#define CMN_TXPUCAL_TUNE 0x0103U 140#define CMN_TXPUCAL_INIT_TMR 0x0104U 141#define CMN_TXPUCAL_ITER_TMR 0x0105U 142#define CMN_TXPDCAL_TUNE 0x010BU 143#define CMN_TXPDCAL_INIT_TMR 0x010CU 144#define CMN_TXPDCAL_ITER_TMR 0x010DU 145#define CMN_RXCAL_INIT_TMR 0x0114U 146#define CMN_RXCAL_ITER_TMR 0x0115U 147#define CMN_SD_CAL_INIT_TMR 0x0124U 148#define CMN_SD_CAL_ITER_TMR 0x0125U 149#define CMN_SD_CAL_REFTIM_START 0x0126U 150#define CMN_SD_CAL_PLLCNT_START 0x0128U 151#define CMN_PDIAG_PLL0_CTRL_M0 0x01A0U 152#define CMN_PDIAG_PLL0_CLK_SEL_M0 0x01A1U 153#define CMN_PDIAG_PLL0_CP_PADJ_M0 0x01A4U 154#define CMN_PDIAG_PLL0_CP_IADJ_M0 0x01A5U 155#define CMN_PDIAG_PLL0_FILT_PADJ_M0 0x01A6U 156#define CMN_PDIAG_PLL0_CTRL_M1 0x01B0U 157#define CMN_PDIAG_PLL0_CLK_SEL_M1 0x01B1U 158#define CMN_PDIAG_PLL0_CP_PADJ_M1 0x01B4U 159#define CMN_PDIAG_PLL0_CP_IADJ_M1 0x01B5U 160#define CMN_PDIAG_PLL0_FILT_PADJ_M1 0x01B6U 161#define CMN_PDIAG_PLL1_CTRL_M0 0x01C0U 162#define CMN_PDIAG_PLL1_CLK_SEL_M0 0x01C1U 163#define CMN_PDIAG_PLL1_CP_PADJ_M0 0x01C4U 164#define CMN_PDIAG_PLL1_CP_IADJ_M0 0x01C5U 165#define CMN_PDIAG_PLL1_FILT_PADJ_M0 0x01C6U 166#define CMN_DIAG_BIAS_OVRD1 0x01E1U 167 168/* PMA TX Lane registers */ 169#define TX_TXCC_CTRL 0x0040U 170#define TX_TXCC_CPOST_MULT_00 0x004CU 171#define TX_TXCC_CPOST_MULT_01 0x004DU 172#define TX_TXCC_MGNFS_MULT_000 0x0050U 173#define TX_TXCC_MGNFS_MULT_100 0x0054U 174#define DRV_DIAG_TX_DRV 0x00C6U 175#define XCVR_DIAG_PLLDRC_CTRL 0x00E5U 176#define XCVR_DIAG_HSCLK_SEL 0x00E6U 177#define XCVR_DIAG_HSCLK_DIV 0x00E7U 178#define XCVR_DIAG_RXCLK_CTRL 0x00E9U 179#define XCVR_DIAG_BIDI_CTRL 0x00EAU 180#define XCVR_DIAG_PSC_OVRD 0x00EBU 181#define TX_PSC_A0 0x0100U 182#define TX_PSC_A1 0x0101U 183#define TX_PSC_A2 0x0102U 184#define TX_PSC_A3 0x0103U 185#define TX_RCVDET_ST_TMR 0x0123U 186#define TX_DIAG_ACYA 0x01E7U 187#define TX_DIAG_ACYA_HBDC_MASK 0x0001U 188 189/* PMA RX Lane registers */ 190#define RX_PSC_A0 0x0000U 191#define RX_PSC_A1 0x0001U 192#define RX_PSC_A2 0x0002U 193#define RX_PSC_A3 0x0003U 194#define RX_PSC_CAL 0x0006U 195#define RX_SDCAL0_INIT_TMR 0x0044U 196#define RX_SDCAL0_ITER_TMR 0x0045U 197#define RX_SDCAL1_INIT_TMR 0x004CU 198#define RX_SDCAL1_ITER_TMR 0x004DU 199#define RX_CDRLF_CNFG 0x0080U 200#define RX_CDRLF_CNFG2 0x0081U 201#define RX_CDRLF_CNFG3 0x0082U 202#define RX_SIGDET_HL_FILT_TMR 0x0090U 203#define RX_REE_GCSM1_CTRL 0x0108U 204#define RX_REE_GCSM1_EQENM_PH1 0x0109U 205#define RX_REE_GCSM1_EQENM_PH2 0x010AU 206#define RX_REE_GCSM2_CTRL 0x0110U 207#define RX_REE_PERGCSM_CTRL 0x0118U 208#define RX_REE_PEAK_UTHR 0x0142U 209#define RX_REE_PEAK_LTHR 0x0143U 210#define RX_REE_ATTEN_THR 0x0149U 211#define RX_REE_TAP1_CLIP 0x0171U 212#define RX_REE_TAP2TON_CLIP 0x0172U 213#define RX_REE_SMGM_CTRL1 0x0177U 214#define RX_REE_SMGM_CTRL2 0x0178U 215#define RX_DIAG_DFE_CTRL 0x01E0U 216#define RX_DIAG_DFE_AMP_TUNE_2 0x01E2U 217#define RX_DIAG_DFE_AMP_TUNE_3 0x01E3U 218#define RX_DIAG_REE_DAC_CTRL 0x01E4U 219#define RX_DIAG_NQST_CTRL 0x01E5U 220#define RX_DIAG_SIGDET_TUNE 0x01E8U 221#define RX_DIAG_PI_RATE 0x01F4U 222#define RX_DIAG_PI_CAP 0x01F5U 223#define RX_DIAG_ACYA 0x01FFU 224 225/* PHY PCS common registers */ 226#define PHY_PIPE_CMN_CTRL1 0x0000U 227#define PHY_PLL_CFG 0x000EU 228#define PHY_PIPE_USB3_GEN2_PRE_CFG0 0x0020U 229#define PHY_PIPE_USB3_GEN2_POST_CFG0 0x0022U 230#define PHY_PIPE_USB3_GEN2_POST_CFG1 0x0023U 231 232/* PHY PCS lane registers */ 233#define PHY_PCS_ISO_LINK_CTRL 0x000BU 234 235/* PHY PMA common registers */ 236#define PHY_PMA_CMN_CTRL1 0x0000U 237#define PHY_PMA_CMN_CTRL2 0x0001U 238#define PHY_PMA_PLL_RAW_CTRL 0x0003U 239 240#define CDNS_TORRENT_OUTPUT_CLOCKS 3 241 242static const char * const clk_names[] = { 243 [CDNS_TORRENT_REFCLK_DRIVER] = "refclk-driver", 244 [CDNS_TORRENT_DERIVED_REFCLK] = "refclk-der", 245 [CDNS_TORRENT_RECEIVED_REFCLK] = "refclk-rec", 246}; 247 248static const struct reg_field phy_pll_cfg = 249 REG_FIELD(PHY_PLL_CFG, 0, 1); 250 251static const struct reg_field phy_pma_cmn_ctrl_1 = 252 REG_FIELD(PHY_PMA_CMN_CTRL1, 0, 0); 253 254static const struct reg_field phy_pma_cmn_ctrl_2 = 255 REG_FIELD(PHY_PMA_CMN_CTRL2, 0, 7); 256 257static const struct reg_field phy_pma_pll_raw_ctrl = 258 REG_FIELD(PHY_PMA_PLL_RAW_CTRL, 0, 1); 259 260static const struct reg_field phy_reset_ctrl = 261 REG_FIELD(PHY_RESET, 8, 8); 262 263static const struct reg_field phy_pcs_iso_link_ctrl_1 = 264 REG_FIELD(PHY_PCS_ISO_LINK_CTRL, 1, 1); 265 266static const struct reg_field phy_pipe_cmn_ctrl1_0 = REG_FIELD(PHY_PIPE_CMN_CTRL1, 0, 0); 267 268static const struct reg_field cmn_cdiag_refclk_ovrd_4 = 269 REG_FIELD(CMN_CDIAG_REFCLK_OVRD, 4, 4); 270 271#define REFCLK_OUT_NUM_CMN_CONFIG 4 272 273enum cdns_torrent_refclk_out_cmn { 274 CMN_CDIAG_REFCLK_DRV0_CTRL_1, 275 CMN_CDIAG_REFCLK_DRV0_CTRL_4, 276 CMN_CDIAG_REFCLK_DRV0_CTRL_5, 277 CMN_CDIAG_REFCLK_DRV0_CTRL_6, 278}; 279 280static const struct reg_field refclk_out_cmn_cfg[] = { 281 [CMN_CDIAG_REFCLK_DRV0_CTRL_1] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 1, 1), 282 [CMN_CDIAG_REFCLK_DRV0_CTRL_4] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 4, 4), 283 [CMN_CDIAG_REFCLK_DRV0_CTRL_5] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 5, 5), 284 [CMN_CDIAG_REFCLK_DRV0_CTRL_6] = REG_FIELD(CMN_CDIAG_REFCLK_DRV0_CTRL, 6, 6), 285}; 286 287static const int refclk_driver_parent_index[] = { 288 CDNS_TORRENT_DERIVED_REFCLK, 289 CDNS_TORRENT_RECEIVED_REFCLK 290}; 291 292static const u32 cdns_torrent_refclk_driver_mux_table[] = { 1, 0 }; 293 294enum cdns_torrent_phy_type { 295 TYPE_NONE, 296 TYPE_DP, 297 TYPE_PCIE, 298 TYPE_SGMII, 299 TYPE_QSGMII, 300 TYPE_USB, 301 TYPE_USXGMII, 302 TYPE_PCIE_ML, 303}; 304 305enum cdns_torrent_ref_clk { 306 CLK_19_2_MHZ, 307 CLK_25_MHZ, 308 CLK_100_MHZ, 309 CLK_156_25_MHZ, 310 CLK_ANY, 311}; 312 313enum cdns_torrent_ssc_mode { 314 NO_SSC, 315 EXTERNAL_SSC, 316 INTERNAL_SSC, 317 ANY_SSC, 318}; 319 320/* Unique key id for vals table entry 321 * REFCLK0_RATE | REFCLK1_RATE | LINK0_TYPE | LINK1_TYPE | SSC_TYPE 322 */ 323#define REFCLK0_SHIFT 12 324#define REFCLK0_MASK GENMASK(14, 12) 325#define REFCLK1_SHIFT 9 326#define REFCLK1_MASK GENMASK(11, 9) 327#define LINK0_SHIFT 6 328#define LINK0_MASK GENMASK(8, 6) 329#define LINK1_SHIFT 3 330#define LINK1_MASK GENMASK(5, 3) 331#define SSC_SHIFT 0 332#define SSC_MASK GENMASK(2, 0) 333 334#define CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc) \ 335 ((((refclk0) << REFCLK0_SHIFT) & REFCLK0_MASK) | \ 336 (((refclk1) << REFCLK1_SHIFT) & REFCLK1_MASK) | \ 337 (((link0) << LINK0_SHIFT) & LINK0_MASK) | \ 338 (((link1) << LINK1_SHIFT) & LINK1_MASK) | \ 339 (((ssc) << SSC_SHIFT) & SSC_MASK)) 340 341#define CDNS_TORRENT_KEY_ANYCLK(link0, link1) \ 342 CDNS_TORRENT_KEY(CLK_ANY, CLK_ANY, \ 343 (link0), (link1), ANY_SSC) 344 345struct cdns_torrent_inst { 346 struct phy *phy; 347 u32 mlane; 348 enum cdns_torrent_phy_type phy_type; 349 u32 num_lanes; 350 struct reset_control *lnk_rst; 351 enum cdns_torrent_ssc_mode ssc_mode; 352}; 353 354struct cdns_torrent_phy { 355 void __iomem *base; /* DPTX registers base */ 356 void __iomem *sd_base; /* SD0801 registers base */ 357 u32 max_bit_rate; /* Maximum link bit rate to use (in Mbps) */ 358 u32 dp_pll; 359 u32 protocol_bitmask; 360 struct reset_control *phy_rst; 361 struct reset_control *apb_rst; 362 struct device *dev; 363 struct clk *clk; 364 struct clk *clk1; 365 enum cdns_torrent_ref_clk ref_clk_rate; 366 enum cdns_torrent_ref_clk ref_clk1_rate; 367 struct cdns_torrent_inst phys[MAX_NUM_LANES]; 368 int nsubnodes; 369 int already_configured; 370 const struct cdns_torrent_data *init_data; 371 struct regmap *regmap_common_cdb; 372 struct regmap *regmap_phy_pcs_common_cdb; 373 struct regmap *regmap_phy_pma_common_cdb; 374 struct regmap *regmap_tx_lane_cdb[MAX_NUM_LANES]; 375 struct regmap *regmap_rx_lane_cdb[MAX_NUM_LANES]; 376 struct regmap *regmap_phy_pcs_lane_cdb[MAX_NUM_LANES]; 377 struct regmap *regmap_dptx_phy_reg; 378 struct regmap_field *phy_pll_cfg; 379 struct regmap_field *phy_pipe_cmn_ctrl1_0; 380 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 381 struct regmap_field *phy_pma_cmn_ctrl_1; 382 struct regmap_field *phy_pma_cmn_ctrl_2; 383 struct regmap_field *phy_pma_pll_raw_ctrl; 384 struct regmap_field *phy_reset_ctrl; 385 struct regmap_field *phy_pcs_iso_link_ctrl_1[MAX_NUM_LANES]; 386 struct clk_hw_onecell_data *clk_hw_data; 387}; 388 389enum phy_powerstate { 390 POWERSTATE_A0 = 0, 391 /* Powerstate A1 is unused */ 392 POWERSTATE_A2 = 2, 393 POWERSTATE_A3 = 3, 394}; 395 396struct cdns_torrent_refclk_driver { 397 struct clk_hw hw; 398 struct regmap_field *cmn_fields[REFCLK_OUT_NUM_CMN_CONFIG]; 399 struct clk_init_data clk_data; 400 u8 parent_index; 401}; 402 403#define to_cdns_torrent_refclk_driver(_hw) \ 404 container_of(_hw, struct cdns_torrent_refclk_driver, hw) 405 406struct cdns_torrent_derived_refclk { 407 struct clk_hw hw; 408 struct regmap_field *phy_pipe_cmn_ctrl1_0; 409 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 410 struct clk_init_data clk_data; 411}; 412 413#define to_cdns_torrent_derived_refclk(_hw) \ 414 container_of(_hw, struct cdns_torrent_derived_refclk, hw) 415 416struct cdns_torrent_received_refclk { 417 struct clk_hw hw; 418 struct regmap_field *phy_pipe_cmn_ctrl1_0; 419 struct regmap_field *cmn_cdiag_refclk_ovrd_4; 420 struct clk_init_data clk_data; 421}; 422 423#define to_cdns_torrent_received_refclk(_hw) \ 424 container_of(_hw, struct cdns_torrent_received_refclk, hw) 425 426struct cdns_reg_pairs { 427 u32 val; 428 u32 off; 429}; 430 431struct cdns_torrent_vals { 432 const struct cdns_reg_pairs *reg_pairs; 433 u32 num_regs; 434}; 435 436struct cdns_torrent_vals_entry { 437 u32 key; 438 const struct cdns_torrent_vals *vals; 439}; 440 441struct cdns_torrent_vals_table { 442 const struct cdns_torrent_vals_entry *entries; 443 u32 num_entries; 444}; 445 446struct cdns_torrent_data { 447 u8 block_offset_shift; 448 u8 reg_offset_shift; 449 struct cdns_torrent_vals_table link_cmn_vals_tbl; 450 struct cdns_torrent_vals_table xcvr_diag_vals_tbl; 451 struct cdns_torrent_vals_table pcs_cmn_vals_tbl; 452 struct cdns_torrent_vals_table phy_pma_cmn_vals_tbl; 453 struct cdns_torrent_vals_table cmn_vals_tbl; 454 struct cdns_torrent_vals_table tx_ln_vals_tbl; 455 struct cdns_torrent_vals_table rx_ln_vals_tbl; 456}; 457 458struct cdns_regmap_cdb_context { 459 struct device *dev; 460 void __iomem *base; 461 u8 reg_offset_shift; 462}; 463 464static const struct cdns_torrent_vals *cdns_torrent_get_tbl_vals(const struct cdns_torrent_vals_table *tbl, 465 enum cdns_torrent_ref_clk refclk0, 466 enum cdns_torrent_ref_clk refclk1, 467 enum cdns_torrent_phy_type link0, 468 enum cdns_torrent_phy_type link1, 469 enum cdns_torrent_ssc_mode ssc) 470{ 471 int i; 472 u32 key = CDNS_TORRENT_KEY(refclk0, refclk1, link0, link1, ssc); 473 474 for (i = 0; i < tbl->num_entries; i++) { 475 if (tbl->entries[i].key == key) 476 return tbl->entries[i].vals; 477 } 478 479 return NULL; 480} 481 482static int cdns_regmap_write(void *context, unsigned int reg, unsigned int val) 483{ 484 struct cdns_regmap_cdb_context *ctx = context; 485 u32 offset = reg << ctx->reg_offset_shift; 486 487 writew(val, ctx->base + offset); 488 489 return 0; 490} 491 492static int cdns_regmap_read(void *context, unsigned int reg, unsigned int *val) 493{ 494 struct cdns_regmap_cdb_context *ctx = context; 495 u32 offset = reg << ctx->reg_offset_shift; 496 497 *val = readw(ctx->base + offset); 498 return 0; 499} 500 501static int cdns_regmap_dptx_write(void *context, unsigned int reg, 502 unsigned int val) 503{ 504 struct cdns_regmap_cdb_context *ctx = context; 505 u32 offset = reg; 506 507 writel(val, ctx->base + offset); 508 509 return 0; 510} 511 512static int cdns_regmap_dptx_read(void *context, unsigned int reg, 513 unsigned int *val) 514{ 515 struct cdns_regmap_cdb_context *ctx = context; 516 u32 offset = reg; 517 518 *val = readl(ctx->base + offset); 519 return 0; 520} 521 522#define TORRENT_TX_LANE_CDB_REGMAP_CONF(n) \ 523{ \ 524 .name = "torrent_tx_lane" n "_cdb", \ 525 .reg_stride = 1, \ 526 .fast_io = true, \ 527 .reg_write = cdns_regmap_write, \ 528 .reg_read = cdns_regmap_read, \ 529} 530 531#define TORRENT_RX_LANE_CDB_REGMAP_CONF(n) \ 532{ \ 533 .name = "torrent_rx_lane" n "_cdb", \ 534 .reg_stride = 1, \ 535 .fast_io = true, \ 536 .reg_write = cdns_regmap_write, \ 537 .reg_read = cdns_regmap_read, \ 538} 539 540static const struct regmap_config cdns_torrent_tx_lane_cdb_config[] = { 541 TORRENT_TX_LANE_CDB_REGMAP_CONF("0"), 542 TORRENT_TX_LANE_CDB_REGMAP_CONF("1"), 543 TORRENT_TX_LANE_CDB_REGMAP_CONF("2"), 544 TORRENT_TX_LANE_CDB_REGMAP_CONF("3"), 545}; 546 547static const struct regmap_config cdns_torrent_rx_lane_cdb_config[] = { 548 TORRENT_RX_LANE_CDB_REGMAP_CONF("0"), 549 TORRENT_RX_LANE_CDB_REGMAP_CONF("1"), 550 TORRENT_RX_LANE_CDB_REGMAP_CONF("2"), 551 TORRENT_RX_LANE_CDB_REGMAP_CONF("3"), 552}; 553 554static const struct regmap_config cdns_torrent_common_cdb_config = { 555 .name = "torrent_common_cdb", 556 .reg_stride = 1, 557 .fast_io = true, 558 .reg_write = cdns_regmap_write, 559 .reg_read = cdns_regmap_read, 560}; 561 562#define TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF(n) \ 563{ \ 564 .name = "torrent_phy_pcs_lane" n "_cdb", \ 565 .reg_stride = 1, \ 566 .fast_io = true, \ 567 .reg_write = cdns_regmap_write, \ 568 .reg_read = cdns_regmap_read, \ 569} 570 571static const struct regmap_config cdns_torrent_phy_pcs_lane_cdb_config[] = { 572 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("0"), 573 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("1"), 574 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("2"), 575 TORRENT_PHY_PCS_LANE_CDB_REGMAP_CONF("3"), 576}; 577 578static const struct regmap_config cdns_torrent_phy_pcs_cmn_cdb_config = { 579 .name = "torrent_phy_pcs_cmn_cdb", 580 .reg_stride = 1, 581 .fast_io = true, 582 .reg_write = cdns_regmap_write, 583 .reg_read = cdns_regmap_read, 584}; 585 586static const struct regmap_config cdns_torrent_phy_pma_cmn_cdb_config = { 587 .name = "torrent_phy_pma_cmn_cdb", 588 .reg_stride = 1, 589 .fast_io = true, 590 .reg_write = cdns_regmap_write, 591 .reg_read = cdns_regmap_read, 592}; 593 594static const struct regmap_config cdns_torrent_dptx_phy_config = { 595 .name = "torrent_dptx_phy", 596 .reg_stride = 1, 597 .fast_io = true, 598 .reg_write = cdns_regmap_dptx_write, 599 .reg_read = cdns_regmap_dptx_read, 600}; 601 602/* PHY mmr access functions */ 603 604static void cdns_torrent_phy_write(struct regmap *regmap, u32 offset, u32 val) 605{ 606 regmap_write(regmap, offset, val); 607} 608 609static u32 cdns_torrent_phy_read(struct regmap *regmap, u32 offset) 610{ 611 unsigned int val; 612 613 regmap_read(regmap, offset, &val); 614 return val; 615} 616 617/* DPTX mmr access functions */ 618 619static void cdns_torrent_dp_write(struct regmap *regmap, u32 offset, u32 val) 620{ 621 regmap_write(regmap, offset, val); 622} 623 624static u32 cdns_torrent_dp_read(struct regmap *regmap, u32 offset) 625{ 626 u32 val; 627 628 regmap_read(regmap, offset, &val); 629 return val; 630} 631 632/* 633 * Structure used to store values of PHY registers for voltage-related 634 * coefficients, for particular voltage swing and pre-emphasis level. Values 635 * are shared across all physical lanes. 636 */ 637struct coefficients { 638 /* Value of DRV_DIAG_TX_DRV register to use */ 639 u16 diag_tx_drv; 640 /* Value of TX_TXCC_MGNFS_MULT_000 register to use */ 641 u16 mgnfs_mult; 642 /* Value of TX_TXCC_CPOST_MULT_00 register to use */ 643 u16 cpost_mult; 644}; 645 646/* 647 * Array consists of values of voltage-related registers for sd0801 PHY. A value 648 * of 0xFFFF is a placeholder for invalid combination, and will never be used. 649 */ 650static const struct coefficients vltg_coeff[4][4] = { 651 /* voltage swing 0, pre-emphasis 0->3 */ 652 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x002A, 653 .cpost_mult = 0x0000}, 654 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 655 .cpost_mult = 0x0014}, 656 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0012, 657 .cpost_mult = 0x0020}, 658 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 659 .cpost_mult = 0x002A} 660 }, 661 662 /* voltage swing 1, pre-emphasis 0->3 */ 663 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x001F, 664 .cpost_mult = 0x0000}, 665 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 666 .cpost_mult = 0x0012}, 667 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 668 .cpost_mult = 0x001F}, 669 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 670 .cpost_mult = 0xFFFF} 671 }, 672 673 /* voltage swing 2, pre-emphasis 0->3 */ 674 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0013, 675 .cpost_mult = 0x0000}, 676 {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 677 .cpost_mult = 0x0013}, 678 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 679 .cpost_mult = 0xFFFF}, 680 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 681 .cpost_mult = 0xFFFF} 682 }, 683 684 /* voltage swing 3, pre-emphasis 0->3 */ 685 { {.diag_tx_drv = 0x0003, .mgnfs_mult = 0x0000, 686 .cpost_mult = 0x0000}, 687 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 688 .cpost_mult = 0xFFFF}, 689 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 690 .cpost_mult = 0xFFFF}, 691 {.diag_tx_drv = 0xFFFF, .mgnfs_mult = 0xFFFF, 692 .cpost_mult = 0xFFFF} 693 } 694}; 695 696static const char *cdns_torrent_get_phy_type(enum cdns_torrent_phy_type phy_type) 697{ 698 switch (phy_type) { 699 case TYPE_DP: 700 return "DisplayPort"; 701 case TYPE_PCIE: 702 case TYPE_PCIE_ML: 703 return "PCIe"; 704 case TYPE_SGMII: 705 return "SGMII"; 706 case TYPE_QSGMII: 707 return "QSGMII"; 708 case TYPE_USB: 709 return "USB"; 710 case TYPE_USXGMII: 711 return "USXGMII"; 712 default: 713 return "None"; 714 } 715} 716 717/* 718 * Set registers responsible for enabling and configuring SSC, with second and 719 * third register values provided by parameters. 720 */ 721static 722void cdns_torrent_dp_enable_ssc_19_2mhz(struct cdns_torrent_phy *cdns_phy, 723 u32 ctrl2_val, u32 ctrl3_val) 724{ 725 struct regmap *regmap = cdns_phy->regmap_common_cdb; 726 727 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 728 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 729 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl3_val); 730 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 731 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 732 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 733 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl3_val); 734 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 735} 736 737static 738void cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(struct cdns_torrent_phy *cdns_phy, 739 u32 rate, bool ssc) 740{ 741 struct regmap *regmap = cdns_phy->regmap_common_cdb; 742 743 /* Assumes 19.2 MHz refclock */ 744 switch (rate) { 745 /* Setting VCO for 10.8GHz */ 746 case 2700: 747 case 5400: 748 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0119); 749 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 750 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 751 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00BC); 752 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0012); 753 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0119); 754 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 755 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 756 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00BC); 757 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0012); 758 if (ssc) 759 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x033A, 0x006A); 760 break; 761 /* Setting VCO for 9.72GHz */ 762 case 1620: 763 case 2430: 764 case 3240: 765 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01FA); 766 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x4000); 767 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 768 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0152); 769 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 770 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01FA); 771 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x4000); 772 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 773 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0152); 774 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 775 if (ssc) 776 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x05DD, 0x0069); 777 break; 778 /* Setting VCO for 8.64GHz */ 779 case 2160: 780 case 4320: 781 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01C2); 782 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 783 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 784 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x012C); 785 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 786 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01C2); 787 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 788 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 789 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x012C); 790 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 791 if (ssc) 792 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x0536, 0x0069); 793 break; 794 /* Setting VCO for 8.1GHz */ 795 case 8100: 796 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01A5); 797 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xE000); 798 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 799 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x011A); 800 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 801 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01A5); 802 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xE000); 803 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 804 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x011A); 805 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 806 if (ssc) 807 cdns_torrent_dp_enable_ssc_19_2mhz(cdns_phy, 0x04D7, 0x006A); 808 break; 809 } 810 811 if (ssc) { 812 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x025E); 813 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 814 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x025E); 815 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 816 } else { 817 cdns_torrent_phy_write(regmap, CMN_PLL0_VCOCAL_PLLCNT_START, 0x0260); 818 cdns_torrent_phy_write(regmap, CMN_PLL1_VCOCAL_PLLCNT_START, 0x0260); 819 /* Set reset register values to disable SSC */ 820 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 821 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 822 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 823 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 824 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 825 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 826 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 827 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 828 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 829 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 830 } 831 832 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x0099); 833 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x0099); 834 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x0099); 835 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x0099); 836} 837 838/* 839 * Set registers responsible for enabling and configuring SSC, with second 840 * register value provided by a parameter. 841 */ 842static void cdns_torrent_dp_enable_ssc_25mhz(struct cdns_torrent_phy *cdns_phy, 843 u32 ctrl2_val) 844{ 845 struct regmap *regmap = cdns_phy->regmap_common_cdb; 846 847 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0001); 848 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, ctrl2_val); 849 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x007F); 850 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0003); 851 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0001); 852 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, ctrl2_val); 853 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x007F); 854 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0003); 855} 856 857static 858void cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(struct cdns_torrent_phy *cdns_phy, 859 u32 rate, bool ssc) 860{ 861 struct regmap *regmap = cdns_phy->regmap_common_cdb; 862 863 /* Assumes 25 MHz refclock */ 864 switch (rate) { 865 /* Setting VCO for 10.8GHz */ 866 case 2700: 867 case 5400: 868 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x01B0); 869 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 870 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 871 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0120); 872 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x01B0); 873 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 874 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 875 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0120); 876 if (ssc) 877 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x0423); 878 break; 879 /* Setting VCO for 9.72GHz */ 880 case 1620: 881 case 2430: 882 case 3240: 883 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0184); 884 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0xCCCD); 885 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 886 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0104); 887 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0184); 888 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0xCCCD); 889 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 890 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0104); 891 if (ssc) 892 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x03B9); 893 break; 894 /* Setting VCO for 8.64GHz */ 895 case 2160: 896 case 4320: 897 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0159); 898 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x999A); 899 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 900 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00E7); 901 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0159); 902 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x999A); 903 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 904 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00E7); 905 if (ssc) 906 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x034F); 907 break; 908 /* Setting VCO for 8.1GHz */ 909 case 8100: 910 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0144); 911 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x0000); 912 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 913 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x00D8); 914 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0144); 915 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x0000); 916 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 917 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x00D8); 918 if (ssc) 919 cdns_torrent_dp_enable_ssc_25mhz(cdns_phy, 0x031A); 920 break; 921 } 922 923 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 924 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 925 926 if (ssc) { 927 cdns_torrent_phy_write(regmap, 928 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0315); 929 cdns_torrent_phy_write(regmap, 930 CMN_PLL0_LOCK_PLLCNT_THR, 0x0005); 931 cdns_torrent_phy_write(regmap, 932 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0315); 933 cdns_torrent_phy_write(regmap, 934 CMN_PLL1_LOCK_PLLCNT_THR, 0x0005); 935 } else { 936 cdns_torrent_phy_write(regmap, 937 CMN_PLL0_VCOCAL_PLLCNT_START, 0x0317); 938 cdns_torrent_phy_write(regmap, 939 CMN_PLL1_VCOCAL_PLLCNT_START, 0x0317); 940 /* Set reset register values to disable SSC */ 941 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL1_M0, 0x0002); 942 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL2_M0, 0x0000); 943 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL3_M0, 0x0000); 944 cdns_torrent_phy_write(regmap, CMN_PLL0_SS_CTRL4_M0, 0x0000); 945 cdns_torrent_phy_write(regmap, 946 CMN_PLL0_LOCK_PLLCNT_THR, 0x0003); 947 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL1_M0, 0x0002); 948 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL2_M0, 0x0000); 949 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL3_M0, 0x0000); 950 cdns_torrent_phy_write(regmap, CMN_PLL1_SS_CTRL4_M0, 0x0000); 951 cdns_torrent_phy_write(regmap, 952 CMN_PLL1_LOCK_PLLCNT_THR, 0x0003); 953 } 954 955 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_REFCNT_START, 0x00C7); 956 cdns_torrent_phy_write(regmap, CMN_PLL0_LOCK_PLLCNT_START, 0x00C7); 957 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_REFCNT_START, 0x00C7); 958 cdns_torrent_phy_write(regmap, CMN_PLL1_LOCK_PLLCNT_START, 0x00C7); 959} 960 961static 962void cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(struct cdns_torrent_phy *cdns_phy, 963 u32 rate, bool ssc) 964{ 965 struct regmap *regmap = cdns_phy->regmap_common_cdb; 966 967 /* Assumes 100 MHz refclock */ 968 switch (rate) { 969 /* Setting VCO for 10.8GHz */ 970 case 2700: 971 case 5400: 972 if (cdns_phy->dp_pll & DP_PLL0) 973 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_FBH_OVRD_M0, 0x0022); 974 975 if (cdns_phy->dp_pll & DP_PLL1) { 976 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0028); 977 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBH_OVRD_M0, 0x0022); 978 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_FBL_OVRD_M0, 0x000C); 979 } 980 break; 981 /* Setting VCO for 9.72GHz */ 982 case 1620: 983 case 2430: 984 case 3240: 985 if (cdns_phy->dp_pll & DP_PLL0) { 986 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 987 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 988 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 989 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 990 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0061); 991 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x3333); 992 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 993 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0042); 994 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 995 } 996 if (cdns_phy->dp_pll & DP_PLL1) { 997 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 998 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 999 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 1000 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 1001 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0061); 1002 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x3333); 1003 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1004 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0042); 1005 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1006 } 1007 break; 1008 /* Setting VCO for 8.64GHz */ 1009 case 2160: 1010 case 4320: 1011 if (cdns_phy->dp_pll & DP_PLL0) { 1012 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 1013 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 1014 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 1015 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 1016 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0056); 1017 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVL_M0, 0x6666); 1018 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1019 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x003A); 1020 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1021 } 1022 if (cdns_phy->dp_pll & DP_PLL1) { 1023 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 1024 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 1025 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 1026 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 1027 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0056); 1028 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVL_M0, 0x6666); 1029 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1030 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x003A); 1031 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1032 } 1033 break; 1034 /* Setting VCO for 8.1GHz */ 1035 case 8100: 1036 if (cdns_phy->dp_pll & DP_PLL0) { 1037 cdns_torrent_phy_write(regmap, CMN_PLL0_DSM_DIAG_M0, 0x0004); 1038 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_PADJ_M0, 0x0509); 1039 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CP_IADJ_M0, 0x0F00); 1040 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_FILT_PADJ_M0, 0x0F08); 1041 cdns_torrent_phy_write(regmap, CMN_PLL0_INTDIV_M0, 0x0051); 1042 cdns_torrent_phy_write(regmap, CMN_PLL0_FRACDIVH_M0, 0x0002); 1043 cdns_torrent_phy_write(regmap, CMN_PLL0_HIGH_THR_M0, 0x0036); 1044 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL0_CTRL_M0, 0x0002); 1045 } 1046 if (cdns_phy->dp_pll & DP_PLL1) { 1047 cdns_torrent_phy_write(regmap, CMN_PLL1_DSM_DIAG_M0, 0x0004); 1048 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_PADJ_M0, 0x0509); 1049 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CP_IADJ_M0, 0x0F00); 1050 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_FILT_PADJ_M0, 0x0F08); 1051 cdns_torrent_phy_write(regmap, CMN_PLL1_INTDIV_M0, 0x0051); 1052 cdns_torrent_phy_write(regmap, CMN_PLL1_FRACDIVH_M0, 0x0002); 1053 cdns_torrent_phy_write(regmap, CMN_PLL1_HIGH_THR_M0, 0x0036); 1054 cdns_torrent_phy_write(regmap, CMN_PDIAG_PLL1_CTRL_M0, 0x0002); 1055 } 1056 break; 1057 } 1058} 1059 1060/* Set PLL used for DP configuration */ 1061static int cdns_torrent_dp_get_pll(struct cdns_torrent_phy *cdns_phy, 1062 enum cdns_torrent_phy_type phy_t2) 1063{ 1064 switch (phy_t2) { 1065 case TYPE_PCIE: 1066 case TYPE_USB: 1067 cdns_phy->dp_pll = DP_PLL1; 1068 break; 1069 case TYPE_SGMII: 1070 case TYPE_QSGMII: 1071 cdns_phy->dp_pll = DP_PLL0; 1072 break; 1073 case TYPE_NONE: 1074 cdns_phy->dp_pll = DP_PLL0 | DP_PLL1; 1075 break; 1076 default: 1077 dev_err(cdns_phy->dev, "Unsupported PHY configuration\n"); 1078 return -EINVAL; 1079 } 1080 1081 return 0; 1082} 1083 1084/* 1085 * Enable or disable PLL for selected lanes. 1086 */ 1087static int cdns_torrent_dp_set_pll_en(struct cdns_torrent_phy *cdns_phy, 1088 struct cdns_torrent_inst *inst, 1089 struct phy_configure_opts_dp *dp, 1090 bool enable) 1091{ 1092 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1093 u32 rd_val, pll_ack_val; 1094 int ret; 1095 1096 /* 1097 * Used to determine, which bits to check for or enable in 1098 * PHY_PMA_XCVR_PLLCLK_EN register. 1099 */ 1100 u32 pll_bits; 1101 /* Used to enable or disable lanes. */ 1102 u32 pll_val; 1103 1104 /* Select values of registers and mask, depending on enabled lane count. */ 1105 pll_val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN); 1106 1107 if (enable) { 1108 pll_bits = ((1 << dp->lanes) - 1); 1109 pll_val |= pll_bits; 1110 pll_ack_val = pll_bits; 1111 } else { 1112 pll_bits = ((1 << inst->num_lanes) - 1); 1113 pll_val &= (~pll_bits); 1114 pll_ack_val = 0; 1115 } 1116 1117 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_val); 1118 1119 /* Wait for acknowledgment from PHY. */ 1120 ret = regmap_read_poll_timeout(regmap, 1121 PHY_PMA_XCVR_PLLCLK_EN_ACK, 1122 rd_val, 1123 (rd_val & pll_bits) == pll_ack_val, 1124 0, POLL_TIMEOUT_US); 1125 ndelay(100); 1126 return ret; 1127} 1128 1129static int cdns_torrent_dp_set_power_state(struct cdns_torrent_phy *cdns_phy, 1130 struct cdns_torrent_inst *inst, 1131 u32 num_lanes, 1132 enum phy_powerstate powerstate) 1133{ 1134 /* Register value for power state for a single byte. */ 1135 u32 value_part, i; 1136 u32 value = 0; 1137 u32 mask = 0; 1138 u32 read_val; 1139 int ret; 1140 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1141 1142 switch (powerstate) { 1143 case (POWERSTATE_A0): 1144 value_part = 0x01U; 1145 break; 1146 case (POWERSTATE_A2): 1147 value_part = 0x04U; 1148 break; 1149 default: 1150 /* Powerstate A3 */ 1151 value_part = 0x08U; 1152 break; 1153 } 1154 1155 /* Select values of registers and mask, depending on enabled lane count. */ 1156 1157 for (i = 0; i < num_lanes; i++) { 1158 value |= (value_part << PHY_POWER_STATE_LN(i)); 1159 mask |= (PMA_XCVR_POWER_STATE_REQ_LN_MASK << PHY_POWER_STATE_LN(i)); 1160 } 1161 1162 /* Set power state A<n>. */ 1163 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, value); 1164 /* Wait, until PHY acknowledges power state completion. */ 1165 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_POWER_STATE_ACK, 1166 read_val, (read_val & mask) == value, 0, 1167 POLL_TIMEOUT_US); 1168 if (ret) 1169 return ret; 1170 1171 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, 0x00000000); 1172 ndelay(100); 1173 1174 return ret; 1175} 1176 1177static int cdns_torrent_dp_run(struct cdns_torrent_phy *cdns_phy, 1178 struct cdns_torrent_inst *inst, u32 num_lanes) 1179{ 1180 unsigned int read_val; 1181 int ret; 1182 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1183 1184 /* 1185 * waiting for ACK of pma_xcvr_pllclk_en_ln_*, only for the 1186 * master lane 1187 */ 1188 ret = regmap_read_poll_timeout(regmap, PHY_PMA_XCVR_PLLCLK_EN_ACK, 1189 read_val, read_val & 1, 1190 0, POLL_TIMEOUT_US); 1191 if (ret == -ETIMEDOUT) { 1192 dev_err(cdns_phy->dev, 1193 "timeout waiting for link PLL clock enable ack\n"); 1194 return ret; 1195 } 1196 1197 ndelay(100); 1198 1199 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, 1200 POWERSTATE_A2); 1201 if (ret) 1202 return ret; 1203 1204 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, num_lanes, 1205 POWERSTATE_A0); 1206 1207 return ret; 1208} 1209 1210static int cdns_torrent_dp_wait_pma_cmn_ready(struct cdns_torrent_phy *cdns_phy) 1211{ 1212 unsigned int reg; 1213 int ret; 1214 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1215 1216 ret = regmap_read_poll_timeout(regmap, PHY_PMA_CMN_READY, reg, 1217 reg & 1, 0, POLL_TIMEOUT_US); 1218 if (ret == -ETIMEDOUT) { 1219 dev_err(cdns_phy->dev, 1220 "timeout waiting for PMA common ready\n"); 1221 return -ETIMEDOUT; 1222 } 1223 1224 return 0; 1225} 1226 1227static void cdns_torrent_dp_pma_cmn_rate(struct cdns_torrent_phy *cdns_phy, 1228 struct cdns_torrent_inst *inst, 1229 u32 rate, u32 num_lanes) 1230{ 1231 unsigned int clk_sel_val = 0; 1232 unsigned int hsclk_div_val = 0; 1233 unsigned int i; 1234 1235 switch (rate) { 1236 case 1620: 1237 clk_sel_val = 0x0f01; 1238 hsclk_div_val = 2; 1239 break; 1240 case 2160: 1241 case 2430: 1242 case 2700: 1243 clk_sel_val = 0x0701; 1244 hsclk_div_val = 1; 1245 break; 1246 case 3240: 1247 clk_sel_val = 0x0b00; 1248 hsclk_div_val = 2; 1249 break; 1250 case 4320: 1251 case 5400: 1252 clk_sel_val = 0x0301; 1253 hsclk_div_val = 0; 1254 break; 1255 case 8100: 1256 clk_sel_val = 0x0200; 1257 hsclk_div_val = 0; 1258 break; 1259 } 1260 1261 if (cdns_phy->dp_pll & DP_PLL0) 1262 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1263 CMN_PDIAG_PLL0_CLK_SEL_M0, clk_sel_val); 1264 1265 if (cdns_phy->dp_pll & DP_PLL1) 1266 cdns_torrent_phy_write(cdns_phy->regmap_common_cdb, 1267 CMN_PDIAG_PLL1_CLK_SEL_M0, clk_sel_val); 1268 1269 /* PMA lane configuration to deal with multi-link operation */ 1270 for (i = 0; i < num_lanes; i++) 1271 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + i], 1272 XCVR_DIAG_HSCLK_DIV, hsclk_div_val); 1273} 1274 1275/* 1276 * Perform register operations related to setting link rate, once powerstate is 1277 * set and PLL disable request was processed. 1278 */ 1279static int cdns_torrent_dp_configure_rate(struct cdns_torrent_phy *cdns_phy, 1280 struct cdns_torrent_inst *inst, 1281 struct phy_configure_opts_dp *dp) 1282{ 1283 u32 read_val, field_val; 1284 int ret; 1285 1286 /* 1287 * Disable the associated PLL (cmn_pll0_en or cmn_pll1_en) before 1288 * re-programming the new data rate. 1289 */ 1290 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); 1291 if (ret) 1292 return ret; 1293 field_val &= ~(cdns_phy->dp_pll); 1294 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); 1295 1296 /* 1297 * Wait for PLL ready de-assertion. 1298 * For PLL0 - PHY_PMA_CMN_CTRL2[2] == 1 1299 * For PLL1 - PHY_PMA_CMN_CTRL2[3] == 1 1300 */ 1301 if (cdns_phy->dp_pll & DP_PLL0) { 1302 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1303 read_val, 1304 ((read_val >> 2) & 0x01) != 0, 1305 0, POLL_TIMEOUT_US); 1306 if (ret) 1307 return ret; 1308 } 1309 1310 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) { 1311 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1312 read_val, 1313 ((read_val >> 3) & 0x01) != 0, 1314 0, POLL_TIMEOUT_US); 1315 if (ret) 1316 return ret; 1317 } 1318 ndelay(200); 1319 1320 /* DP Rate Change - VCO Output settings. */ 1321 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1322 /* PMA common configuration 19.2MHz */ 1323 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, dp->link_rate, dp->ssc); 1324 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1325 /* PMA common configuration 25MHz */ 1326 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, dp->link_rate, dp->ssc); 1327 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1328 /* PMA common configuration 100MHz */ 1329 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, dp->link_rate, dp->ssc); 1330 1331 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, dp->link_rate, dp->lanes); 1332 1333 /* Enable the associated PLL (cmn_pll0_en or cmn_pll1_en) */ 1334 ret = regmap_field_read(cdns_phy->phy_pma_pll_raw_ctrl, &field_val); 1335 if (ret) 1336 return ret; 1337 field_val |= cdns_phy->dp_pll; 1338 regmap_field_write(cdns_phy->phy_pma_pll_raw_ctrl, field_val); 1339 1340 /* 1341 * Wait for PLL ready assertion. 1342 * For PLL0 - PHY_PMA_CMN_CTRL2[0] == 1 1343 * For PLL1 - PHY_PMA_CMN_CTRL2[1] == 1 1344 */ 1345 if (cdns_phy->dp_pll & DP_PLL0) { 1346 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1347 read_val, 1348 (read_val & 0x01) != 0, 1349 0, POLL_TIMEOUT_US); 1350 if (ret) 1351 return ret; 1352 } 1353 1354 if ((cdns_phy->dp_pll & DP_PLL1) && cdns_phy->nsubnodes != 1) 1355 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_2, 1356 read_val, 1357 ((read_val >> 1) & 0x01) != 0, 1358 0, POLL_TIMEOUT_US); 1359 1360 return ret; 1361} 1362 1363/* 1364 * Verify, that parameters to configure PHY with are correct. 1365 */ 1366static int cdns_torrent_dp_verify_config(struct cdns_torrent_inst *inst, 1367 struct phy_configure_opts_dp *dp) 1368{ 1369 u8 i; 1370 1371 /* If changing link rate was required, verify it's supported. */ 1372 if (dp->set_rate) { 1373 switch (dp->link_rate) { 1374 case 1620: 1375 case 2160: 1376 case 2430: 1377 case 2700: 1378 case 3240: 1379 case 4320: 1380 case 5400: 1381 case 8100: 1382 /* valid bit rate */ 1383 break; 1384 default: 1385 return -EINVAL; 1386 } 1387 } 1388 1389 /* Verify lane count. */ 1390 switch (dp->lanes) { 1391 case 1: 1392 case 2: 1393 case 4: 1394 /* valid lane count. */ 1395 break; 1396 default: 1397 return -EINVAL; 1398 } 1399 1400 /* Check against actual number of PHY's lanes. */ 1401 if (dp->lanes > inst->num_lanes) 1402 return -EINVAL; 1403 1404 /* 1405 * If changing voltages is required, check swing and pre-emphasis 1406 * levels, per-lane. 1407 */ 1408 if (dp->set_voltages) { 1409 /* Lane count verified previously. */ 1410 for (i = 0; i < dp->lanes; i++) { 1411 if (dp->voltage[i] > 3 || dp->pre[i] > 3) 1412 return -EINVAL; 1413 1414 /* Sum of voltage swing and pre-emphasis levels cannot 1415 * exceed 3. 1416 */ 1417 if (dp->voltage[i] + dp->pre[i] > 3) 1418 return -EINVAL; 1419 } 1420 } 1421 1422 return 0; 1423} 1424 1425/* Set power state A0 and PLL clock enable to 0 on enabled lanes. */ 1426static void cdns_torrent_dp_set_a0_pll(struct cdns_torrent_phy *cdns_phy, 1427 struct cdns_torrent_inst *inst, 1428 u32 num_lanes) 1429{ 1430 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1431 u32 pwr_state = cdns_torrent_dp_read(regmap, 1432 PHY_PMA_XCVR_POWER_STATE_REQ); 1433 u32 pll_clk_en = cdns_torrent_dp_read(regmap, 1434 PHY_PMA_XCVR_PLLCLK_EN); 1435 u32 i; 1436 1437 for (i = 0; i < num_lanes; i++) { 1438 pwr_state &= ~(PMA_XCVR_POWER_STATE_REQ_LN_MASK 1439 << PHY_POWER_STATE_LN(inst->mlane + i)); 1440 1441 pll_clk_en &= ~(0x01U << (inst->mlane + i)); 1442 } 1443 1444 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_POWER_STATE_REQ, pwr_state); 1445 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, pll_clk_en); 1446} 1447 1448/* Configure lane count as required. */ 1449static int cdns_torrent_dp_set_lanes(struct cdns_torrent_phy *cdns_phy, 1450 struct cdns_torrent_inst *inst, 1451 struct phy_configure_opts_dp *dp) 1452{ 1453 u32 value, i; 1454 int ret; 1455 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1456 u8 lane_mask = (1 << dp->lanes) - 1; 1457 u8 pma_tx_elec_idle_mask = 0; 1458 u32 clane = inst->mlane; 1459 1460 lane_mask <<= clane; 1461 1462 value = cdns_torrent_dp_read(regmap, PHY_RESET); 1463 /* clear pma_tx_elec_idle_ln_* bits. */ 1464 pma_tx_elec_idle_mask = ((1 << inst->num_lanes) - 1) << clane; 1465 1466 pma_tx_elec_idle_mask <<= PMA_TX_ELEC_IDLE_SHIFT; 1467 1468 value &= ~pma_tx_elec_idle_mask; 1469 1470 /* Assert pma_tx_elec_idle_ln_* for disabled lanes. */ 1471 value |= ((~lane_mask) << PMA_TX_ELEC_IDLE_SHIFT) & 1472 pma_tx_elec_idle_mask; 1473 1474 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1475 1476 /* reset the link by asserting master lane phy_l0*_reset_n low */ 1477 cdns_torrent_dp_write(regmap, PHY_RESET, 1478 value & (~(1 << clane))); 1479 1480 /* 1481 * Assert lane reset on unused lanes and master lane so they remain in reset 1482 * and powered down when re-enabling the link 1483 */ 1484 for (i = 0; i < inst->num_lanes; i++) 1485 value &= (~(1 << (clane + i))); 1486 1487 for (i = 1; i < inst->num_lanes; i++) 1488 value |= ((1 << (clane + i)) & lane_mask); 1489 1490 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1491 1492 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, dp->lanes); 1493 1494 /* release phy_l0*_reset_n based on used laneCount */ 1495 for (i = 0; i < inst->num_lanes; i++) 1496 value &= (~(1 << (clane + i))); 1497 1498 for (i = 0; i < inst->num_lanes; i++) 1499 value |= ((1 << (clane + i)) & lane_mask); 1500 1501 cdns_torrent_dp_write(regmap, PHY_RESET, value); 1502 1503 /* Wait, until PHY gets ready after releasing PHY reset signal. */ 1504 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1505 if (ret) 1506 return ret; 1507 1508 ndelay(100); 1509 1510 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1511 value = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN); 1512 value |= (1 << clane); 1513 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, value); 1514 1515 ret = cdns_torrent_dp_run(cdns_phy, inst, dp->lanes); 1516 1517 return ret; 1518} 1519 1520/* Configure link rate as required. */ 1521static int cdns_torrent_dp_set_rate(struct cdns_torrent_phy *cdns_phy, 1522 struct cdns_torrent_inst *inst, 1523 struct phy_configure_opts_dp *dp) 1524{ 1525 int ret; 1526 1527 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes, 1528 POWERSTATE_A3); 1529 if (ret) 1530 return ret; 1531 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, false); 1532 if (ret) 1533 return ret; 1534 ndelay(200); 1535 1536 ret = cdns_torrent_dp_configure_rate(cdns_phy, inst, dp); 1537 if (ret) 1538 return ret; 1539 ndelay(200); 1540 1541 ret = cdns_torrent_dp_set_pll_en(cdns_phy, inst, dp, true); 1542 if (ret) 1543 return ret; 1544 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes, 1545 POWERSTATE_A2); 1546 if (ret) 1547 return ret; 1548 ret = cdns_torrent_dp_set_power_state(cdns_phy, inst, dp->lanes, 1549 POWERSTATE_A0); 1550 if (ret) 1551 return ret; 1552 ndelay(900); 1553 1554 return ret; 1555} 1556 1557/* Configure voltage swing and pre-emphasis for all enabled lanes. */ 1558static void cdns_torrent_dp_set_voltages(struct cdns_torrent_phy *cdns_phy, 1559 struct cdns_torrent_inst *inst, 1560 struct phy_configure_opts_dp *dp) 1561{ 1562 u8 lane; 1563 u16 val; 1564 1565 for (lane = 0; lane < dp->lanes; lane++) { 1566 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1567 TX_DIAG_ACYA); 1568 /* 1569 * Write 1 to register bit TX_DIAG_ACYA[0] to freeze the 1570 * current state of the analog TX driver. 1571 */ 1572 val |= TX_DIAG_ACYA_HBDC_MASK; 1573 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1574 TX_DIAG_ACYA, val); 1575 1576 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1577 TX_TXCC_CTRL, 0x08A4); 1578 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].diag_tx_drv; 1579 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1580 DRV_DIAG_TX_DRV, val); 1581 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].mgnfs_mult; 1582 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1583 TX_TXCC_MGNFS_MULT_000, 1584 val); 1585 val = vltg_coeff[dp->voltage[lane]][dp->pre[lane]].cpost_mult; 1586 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1587 TX_TXCC_CPOST_MULT_00, 1588 val); 1589 1590 val = cdns_torrent_phy_read(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1591 TX_DIAG_ACYA); 1592 /* 1593 * Write 0 to register bit TX_DIAG_ACYA[0] to allow the state of 1594 * analog TX driver to reflect the new programmed one. 1595 */ 1596 val &= ~TX_DIAG_ACYA_HBDC_MASK; 1597 cdns_torrent_phy_write(cdns_phy->regmap_tx_lane_cdb[inst->mlane + lane], 1598 TX_DIAG_ACYA, val); 1599 } 1600}; 1601 1602static int cdns_torrent_dp_configure(struct phy *phy, 1603 union phy_configure_opts *opts) 1604{ 1605 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1606 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1607 int ret; 1608 1609 if (cdns_phy->already_configured) 1610 return 0; 1611 1612 ret = cdns_torrent_dp_verify_config(inst, &opts->dp); 1613 if (ret) { 1614 dev_err(&phy->dev, "invalid params for phy configure\n"); 1615 return ret; 1616 } 1617 1618 if (opts->dp.set_lanes) { 1619 ret = cdns_torrent_dp_set_lanes(cdns_phy, inst, &opts->dp); 1620 if (ret) { 1621 dev_err(&phy->dev, "cdns_torrent_dp_set_lanes failed\n"); 1622 return ret; 1623 } 1624 } 1625 1626 if (opts->dp.set_rate) { 1627 ret = cdns_torrent_dp_set_rate(cdns_phy, inst, &opts->dp); 1628 if (ret) { 1629 dev_err(&phy->dev, "cdns_torrent_dp_set_rate failed\n"); 1630 return ret; 1631 } 1632 } 1633 1634 if (opts->dp.set_voltages) 1635 cdns_torrent_dp_set_voltages(cdns_phy, inst, &opts->dp); 1636 1637 return ret; 1638} 1639 1640static int cdns_torrent_phy_on(struct phy *phy) 1641{ 1642 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1643 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1644 u32 read_val; 1645 int ret; 1646 1647 if (cdns_phy->already_configured) { 1648 /* Give 5ms to 10ms delay for the PIPE clock to be stable */ 1649 usleep_range(5000, 10000); 1650 return 0; 1651 } 1652 1653 if (cdns_phy->nsubnodes == 1) { 1654 /* Take the PHY lane group out of reset */ 1655 reset_control_deassert(inst->lnk_rst); 1656 1657 /* Take the PHY out of reset */ 1658 ret = reset_control_deassert(cdns_phy->phy_rst); 1659 if (ret) 1660 return ret; 1661 } 1662 1663 /* 1664 * Wait for cmn_ready assertion 1665 * PHY_PMA_CMN_CTRL1[0] == 1 1666 */ 1667 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pma_cmn_ctrl_1, 1668 read_val, read_val, 1000, 1669 PLL_LOCK_TIMEOUT); 1670 if (ret) { 1671 dev_err(cdns_phy->dev, "Timeout waiting for CMN ready\n"); 1672 return ret; 1673 } 1674 1675 if (inst->phy_type == TYPE_PCIE || inst->phy_type == TYPE_USB) { 1676 ret = regmap_field_read_poll_timeout(cdns_phy->phy_pcs_iso_link_ctrl_1[inst->mlane], 1677 read_val, !read_val, 1000, 1678 PLL_LOCK_TIMEOUT); 1679 if (ret == -ETIMEDOUT) { 1680 dev_err(cdns_phy->dev, "Timeout waiting for PHY status ready\n"); 1681 return ret; 1682 } 1683 } 1684 1685 return 0; 1686} 1687 1688static int cdns_torrent_phy_off(struct phy *phy) 1689{ 1690 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1691 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1692 int ret; 1693 1694 if (cdns_phy->nsubnodes != 1) 1695 return 0; 1696 1697 ret = reset_control_assert(cdns_phy->phy_rst); 1698 if (ret) 1699 return ret; 1700 1701 return reset_control_assert(inst->lnk_rst); 1702} 1703 1704static void cdns_torrent_dp_common_init(struct cdns_torrent_phy *cdns_phy, 1705 struct cdns_torrent_inst *inst) 1706{ 1707 struct regmap *regmap = cdns_phy->regmap_dptx_phy_reg; 1708 unsigned char lane_bits; 1709 u32 val; 1710 1711 cdns_torrent_dp_write(regmap, PHY_AUX_CTRL, 0x0003); /* enable AUX */ 1712 1713 /* 1714 * Set lines power state to A0 1715 * Set lines pll clk enable to 0 1716 */ 1717 cdns_torrent_dp_set_a0_pll(cdns_phy, inst, inst->num_lanes); 1718 1719 /* 1720 * release phy_l0*_reset_n and pma_tx_elec_idle_ln_* based on 1721 * used lanes 1722 */ 1723 lane_bits = (1 << inst->num_lanes) - 1; 1724 1725 val = cdns_torrent_dp_read(regmap, PHY_RESET); 1726 val |= (0xF & lane_bits); 1727 val &= ~(lane_bits << 4); 1728 cdns_torrent_dp_write(regmap, PHY_RESET, val); 1729 1730 /* release pma_xcvr_pllclk_en_ln_*, only for the master lane */ 1731 val = cdns_torrent_dp_read(regmap, PHY_PMA_XCVR_PLLCLK_EN); 1732 val |= 1; 1733 cdns_torrent_dp_write(regmap, PHY_PMA_XCVR_PLLCLK_EN, val); 1734 1735 /* 1736 * PHY PMA registers configuration functions 1737 * Initialize PHY with max supported link rate, without SSC. 1738 */ 1739 if (cdns_phy->ref_clk_rate == CLK_19_2_MHZ) 1740 cdns_torrent_dp_pma_cmn_vco_cfg_19_2mhz(cdns_phy, 1741 cdns_phy->max_bit_rate, 1742 false); 1743 else if (cdns_phy->ref_clk_rate == CLK_25_MHZ) 1744 cdns_torrent_dp_pma_cmn_vco_cfg_25mhz(cdns_phy, 1745 cdns_phy->max_bit_rate, 1746 false); 1747 else if (cdns_phy->ref_clk_rate == CLK_100_MHZ) 1748 cdns_torrent_dp_pma_cmn_vco_cfg_100mhz(cdns_phy, 1749 cdns_phy->max_bit_rate, 1750 false); 1751 1752 cdns_torrent_dp_pma_cmn_rate(cdns_phy, inst, cdns_phy->max_bit_rate, 1753 inst->num_lanes); 1754 1755 /* take out of reset */ 1756 regmap_field_write(cdns_phy->phy_reset_ctrl, 0x1); 1757} 1758 1759static int cdns_torrent_dp_start(struct cdns_torrent_phy *cdns_phy, 1760 struct cdns_torrent_inst *inst, 1761 struct phy *phy) 1762{ 1763 int ret; 1764 1765 ret = cdns_torrent_phy_on(phy); 1766 if (ret) 1767 return ret; 1768 1769 ret = cdns_torrent_dp_wait_pma_cmn_ready(cdns_phy); 1770 if (ret) 1771 return ret; 1772 1773 ret = cdns_torrent_dp_run(cdns_phy, inst, inst->num_lanes); 1774 1775 return ret; 1776} 1777 1778static int cdns_torrent_dp_init(struct phy *phy) 1779{ 1780 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 1781 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 1782 int ret; 1783 1784 switch (cdns_phy->ref_clk_rate) { 1785 case CLK_19_2_MHZ: 1786 case CLK_25_MHZ: 1787 case CLK_100_MHZ: 1788 /* Valid Ref Clock Rate */ 1789 break; 1790 default: 1791 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 1792 return -EINVAL; 1793 } 1794 1795 ret = cdns_torrent_dp_get_pll(cdns_phy, TYPE_NONE); 1796 if (ret) 1797 return ret; 1798 1799 cdns_torrent_dp_common_init(cdns_phy, inst); 1800 1801 return cdns_torrent_dp_start(cdns_phy, inst, phy); 1802} 1803 1804static int cdns_torrent_dp_multilink_init(struct cdns_torrent_phy *cdns_phy, 1805 struct cdns_torrent_inst *inst, 1806 struct phy *phy) 1807{ 1808 if (cdns_phy->ref_clk_rate != CLK_100_MHZ) { 1809 dev_err(cdns_phy->dev, "Unsupported Ref Clock Rate\n"); 1810 return -EINVAL; 1811 } 1812 1813 cdns_torrent_dp_common_init(cdns_phy, inst); 1814 1815 return cdns_torrent_dp_start(cdns_phy, inst, phy); 1816} 1817 1818static int cdns_torrent_derived_refclk_enable(struct clk_hw *hw) 1819{ 1820 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1821 1822 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 1); 1823 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 1); 1824 1825 return 0; 1826} 1827 1828static void cdns_torrent_derived_refclk_disable(struct clk_hw *hw) 1829{ 1830 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1831 1832 regmap_field_write(derived_refclk->phy_pipe_cmn_ctrl1_0, 0); 1833 regmap_field_write(derived_refclk->cmn_cdiag_refclk_ovrd_4, 0); 1834} 1835 1836static int cdns_torrent_derived_refclk_is_enabled(struct clk_hw *hw) 1837{ 1838 struct cdns_torrent_derived_refclk *derived_refclk = to_cdns_torrent_derived_refclk(hw); 1839 int val; 1840 1841 regmap_field_read(derived_refclk->cmn_cdiag_refclk_ovrd_4, &val); 1842 1843 return !!val; 1844} 1845 1846static const struct clk_ops cdns_torrent_derived_refclk_ops = { 1847 .enable = cdns_torrent_derived_refclk_enable, 1848 .disable = cdns_torrent_derived_refclk_disable, 1849 .is_enabled = cdns_torrent_derived_refclk_is_enabled, 1850}; 1851 1852static int cdns_torrent_derived_refclk_register(struct cdns_torrent_phy *cdns_phy) 1853{ 1854 struct cdns_torrent_derived_refclk *derived_refclk; 1855 struct device *dev = cdns_phy->dev; 1856 struct clk_init_data *init; 1857 const char *parent_name; 1858 char clk_name[100]; 1859 struct clk_hw *hw; 1860 struct clk *clk; 1861 int ret; 1862 1863 derived_refclk = devm_kzalloc(dev, sizeof(*derived_refclk), GFP_KERNEL); 1864 if (!derived_refclk) 1865 return -ENOMEM; 1866 1867 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1868 clk_names[CDNS_TORRENT_DERIVED_REFCLK]); 1869 1870 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1871 if (IS_ERR(clk)) { 1872 dev_err(dev, "No parent clock for derived_refclk\n"); 1873 return PTR_ERR(clk); 1874 } 1875 1876 init = &derived_refclk->clk_data; 1877 1878 if (clk) { 1879 parent_name = __clk_get_name(clk); 1880 init->parent_names = &parent_name; 1881 init->num_parents = 1; 1882 } 1883 init->ops = &cdns_torrent_derived_refclk_ops; 1884 init->flags = 0; 1885 init->name = clk_name; 1886 1887 derived_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; 1888 derived_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; 1889 1890 derived_refclk->hw.init = init; 1891 1892 hw = &derived_refclk->hw; 1893 ret = devm_clk_hw_register(dev, hw); 1894 if (ret) 1895 return ret; 1896 1897 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_DERIVED_REFCLK] = hw; 1898 1899 return 0; 1900} 1901 1902static int cdns_torrent_received_refclk_enable(struct clk_hw *hw) 1903{ 1904 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1905 1906 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 1); 1907 1908 return 0; 1909} 1910 1911static void cdns_torrent_received_refclk_disable(struct clk_hw *hw) 1912{ 1913 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1914 1915 regmap_field_write(received_refclk->phy_pipe_cmn_ctrl1_0, 0); 1916} 1917 1918static int cdns_torrent_received_refclk_is_enabled(struct clk_hw *hw) 1919{ 1920 struct cdns_torrent_received_refclk *received_refclk = to_cdns_torrent_received_refclk(hw); 1921 int val, cmn_val; 1922 1923 regmap_field_read(received_refclk->phy_pipe_cmn_ctrl1_0, &val); 1924 regmap_field_read(received_refclk->cmn_cdiag_refclk_ovrd_4, &cmn_val); 1925 1926 return val && !cmn_val; 1927} 1928 1929static const struct clk_ops cdns_torrent_received_refclk_ops = { 1930 .enable = cdns_torrent_received_refclk_enable, 1931 .disable = cdns_torrent_received_refclk_disable, 1932 .is_enabled = cdns_torrent_received_refclk_is_enabled, 1933}; 1934 1935static int cdns_torrent_received_refclk_register(struct cdns_torrent_phy *cdns_phy) 1936{ 1937 struct cdns_torrent_received_refclk *received_refclk; 1938 struct device *dev = cdns_phy->dev; 1939 struct clk_init_data *init; 1940 const char *parent_name; 1941 char clk_name[100]; 1942 struct clk_hw *hw; 1943 struct clk *clk; 1944 int ret; 1945 1946 received_refclk = devm_kzalloc(dev, sizeof(*received_refclk), GFP_KERNEL); 1947 if (!received_refclk) 1948 return -ENOMEM; 1949 1950 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 1951 clk_names[CDNS_TORRENT_RECEIVED_REFCLK]); 1952 1953 clk = devm_clk_get_optional(dev, "phy_en_refclk"); 1954 if (IS_ERR(clk)) { 1955 dev_err(dev, "No parent clock for received_refclk\n"); 1956 return PTR_ERR(clk); 1957 } 1958 1959 init = &received_refclk->clk_data; 1960 1961 if (clk) { 1962 parent_name = __clk_get_name(clk); 1963 init->parent_names = &parent_name; 1964 init->num_parents = 1; 1965 } 1966 init->ops = &cdns_torrent_received_refclk_ops; 1967 init->flags = 0; 1968 init->name = clk_name; 1969 1970 received_refclk->phy_pipe_cmn_ctrl1_0 = cdns_phy->phy_pipe_cmn_ctrl1_0; 1971 received_refclk->cmn_cdiag_refclk_ovrd_4 = cdns_phy->cmn_cdiag_refclk_ovrd_4; 1972 1973 received_refclk->hw.init = init; 1974 1975 hw = &received_refclk->hw; 1976 ret = devm_clk_hw_register(dev, hw); 1977 if (ret) 1978 return ret; 1979 1980 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_RECEIVED_REFCLK] = hw; 1981 1982 return 0; 1983} 1984 1985static int cdns_torrent_refclk_driver_enable(struct clk_hw *hw) 1986{ 1987 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1988 1989 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_6], 0); 1990 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_5], 1); 1991 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 0); 1992 1993 return 0; 1994} 1995 1996static void cdns_torrent_refclk_driver_disable(struct clk_hw *hw) 1997{ 1998 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 1999 2000 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], 1); 2001} 2002 2003static int cdns_torrent_refclk_driver_is_enabled(struct clk_hw *hw) 2004{ 2005 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 2006 int val; 2007 2008 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_1], &val); 2009 2010 return !val; 2011} 2012 2013static u8 cdns_torrent_refclk_driver_get_parent(struct clk_hw *hw) 2014{ 2015 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 2016 unsigned int val; 2017 2018 regmap_field_read(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], &val); 2019 return clk_mux_val_to_index(hw, cdns_torrent_refclk_driver_mux_table, 0, val); 2020} 2021 2022static int cdns_torrent_refclk_driver_set_parent(struct clk_hw *hw, u8 index) 2023{ 2024 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 2025 unsigned int val; 2026 2027 val = cdns_torrent_refclk_driver_mux_table[index]; 2028 return regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], val); 2029} 2030 2031static const struct clk_ops cdns_torrent_refclk_driver_ops = { 2032 .enable = cdns_torrent_refclk_driver_enable, 2033 .disable = cdns_torrent_refclk_driver_disable, 2034 .is_enabled = cdns_torrent_refclk_driver_is_enabled, 2035 .determine_rate = __clk_mux_determine_rate, 2036 .set_parent = cdns_torrent_refclk_driver_set_parent, 2037 .get_parent = cdns_torrent_refclk_driver_get_parent, 2038}; 2039 2040static int cdns_torrent_refclk_driver_register(struct cdns_torrent_phy *cdns_phy) 2041{ 2042 struct cdns_torrent_refclk_driver *refclk_driver; 2043 struct device *dev = cdns_phy->dev; 2044 struct regmap_field *field; 2045 struct clk_init_data *init; 2046 const char **parent_names; 2047 unsigned int num_parents; 2048 struct regmap *regmap; 2049 char clk_name[100]; 2050 struct clk_hw *hw; 2051 int i, ret; 2052 2053 refclk_driver = devm_kzalloc(dev, sizeof(*refclk_driver), GFP_KERNEL); 2054 if (!refclk_driver) 2055 return -ENOMEM; 2056 2057 num_parents = ARRAY_SIZE(refclk_driver_parent_index); 2058 parent_names = devm_kzalloc(dev, (sizeof(char *) * num_parents), GFP_KERNEL); 2059 if (!parent_names) 2060 return -ENOMEM; 2061 2062 for (i = 0; i < num_parents; i++) { 2063 hw = cdns_phy->clk_hw_data->hws[refclk_driver_parent_index[i]]; 2064 if (IS_ERR_OR_NULL(hw)) { 2065 dev_err(dev, "No parent clock for refclk driver clock\n"); 2066 return IS_ERR(hw) ? PTR_ERR(hw) : -ENOENT; 2067 } 2068 parent_names[i] = clk_hw_get_name(hw); 2069 } 2070 2071 snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), 2072 clk_names[CDNS_TORRENT_REFCLK_DRIVER]); 2073 2074 init = &refclk_driver->clk_data; 2075 2076 init->ops = &cdns_torrent_refclk_driver_ops; 2077 init->flags = CLK_SET_RATE_NO_REPARENT; 2078 init->parent_names = parent_names; 2079 init->num_parents = num_parents; 2080 init->name = clk_name; 2081 2082 regmap = cdns_phy->regmap_common_cdb; 2083 2084 for (i = 0; i < REFCLK_OUT_NUM_CMN_CONFIG; i++) { 2085 field = devm_regmap_field_alloc(dev, regmap, refclk_out_cmn_cfg[i]); 2086 if (IS_ERR(field)) { 2087 dev_err(dev, "Refclk driver CMN reg field init failed\n"); 2088 return PTR_ERR(field); 2089 } 2090 refclk_driver->cmn_fields[i] = field; 2091 } 2092 2093 /* Enable Derived reference clock as default */ 2094 regmap_field_write(refclk_driver->cmn_fields[CMN_CDIAG_REFCLK_DRV0_CTRL_4], 1); 2095 2096 refclk_driver->hw.init = init; 2097 2098 hw = &refclk_driver->hw; 2099 ret = devm_clk_hw_register(dev, hw); 2100 if (ret) 2101 return ret; 2102 2103 cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER] = hw; 2104 2105 return 0; 2106} 2107 2108static struct regmap *cdns_regmap_init(struct device *dev, void __iomem *base, 2109 u32 block_offset, 2110 u8 reg_offset_shift, 2111 const struct regmap_config *config) 2112{ 2113 struct cdns_regmap_cdb_context *ctx; 2114 2115 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 2116 if (!ctx) 2117 return ERR_PTR(-ENOMEM); 2118 2119 ctx->dev = dev; 2120 ctx->base = base + block_offset; 2121 ctx->reg_offset_shift = reg_offset_shift; 2122 2123 return devm_regmap_init(dev, NULL, ctx, config); 2124} 2125 2126static int cdns_torrent_dp_regfield_init(struct cdns_torrent_phy *cdns_phy) 2127{ 2128 struct device *dev = cdns_phy->dev; 2129 struct regmap_field *field; 2130 struct regmap *regmap; 2131 2132 regmap = cdns_phy->regmap_dptx_phy_reg; 2133 field = devm_regmap_field_alloc(dev, regmap, phy_reset_ctrl); 2134 if (IS_ERR(field)) { 2135 dev_err(dev, "PHY_RESET reg field init failed\n"); 2136 return PTR_ERR(field); 2137 } 2138 cdns_phy->phy_reset_ctrl = field; 2139 2140 return 0; 2141} 2142 2143static int cdns_torrent_regfield_init(struct cdns_torrent_phy *cdns_phy) 2144{ 2145 struct device *dev = cdns_phy->dev; 2146 struct regmap_field *field; 2147 struct regmap *regmap; 2148 int i; 2149 2150 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2151 field = devm_regmap_field_alloc(dev, regmap, phy_pll_cfg); 2152 if (IS_ERR(field)) { 2153 dev_err(dev, "PHY_PLL_CFG reg field init failed\n"); 2154 return PTR_ERR(field); 2155 } 2156 cdns_phy->phy_pll_cfg = field; 2157 2158 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2159 field = devm_regmap_field_alloc(dev, regmap, phy_pipe_cmn_ctrl1_0); 2160 if (IS_ERR(field)) { 2161 dev_err(dev, "phy_pipe_cmn_ctrl1_0 reg field init failed\n"); 2162 return PTR_ERR(field); 2163 } 2164 cdns_phy->phy_pipe_cmn_ctrl1_0 = field; 2165 2166 regmap = cdns_phy->regmap_common_cdb; 2167 field = devm_regmap_field_alloc(dev, regmap, cmn_cdiag_refclk_ovrd_4); 2168 if (IS_ERR(field)) { 2169 dev_err(dev, "cmn_cdiag_refclk_ovrd_4 reg field init failed\n"); 2170 return PTR_ERR(field); 2171 } 2172 cdns_phy->cmn_cdiag_refclk_ovrd_4 = field; 2173 2174 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2175 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_1); 2176 if (IS_ERR(field)) { 2177 dev_err(dev, "PHY_PMA_CMN_CTRL1 reg field init failed\n"); 2178 return PTR_ERR(field); 2179 } 2180 cdns_phy->phy_pma_cmn_ctrl_1 = field; 2181 2182 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2183 field = devm_regmap_field_alloc(dev, regmap, phy_pma_cmn_ctrl_2); 2184 if (IS_ERR(field)) { 2185 dev_err(dev, "PHY_PMA_CMN_CTRL2 reg field init failed\n"); 2186 return PTR_ERR(field); 2187 } 2188 cdns_phy->phy_pma_cmn_ctrl_2 = field; 2189 2190 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2191 field = devm_regmap_field_alloc(dev, regmap, phy_pma_pll_raw_ctrl); 2192 if (IS_ERR(field)) { 2193 dev_err(dev, "PHY_PMA_PLL_RAW_CTRL reg field init failed\n"); 2194 return PTR_ERR(field); 2195 } 2196 cdns_phy->phy_pma_pll_raw_ctrl = field; 2197 2198 for (i = 0; i < MAX_NUM_LANES; i++) { 2199 regmap = cdns_phy->regmap_phy_pcs_lane_cdb[i]; 2200 field = devm_regmap_field_alloc(dev, regmap, phy_pcs_iso_link_ctrl_1); 2201 if (IS_ERR(field)) { 2202 dev_err(dev, "PHY_PCS_ISO_LINK_CTRL reg field init for ln %d failed\n", i); 2203 return PTR_ERR(field); 2204 } 2205 cdns_phy->phy_pcs_iso_link_ctrl_1[i] = field; 2206 } 2207 2208 return 0; 2209} 2210 2211static int cdns_torrent_dp_regmap_init(struct cdns_torrent_phy *cdns_phy) 2212{ 2213 void __iomem *base = cdns_phy->base; 2214 struct device *dev = cdns_phy->dev; 2215 struct regmap *regmap; 2216 u8 reg_offset_shift; 2217 u32 block_offset; 2218 2219 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 2220 2221 block_offset = TORRENT_DPTX_PHY_OFFSET; 2222 regmap = cdns_regmap_init(dev, base, block_offset, 2223 reg_offset_shift, 2224 &cdns_torrent_dptx_phy_config); 2225 if (IS_ERR(regmap)) { 2226 dev_err(dev, "Failed to init DPTX PHY regmap\n"); 2227 return PTR_ERR(regmap); 2228 } 2229 cdns_phy->regmap_dptx_phy_reg = regmap; 2230 2231 return 0; 2232} 2233 2234static int cdns_torrent_regmap_init(struct cdns_torrent_phy *cdns_phy) 2235{ 2236 void __iomem *sd_base = cdns_phy->sd_base; 2237 u8 block_offset_shift, reg_offset_shift; 2238 struct device *dev = cdns_phy->dev; 2239 struct regmap *regmap; 2240 u32 block_offset; 2241 int i; 2242 2243 block_offset_shift = cdns_phy->init_data->block_offset_shift; 2244 reg_offset_shift = cdns_phy->init_data->reg_offset_shift; 2245 2246 for (i = 0; i < MAX_NUM_LANES; i++) { 2247 block_offset = TORRENT_TX_LANE_CDB_OFFSET(i, block_offset_shift, 2248 reg_offset_shift); 2249 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2250 reg_offset_shift, 2251 &cdns_torrent_tx_lane_cdb_config[i]); 2252 if (IS_ERR(regmap)) { 2253 dev_err(dev, "Failed to init tx lane CDB regmap\n"); 2254 return PTR_ERR(regmap); 2255 } 2256 cdns_phy->regmap_tx_lane_cdb[i] = regmap; 2257 2258 block_offset = TORRENT_RX_LANE_CDB_OFFSET(i, block_offset_shift, 2259 reg_offset_shift); 2260 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2261 reg_offset_shift, 2262 &cdns_torrent_rx_lane_cdb_config[i]); 2263 if (IS_ERR(regmap)) { 2264 dev_err(dev, "Failed to init rx lane CDB regmap\n"); 2265 return PTR_ERR(regmap); 2266 } 2267 cdns_phy->regmap_rx_lane_cdb[i] = regmap; 2268 2269 block_offset = TORRENT_PHY_PCS_LANE_CDB_OFFSET(i, block_offset_shift, 2270 reg_offset_shift); 2271 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2272 reg_offset_shift, 2273 &cdns_torrent_phy_pcs_lane_cdb_config[i]); 2274 if (IS_ERR(regmap)) { 2275 dev_err(dev, "Failed to init PHY PCS lane CDB regmap\n"); 2276 return PTR_ERR(regmap); 2277 } 2278 cdns_phy->regmap_phy_pcs_lane_cdb[i] = regmap; 2279 } 2280 2281 block_offset = TORRENT_COMMON_CDB_OFFSET; 2282 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2283 reg_offset_shift, 2284 &cdns_torrent_common_cdb_config); 2285 if (IS_ERR(regmap)) { 2286 dev_err(dev, "Failed to init common CDB regmap\n"); 2287 return PTR_ERR(regmap); 2288 } 2289 cdns_phy->regmap_common_cdb = regmap; 2290 2291 block_offset = TORRENT_PHY_PCS_COMMON_OFFSET(block_offset_shift); 2292 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2293 reg_offset_shift, 2294 &cdns_torrent_phy_pcs_cmn_cdb_config); 2295 if (IS_ERR(regmap)) { 2296 dev_err(dev, "Failed to init PHY PCS common CDB regmap\n"); 2297 return PTR_ERR(regmap); 2298 } 2299 cdns_phy->regmap_phy_pcs_common_cdb = regmap; 2300 2301 block_offset = TORRENT_PHY_PMA_COMMON_OFFSET(block_offset_shift); 2302 regmap = cdns_regmap_init(dev, sd_base, block_offset, 2303 reg_offset_shift, 2304 &cdns_torrent_phy_pma_cmn_cdb_config); 2305 if (IS_ERR(regmap)) { 2306 dev_err(dev, "Failed to init PHY PMA common CDB regmap\n"); 2307 return PTR_ERR(regmap); 2308 } 2309 cdns_phy->regmap_phy_pma_common_cdb = regmap; 2310 2311 return 0; 2312} 2313 2314static int cdns_torrent_phy_init(struct phy *phy) 2315{ 2316 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(phy->dev.parent); 2317 const struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2318 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2319 const struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2320 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2321 struct cdns_torrent_inst *inst = phy_get_drvdata(phy); 2322 enum cdns_torrent_phy_type phy_type = inst->phy_type; 2323 const struct cdns_torrent_vals *phy_pma_cmn_vals; 2324 enum cdns_torrent_ssc_mode ssc = inst->ssc_mode; 2325 const struct cdns_torrent_vals *pcs_cmn_vals; 2326 const struct cdns_reg_pairs *reg_pairs; 2327 struct regmap *regmap; 2328 u32 num_regs; 2329 int i, j; 2330 2331 if (cdns_phy->already_configured) 2332 return 0; 2333 2334 if (cdns_phy->nsubnodes > 1) { 2335 if (phy_type == TYPE_DP) 2336 return cdns_torrent_dp_multilink_init(cdns_phy, inst, phy); 2337 return 0; 2338 } 2339 2340 /** 2341 * Spread spectrum generation is not required or supported 2342 * for SGMII/QSGMII/USXGMII 2343 */ 2344 if (phy_type == TYPE_SGMII || phy_type == TYPE_QSGMII || phy_type == TYPE_USXGMII) 2345 ssc = NO_SSC; 2346 2347 /* PHY configuration specific registers for single link */ 2348 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl, 2349 CLK_ANY, CLK_ANY, 2350 phy_type, TYPE_NONE, 2351 ANY_SSC); 2352 if (link_cmn_vals) { 2353 reg_pairs = link_cmn_vals->reg_pairs; 2354 num_regs = link_cmn_vals->num_regs; 2355 regmap = cdns_phy->regmap_common_cdb; 2356 2357 /** 2358 * First array value in link_cmn_vals must be of 2359 * PHY_PLL_CFG register 2360 */ 2361 regmap_field_write(cdns_phy->phy_pll_cfg, reg_pairs[0].val); 2362 2363 for (i = 1; i < num_regs; i++) 2364 regmap_write(regmap, reg_pairs[i].off, 2365 reg_pairs[i].val); 2366 } 2367 2368 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl, 2369 CLK_ANY, CLK_ANY, 2370 phy_type, TYPE_NONE, 2371 ANY_SSC); 2372 if (xcvr_diag_vals) { 2373 reg_pairs = xcvr_diag_vals->reg_pairs; 2374 num_regs = xcvr_diag_vals->num_regs; 2375 for (i = 0; i < inst->num_lanes; i++) { 2376 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 2377 for (j = 0; j < num_regs; j++) 2378 regmap_write(regmap, reg_pairs[j].off, 2379 reg_pairs[j].val); 2380 } 2381 } 2382 2383 /* PHY PCS common registers configurations */ 2384 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl, 2385 CLK_ANY, CLK_ANY, 2386 phy_type, TYPE_NONE, 2387 ANY_SSC); 2388 if (pcs_cmn_vals) { 2389 reg_pairs = pcs_cmn_vals->reg_pairs; 2390 num_regs = pcs_cmn_vals->num_regs; 2391 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2392 for (i = 0; i < num_regs; i++) 2393 regmap_write(regmap, reg_pairs[i].off, 2394 reg_pairs[i].val); 2395 } 2396 2397 /* PHY PMA common registers configurations */ 2398 phy_pma_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl, 2399 CLK_ANY, CLK_ANY, 2400 phy_type, TYPE_NONE, 2401 ANY_SSC); 2402 if (phy_pma_cmn_vals) { 2403 reg_pairs = phy_pma_cmn_vals->reg_pairs; 2404 num_regs = phy_pma_cmn_vals->num_regs; 2405 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2406 for (i = 0; i < num_regs; i++) 2407 regmap_write(regmap, reg_pairs[i].off, 2408 reg_pairs[i].val); 2409 } 2410 2411 /* PMA common registers configurations */ 2412 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl, 2413 ref_clk, ref_clk, 2414 phy_type, TYPE_NONE, 2415 ssc); 2416 if (cmn_vals) { 2417 reg_pairs = cmn_vals->reg_pairs; 2418 num_regs = cmn_vals->num_regs; 2419 regmap = cdns_phy->regmap_common_cdb; 2420 for (i = 0; i < num_regs; i++) 2421 regmap_write(regmap, reg_pairs[i].off, 2422 reg_pairs[i].val); 2423 } 2424 2425 /* PMA TX lane registers configurations */ 2426 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl, 2427 ref_clk, ref_clk, 2428 phy_type, TYPE_NONE, 2429 ssc); 2430 if (tx_ln_vals) { 2431 reg_pairs = tx_ln_vals->reg_pairs; 2432 num_regs = tx_ln_vals->num_regs; 2433 for (i = 0; i < inst->num_lanes; i++) { 2434 regmap = cdns_phy->regmap_tx_lane_cdb[i + inst->mlane]; 2435 for (j = 0; j < num_regs; j++) 2436 regmap_write(regmap, reg_pairs[j].off, 2437 reg_pairs[j].val); 2438 } 2439 } 2440 2441 /* PMA RX lane registers configurations */ 2442 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl, 2443 ref_clk, ref_clk, 2444 phy_type, TYPE_NONE, 2445 ssc); 2446 if (rx_ln_vals) { 2447 reg_pairs = rx_ln_vals->reg_pairs; 2448 num_regs = rx_ln_vals->num_regs; 2449 for (i = 0; i < inst->num_lanes; i++) { 2450 regmap = cdns_phy->regmap_rx_lane_cdb[i + inst->mlane]; 2451 for (j = 0; j < num_regs; j++) 2452 regmap_write(regmap, reg_pairs[j].off, 2453 reg_pairs[j].val); 2454 } 2455 } 2456 2457 if (phy_type == TYPE_DP) 2458 return cdns_torrent_dp_init(phy); 2459 2460 return 0; 2461} 2462 2463static const struct phy_ops cdns_torrent_phy_ops = { 2464 .init = cdns_torrent_phy_init, 2465 .configure = cdns_torrent_dp_configure, 2466 .power_on = cdns_torrent_phy_on, 2467 .power_off = cdns_torrent_phy_off, 2468 .owner = THIS_MODULE, 2469}; 2470 2471static 2472int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) 2473{ 2474 const struct cdns_torrent_vals *cmn_vals, *tx_ln_vals, *rx_ln_vals; 2475 const struct cdns_torrent_data *init_data = cdns_phy->init_data; 2476 const struct cdns_torrent_vals *link_cmn_vals, *xcvr_diag_vals; 2477 enum cdns_torrent_ref_clk ref_clk1 = cdns_phy->ref_clk1_rate; 2478 enum cdns_torrent_ref_clk ref_clk = cdns_phy->ref_clk_rate; 2479 const struct cdns_torrent_vals *phy_pma_cmn_vals; 2480 const struct cdns_torrent_vals *pcs_cmn_vals; 2481 enum cdns_torrent_phy_type phy_t1, phy_t2; 2482 const struct cdns_reg_pairs *reg_pairs; 2483 int i, j, node, mlane, num_lanes, ret; 2484 struct device *dev = cdns_phy->dev; 2485 enum cdns_torrent_ssc_mode ssc; 2486 struct regmap *regmap; 2487 u32 num_regs, num_protocols, protocol; 2488 u32 num_pcie_links = 0; 2489 2490 num_protocols = hweight32(cdns_phy->protocol_bitmask); 2491 /* Maximum 2 protocols are supported */ 2492 if (num_protocols > 2) { 2493 dev_err(dev, "at most 2 protocols are supported\n"); 2494 return -EINVAL; 2495 } 2496 2497 2498 /** 2499 * Get PHY types directly from subnodes if only 2 subnodes exist. 2500 * It is possible for phy_t1 to be the same as phy_t2 for special 2501 * configurations such as PCIe Multilink. 2502 */ 2503 if (cdns_phy->nsubnodes == 2) { 2504 phy_t1 = cdns_phy->phys[0].phy_type; 2505 phy_t2 = cdns_phy->phys[1].phy_type; 2506 } else { 2507 /** 2508 * Both PHY types / protocols should be unique. 2509 * If they are the same, it should be expressed with either 2510 * a) Single-Link (1 Sub-node) - handled via PHY APIs 2511 * OR 2512 * b) Double-Link (2 Sub-nodes) - handled above 2513 */ 2514 if (num_protocols != 2) { 2515 dev_err(dev, "incorrect representation of link\n"); 2516 return -EINVAL; 2517 } 2518 2519 phy_t1 = fns(cdns_phy->protocol_bitmask, 0); 2520 phy_t2 = fns(cdns_phy->protocol_bitmask, 1); 2521 2522 /* 2523 * PCIe Multilink configuration can be supported along with a 2524 * non-PCIe protocol. The existing limitation associated with 2525 * the standalone PCIe Multilink configuration still remains, 2526 * implying that there can be only two links (subnodes) of the 2527 * PHY type PCIe which constitute the PCIe Multilink. 2528 * 2529 * Such configurations are handled by introducing a new protocol 2530 * namely TYPE_PCIE_ML. Both of the PCIe links which have the 2531 * protocol as TYPE_PCIE shall be treated as though the protocol 2532 * corresponding to them is TYPE_PCIE_ML only for the sake of 2533 * configuring the SERDES. 2534 * 2535 * PCIe Multilink configuration can be identified by checking if 2536 * there are exactly two links with phy_type set to TYPE_PCIE. 2537 * phy_t1 and phy_t2 are modified in such cases to support the 2538 * PCIe Multilink configuration with a non-PCIe protocol. 2539 */ 2540 for (node = 0; node < cdns_phy->nsubnodes; node++) { 2541 if (cdns_phy->phys[node].phy_type == TYPE_PCIE) 2542 num_pcie_links++; 2543 } 2544 2545 if (num_pcie_links > 2) { 2546 dev_err(dev, "cannot support PCIe Multilink with %u PCIe links\n", 2547 num_pcie_links); 2548 return -EINVAL; 2549 } else if (num_pcie_links == 2) { 2550 phy_t1 = TYPE_PCIE_ML; 2551 for (node = 0; node < cdns_phy->nsubnodes; node++) { 2552 if (cdns_phy->phys[node].phy_type == TYPE_PCIE) { 2553 cdns_phy->phys[node].phy_type = TYPE_PCIE_ML; 2554 continue; 2555 } 2556 phy_t2 = cdns_phy->phys[node].phy_type; 2557 } 2558 } 2559 } 2560 2561 /** 2562 * Configure all links with the protocol phy_t1 first followed by 2563 * configuring all links with the protocol phy_t2. 2564 * 2565 * When phy_t1 = phy_t2, it is a single protocol and configuration 2566 * is performed with a single iteration of the protocol and multiple 2567 * iterations over the sub-nodes (links). 2568 * 2569 * When phy_t1 != phy_t2, there are two protocols and configuration 2570 * is performed by iterating over all sub-nodes matching the first 2571 * protocol and configuring them first, followed by iterating over 2572 * all sub-nodes matching the second protocol and configuring them 2573 * next. 2574 */ 2575 for (protocol = 0; protocol < num_protocols; protocol++) { 2576 /** 2577 * For the case where num_protocols is 1, 2578 * phy_t1 = phy_t2 and the swap is unnecessary. 2579 * 2580 * Swapping phy_t1 and phy_t2 is only required when the 2581 * number of protocols is 2 and there are 2 or more links. 2582 */ 2583 if (protocol == 1) { 2584 /** 2585 * If first protocol with phy_t1 is configured, then 2586 * configure the PHY for second protocol with phy_t2. 2587 * Get the array values as [phy_t2][phy_t1][ssc]. 2588 */ 2589 swap(phy_t1, phy_t2); 2590 swap(ref_clk, ref_clk1); 2591 } 2592 2593 for (node = 0; node < cdns_phy->nsubnodes; node++) { 2594 if (cdns_phy->phys[node].phy_type != phy_t1) 2595 continue; 2596 2597 mlane = cdns_phy->phys[node].mlane; 2598 ssc = cdns_phy->phys[node].ssc_mode; 2599 num_lanes = cdns_phy->phys[node].num_lanes; 2600 2601 /** 2602 * PHY configuration specific registers: 2603 * link_cmn_vals depend on combination of PHY types being 2604 * configured and are common for both PHY types, so array 2605 * values should be same for [phy_t1][phy_t2][ssc] and 2606 * [phy_t2][phy_t1][ssc]. 2607 * xcvr_diag_vals also depend on combination of PHY types 2608 * being configured, but these can be different for particular 2609 * PHY type and are per lane. 2610 */ 2611 link_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->link_cmn_vals_tbl, 2612 CLK_ANY, CLK_ANY, 2613 phy_t1, phy_t2, ANY_SSC); 2614 if (link_cmn_vals) { 2615 reg_pairs = link_cmn_vals->reg_pairs; 2616 num_regs = link_cmn_vals->num_regs; 2617 regmap = cdns_phy->regmap_common_cdb; 2618 2619 /** 2620 * First array value in link_cmn_vals must be of 2621 * PHY_PLL_CFG register 2622 */ 2623 regmap_field_write(cdns_phy->phy_pll_cfg, 2624 reg_pairs[0].val); 2625 2626 for (i = 1; i < num_regs; i++) 2627 regmap_write(regmap, reg_pairs[i].off, 2628 reg_pairs[i].val); 2629 } 2630 2631 xcvr_diag_vals = cdns_torrent_get_tbl_vals(&init_data->xcvr_diag_vals_tbl, 2632 CLK_ANY, CLK_ANY, 2633 phy_t1, phy_t2, ANY_SSC); 2634 if (xcvr_diag_vals) { 2635 reg_pairs = xcvr_diag_vals->reg_pairs; 2636 num_regs = xcvr_diag_vals->num_regs; 2637 for (i = 0; i < num_lanes; i++) { 2638 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2639 for (j = 0; j < num_regs; j++) 2640 regmap_write(regmap, reg_pairs[j].off, 2641 reg_pairs[j].val); 2642 } 2643 } 2644 2645 /* PHY PCS common registers configurations */ 2646 pcs_cmn_vals = cdns_torrent_get_tbl_vals(&init_data->pcs_cmn_vals_tbl, 2647 CLK_ANY, CLK_ANY, 2648 phy_t1, phy_t2, ANY_SSC); 2649 if (pcs_cmn_vals) { 2650 reg_pairs = pcs_cmn_vals->reg_pairs; 2651 num_regs = pcs_cmn_vals->num_regs; 2652 regmap = cdns_phy->regmap_phy_pcs_common_cdb; 2653 for (i = 0; i < num_regs; i++) 2654 regmap_write(regmap, reg_pairs[i].off, 2655 reg_pairs[i].val); 2656 } 2657 2658 /* PHY PMA common registers configurations */ 2659 phy_pma_cmn_vals = 2660 cdns_torrent_get_tbl_vals(&init_data->phy_pma_cmn_vals_tbl, 2661 CLK_ANY, CLK_ANY, phy_t1, phy_t2, 2662 ANY_SSC); 2663 if (phy_pma_cmn_vals) { 2664 reg_pairs = phy_pma_cmn_vals->reg_pairs; 2665 num_regs = phy_pma_cmn_vals->num_regs; 2666 regmap = cdns_phy->regmap_phy_pma_common_cdb; 2667 for (i = 0; i < num_regs; i++) 2668 regmap_write(regmap, reg_pairs[i].off, 2669 reg_pairs[i].val); 2670 } 2671 2672 /* PMA common registers configurations */ 2673 cmn_vals = cdns_torrent_get_tbl_vals(&init_data->cmn_vals_tbl, 2674 ref_clk, ref_clk1, 2675 phy_t1, phy_t2, ssc); 2676 if (cmn_vals) { 2677 reg_pairs = cmn_vals->reg_pairs; 2678 num_regs = cmn_vals->num_regs; 2679 regmap = cdns_phy->regmap_common_cdb; 2680 for (i = 0; i < num_regs; i++) 2681 regmap_write(regmap, reg_pairs[i].off, 2682 reg_pairs[i].val); 2683 } 2684 2685 /* PMA TX lane registers configurations */ 2686 tx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->tx_ln_vals_tbl, 2687 ref_clk, ref_clk1, 2688 phy_t1, phy_t2, ssc); 2689 if (tx_ln_vals) { 2690 reg_pairs = tx_ln_vals->reg_pairs; 2691 num_regs = tx_ln_vals->num_regs; 2692 for (i = 0; i < num_lanes; i++) { 2693 regmap = cdns_phy->regmap_tx_lane_cdb[i + mlane]; 2694 for (j = 0; j < num_regs; j++) 2695 regmap_write(regmap, reg_pairs[j].off, 2696 reg_pairs[j].val); 2697 } 2698 } 2699 2700 /* PMA RX lane registers configurations */ 2701 rx_ln_vals = cdns_torrent_get_tbl_vals(&init_data->rx_ln_vals_tbl, 2702 ref_clk, ref_clk1, 2703 phy_t1, phy_t2, ssc); 2704 if (rx_ln_vals) { 2705 reg_pairs = rx_ln_vals->reg_pairs; 2706 num_regs = rx_ln_vals->num_regs; 2707 for (i = 0; i < num_lanes; i++) { 2708 regmap = cdns_phy->regmap_rx_lane_cdb[i + mlane]; 2709 for (j = 0; j < num_regs; j++) 2710 regmap_write(regmap, reg_pairs[j].off, 2711 reg_pairs[j].val); 2712 } 2713 } 2714 2715 if (phy_t1 == TYPE_DP) { 2716 ret = cdns_torrent_dp_get_pll(cdns_phy, phy_t2); 2717 if (ret) 2718 return ret; 2719 } 2720 2721 reset_control_deassert(cdns_phy->phys[node].lnk_rst); 2722 } 2723 } 2724 2725 /* Restore TYPE_PCIE_ML to TYPE_PCIE to be compatible with suspend-resume */ 2726 for (node = 0; node < cdns_phy->nsubnodes; node++) 2727 if (cdns_phy->phys[node].phy_type == TYPE_PCIE_ML) 2728 cdns_phy->phys[node].phy_type = TYPE_PCIE; 2729 2730 /* Take the PHY out of reset */ 2731 ret = reset_control_deassert(cdns_phy->phy_rst); 2732 if (ret) 2733 return ret; 2734 2735 return 0; 2736} 2737 2738static void cdns_torrent_clk_cleanup(struct cdns_torrent_phy *cdns_phy) 2739{ 2740 struct device *dev = cdns_phy->dev; 2741 2742 of_clk_del_provider(dev->of_node); 2743} 2744 2745static int cdns_torrent_clk_register(struct cdns_torrent_phy *cdns_phy) 2746{ 2747 struct device *dev = cdns_phy->dev; 2748 struct device_node *node = dev->of_node; 2749 struct clk_hw_onecell_data *data; 2750 int ret; 2751 2752 data = devm_kzalloc(dev, struct_size(data, hws, CDNS_TORRENT_OUTPUT_CLOCKS), GFP_KERNEL); 2753 if (!data) 2754 return -ENOMEM; 2755 2756 data->num = CDNS_TORRENT_OUTPUT_CLOCKS; 2757 cdns_phy->clk_hw_data = data; 2758 2759 ret = cdns_torrent_derived_refclk_register(cdns_phy); 2760 if (ret) { 2761 dev_err(dev, "failed to register derived refclk\n"); 2762 return ret; 2763 } 2764 2765 ret = cdns_torrent_received_refclk_register(cdns_phy); 2766 if (ret) { 2767 dev_err(dev, "failed to register received refclk\n"); 2768 return ret; 2769 } 2770 2771 ret = cdns_torrent_refclk_driver_register(cdns_phy); 2772 if (ret) { 2773 dev_err(dev, "failed to register refclk driver\n"); 2774 return ret; 2775 } 2776 2777 ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, data); 2778 if (ret) { 2779 dev_err(dev, "Failed to add clock provider: %s\n", node->name); 2780 return ret; 2781 } 2782 2783 return 0; 2784} 2785 2786static int cdns_torrent_of_get_reset(struct cdns_torrent_phy *cdns_phy) 2787{ 2788 struct device *dev = cdns_phy->dev; 2789 2790 cdns_phy->phy_rst = devm_reset_control_get_exclusive_by_index(dev, 0); 2791 if (IS_ERR(cdns_phy->phy_rst)) { 2792 dev_err(dev, "%s: failed to get reset\n", 2793 dev->of_node->full_name); 2794 return PTR_ERR(cdns_phy->phy_rst); 2795 } 2796 2797 cdns_phy->apb_rst = devm_reset_control_get_optional_exclusive(dev, "torrent_apb"); 2798 if (IS_ERR(cdns_phy->apb_rst)) { 2799 dev_err(dev, "%s: failed to get apb reset\n", 2800 dev->of_node->full_name); 2801 return PTR_ERR(cdns_phy->apb_rst); 2802 } 2803 2804 return 0; 2805} 2806 2807static int cdns_torrent_of_get_clk(struct cdns_torrent_phy *cdns_phy) 2808{ 2809 /* refclk: Input reference clock for PLL0 */ 2810 cdns_phy->clk = devm_clk_get(cdns_phy->dev, "refclk"); 2811 if (IS_ERR(cdns_phy->clk)) 2812 return dev_err_probe(cdns_phy->dev, PTR_ERR(cdns_phy->clk), 2813 "phy ref clock not found\n"); 2814 2815 /* refclk1: Input reference clock for PLL1 */ 2816 cdns_phy->clk1 = devm_clk_get_optional(cdns_phy->dev, "pll1_refclk"); 2817 if (IS_ERR(cdns_phy->clk1)) 2818 return dev_err_probe(cdns_phy->dev, PTR_ERR(cdns_phy->clk1), 2819 "phy PLL1 ref clock not found\n"); 2820 2821 return 0; 2822} 2823 2824static int cdns_torrent_clk(struct cdns_torrent_phy *cdns_phy) 2825{ 2826 unsigned long ref_clk1_rate; 2827 unsigned long ref_clk_rate; 2828 int ret; 2829 2830 ret = clk_prepare_enable(cdns_phy->clk); 2831 if (ret) { 2832 dev_err(cdns_phy->dev, "Failed to prepare ref clock: %d\n", ret); 2833 return ret; 2834 } 2835 2836 ref_clk_rate = clk_get_rate(cdns_phy->clk); 2837 if (!ref_clk_rate) { 2838 dev_err(cdns_phy->dev, "Failed to get ref clock rate\n"); 2839 ret = -EINVAL; 2840 goto disable_clk; 2841 } 2842 2843 switch (ref_clk_rate) { 2844 case REF_CLK_19_2MHZ: 2845 cdns_phy->ref_clk_rate = CLK_19_2_MHZ; 2846 break; 2847 case REF_CLK_25MHZ: 2848 cdns_phy->ref_clk_rate = CLK_25_MHZ; 2849 break; 2850 case REF_CLK_100MHZ: 2851 cdns_phy->ref_clk_rate = CLK_100_MHZ; 2852 break; 2853 case REF_CLK_156_25MHZ: 2854 cdns_phy->ref_clk_rate = CLK_156_25_MHZ; 2855 break; 2856 default: 2857 dev_err(cdns_phy->dev, "Invalid ref clock rate\n"); 2858 ret = -EINVAL; 2859 goto disable_clk; 2860 } 2861 2862 if (cdns_phy->clk1) { 2863 ret = clk_prepare_enable(cdns_phy->clk1); 2864 if (ret) { 2865 dev_err(cdns_phy->dev, "Failed to prepare PLL1 ref clock: %d\n", ret); 2866 goto disable_clk; 2867 } 2868 2869 ref_clk1_rate = clk_get_rate(cdns_phy->clk1); 2870 if (!ref_clk1_rate) { 2871 dev_err(cdns_phy->dev, "Failed to get PLL1 ref clock rate\n"); 2872 ret = -EINVAL; 2873 goto disable_clk1; 2874 } 2875 2876 switch (ref_clk1_rate) { 2877 case REF_CLK_19_2MHZ: 2878 cdns_phy->ref_clk1_rate = CLK_19_2_MHZ; 2879 break; 2880 case REF_CLK_25MHZ: 2881 cdns_phy->ref_clk1_rate = CLK_25_MHZ; 2882 break; 2883 case REF_CLK_100MHZ: 2884 cdns_phy->ref_clk1_rate = CLK_100_MHZ; 2885 break; 2886 case REF_CLK_156_25MHZ: 2887 cdns_phy->ref_clk1_rate = CLK_156_25_MHZ; 2888 break; 2889 default: 2890 dev_err(cdns_phy->dev, "Invalid PLL1 ref clock rate\n"); 2891 ret = -EINVAL; 2892 goto disable_clk1; 2893 } 2894 } else { 2895 cdns_phy->ref_clk1_rate = cdns_phy->ref_clk_rate; 2896 } 2897 2898 return 0; 2899 2900disable_clk1: 2901 clk_disable_unprepare(cdns_phy->clk1); 2902disable_clk: 2903 clk_disable_unprepare(cdns_phy->clk); 2904 return ret; 2905} 2906 2907static int cdns_torrent_phy_probe(struct platform_device *pdev) 2908{ 2909 struct cdns_torrent_phy *cdns_phy; 2910 struct device *dev = &pdev->dev; 2911 struct phy_provider *phy_provider; 2912 const struct cdns_torrent_data *data; 2913 struct device_node *child; 2914 int ret, subnodes, node = 0, i; 2915 u32 total_num_lanes = 0; 2916 u8 init_dp_regmap = 0; 2917 u32 phy_type; 2918 2919 /* Get init data for this PHY */ 2920 data = of_device_get_match_data(dev); 2921 if (!data) 2922 return -EINVAL; 2923 2924 cdns_phy = devm_kzalloc(dev, sizeof(*cdns_phy), GFP_KERNEL); 2925 if (!cdns_phy) 2926 return -ENOMEM; 2927 2928 dev_set_drvdata(dev, cdns_phy); 2929 cdns_phy->dev = dev; 2930 cdns_phy->init_data = data; 2931 cdns_phy->protocol_bitmask = 0; 2932 2933 cdns_phy->sd_base = devm_platform_ioremap_resource(pdev, 0); 2934 if (IS_ERR(cdns_phy->sd_base)) 2935 return PTR_ERR(cdns_phy->sd_base); 2936 2937 subnodes = of_get_available_child_count(dev->of_node); 2938 if (subnodes == 0) { 2939 dev_err(dev, "No available link subnodes found\n"); 2940 return -EINVAL; 2941 } 2942 2943 ret = cdns_torrent_regmap_init(cdns_phy); 2944 if (ret) 2945 return ret; 2946 2947 ret = cdns_torrent_regfield_init(cdns_phy); 2948 if (ret) 2949 return ret; 2950 2951 ret = cdns_torrent_clk_register(cdns_phy); 2952 if (ret) 2953 return ret; 2954 2955 ret = cdns_torrent_of_get_reset(cdns_phy); 2956 if (ret) 2957 goto clk_cleanup; 2958 2959 ret = cdns_torrent_of_get_clk(cdns_phy); 2960 if (ret) 2961 goto clk_cleanup; 2962 2963 regmap_field_read(cdns_phy->phy_pma_cmn_ctrl_1, &cdns_phy->already_configured); 2964 2965 if (!cdns_phy->already_configured) { 2966 ret = cdns_torrent_clk(cdns_phy); 2967 if (ret) 2968 goto clk_cleanup; 2969 2970 /* Enable APB */ 2971 reset_control_deassert(cdns_phy->apb_rst); 2972 } 2973 2974 for_each_available_child_of_node(dev->of_node, child) { 2975 struct phy *gphy; 2976 2977 /* PHY subnode name must be 'phy'. */ 2978 if (!(of_node_name_eq(child, "phy"))) 2979 continue; 2980 2981 cdns_phy->phys[node].lnk_rst = 2982 of_reset_control_array_get_exclusive(child); 2983 if (IS_ERR(cdns_phy->phys[node].lnk_rst)) { 2984 dev_err(dev, "%s: failed to get reset\n", 2985 child->full_name); 2986 ret = PTR_ERR(cdns_phy->phys[node].lnk_rst); 2987 goto put_lnk_rst; 2988 } 2989 2990 if (of_property_read_u32(child, "reg", 2991 &cdns_phy->phys[node].mlane)) { 2992 dev_err(dev, "%s: No \"reg\"-property.\n", 2993 child->full_name); 2994 ret = -EINVAL; 2995 goto put_child; 2996 } 2997 2998 if (of_property_read_u32(child, "cdns,phy-type", &phy_type)) { 2999 dev_err(dev, "%s: No \"cdns,phy-type\"-property.\n", 3000 child->full_name); 3001 ret = -EINVAL; 3002 goto put_child; 3003 } 3004 3005 switch (phy_type) { 3006 case PHY_TYPE_PCIE: 3007 cdns_phy->phys[node].phy_type = TYPE_PCIE; 3008 break; 3009 case PHY_TYPE_DP: 3010 cdns_phy->phys[node].phy_type = TYPE_DP; 3011 break; 3012 case PHY_TYPE_SGMII: 3013 cdns_phy->phys[node].phy_type = TYPE_SGMII; 3014 break; 3015 case PHY_TYPE_QSGMII: 3016 cdns_phy->phys[node].phy_type = TYPE_QSGMII; 3017 break; 3018 case PHY_TYPE_USB3: 3019 cdns_phy->phys[node].phy_type = TYPE_USB; 3020 break; 3021 case PHY_TYPE_USXGMII: 3022 cdns_phy->phys[node].phy_type = TYPE_USXGMII; 3023 break; 3024 default: 3025 dev_err(dev, "Unsupported protocol\n"); 3026 ret = -EINVAL; 3027 goto put_child; 3028 } 3029 3030 if (of_property_read_u32(child, "cdns,num-lanes", 3031 &cdns_phy->phys[node].num_lanes)) { 3032 dev_err(dev, "%s: No \"cdns,num-lanes\"-property.\n", 3033 child->full_name); 3034 ret = -EINVAL; 3035 goto put_child; 3036 } 3037 3038 total_num_lanes += cdns_phy->phys[node].num_lanes; 3039 3040 /* Get SSC mode */ 3041 cdns_phy->phys[node].ssc_mode = NO_SSC; 3042 of_property_read_u32(child, "cdns,ssc-mode", 3043 &cdns_phy->phys[node].ssc_mode); 3044 3045 gphy = devm_phy_create(dev, child, &cdns_torrent_phy_ops); 3046 if (IS_ERR(gphy)) { 3047 ret = PTR_ERR(gphy); 3048 goto put_child; 3049 } 3050 3051 if (cdns_phy->phys[node].phy_type == TYPE_DP) { 3052 switch (cdns_phy->phys[node].num_lanes) { 3053 case 1: 3054 case 2: 3055 case 4: 3056 /* valid number of lanes */ 3057 break; 3058 default: 3059 dev_err(dev, "unsupported number of lanes: %d\n", 3060 cdns_phy->phys[node].num_lanes); 3061 ret = -EINVAL; 3062 goto put_child; 3063 } 3064 3065 cdns_phy->max_bit_rate = DEFAULT_MAX_BIT_RATE; 3066 of_property_read_u32(child, "cdns,max-bit-rate", 3067 &cdns_phy->max_bit_rate); 3068 3069 switch (cdns_phy->max_bit_rate) { 3070 case 1620: 3071 case 2160: 3072 case 2430: 3073 case 2700: 3074 case 3240: 3075 case 4320: 3076 case 5400: 3077 case 8100: 3078 /* valid bit rate */ 3079 break; 3080 default: 3081 dev_err(dev, "unsupported max bit rate: %dMbps\n", 3082 cdns_phy->max_bit_rate); 3083 ret = -EINVAL; 3084 goto put_child; 3085 } 3086 3087 /* DPTX registers */ 3088 cdns_phy->base = devm_platform_ioremap_resource(pdev, 1); 3089 if (IS_ERR(cdns_phy->base)) { 3090 ret = PTR_ERR(cdns_phy->base); 3091 goto put_child; 3092 } 3093 3094 if (!init_dp_regmap) { 3095 ret = cdns_torrent_dp_regmap_init(cdns_phy); 3096 if (ret) 3097 goto put_child; 3098 3099 ret = cdns_torrent_dp_regfield_init(cdns_phy); 3100 if (ret) 3101 goto put_child; 3102 3103 init_dp_regmap++; 3104 } 3105 3106 dev_dbg(dev, "DP max bit rate %d.%03d Gbps\n", 3107 cdns_phy->max_bit_rate / 1000, 3108 cdns_phy->max_bit_rate % 1000); 3109 3110 gphy->attrs.bus_width = cdns_phy->phys[node].num_lanes; 3111 gphy->attrs.max_link_rate = cdns_phy->max_bit_rate; 3112 gphy->attrs.mode = PHY_MODE_DP; 3113 } 3114 3115 cdns_phy->phys[node].phy = gphy; 3116 cdns_phy->protocol_bitmask |= BIT(cdns_phy->phys[node].phy_type); 3117 phy_set_drvdata(gphy, &cdns_phy->phys[node]); 3118 3119 node++; 3120 } 3121 cdns_phy->nsubnodes = node; 3122 3123 if (total_num_lanes > MAX_NUM_LANES) { 3124 dev_err(dev, "Invalid lane configuration\n"); 3125 ret = -EINVAL; 3126 goto put_lnk_rst; 3127 } 3128 3129 if (cdns_phy->nsubnodes > 1 && !cdns_phy->already_configured) { 3130 ret = cdns_torrent_phy_configure_multilink(cdns_phy); 3131 if (ret) 3132 goto put_lnk_rst; 3133 } 3134 3135 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 3136 if (IS_ERR(phy_provider)) { 3137 ret = PTR_ERR(phy_provider); 3138 goto put_lnk_rst; 3139 } 3140 3141 if (cdns_phy->nsubnodes > 1) 3142 dev_dbg(dev, "Multi link configuration:\n"); 3143 else 3144 dev_dbg(dev, "Single link configuration:\n"); 3145 3146 for (i = 0; i < cdns_phy->nsubnodes; i++) 3147 dev_dbg(dev, "%s (%d lanes)", 3148 cdns_torrent_get_phy_type(cdns_phy->phys[i].phy_type), 3149 cdns_phy->phys[i].num_lanes); 3150 3151 return 0; 3152 3153put_child: 3154 node++; 3155put_lnk_rst: 3156 for (i = 0; i < node; i++) 3157 reset_control_put(cdns_phy->phys[i].lnk_rst); 3158 of_node_put(child); 3159 reset_control_assert(cdns_phy->apb_rst); 3160 clk_disable_unprepare(cdns_phy->clk1); 3161 clk_disable_unprepare(cdns_phy->clk); 3162clk_cleanup: 3163 cdns_torrent_clk_cleanup(cdns_phy); 3164 return ret; 3165} 3166 3167static void cdns_torrent_phy_remove(struct platform_device *pdev) 3168{ 3169 struct cdns_torrent_phy *cdns_phy = platform_get_drvdata(pdev); 3170 int i; 3171 3172 reset_control_assert(cdns_phy->phy_rst); 3173 reset_control_assert(cdns_phy->apb_rst); 3174 for (i = 0; i < cdns_phy->nsubnodes; i++) { 3175 reset_control_assert(cdns_phy->phys[i].lnk_rst); 3176 reset_control_put(cdns_phy->phys[i].lnk_rst); 3177 } 3178 3179 clk_disable_unprepare(cdns_phy->clk1); 3180 clk_disable_unprepare(cdns_phy->clk); 3181 cdns_torrent_clk_cleanup(cdns_phy); 3182} 3183 3184/* Multilink PCIe and USB Same SSC link configuration */ 3185static const struct cdns_reg_pairs ml_pcie_usb_link_cmn_regs[] = { 3186 {0x0002, PHY_PLL_CFG}, 3187 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3188}; 3189 3190static const struct cdns_reg_pairs ml_pcie_usb_xcvr_diag_ln_regs[] = { 3191 {0x0100, XCVR_DIAG_HSCLK_SEL}, 3192 {0x0013, XCVR_DIAG_HSCLK_DIV}, 3193 {0x0812, XCVR_DIAG_PLLDRC_CTRL} 3194}; 3195 3196static const struct cdns_reg_pairs usb_ml_pcie_xcvr_diag_ln_regs[] = { 3197 {0x0041, XCVR_DIAG_PLLDRC_CTRL}, 3198}; 3199 3200static const struct cdns_torrent_vals ml_pcie_usb_link_cmn_vals = { 3201 .reg_pairs = ml_pcie_usb_link_cmn_regs, 3202 .num_regs = ARRAY_SIZE(ml_pcie_usb_link_cmn_regs), 3203}; 3204 3205static const struct cdns_torrent_vals ml_pcie_usb_xcvr_diag_ln_vals = { 3206 .reg_pairs = ml_pcie_usb_xcvr_diag_ln_regs, 3207 .num_regs = ARRAY_SIZE(ml_pcie_usb_xcvr_diag_ln_regs), 3208}; 3209 3210static const struct cdns_torrent_vals usb_ml_pcie_xcvr_diag_ln_vals = { 3211 .reg_pairs = usb_ml_pcie_xcvr_diag_ln_regs, 3212 .num_regs = ARRAY_SIZE(usb_ml_pcie_xcvr_diag_ln_regs), 3213}; 3214 3215/* Multi link PCIe configuration */ 3216static const struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = { 3217 {0x0002, PHY_PLL_CFG}, 3218 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} 3219}; 3220 3221static const struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = { 3222 {0x0100, XCVR_DIAG_HSCLK_SEL}, 3223 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3224 {0x0812, XCVR_DIAG_PLLDRC_CTRL} 3225}; 3226 3227static const struct cdns_torrent_vals ml_pcie_link_cmn_vals = { 3228 .reg_pairs = ml_pcie_link_cmn_regs, 3229 .num_regs = ARRAY_SIZE(ml_pcie_link_cmn_regs), 3230}; 3231 3232static const struct cdns_torrent_vals ml_pcie_xcvr_diag_ln_vals = { 3233 .reg_pairs = ml_pcie_xcvr_diag_ln_regs, 3234 .num_regs = ARRAY_SIZE(ml_pcie_xcvr_diag_ln_regs), 3235}; 3236 3237/* Multi link PCIe, 100 MHz Ref clk, no SSC */ 3238static const struct cdns_reg_pairs ml_pcie_100_no_ssc_cmn_regs[] = { 3239 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3240 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3241}; 3242 3243static const struct cdns_reg_pairs ml_pcie_100_no_ssc_rx_ln_regs[] = { 3244 {0x0019, RX_REE_TAP1_CLIP}, 3245 {0x0019, RX_REE_TAP2TON_CLIP}, 3246 {0x0008, RX_REE_PEAK_UTHR}, 3247 {0x018E, RX_CDRLF_CNFG}, 3248 {0x2E33, RX_CDRLF_CNFG2}, 3249 {0x0001, RX_DIAG_ACYA}, 3250 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2}, 3251 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 3252 {0x0005, RX_DIAG_REE_DAC_CTRL} 3253}; 3254 3255static const struct cdns_torrent_vals ml_pcie_100_no_ssc_cmn_vals = { 3256 .reg_pairs = ml_pcie_100_no_ssc_cmn_regs, 3257 .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_cmn_regs), 3258}; 3259 3260static const struct cdns_torrent_vals ml_pcie_100_no_ssc_rx_ln_vals = { 3261 .reg_pairs = ml_pcie_100_no_ssc_rx_ln_regs, 3262 .num_regs = ARRAY_SIZE(ml_pcie_100_no_ssc_rx_ln_regs), 3263}; 3264 3265/* Multi link PCIe, 100 MHz Ref clk, internal SSC */ 3266static const struct cdns_reg_pairs ml_pcie_100_int_ssc_cmn_regs[] = { 3267 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3268 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3269 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3270 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3271 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3272 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3273 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3274 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3275 {0x0064, CMN_PLL0_INTDIV_M0}, 3276 {0x0050, CMN_PLL1_INTDIV_M0}, 3277 {0x0002, CMN_PLL0_FRACDIVH_M0}, 3278 {0x0002, CMN_PLL1_FRACDIVH_M0}, 3279 {0x0044, CMN_PLL0_HIGH_THR_M0}, 3280 {0x0036, CMN_PLL1_HIGH_THR_M0}, 3281 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 3282 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 3283 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 3284 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 3285 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 3286 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 3287 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 3288 {0x0058, CMN_PLL1_SS_CTRL3_M0}, 3289 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 3290 {0x0012, CMN_PLL1_SS_CTRL4_M0}, 3291 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 3292 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 3293 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 3294 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 3295 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3296 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3297 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 3298 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 3299 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 3300 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 3301 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 3302 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 3303}; 3304 3305static const struct cdns_torrent_vals ml_pcie_100_int_ssc_cmn_vals = { 3306 .reg_pairs = ml_pcie_100_int_ssc_cmn_regs, 3307 .num_regs = ARRAY_SIZE(ml_pcie_100_int_ssc_cmn_regs), 3308}; 3309 3310/* SGMII and QSGMII link configuration */ 3311static const struct cdns_reg_pairs sgmii_qsgmii_link_cmn_regs[] = { 3312 {0x0002, PHY_PLL_CFG} 3313}; 3314 3315static const struct cdns_reg_pairs sgmii_qsgmii_xcvr_diag_ln_regs[] = { 3316 {0x0003, XCVR_DIAG_HSCLK_DIV}, 3317 {0x0113, XCVR_DIAG_PLLDRC_CTRL} 3318}; 3319 3320static const struct cdns_torrent_vals sgmii_qsgmii_link_cmn_vals = { 3321 .reg_pairs = sgmii_qsgmii_link_cmn_regs, 3322 .num_regs = ARRAY_SIZE(sgmii_qsgmii_link_cmn_regs), 3323}; 3324 3325static const struct cdns_torrent_vals sgmii_qsgmii_xcvr_diag_ln_vals = { 3326 .reg_pairs = sgmii_qsgmii_xcvr_diag_ln_regs, 3327 .num_regs = ARRAY_SIZE(sgmii_qsgmii_xcvr_diag_ln_regs), 3328}; 3329 3330static void cdns_torrent_refclk_driver_suspend(struct cdns_torrent_phy *cdns_phy) 3331{ 3332 struct clk_hw *hw = cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER]; 3333 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 3334 3335 refclk_driver->parent_index = cdns_torrent_refclk_driver_get_parent(hw); 3336} 3337 3338static int cdns_torrent_refclk_driver_resume(struct cdns_torrent_phy *cdns_phy) 3339{ 3340 struct clk_hw *hw = cdns_phy->clk_hw_data->hws[CDNS_TORRENT_REFCLK_DRIVER]; 3341 struct cdns_torrent_refclk_driver *refclk_driver = to_cdns_torrent_refclk_driver(hw); 3342 3343 return cdns_torrent_refclk_driver_set_parent(hw, refclk_driver->parent_index); 3344} 3345 3346static int cdns_torrent_phy_suspend_noirq(struct device *dev) 3347{ 3348 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(dev); 3349 int i; 3350 3351 cdns_torrent_refclk_driver_suspend(cdns_phy); 3352 3353 reset_control_assert(cdns_phy->phy_rst); 3354 reset_control_assert(cdns_phy->apb_rst); 3355 for (i = 0; i < cdns_phy->nsubnodes; i++) 3356 reset_control_assert(cdns_phy->phys[i].lnk_rst); 3357 3358 if (cdns_phy->already_configured) 3359 cdns_phy->already_configured = 0; 3360 else { 3361 clk_disable_unprepare(cdns_phy->clk1); 3362 clk_disable_unprepare(cdns_phy->clk); 3363 } 3364 3365 return 0; 3366} 3367 3368static int cdns_torrent_phy_resume_noirq(struct device *dev) 3369{ 3370 struct cdns_torrent_phy *cdns_phy = dev_get_drvdata(dev); 3371 int node = cdns_phy->nsubnodes; 3372 int ret, i; 3373 3374 ret = cdns_torrent_refclk_driver_resume(cdns_phy); 3375 if (ret) 3376 return ret; 3377 3378 ret = cdns_torrent_clk(cdns_phy); 3379 if (ret) 3380 return ret; 3381 3382 /* Enable APB */ 3383 reset_control_deassert(cdns_phy->apb_rst); 3384 3385 if (cdns_phy->nsubnodes > 1) { 3386 ret = cdns_torrent_phy_configure_multilink(cdns_phy); 3387 if (ret) 3388 goto put_lnk_rst; 3389 } 3390 3391 return 0; 3392 3393put_lnk_rst: 3394 for (i = 0; i < node; i++) 3395 reset_control_assert(cdns_phy->phys[i].lnk_rst); 3396 reset_control_assert(cdns_phy->apb_rst); 3397 3398 clk_disable_unprepare(cdns_phy->clk1); 3399 clk_disable_unprepare(cdns_phy->clk); 3400 3401 return ret; 3402} 3403 3404static DEFINE_NOIRQ_DEV_PM_OPS(cdns_torrent_phy_pm_ops, 3405 cdns_torrent_phy_suspend_noirq, 3406 cdns_torrent_phy_resume_noirq); 3407 3408/* USB and DP link configuration */ 3409static const struct cdns_reg_pairs usb_dp_link_cmn_regs[] = { 3410 {0x0002, PHY_PLL_CFG}, 3411 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 3412}; 3413 3414static const struct cdns_reg_pairs usb_dp_xcvr_diag_ln_regs[] = { 3415 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3416 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3417 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 3418}; 3419 3420static const struct cdns_reg_pairs dp_usb_xcvr_diag_ln_regs[] = { 3421 {0x0001, XCVR_DIAG_HSCLK_SEL}, 3422 {0x0009, XCVR_DIAG_PLLDRC_CTRL} 3423}; 3424 3425static const struct cdns_torrent_vals usb_dp_link_cmn_vals = { 3426 .reg_pairs = usb_dp_link_cmn_regs, 3427 .num_regs = ARRAY_SIZE(usb_dp_link_cmn_regs), 3428}; 3429 3430static const struct cdns_torrent_vals usb_dp_xcvr_diag_ln_vals = { 3431 .reg_pairs = usb_dp_xcvr_diag_ln_regs, 3432 .num_regs = ARRAY_SIZE(usb_dp_xcvr_diag_ln_regs), 3433}; 3434 3435static const struct cdns_torrent_vals dp_usb_xcvr_diag_ln_vals = { 3436 .reg_pairs = dp_usb_xcvr_diag_ln_regs, 3437 .num_regs = ARRAY_SIZE(dp_usb_xcvr_diag_ln_regs), 3438}; 3439 3440/* USXGMII and SGMII/QSGMII link configuration */ 3441static const struct cdns_reg_pairs usxgmii_sgmii_link_cmn_regs[] = { 3442 {0x0002, PHY_PLL_CFG}, 3443 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3444 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 3445}; 3446 3447static const struct cdns_reg_pairs usxgmii_sgmii_xcvr_diag_ln_regs[] = { 3448 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3449 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3450 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3451}; 3452 3453static const struct cdns_reg_pairs sgmii_usxgmii_xcvr_diag_ln_regs[] = { 3454 {0x0111, XCVR_DIAG_HSCLK_SEL}, 3455 {0x0103, XCVR_DIAG_HSCLK_DIV}, 3456 {0x0A9B, XCVR_DIAG_PLLDRC_CTRL} 3457}; 3458 3459static const struct cdns_torrent_vals usxgmii_sgmii_link_cmn_vals = { 3460 .reg_pairs = usxgmii_sgmii_link_cmn_regs, 3461 .num_regs = ARRAY_SIZE(usxgmii_sgmii_link_cmn_regs), 3462}; 3463 3464static const struct cdns_torrent_vals usxgmii_sgmii_xcvr_diag_ln_vals = { 3465 .reg_pairs = usxgmii_sgmii_xcvr_diag_ln_regs, 3466 .num_regs = ARRAY_SIZE(usxgmii_sgmii_xcvr_diag_ln_regs), 3467}; 3468 3469static const struct cdns_torrent_vals sgmii_usxgmii_xcvr_diag_ln_vals = { 3470 .reg_pairs = sgmii_usxgmii_xcvr_diag_ln_regs, 3471 .num_regs = ARRAY_SIZE(sgmii_usxgmii_xcvr_diag_ln_regs), 3472}; 3473 3474/* Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */ 3475static const struct cdns_reg_pairs ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = { 3476 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0}, 3477 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0}, 3478 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR}, 3479 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR}, 3480 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START}, 3481 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START}, 3482 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3483 {0x0138, CMN_PLL0_LOCK_REFCNT_START}, 3484 {0x0138, CMN_PLL0_LOCK_PLLCNT_START} 3485}; 3486 3487static const struct cdns_torrent_vals ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = { 3488 .reg_pairs = ml_usxgmii_pll0_156_25_no_ssc_cmn_regs, 3489 .num_regs = ARRAY_SIZE(ml_usxgmii_pll0_156_25_no_ssc_cmn_regs), 3490}; 3491 3492/* Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */ 3493static const struct cdns_reg_pairs ml_sgmii_pll1_100_no_ssc_cmn_regs[] = { 3494 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3495 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3496 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3497 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3498 {0x007F, CMN_TXPUCAL_TUNE}, 3499 {0x007F, CMN_TXPDCAL_TUNE} 3500}; 3501 3502static const struct cdns_torrent_vals ml_sgmii_pll1_100_no_ssc_cmn_vals = { 3503 .reg_pairs = ml_sgmii_pll1_100_no_ssc_cmn_regs, 3504 .num_regs = ARRAY_SIZE(ml_sgmii_pll1_100_no_ssc_cmn_regs), 3505}; 3506 3507/* TI J7200, Multilink USXGMII, using PLL0, 156.25 MHz Ref clk, no SSC */ 3508static const struct cdns_reg_pairs j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs[] = { 3509 {0x0014, CMN_SSM_BIAS_TMR}, 3510 {0x0028, CMN_PLLSM0_PLLPRE_TMR}, 3511 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR}, 3512 {0x0062, CMN_BGCAL_INIT_TMR}, 3513 {0x0062, CMN_BGCAL_ITER_TMR}, 3514 {0x0014, CMN_IBCAL_INIT_TMR}, 3515 {0x0018, CMN_TXPUCAL_INIT_TMR}, 3516 {0x0005, CMN_TXPUCAL_ITER_TMR}, 3517 {0x0018, CMN_TXPDCAL_INIT_TMR}, 3518 {0x0005, CMN_TXPDCAL_ITER_TMR}, 3519 {0x024A, CMN_RXCAL_INIT_TMR}, 3520 {0x0005, CMN_RXCAL_ITER_TMR}, 3521 {0x000B, CMN_SD_CAL_REFTIM_START}, 3522 {0x0132, CMN_SD_CAL_PLLCNT_START}, 3523 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0}, 3524 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0}, 3525 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR}, 3526 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR}, 3527 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START}, 3528 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START}, 3529 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3530 {0x0138, CMN_PLL0_LOCK_REFCNT_START}, 3531 {0x0138, CMN_PLL0_LOCK_PLLCNT_START} 3532}; 3533 3534static const struct cdns_torrent_vals j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals = { 3535 .reg_pairs = j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs, 3536 .num_regs = ARRAY_SIZE(j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_regs), 3537}; 3538 3539/* TI J7200, Multilink SGMII/QSGMII, using PLL1, 100 MHz Ref clk, no SSC */ 3540static const struct cdns_reg_pairs j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs[] = { 3541 {0x0028, CMN_PLLSM1_PLLPRE_TMR}, 3542 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR}, 3543 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3544 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 3545 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 3546 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3547 {0x007F, CMN_TXPUCAL_TUNE}, 3548 {0x007F, CMN_TXPDCAL_TUNE} 3549}; 3550 3551static const struct cdns_torrent_vals j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals = { 3552 .reg_pairs = j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs, 3553 .num_regs = ARRAY_SIZE(j7200_ml_sgmii_pll1_100_no_ssc_cmn_regs), 3554}; 3555 3556/* PCIe and USXGMII link configuration */ 3557static const struct cdns_reg_pairs pcie_usxgmii_link_cmn_regs[] = { 3558 {0x0003, PHY_PLL_CFG}, 3559 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3560 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 3561 {0x0400, CMN_PDIAG_PLL1_CLK_SEL_M0} 3562}; 3563 3564static const struct cdns_reg_pairs pcie_usxgmii_xcvr_diag_ln_regs[] = { 3565 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3566 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3567 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3568}; 3569 3570static const struct cdns_reg_pairs usxgmii_pcie_xcvr_diag_ln_regs[] = { 3571 {0x0011, XCVR_DIAG_HSCLK_SEL}, 3572 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3573 {0x0089, XCVR_DIAG_PLLDRC_CTRL} 3574}; 3575 3576static const struct cdns_torrent_vals pcie_usxgmii_link_cmn_vals = { 3577 .reg_pairs = pcie_usxgmii_link_cmn_regs, 3578 .num_regs = ARRAY_SIZE(pcie_usxgmii_link_cmn_regs), 3579}; 3580 3581static const struct cdns_torrent_vals pcie_usxgmii_xcvr_diag_ln_vals = { 3582 .reg_pairs = pcie_usxgmii_xcvr_diag_ln_regs, 3583 .num_regs = ARRAY_SIZE(pcie_usxgmii_xcvr_diag_ln_regs), 3584}; 3585 3586static const struct cdns_torrent_vals usxgmii_pcie_xcvr_diag_ln_vals = { 3587 .reg_pairs = usxgmii_pcie_xcvr_diag_ln_regs, 3588 .num_regs = ARRAY_SIZE(usxgmii_pcie_xcvr_diag_ln_regs), 3589}; 3590 3591/* 3592 * Multilink USXGMII, using PLL1, 156.25 MHz Ref clk, no SSC 3593 */ 3594static const struct cdns_reg_pairs ml_usxgmii_pll1_156_25_no_ssc_cmn_regs[] = { 3595 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3596 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0}, 3597 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0}, 3598 {0x061B, CMN_PLL1_VCOCAL_INIT_TMR}, 3599 {0x0019, CMN_PLL1_VCOCAL_ITER_TMR}, 3600 {0x1354, CMN_PLL1_VCOCAL_REFTIM_START}, 3601 {0x1354, CMN_PLL1_VCOCAL_PLLCNT_START}, 3602 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3603 {0x0138, CMN_PLL1_LOCK_REFCNT_START}, 3604 {0x0138, CMN_PLL1_LOCK_PLLCNT_START}, 3605 {0x007F, CMN_TXPUCAL_TUNE}, 3606 {0x007F, CMN_TXPDCAL_TUNE} 3607}; 3608 3609static const struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3610 {0x00F3, TX_PSC_A0}, 3611 {0x04A2, TX_PSC_A2}, 3612 {0x04A2, TX_PSC_A3 }, 3613 {0x0000, TX_TXCC_CPOST_MULT_00}, 3614 {0x0000, XCVR_DIAG_PSC_OVRD} 3615}; 3616 3617static const struct cdns_reg_pairs ml_usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3618 {0x091D, RX_PSC_A0}, 3619 {0x0900, RX_PSC_A2}, 3620 {0x0100, RX_PSC_A3}, 3621 {0x0030, RX_REE_SMGM_CTRL1}, 3622 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3623 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3624 {0x0000, RX_DIAG_DFE_CTRL}, 3625 {0x0019, RX_REE_TAP1_CLIP}, 3626 {0x0019, RX_REE_TAP2TON_CLIP}, 3627 {0x00B9, RX_DIAG_NQST_CTRL}, 3628 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2}, 3629 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 3630 {0x0033, RX_DIAG_PI_RATE}, 3631 {0x0001, RX_DIAG_ACYA}, 3632 {0x018C, RX_CDRLF_CNFG} 3633}; 3634 3635static const struct cdns_torrent_vals ml_usxgmii_pll1_156_25_no_ssc_cmn_vals = { 3636 .reg_pairs = ml_usxgmii_pll1_156_25_no_ssc_cmn_regs, 3637 .num_regs = ARRAY_SIZE(ml_usxgmii_pll1_156_25_no_ssc_cmn_regs), 3638}; 3639 3640static const struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_tx_ln_vals = { 3641 .reg_pairs = ml_usxgmii_156_25_no_ssc_tx_ln_regs, 3642 .num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_tx_ln_regs), 3643}; 3644 3645static const struct cdns_torrent_vals ml_usxgmii_156_25_no_ssc_rx_ln_vals = { 3646 .reg_pairs = ml_usxgmii_156_25_no_ssc_rx_ln_regs, 3647 .num_regs = ARRAY_SIZE(ml_usxgmii_156_25_no_ssc_rx_ln_regs), 3648}; 3649 3650/* TI USXGMII configuration: Enable cmn_refclk_rcv_out_en */ 3651static const struct cdns_reg_pairs ti_usxgmii_phy_pma_cmn_regs[] = { 3652 {0x0040, PHY_PMA_CMN_CTRL1}, 3653}; 3654 3655static const struct cdns_torrent_vals ti_usxgmii_phy_pma_cmn_vals = { 3656 .reg_pairs = ti_usxgmii_phy_pma_cmn_regs, 3657 .num_regs = ARRAY_SIZE(ti_usxgmii_phy_pma_cmn_regs), 3658}; 3659 3660/* Single USXGMII link configuration */ 3661static const struct cdns_reg_pairs sl_usxgmii_link_cmn_regs[] = { 3662 {0x0000, PHY_PLL_CFG}, 3663 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M0} 3664}; 3665 3666static const struct cdns_reg_pairs sl_usxgmii_xcvr_diag_ln_regs[] = { 3667 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3668 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3669 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3670}; 3671 3672static const struct cdns_torrent_vals sl_usxgmii_link_cmn_vals = { 3673 .reg_pairs = sl_usxgmii_link_cmn_regs, 3674 .num_regs = ARRAY_SIZE(sl_usxgmii_link_cmn_regs), 3675}; 3676 3677static const struct cdns_torrent_vals sl_usxgmii_xcvr_diag_ln_vals = { 3678 .reg_pairs = sl_usxgmii_xcvr_diag_ln_regs, 3679 .num_regs = ARRAY_SIZE(sl_usxgmii_xcvr_diag_ln_regs), 3680}; 3681 3682/* Single link USXGMII, 156.25 MHz Ref clk, no SSC */ 3683static const struct cdns_reg_pairs sl_usxgmii_156_25_no_ssc_cmn_regs[] = { 3684 {0x0014, CMN_SSM_BIAS_TMR}, 3685 {0x0028, CMN_PLLSM0_PLLPRE_TMR}, 3686 {0x00A4, CMN_PLLSM0_PLLLOCK_TMR}, 3687 {0x0028, CMN_PLLSM1_PLLPRE_TMR}, 3688 {0x00A4, CMN_PLLSM1_PLLLOCK_TMR}, 3689 {0x0062, CMN_BGCAL_INIT_TMR}, 3690 {0x0062, CMN_BGCAL_ITER_TMR}, 3691 {0x0014, CMN_IBCAL_INIT_TMR}, 3692 {0x0018, CMN_TXPUCAL_INIT_TMR}, 3693 {0x0005, CMN_TXPUCAL_ITER_TMR}, 3694 {0x0018, CMN_TXPDCAL_INIT_TMR}, 3695 {0x0005, CMN_TXPDCAL_ITER_TMR}, 3696 {0x024A, CMN_RXCAL_INIT_TMR}, 3697 {0x0005, CMN_RXCAL_ITER_TMR}, 3698 {0x000B, CMN_SD_CAL_REFTIM_START}, 3699 {0x0132, CMN_SD_CAL_PLLCNT_START}, 3700 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3701 {0x0014, CMN_PLL0_DSM_FBH_OVRD_M0}, 3702 {0x0014, CMN_PLL1_DSM_FBH_OVRD_M0}, 3703 {0x0005, CMN_PLL0_DSM_FBL_OVRD_M0}, 3704 {0x0005, CMN_PLL1_DSM_FBL_OVRD_M0}, 3705 {0x061B, CMN_PLL0_VCOCAL_INIT_TMR}, 3706 {0x061B, CMN_PLL1_VCOCAL_INIT_TMR}, 3707 {0x0019, CMN_PLL0_VCOCAL_ITER_TMR}, 3708 {0x0019, CMN_PLL1_VCOCAL_ITER_TMR}, 3709 {0x1354, CMN_PLL0_VCOCAL_REFTIM_START}, 3710 {0x1354, CMN_PLL1_VCOCAL_REFTIM_START}, 3711 {0x1354, CMN_PLL0_VCOCAL_PLLCNT_START}, 3712 {0x1354, CMN_PLL1_VCOCAL_PLLCNT_START}, 3713 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3714 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 3715 {0x0138, CMN_PLL0_LOCK_REFCNT_START}, 3716 {0x0138, CMN_PLL1_LOCK_REFCNT_START}, 3717 {0x0138, CMN_PLL0_LOCK_PLLCNT_START}, 3718 {0x0138, CMN_PLL1_LOCK_PLLCNT_START} 3719}; 3720 3721static const struct cdns_reg_pairs usxgmii_156_25_no_ssc_tx_ln_regs[] = { 3722 {0x07A2, TX_RCVDET_ST_TMR}, 3723 {0x00F3, TX_PSC_A0}, 3724 {0x04A2, TX_PSC_A2}, 3725 {0x04A2, TX_PSC_A3}, 3726 {0x0000, TX_TXCC_CPOST_MULT_00}, 3727 {0x0000, XCVR_DIAG_PSC_OVRD} 3728}; 3729 3730static const struct cdns_reg_pairs usxgmii_156_25_no_ssc_rx_ln_regs[] = { 3731 {0x0014, RX_SDCAL0_INIT_TMR}, 3732 {0x0062, RX_SDCAL0_ITER_TMR}, 3733 {0x0014, RX_SDCAL1_INIT_TMR}, 3734 {0x0062, RX_SDCAL1_ITER_TMR}, 3735 {0x091D, RX_PSC_A0}, 3736 {0x0900, RX_PSC_A2}, 3737 {0x0100, RX_PSC_A3}, 3738 {0x0030, RX_REE_SMGM_CTRL1}, 3739 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 3740 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 3741 {0x0000, RX_DIAG_DFE_CTRL}, 3742 {0x0019, RX_REE_TAP1_CLIP}, 3743 {0x0019, RX_REE_TAP2TON_CLIP}, 3744 {0x00B9, RX_DIAG_NQST_CTRL}, 3745 {0x0C21, RX_DIAG_DFE_AMP_TUNE_2}, 3746 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 3747 {0x0033, RX_DIAG_PI_RATE}, 3748 {0x0001, RX_DIAG_ACYA}, 3749 {0x018C, RX_CDRLF_CNFG} 3750}; 3751 3752static const struct cdns_torrent_vals sl_usxgmii_156_25_no_ssc_cmn_vals = { 3753 .reg_pairs = sl_usxgmii_156_25_no_ssc_cmn_regs, 3754 .num_regs = ARRAY_SIZE(sl_usxgmii_156_25_no_ssc_cmn_regs), 3755}; 3756 3757static const struct cdns_torrent_vals usxgmii_156_25_no_ssc_tx_ln_vals = { 3758 .reg_pairs = usxgmii_156_25_no_ssc_tx_ln_regs, 3759 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_tx_ln_regs), 3760}; 3761 3762static const struct cdns_torrent_vals usxgmii_156_25_no_ssc_rx_ln_vals = { 3763 .reg_pairs = usxgmii_156_25_no_ssc_rx_ln_regs, 3764 .num_regs = ARRAY_SIZE(usxgmii_156_25_no_ssc_rx_ln_regs), 3765}; 3766 3767/* PCIe and DP link configuration */ 3768static const struct cdns_reg_pairs pcie_dp_link_cmn_regs[] = { 3769 {0x0003, PHY_PLL_CFG}, 3770 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 3771 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1} 3772}; 3773 3774static const struct cdns_reg_pairs pcie_dp_xcvr_diag_ln_regs[] = { 3775 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3776 {0x0001, XCVR_DIAG_HSCLK_DIV}, 3777 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 3778}; 3779 3780static const struct cdns_reg_pairs dp_pcie_xcvr_diag_ln_regs[] = { 3781 {0x0001, XCVR_DIAG_HSCLK_SEL}, 3782 {0x0009, XCVR_DIAG_PLLDRC_CTRL} 3783}; 3784 3785static const struct cdns_torrent_vals pcie_dp_link_cmn_vals = { 3786 .reg_pairs = pcie_dp_link_cmn_regs, 3787 .num_regs = ARRAY_SIZE(pcie_dp_link_cmn_regs), 3788}; 3789 3790static const struct cdns_torrent_vals pcie_dp_xcvr_diag_ln_vals = { 3791 .reg_pairs = pcie_dp_xcvr_diag_ln_regs, 3792 .num_regs = ARRAY_SIZE(pcie_dp_xcvr_diag_ln_regs), 3793}; 3794 3795static const struct cdns_torrent_vals dp_pcie_xcvr_diag_ln_vals = { 3796 .reg_pairs = dp_pcie_xcvr_diag_ln_regs, 3797 .num_regs = ARRAY_SIZE(dp_pcie_xcvr_diag_ln_regs), 3798}; 3799 3800/* DP Multilink, 100 MHz Ref clk, no SSC */ 3801static const struct cdns_reg_pairs dp_100_no_ssc_cmn_regs[] = { 3802 {0x007F, CMN_TXPUCAL_TUNE}, 3803 {0x007F, CMN_TXPDCAL_TUNE} 3804}; 3805 3806static const struct cdns_reg_pairs dp_100_no_ssc_tx_ln_regs[] = { 3807 {0x00FB, TX_PSC_A0}, 3808 {0x04AA, TX_PSC_A2}, 3809 {0x04AA, TX_PSC_A3}, 3810 {0x000F, XCVR_DIAG_BIDI_CTRL} 3811}; 3812 3813static const struct cdns_reg_pairs dp_100_no_ssc_rx_ln_regs[] = { 3814 {0x0000, RX_PSC_A0}, 3815 {0x0000, RX_PSC_A2}, 3816 {0x0000, RX_PSC_A3}, 3817 {0x0000, RX_PSC_CAL}, 3818 {0x0000, RX_REE_GCSM1_CTRL}, 3819 {0x0000, RX_REE_GCSM2_CTRL}, 3820 {0x0000, RX_REE_PERGCSM_CTRL} 3821}; 3822 3823static const struct cdns_torrent_vals dp_100_no_ssc_cmn_vals = { 3824 .reg_pairs = dp_100_no_ssc_cmn_regs, 3825 .num_regs = ARRAY_SIZE(dp_100_no_ssc_cmn_regs), 3826}; 3827 3828static const struct cdns_torrent_vals dp_100_no_ssc_tx_ln_vals = { 3829 .reg_pairs = dp_100_no_ssc_tx_ln_regs, 3830 .num_regs = ARRAY_SIZE(dp_100_no_ssc_tx_ln_regs), 3831}; 3832 3833static const struct cdns_torrent_vals dp_100_no_ssc_rx_ln_vals = { 3834 .reg_pairs = dp_100_no_ssc_rx_ln_regs, 3835 .num_regs = ARRAY_SIZE(dp_100_no_ssc_rx_ln_regs), 3836}; 3837 3838/* Single DisplayPort(DP) link configuration */ 3839static const struct cdns_reg_pairs sl_dp_link_cmn_regs[] = { 3840 {0x0000, PHY_PLL_CFG}, 3841}; 3842 3843static const struct cdns_reg_pairs sl_dp_xcvr_diag_ln_regs[] = { 3844 {0x0000, XCVR_DIAG_HSCLK_SEL}, 3845 {0x0001, XCVR_DIAG_PLLDRC_CTRL} 3846}; 3847 3848static const struct cdns_torrent_vals sl_dp_link_cmn_vals = { 3849 .reg_pairs = sl_dp_link_cmn_regs, 3850 .num_regs = ARRAY_SIZE(sl_dp_link_cmn_regs), 3851}; 3852 3853static const struct cdns_torrent_vals sl_dp_xcvr_diag_ln_vals = { 3854 .reg_pairs = sl_dp_xcvr_diag_ln_regs, 3855 .num_regs = ARRAY_SIZE(sl_dp_xcvr_diag_ln_regs), 3856}; 3857 3858/* Single DP, 19.2 MHz Ref clk, no SSC */ 3859static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_cmn_regs[] = { 3860 {0x0014, CMN_SSM_BIAS_TMR}, 3861 {0x0027, CMN_PLLSM0_PLLPRE_TMR}, 3862 {0x00A1, CMN_PLLSM0_PLLLOCK_TMR}, 3863 {0x0027, CMN_PLLSM1_PLLPRE_TMR}, 3864 {0x00A1, CMN_PLLSM1_PLLLOCK_TMR}, 3865 {0x0060, CMN_BGCAL_INIT_TMR}, 3866 {0x0060, CMN_BGCAL_ITER_TMR}, 3867 {0x0014, CMN_IBCAL_INIT_TMR}, 3868 {0x0018, CMN_TXPUCAL_INIT_TMR}, 3869 {0x0005, CMN_TXPUCAL_ITER_TMR}, 3870 {0x0018, CMN_TXPDCAL_INIT_TMR}, 3871 {0x0005, CMN_TXPDCAL_ITER_TMR}, 3872 {0x0240, CMN_RXCAL_INIT_TMR}, 3873 {0x0005, CMN_RXCAL_ITER_TMR}, 3874 {0x0002, CMN_SD_CAL_INIT_TMR}, 3875 {0x0002, CMN_SD_CAL_ITER_TMR}, 3876 {0x000B, CMN_SD_CAL_REFTIM_START}, 3877 {0x0137, CMN_SD_CAL_PLLCNT_START}, 3878 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3879 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3880 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3881 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3882 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3883 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3884 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3885 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3886 {0x00C0, CMN_PLL0_VCOCAL_INIT_TMR}, 3887 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 3888 {0x00C0, CMN_PLL1_VCOCAL_INIT_TMR}, 3889 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 3890 {0x0260, CMN_PLL0_VCOCAL_REFTIM_START}, 3891 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3892 {0x0260, CMN_PLL1_VCOCAL_REFTIM_START}, 3893 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3894}; 3895 3896static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_tx_ln_regs[] = { 3897 {0x0780, TX_RCVDET_ST_TMR}, 3898 {0x00FB, TX_PSC_A0}, 3899 {0x04AA, TX_PSC_A2}, 3900 {0x04AA, TX_PSC_A3}, 3901 {0x000F, XCVR_DIAG_BIDI_CTRL} 3902}; 3903 3904static const struct cdns_reg_pairs sl_dp_19_2_no_ssc_rx_ln_regs[] = { 3905 {0x0000, RX_PSC_A0}, 3906 {0x0000, RX_PSC_A2}, 3907 {0x0000, RX_PSC_A3}, 3908 {0x0000, RX_PSC_CAL}, 3909 {0x0000, RX_REE_GCSM1_CTRL}, 3910 {0x0000, RX_REE_GCSM2_CTRL}, 3911 {0x0000, RX_REE_PERGCSM_CTRL} 3912}; 3913 3914static const struct cdns_torrent_vals sl_dp_19_2_no_ssc_cmn_vals = { 3915 .reg_pairs = sl_dp_19_2_no_ssc_cmn_regs, 3916 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_cmn_regs), 3917}; 3918 3919static const struct cdns_torrent_vals sl_dp_19_2_no_ssc_tx_ln_vals = { 3920 .reg_pairs = sl_dp_19_2_no_ssc_tx_ln_regs, 3921 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_tx_ln_regs), 3922}; 3923 3924static const struct cdns_torrent_vals sl_dp_19_2_no_ssc_rx_ln_vals = { 3925 .reg_pairs = sl_dp_19_2_no_ssc_rx_ln_regs, 3926 .num_regs = ARRAY_SIZE(sl_dp_19_2_no_ssc_rx_ln_regs), 3927}; 3928 3929/* Single DP, 25 MHz Ref clk, no SSC */ 3930static const struct cdns_reg_pairs sl_dp_25_no_ssc_cmn_regs[] = { 3931 {0x0019, CMN_SSM_BIAS_TMR}, 3932 {0x0032, CMN_PLLSM0_PLLPRE_TMR}, 3933 {0x00D1, CMN_PLLSM0_PLLLOCK_TMR}, 3934 {0x0032, CMN_PLLSM1_PLLPRE_TMR}, 3935 {0x00D1, CMN_PLLSM1_PLLLOCK_TMR}, 3936 {0x007D, CMN_BGCAL_INIT_TMR}, 3937 {0x007D, CMN_BGCAL_ITER_TMR}, 3938 {0x0019, CMN_IBCAL_INIT_TMR}, 3939 {0x001E, CMN_TXPUCAL_INIT_TMR}, 3940 {0x0006, CMN_TXPUCAL_ITER_TMR}, 3941 {0x001E, CMN_TXPDCAL_INIT_TMR}, 3942 {0x0006, CMN_TXPDCAL_ITER_TMR}, 3943 {0x02EE, CMN_RXCAL_INIT_TMR}, 3944 {0x0006, CMN_RXCAL_ITER_TMR}, 3945 {0x0002, CMN_SD_CAL_INIT_TMR}, 3946 {0x0002, CMN_SD_CAL_ITER_TMR}, 3947 {0x000E, CMN_SD_CAL_REFTIM_START}, 3948 {0x012B, CMN_SD_CAL_PLLCNT_START}, 3949 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 3950 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 3951 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 3952 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 3953 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 3954 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 3955 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 3956 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 3957 {0x00FA, CMN_PLL0_VCOCAL_INIT_TMR}, 3958 {0x0004, CMN_PLL0_VCOCAL_ITER_TMR}, 3959 {0x00FA, CMN_PLL1_VCOCAL_INIT_TMR}, 3960 {0x0004, CMN_PLL1_VCOCAL_ITER_TMR}, 3961 {0x0317, CMN_PLL0_VCOCAL_REFTIM_START}, 3962 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 3963 {0x0317, CMN_PLL1_VCOCAL_REFTIM_START}, 3964 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 3965}; 3966 3967static const struct cdns_reg_pairs sl_dp_25_no_ssc_tx_ln_regs[] = { 3968 {0x09C4, TX_RCVDET_ST_TMR}, 3969 {0x00FB, TX_PSC_A0}, 3970 {0x04AA, TX_PSC_A2}, 3971 {0x04AA, TX_PSC_A3}, 3972 {0x000F, XCVR_DIAG_BIDI_CTRL} 3973}; 3974 3975static const struct cdns_reg_pairs sl_dp_25_no_ssc_rx_ln_regs[] = { 3976 {0x0000, RX_PSC_A0}, 3977 {0x0000, RX_PSC_A2}, 3978 {0x0000, RX_PSC_A3}, 3979 {0x0000, RX_PSC_CAL}, 3980 {0x0000, RX_REE_GCSM1_CTRL}, 3981 {0x0000, RX_REE_GCSM2_CTRL}, 3982 {0x0000, RX_REE_PERGCSM_CTRL} 3983}; 3984 3985static const struct cdns_torrent_vals sl_dp_25_no_ssc_cmn_vals = { 3986 .reg_pairs = sl_dp_25_no_ssc_cmn_regs, 3987 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_cmn_regs), 3988}; 3989 3990static const struct cdns_torrent_vals sl_dp_25_no_ssc_tx_ln_vals = { 3991 .reg_pairs = sl_dp_25_no_ssc_tx_ln_regs, 3992 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_tx_ln_regs), 3993}; 3994 3995static const struct cdns_torrent_vals sl_dp_25_no_ssc_rx_ln_vals = { 3996 .reg_pairs = sl_dp_25_no_ssc_rx_ln_regs, 3997 .num_regs = ARRAY_SIZE(sl_dp_25_no_ssc_rx_ln_regs), 3998}; 3999 4000/* Single DP, 100 MHz Ref clk, no SSC */ 4001static const struct cdns_reg_pairs sl_dp_100_no_ssc_cmn_regs[] = { 4002 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 4003 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 4004}; 4005 4006static const struct cdns_reg_pairs sl_dp_100_no_ssc_tx_ln_regs[] = { 4007 {0x00FB, TX_PSC_A0}, 4008 {0x04AA, TX_PSC_A2}, 4009 {0x04AA, TX_PSC_A3}, 4010 {0x000F, XCVR_DIAG_BIDI_CTRL} 4011}; 4012 4013static const struct cdns_reg_pairs sl_dp_100_no_ssc_rx_ln_regs[] = { 4014 {0x0000, RX_PSC_A0}, 4015 {0x0000, RX_PSC_A2}, 4016 {0x0000, RX_PSC_A3}, 4017 {0x0000, RX_PSC_CAL}, 4018 {0x0000, RX_REE_GCSM1_CTRL}, 4019 {0x0000, RX_REE_GCSM2_CTRL}, 4020 {0x0000, RX_REE_PERGCSM_CTRL} 4021}; 4022 4023static const struct cdns_torrent_vals sl_dp_100_no_ssc_cmn_vals = { 4024 .reg_pairs = sl_dp_100_no_ssc_cmn_regs, 4025 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_cmn_regs), 4026}; 4027 4028static const struct cdns_torrent_vals sl_dp_100_no_ssc_tx_ln_vals = { 4029 .reg_pairs = sl_dp_100_no_ssc_tx_ln_regs, 4030 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_tx_ln_regs), 4031}; 4032 4033static const struct cdns_torrent_vals sl_dp_100_no_ssc_rx_ln_vals = { 4034 .reg_pairs = sl_dp_100_no_ssc_rx_ln_regs, 4035 .num_regs = ARRAY_SIZE(sl_dp_100_no_ssc_rx_ln_regs), 4036}; 4037 4038/* USB and SGMII/QSGMII link configuration */ 4039static const struct cdns_reg_pairs usb_sgmii_link_cmn_regs[] = { 4040 {0x0002, PHY_PLL_CFG}, 4041 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0}, 4042 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 4043}; 4044 4045static const struct cdns_reg_pairs usb_sgmii_xcvr_diag_ln_regs[] = { 4046 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4047 {0x0001, XCVR_DIAG_HSCLK_DIV}, 4048 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 4049}; 4050 4051static const struct cdns_reg_pairs sgmii_usb_xcvr_diag_ln_regs[] = { 4052 {0x0011, XCVR_DIAG_HSCLK_SEL}, 4053 {0x0003, XCVR_DIAG_HSCLK_DIV}, 4054 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 4055}; 4056 4057static const struct cdns_torrent_vals usb_sgmii_link_cmn_vals = { 4058 .reg_pairs = usb_sgmii_link_cmn_regs, 4059 .num_regs = ARRAY_SIZE(usb_sgmii_link_cmn_regs), 4060}; 4061 4062static const struct cdns_torrent_vals usb_sgmii_xcvr_diag_ln_vals = { 4063 .reg_pairs = usb_sgmii_xcvr_diag_ln_regs, 4064 .num_regs = ARRAY_SIZE(usb_sgmii_xcvr_diag_ln_regs), 4065}; 4066 4067static const struct cdns_torrent_vals sgmii_usb_xcvr_diag_ln_vals = { 4068 .reg_pairs = sgmii_usb_xcvr_diag_ln_regs, 4069 .num_regs = ARRAY_SIZE(sgmii_usb_xcvr_diag_ln_regs), 4070}; 4071 4072/* PCIe and USB Unique SSC link configuration */ 4073static const struct cdns_reg_pairs pcie_usb_link_cmn_regs[] = { 4074 {0x0003, PHY_PLL_CFG}, 4075 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 4076 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 4077 {0x8600, CMN_PDIAG_PLL1_CLK_SEL_M0} 4078}; 4079 4080static const struct cdns_reg_pairs pcie_usb_xcvr_diag_ln_regs[] = { 4081 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4082 {0x0001, XCVR_DIAG_HSCLK_DIV}, 4083 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 4084}; 4085 4086static const struct cdns_reg_pairs usb_pcie_xcvr_diag_ln_regs[] = { 4087 {0x0011, XCVR_DIAG_HSCLK_SEL}, 4088 {0x0001, XCVR_DIAG_HSCLK_DIV}, 4089 {0x00C9, XCVR_DIAG_PLLDRC_CTRL} 4090}; 4091 4092static const struct cdns_torrent_vals pcie_usb_link_cmn_vals = { 4093 .reg_pairs = pcie_usb_link_cmn_regs, 4094 .num_regs = ARRAY_SIZE(pcie_usb_link_cmn_regs), 4095}; 4096 4097static const struct cdns_torrent_vals pcie_usb_xcvr_diag_ln_vals = { 4098 .reg_pairs = pcie_usb_xcvr_diag_ln_regs, 4099 .num_regs = ARRAY_SIZE(pcie_usb_xcvr_diag_ln_regs), 4100}; 4101 4102static const struct cdns_torrent_vals usb_pcie_xcvr_diag_ln_vals = { 4103 .reg_pairs = usb_pcie_xcvr_diag_ln_regs, 4104 .num_regs = ARRAY_SIZE(usb_pcie_xcvr_diag_ln_regs), 4105}; 4106 4107/* USB 100 MHz Ref clk, internal SSC */ 4108static const struct cdns_reg_pairs usb_100_int_ssc_cmn_regs[] = { 4109 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4110 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4111 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4112 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4113 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4114 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4115 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4116 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4117 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4118 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4119 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4120 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4121 {0x0064, CMN_PLL0_INTDIV_M0}, 4122 {0x0050, CMN_PLL0_INTDIV_M1}, 4123 {0x0064, CMN_PLL1_INTDIV_M0}, 4124 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4125 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4126 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4127 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4128 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4129 {0x0044, CMN_PLL1_HIGH_THR_M0}, 4130 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4131 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4132 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4133 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4134 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4135 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4136 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4137 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4138 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4139 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4140 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4141 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 4142 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4143 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4144 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 4145 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4146 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4147 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4148 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4149 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4150 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4151 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4152 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4153 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4154 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 4155 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 4156 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 4157 {0x007F, CMN_TXPUCAL_TUNE}, 4158 {0x007F, CMN_TXPDCAL_TUNE} 4159}; 4160 4161static const struct cdns_torrent_vals usb_100_int_ssc_cmn_vals = { 4162 .reg_pairs = usb_100_int_ssc_cmn_regs, 4163 .num_regs = ARRAY_SIZE(usb_100_int_ssc_cmn_regs), 4164}; 4165 4166/* Single USB link configuration */ 4167static const struct cdns_reg_pairs sl_usb_link_cmn_regs[] = { 4168 {0x0000, PHY_PLL_CFG}, 4169 {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} 4170}; 4171 4172static const struct cdns_reg_pairs sl_usb_xcvr_diag_ln_regs[] = { 4173 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4174 {0x0001, XCVR_DIAG_HSCLK_DIV}, 4175 {0x0041, XCVR_DIAG_PLLDRC_CTRL} 4176}; 4177 4178static const struct cdns_torrent_vals sl_usb_link_cmn_vals = { 4179 .reg_pairs = sl_usb_link_cmn_regs, 4180 .num_regs = ARRAY_SIZE(sl_usb_link_cmn_regs), 4181}; 4182 4183static const struct cdns_torrent_vals sl_usb_xcvr_diag_ln_vals = { 4184 .reg_pairs = sl_usb_xcvr_diag_ln_regs, 4185 .num_regs = ARRAY_SIZE(sl_usb_xcvr_diag_ln_regs), 4186}; 4187 4188/* USB PHY PCS common configuration */ 4189static const struct cdns_reg_pairs usb_phy_pcs_cmn_regs[] = { 4190 {0x0A0A, PHY_PIPE_USB3_GEN2_PRE_CFG0}, 4191 {0x1000, PHY_PIPE_USB3_GEN2_POST_CFG0}, 4192 {0x0010, PHY_PIPE_USB3_GEN2_POST_CFG1} 4193}; 4194 4195static const struct cdns_torrent_vals usb_phy_pcs_cmn_vals = { 4196 .reg_pairs = usb_phy_pcs_cmn_regs, 4197 .num_regs = ARRAY_SIZE(usb_phy_pcs_cmn_regs), 4198}; 4199 4200/* USB 100 MHz Ref clk, no SSC */ 4201static const struct cdns_reg_pairs sl_usb_100_no_ssc_cmn_regs[] = { 4202 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4203 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4204 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 4205 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 4206 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 4207 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 4208 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 4209}; 4210 4211static const struct cdns_torrent_vals sl_usb_100_no_ssc_cmn_vals = { 4212 .reg_pairs = sl_usb_100_no_ssc_cmn_regs, 4213 .num_regs = ARRAY_SIZE(sl_usb_100_no_ssc_cmn_regs), 4214}; 4215 4216static const struct cdns_reg_pairs usb_100_no_ssc_cmn_regs[] = { 4217 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 4218 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD}, 4219 {0x007F, CMN_TXPUCAL_TUNE}, 4220 {0x007F, CMN_TXPDCAL_TUNE} 4221}; 4222 4223static const struct cdns_reg_pairs usb_100_no_ssc_tx_ln_regs[] = { 4224 {0x02FF, TX_PSC_A0}, 4225 {0x06AF, TX_PSC_A1}, 4226 {0x06AE, TX_PSC_A2}, 4227 {0x06AE, TX_PSC_A3}, 4228 {0x2A82, TX_TXCC_CTRL}, 4229 {0x0014, TX_TXCC_CPOST_MULT_01}, 4230 {0x0003, XCVR_DIAG_PSC_OVRD} 4231}; 4232 4233static const struct cdns_reg_pairs usb_100_no_ssc_rx_ln_regs[] = { 4234 {0x0D1D, RX_PSC_A0}, 4235 {0x0D1D, RX_PSC_A1}, 4236 {0x0D00, RX_PSC_A2}, 4237 {0x0500, RX_PSC_A3}, 4238 {0x0013, RX_SIGDET_HL_FILT_TMR}, 4239 {0x0000, RX_REE_GCSM1_CTRL}, 4240 {0x0C02, RX_REE_ATTEN_THR}, 4241 {0x0330, RX_REE_SMGM_CTRL1}, 4242 {0x0300, RX_REE_SMGM_CTRL2}, 4243 {0x0000, RX_REE_PEAK_UTHR}, 4244 {0x01F5, RX_REE_PEAK_LTHR}, 4245 {0x0019, RX_REE_TAP1_CLIP}, 4246 {0x0019, RX_REE_TAP2TON_CLIP}, 4247 {0x1004, RX_DIAG_SIGDET_TUNE}, 4248 {0x00F9, RX_DIAG_NQST_CTRL}, 4249 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 4250 {0x0002, RX_DIAG_DFE_AMP_TUNE_3}, 4251 {0x0000, RX_DIAG_PI_CAP}, 4252 {0x0031, RX_DIAG_PI_RATE}, 4253 {0x0001, RX_DIAG_ACYA}, 4254 {0x018C, RX_CDRLF_CNFG}, 4255 {0x0003, RX_CDRLF_CNFG3} 4256}; 4257 4258static const struct cdns_torrent_vals usb_100_no_ssc_cmn_vals = { 4259 .reg_pairs = usb_100_no_ssc_cmn_regs, 4260 .num_regs = ARRAY_SIZE(usb_100_no_ssc_cmn_regs), 4261}; 4262 4263static const struct cdns_torrent_vals usb_100_no_ssc_tx_ln_vals = { 4264 .reg_pairs = usb_100_no_ssc_tx_ln_regs, 4265 .num_regs = ARRAY_SIZE(usb_100_no_ssc_tx_ln_regs), 4266}; 4267 4268static const struct cdns_torrent_vals usb_100_no_ssc_rx_ln_vals = { 4269 .reg_pairs = usb_100_no_ssc_rx_ln_regs, 4270 .num_regs = ARRAY_SIZE(usb_100_no_ssc_rx_ln_regs), 4271}; 4272 4273/* Single link USB, 100 MHz Ref clk, internal SSC */ 4274static const struct cdns_reg_pairs sl_usb_100_int_ssc_cmn_regs[] = { 4275 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4276 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4277 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4278 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4279 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4280 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4281 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4282 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4283 {0x0064, CMN_PLL0_INTDIV_M0}, 4284 {0x0064, CMN_PLL1_INTDIV_M0}, 4285 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4286 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4287 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4288 {0x0044, CMN_PLL1_HIGH_THR_M0}, 4289 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4290 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4291 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4292 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4293 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4294 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4295 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4296 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 4297 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4298 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 4299 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4300 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4301 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4302 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4303 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 4304 {0x0003, CMN_PLL1_VCOCAL_TCTRL}, 4305 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4306 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4307 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4308 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4309 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4310 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 4311 {0x8200, CMN_CDIAG_CDB_PWRI_OVRD}, 4312 {0x8200, CMN_CDIAG_XCVRC_PWRI_OVRD} 4313}; 4314 4315static const struct cdns_torrent_vals sl_usb_100_int_ssc_cmn_vals = { 4316 .reg_pairs = sl_usb_100_int_ssc_cmn_regs, 4317 .num_regs = ARRAY_SIZE(sl_usb_100_int_ssc_cmn_regs), 4318}; 4319 4320/* PCIe and SGMII/QSGMII Unique SSC link configuration */ 4321static const struct cdns_reg_pairs pcie_sgmii_link_cmn_regs[] = { 4322 {0x0003, PHY_PLL_CFG}, 4323 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}, 4324 {0x0400, CMN_PDIAG_PLL0_CLK_SEL_M1}, 4325 {0x0601, CMN_PDIAG_PLL1_CLK_SEL_M0} 4326}; 4327 4328static const struct cdns_reg_pairs pcie_sgmii_xcvr_diag_ln_regs[] = { 4329 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4330 {0x0001, XCVR_DIAG_HSCLK_DIV}, 4331 {0x0012, XCVR_DIAG_PLLDRC_CTRL} 4332}; 4333 4334static const struct cdns_reg_pairs sgmii_pcie_xcvr_diag_ln_regs[] = { 4335 {0x0011, XCVR_DIAG_HSCLK_SEL}, 4336 {0x0003, XCVR_DIAG_HSCLK_DIV}, 4337 {0x009B, XCVR_DIAG_PLLDRC_CTRL} 4338}; 4339 4340static const struct cdns_torrent_vals pcie_sgmii_link_cmn_vals = { 4341 .reg_pairs = pcie_sgmii_link_cmn_regs, 4342 .num_regs = ARRAY_SIZE(pcie_sgmii_link_cmn_regs), 4343}; 4344 4345static const struct cdns_torrent_vals pcie_sgmii_xcvr_diag_ln_vals = { 4346 .reg_pairs = pcie_sgmii_xcvr_diag_ln_regs, 4347 .num_regs = ARRAY_SIZE(pcie_sgmii_xcvr_diag_ln_regs), 4348}; 4349 4350static const struct cdns_torrent_vals sgmii_pcie_xcvr_diag_ln_vals = { 4351 .reg_pairs = sgmii_pcie_xcvr_diag_ln_regs, 4352 .num_regs = ARRAY_SIZE(sgmii_pcie_xcvr_diag_ln_regs), 4353}; 4354 4355/* SGMII 100 MHz Ref clk, no SSC */ 4356static const struct cdns_reg_pairs sl_sgmii_100_no_ssc_cmn_regs[] = { 4357 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4358 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4359 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 4360 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 4361 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 4362}; 4363 4364static const struct cdns_torrent_vals sl_sgmii_100_no_ssc_cmn_vals = { 4365 .reg_pairs = sl_sgmii_100_no_ssc_cmn_regs, 4366 .num_regs = ARRAY_SIZE(sl_sgmii_100_no_ssc_cmn_regs), 4367}; 4368 4369static const struct cdns_reg_pairs sgmii_100_no_ssc_cmn_regs[] = { 4370 {0x007F, CMN_TXPUCAL_TUNE}, 4371 {0x007F, CMN_TXPDCAL_TUNE} 4372}; 4373 4374static const struct cdns_reg_pairs sgmii_100_no_ssc_tx_ln_regs[] = { 4375 {0x00F3, TX_PSC_A0}, 4376 {0x04A2, TX_PSC_A2}, 4377 {0x04A2, TX_PSC_A3}, 4378 {0x0000, TX_TXCC_CPOST_MULT_00}, 4379 {0x00B3, DRV_DIAG_TX_DRV}, 4380 {0x0002, XCVR_DIAG_PSC_OVRD} 4381}; 4382 4383static const struct cdns_reg_pairs ti_sgmii_100_no_ssc_tx_ln_regs[] = { 4384 {0x00F3, TX_PSC_A0}, 4385 {0x04A2, TX_PSC_A2}, 4386 {0x04A2, TX_PSC_A3}, 4387 {0x0000, TX_TXCC_CPOST_MULT_00}, 4388 {0x00B3, DRV_DIAG_TX_DRV}, 4389 {0x0002, XCVR_DIAG_PSC_OVRD}, 4390 {0x4000, XCVR_DIAG_RXCLK_CTRL} 4391}; 4392 4393static const struct cdns_reg_pairs sgmii_100_no_ssc_rx_ln_regs[] = { 4394 {0x091D, RX_PSC_A0}, 4395 {0x0900, RX_PSC_A2}, 4396 {0x0100, RX_PSC_A3}, 4397 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 4398 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 4399 {0x0000, RX_DIAG_DFE_CTRL}, 4400 {0x0019, RX_REE_TAP1_CLIP}, 4401 {0x0019, RX_REE_TAP2TON_CLIP}, 4402 {0x0098, RX_DIAG_NQST_CTRL}, 4403 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 4404 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 4405 {0x0000, RX_DIAG_PI_CAP}, 4406 {0x0010, RX_DIAG_PI_RATE}, 4407 {0x0001, RX_DIAG_ACYA}, 4408 {0x018C, RX_CDRLF_CNFG}, 4409}; 4410 4411static const struct cdns_torrent_vals sgmii_100_no_ssc_cmn_vals = { 4412 .reg_pairs = sgmii_100_no_ssc_cmn_regs, 4413 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_cmn_regs), 4414}; 4415 4416static const struct cdns_torrent_vals sgmii_100_no_ssc_tx_ln_vals = { 4417 .reg_pairs = sgmii_100_no_ssc_tx_ln_regs, 4418 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_tx_ln_regs), 4419}; 4420 4421static const struct cdns_torrent_vals ti_sgmii_100_no_ssc_tx_ln_vals = { 4422 .reg_pairs = ti_sgmii_100_no_ssc_tx_ln_regs, 4423 .num_regs = ARRAY_SIZE(ti_sgmii_100_no_ssc_tx_ln_regs), 4424}; 4425 4426static const struct cdns_torrent_vals sgmii_100_no_ssc_rx_ln_vals = { 4427 .reg_pairs = sgmii_100_no_ssc_rx_ln_regs, 4428 .num_regs = ARRAY_SIZE(sgmii_100_no_ssc_rx_ln_regs), 4429}; 4430 4431/* TI J7200, multilink SGMII */ 4432static const struct cdns_reg_pairs j7200_sgmii_100_no_ssc_tx_ln_regs[] = { 4433 {0x07A2, TX_RCVDET_ST_TMR}, 4434 {0x00F3, TX_PSC_A0}, 4435 {0x04A2, TX_PSC_A2}, 4436 {0x04A2, TX_PSC_A3 }, 4437 {0x0000, TX_TXCC_CPOST_MULT_00}, 4438 {0x00B3, DRV_DIAG_TX_DRV}, 4439 {0x0002, XCVR_DIAG_PSC_OVRD}, 4440 {0x4000, XCVR_DIAG_RXCLK_CTRL} 4441}; 4442 4443static const struct cdns_torrent_vals j7200_sgmii_100_no_ssc_tx_ln_vals = { 4444 .reg_pairs = j7200_sgmii_100_no_ssc_tx_ln_regs, 4445 .num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_tx_ln_regs), 4446}; 4447 4448static const struct cdns_reg_pairs j7200_sgmii_100_no_ssc_rx_ln_regs[] = { 4449 {0x0014, RX_SDCAL0_INIT_TMR}, 4450 {0x0062, RX_SDCAL0_ITER_TMR}, 4451 {0x0014, RX_SDCAL1_INIT_TMR}, 4452 {0x0062, RX_SDCAL1_ITER_TMR}, 4453 {0x091D, RX_PSC_A0}, 4454 {0x0900, RX_PSC_A2}, 4455 {0x0100, RX_PSC_A3}, 4456 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 4457 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 4458 {0x0000, RX_DIAG_DFE_CTRL}, 4459 {0x0019, RX_REE_TAP1_CLIP}, 4460 {0x0019, RX_REE_TAP2TON_CLIP}, 4461 {0x0098, RX_DIAG_NQST_CTRL}, 4462 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 4463 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 4464 {0x0000, RX_DIAG_PI_CAP}, 4465 {0x0010, RX_DIAG_PI_RATE}, 4466 {0x0001, RX_DIAG_ACYA}, 4467 {0x018C, RX_CDRLF_CNFG} 4468}; 4469 4470static const struct cdns_torrent_vals j7200_sgmii_100_no_ssc_rx_ln_vals = { 4471 .reg_pairs = j7200_sgmii_100_no_ssc_rx_ln_regs, 4472 .num_regs = ARRAY_SIZE(j7200_sgmii_100_no_ssc_rx_ln_regs), 4473}; 4474 4475/* SGMII 100 MHz Ref clk, internal SSC */ 4476static const struct cdns_reg_pairs sgmii_100_int_ssc_cmn_regs[] = { 4477 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4478 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4479 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4480 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4481 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4482 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4483 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4484 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4485 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4486 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4487 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4488 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4489 {0x0064, CMN_PLL0_INTDIV_M0}, 4490 {0x0050, CMN_PLL0_INTDIV_M1}, 4491 {0x0064, CMN_PLL1_INTDIV_M0}, 4492 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4493 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4494 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4495 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4496 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4497 {0x0044, CMN_PLL1_HIGH_THR_M0}, 4498 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4499 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4500 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4501 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4502 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4503 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4504 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4505 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4506 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4507 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4508 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4509 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 4510 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4511 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4512 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 4513 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4514 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4515 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4516 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4517 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4518 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4519 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4520 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4521 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4522 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 4523 {0x007F, CMN_TXPUCAL_TUNE}, 4524 {0x007F, CMN_TXPDCAL_TUNE} 4525}; 4526 4527static const struct cdns_torrent_vals sgmii_100_int_ssc_cmn_vals = { 4528 .reg_pairs = sgmii_100_int_ssc_cmn_regs, 4529 .num_regs = ARRAY_SIZE(sgmii_100_int_ssc_cmn_regs), 4530}; 4531 4532/* QSGMII 100 MHz Ref clk, no SSC */ 4533static const struct cdns_reg_pairs sl_qsgmii_100_no_ssc_cmn_regs[] = { 4534 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4535 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4536 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0}, 4537 {0x0003, CMN_PLL0_VCOCAL_TCTRL}, 4538 {0x0003, CMN_PLL1_VCOCAL_TCTRL} 4539}; 4540 4541static const struct cdns_torrent_vals sl_qsgmii_100_no_ssc_cmn_vals = { 4542 .reg_pairs = sl_qsgmii_100_no_ssc_cmn_regs, 4543 .num_regs = ARRAY_SIZE(sl_qsgmii_100_no_ssc_cmn_regs), 4544}; 4545 4546static const struct cdns_reg_pairs qsgmii_100_no_ssc_cmn_regs[] = { 4547 {0x007F, CMN_TXPUCAL_TUNE}, 4548 {0x007F, CMN_TXPDCAL_TUNE} 4549}; 4550 4551static const struct cdns_reg_pairs qsgmii_100_no_ssc_tx_ln_regs[] = { 4552 {0x00F3, TX_PSC_A0}, 4553 {0x04A2, TX_PSC_A2}, 4554 {0x04A2, TX_PSC_A3}, 4555 {0x0000, TX_TXCC_CPOST_MULT_00}, 4556 {0x0011, TX_TXCC_MGNFS_MULT_100}, 4557 {0x0003, DRV_DIAG_TX_DRV}, 4558 {0x0002, XCVR_DIAG_PSC_OVRD} 4559}; 4560 4561static const struct cdns_reg_pairs ti_qsgmii_100_no_ssc_tx_ln_regs[] = { 4562 {0x00F3, TX_PSC_A0}, 4563 {0x04A2, TX_PSC_A2}, 4564 {0x04A2, TX_PSC_A3}, 4565 {0x0000, TX_TXCC_CPOST_MULT_00}, 4566 {0x0011, TX_TXCC_MGNFS_MULT_100}, 4567 {0x0003, DRV_DIAG_TX_DRV}, 4568 {0x0002, XCVR_DIAG_PSC_OVRD}, 4569 {0x4000, XCVR_DIAG_RXCLK_CTRL} 4570}; 4571 4572static const struct cdns_reg_pairs qsgmii_100_no_ssc_rx_ln_regs[] = { 4573 {0x091D, RX_PSC_A0}, 4574 {0x0900, RX_PSC_A2}, 4575 {0x0100, RX_PSC_A3}, 4576 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 4577 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 4578 {0x0000, RX_DIAG_DFE_CTRL}, 4579 {0x0019, RX_REE_TAP1_CLIP}, 4580 {0x0019, RX_REE_TAP2TON_CLIP}, 4581 {0x0098, RX_DIAG_NQST_CTRL}, 4582 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 4583 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 4584 {0x0000, RX_DIAG_PI_CAP}, 4585 {0x0010, RX_DIAG_PI_RATE}, 4586 {0x0001, RX_DIAG_ACYA}, 4587 {0x018C, RX_CDRLF_CNFG}, 4588}; 4589 4590static const struct cdns_torrent_vals qsgmii_100_no_ssc_cmn_vals = { 4591 .reg_pairs = qsgmii_100_no_ssc_cmn_regs, 4592 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_cmn_regs), 4593}; 4594 4595static const struct cdns_torrent_vals qsgmii_100_no_ssc_tx_ln_vals = { 4596 .reg_pairs = qsgmii_100_no_ssc_tx_ln_regs, 4597 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_tx_ln_regs), 4598}; 4599 4600static const struct cdns_torrent_vals ti_qsgmii_100_no_ssc_tx_ln_vals = { 4601 .reg_pairs = ti_qsgmii_100_no_ssc_tx_ln_regs, 4602 .num_regs = ARRAY_SIZE(ti_qsgmii_100_no_ssc_tx_ln_regs), 4603}; 4604 4605static const struct cdns_torrent_vals qsgmii_100_no_ssc_rx_ln_vals = { 4606 .reg_pairs = qsgmii_100_no_ssc_rx_ln_regs, 4607 .num_regs = ARRAY_SIZE(qsgmii_100_no_ssc_rx_ln_regs), 4608}; 4609 4610/* TI J7200, multilink QSGMII */ 4611static const struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_tx_ln_regs[] = { 4612 {0x07A2, TX_RCVDET_ST_TMR}, 4613 {0x00F3, TX_PSC_A0}, 4614 {0x04A2, TX_PSC_A2}, 4615 {0x04A2, TX_PSC_A3 }, 4616 {0x0000, TX_TXCC_CPOST_MULT_00}, 4617 {0x0011, TX_TXCC_MGNFS_MULT_100}, 4618 {0x0003, DRV_DIAG_TX_DRV}, 4619 {0x0002, XCVR_DIAG_PSC_OVRD}, 4620 {0x4000, XCVR_DIAG_RXCLK_CTRL} 4621}; 4622 4623static const struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_tx_ln_vals = { 4624 .reg_pairs = j7200_qsgmii_100_no_ssc_tx_ln_regs, 4625 .num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_tx_ln_regs), 4626}; 4627 4628static const struct cdns_reg_pairs j7200_qsgmii_100_no_ssc_rx_ln_regs[] = { 4629 {0x0014, RX_SDCAL0_INIT_TMR}, 4630 {0x0062, RX_SDCAL0_ITER_TMR}, 4631 {0x0014, RX_SDCAL1_INIT_TMR}, 4632 {0x0062, RX_SDCAL1_ITER_TMR}, 4633 {0x091D, RX_PSC_A0}, 4634 {0x0900, RX_PSC_A2}, 4635 {0x0100, RX_PSC_A3}, 4636 {0x03C7, RX_REE_GCSM1_EQENM_PH1}, 4637 {0x01C7, RX_REE_GCSM1_EQENM_PH2}, 4638 {0x0000, RX_DIAG_DFE_CTRL}, 4639 {0x0019, RX_REE_TAP1_CLIP}, 4640 {0x0019, RX_REE_TAP2TON_CLIP}, 4641 {0x0098, RX_DIAG_NQST_CTRL}, 4642 {0x0C01, RX_DIAG_DFE_AMP_TUNE_2}, 4643 {0x0000, RX_DIAG_DFE_AMP_TUNE_3}, 4644 {0x0000, RX_DIAG_PI_CAP}, 4645 {0x0010, RX_DIAG_PI_RATE}, 4646 {0x0001, RX_DIAG_ACYA}, 4647 {0x018C, RX_CDRLF_CNFG} 4648}; 4649 4650static const struct cdns_torrent_vals j7200_qsgmii_100_no_ssc_rx_ln_vals = { 4651 .reg_pairs = j7200_qsgmii_100_no_ssc_rx_ln_regs, 4652 .num_regs = ARRAY_SIZE(j7200_qsgmii_100_no_ssc_rx_ln_regs), 4653}; 4654 4655/* QSGMII 100 MHz Ref clk, internal SSC */ 4656static const struct cdns_reg_pairs qsgmii_100_int_ssc_cmn_regs[] = { 4657 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4658 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4659 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4660 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4661 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4662 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4663 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4664 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4665 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4666 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4667 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4668 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4669 {0x0064, CMN_PLL0_INTDIV_M0}, 4670 {0x0050, CMN_PLL0_INTDIV_M1}, 4671 {0x0064, CMN_PLL1_INTDIV_M0}, 4672 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4673 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4674 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4675 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4676 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4677 {0x0044, CMN_PLL1_HIGH_THR_M0}, 4678 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4679 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4680 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4681 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4682 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4683 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4684 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4685 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4686 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4687 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4688 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4689 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 4690 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4691 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4692 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 4693 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4694 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4695 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4696 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4697 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4698 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4699 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4700 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4701 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4702 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR}, 4703 {0x007F, CMN_TXPUCAL_TUNE}, 4704 {0x007F, CMN_TXPDCAL_TUNE} 4705}; 4706 4707static const struct cdns_torrent_vals qsgmii_100_int_ssc_cmn_vals = { 4708 .reg_pairs = qsgmii_100_int_ssc_cmn_regs, 4709 .num_regs = ARRAY_SIZE(qsgmii_100_int_ssc_cmn_regs), 4710}; 4711 4712/* Single SGMII/QSGMII link configuration */ 4713static const struct cdns_reg_pairs sl_sgmii_link_cmn_regs[] = { 4714 {0x0000, PHY_PLL_CFG}, 4715 {0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0} 4716}; 4717 4718static const struct cdns_reg_pairs sl_sgmii_xcvr_diag_ln_regs[] = { 4719 {0x0000, XCVR_DIAG_HSCLK_SEL}, 4720 {0x0003, XCVR_DIAG_HSCLK_DIV}, 4721 {0x0013, XCVR_DIAG_PLLDRC_CTRL} 4722}; 4723 4724static const struct cdns_torrent_vals sl_sgmii_link_cmn_vals = { 4725 .reg_pairs = sl_sgmii_link_cmn_regs, 4726 .num_regs = ARRAY_SIZE(sl_sgmii_link_cmn_regs), 4727}; 4728 4729static const struct cdns_torrent_vals sl_sgmii_xcvr_diag_ln_vals = { 4730 .reg_pairs = sl_sgmii_xcvr_diag_ln_regs, 4731 .num_regs = ARRAY_SIZE(sl_sgmii_xcvr_diag_ln_regs), 4732}; 4733 4734/* For PCIe (with some other protocol), 100 MHz Ref clk, internal SSC */ 4735static const struct cdns_reg_pairs pcie_100_int_ssc_cmn_regs[] = { 4736 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4737 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4738 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4739 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4740 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4741 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4742 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4743 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4744 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4745 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4746 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4747 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4748 {0x0064, CMN_PLL0_INTDIV_M0}, 4749 {0x0050, CMN_PLL0_INTDIV_M1}, 4750 {0x0064, CMN_PLL1_INTDIV_M0}, 4751 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4752 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4753 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4754 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4755 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4756 {0x0044, CMN_PLL1_HIGH_THR_M0}, 4757 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4758 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4759 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4760 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4761 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4762 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4763 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4764 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4765 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4766 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4767 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4768 {0x006E, CMN_PLL1_SS_CTRL3_M0}, 4769 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4770 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4771 {0x000E, CMN_PLL1_SS_CTRL4_M0}, 4772 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4773 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4774 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4775 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4776 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4777 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4778 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4779 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4780 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4781 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 4782}; 4783 4784static const struct cdns_torrent_vals pcie_100_int_ssc_cmn_vals = { 4785 .reg_pairs = pcie_100_int_ssc_cmn_regs, 4786 .num_regs = ARRAY_SIZE(pcie_100_int_ssc_cmn_regs), 4787}; 4788 4789/* Single link PCIe, 100 MHz Ref clk, internal SSC */ 4790static const struct cdns_reg_pairs sl_pcie_100_int_ssc_cmn_regs[] = { 4791 {0x0004, CMN_PLL0_DSM_DIAG_M0}, 4792 {0x0004, CMN_PLL0_DSM_DIAG_M1}, 4793 {0x0004, CMN_PLL1_DSM_DIAG_M0}, 4794 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M0}, 4795 {0x0509, CMN_PDIAG_PLL0_CP_PADJ_M1}, 4796 {0x0509, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4797 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M0}, 4798 {0x0F00, CMN_PDIAG_PLL0_CP_IADJ_M1}, 4799 {0x0F00, CMN_PDIAG_PLL1_CP_IADJ_M0}, 4800 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M0}, 4801 {0x0F08, CMN_PDIAG_PLL0_FILT_PADJ_M1}, 4802 {0x0F08, CMN_PDIAG_PLL1_FILT_PADJ_M0}, 4803 {0x0064, CMN_PLL0_INTDIV_M0}, 4804 {0x0050, CMN_PLL0_INTDIV_M1}, 4805 {0x0050, CMN_PLL1_INTDIV_M0}, 4806 {0x0002, CMN_PLL0_FRACDIVH_M0}, 4807 {0x0002, CMN_PLL0_FRACDIVH_M1}, 4808 {0x0002, CMN_PLL1_FRACDIVH_M0}, 4809 {0x0044, CMN_PLL0_HIGH_THR_M0}, 4810 {0x0036, CMN_PLL0_HIGH_THR_M1}, 4811 {0x0036, CMN_PLL1_HIGH_THR_M0}, 4812 {0x0002, CMN_PDIAG_PLL0_CTRL_M0}, 4813 {0x0002, CMN_PDIAG_PLL0_CTRL_M1}, 4814 {0x0002, CMN_PDIAG_PLL1_CTRL_M0}, 4815 {0x0001, CMN_PLL0_SS_CTRL1_M0}, 4816 {0x0001, CMN_PLL0_SS_CTRL1_M1}, 4817 {0x0001, CMN_PLL1_SS_CTRL1_M0}, 4818 {0x011B, CMN_PLL0_SS_CTRL2_M0}, 4819 {0x011B, CMN_PLL0_SS_CTRL2_M1}, 4820 {0x011B, CMN_PLL1_SS_CTRL2_M0}, 4821 {0x006E, CMN_PLL0_SS_CTRL3_M0}, 4822 {0x0058, CMN_PLL0_SS_CTRL3_M1}, 4823 {0x0058, CMN_PLL1_SS_CTRL3_M0}, 4824 {0x000E, CMN_PLL0_SS_CTRL4_M0}, 4825 {0x0012, CMN_PLL0_SS_CTRL4_M1}, 4826 {0x0012, CMN_PLL1_SS_CTRL4_M0}, 4827 {0x0C5E, CMN_PLL0_VCOCAL_REFTIM_START}, 4828 {0x0C5E, CMN_PLL1_VCOCAL_REFTIM_START}, 4829 {0x0C56, CMN_PLL0_VCOCAL_PLLCNT_START}, 4830 {0x0C56, CMN_PLL1_VCOCAL_PLLCNT_START}, 4831 {0x00C7, CMN_PLL0_LOCK_REFCNT_START}, 4832 {0x00C7, CMN_PLL1_LOCK_REFCNT_START}, 4833 {0x00C7, CMN_PLL0_LOCK_PLLCNT_START}, 4834 {0x00C7, CMN_PLL1_LOCK_PLLCNT_START}, 4835 {0x0005, CMN_PLL0_LOCK_PLLCNT_THR}, 4836 {0x0005, CMN_PLL1_LOCK_PLLCNT_THR} 4837}; 4838 4839static const struct cdns_torrent_vals sl_pcie_100_int_ssc_cmn_vals = { 4840 .reg_pairs = sl_pcie_100_int_ssc_cmn_regs, 4841 .num_regs = ARRAY_SIZE(sl_pcie_100_int_ssc_cmn_regs), 4842}; 4843 4844/* PCIe, 100 MHz Ref clk, no SSC & external SSC */ 4845static const struct cdns_reg_pairs pcie_100_ext_no_ssc_cmn_regs[] = { 4846 {0x0028, CMN_PDIAG_PLL1_CP_PADJ_M0}, 4847 {0x001E, CMN_PLL1_DSM_FBH_OVRD_M0}, 4848 {0x000C, CMN_PLL1_DSM_FBL_OVRD_M0} 4849}; 4850 4851static const struct cdns_reg_pairs pcie_100_ext_no_ssc_rx_ln_regs[] = { 4852 {0x0019, RX_REE_TAP1_CLIP}, 4853 {0x0019, RX_REE_TAP2TON_CLIP}, 4854 {0x0001, RX_DIAG_ACYA} 4855}; 4856 4857static const struct cdns_torrent_vals pcie_100_no_ssc_cmn_vals = { 4858 .reg_pairs = pcie_100_ext_no_ssc_cmn_regs, 4859 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_cmn_regs), 4860}; 4861 4862static const struct cdns_torrent_vals pcie_100_no_ssc_rx_ln_vals = { 4863 .reg_pairs = pcie_100_ext_no_ssc_rx_ln_regs, 4864 .num_regs = ARRAY_SIZE(pcie_100_ext_no_ssc_rx_ln_regs), 4865}; 4866 4867static const struct cdns_torrent_vals_entry link_cmn_vals_entries[] = { 4868 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_link_cmn_vals}, 4869 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &pcie_dp_link_cmn_vals}, 4870 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &usb_dp_link_cmn_vals}, 4871 4872 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL}, 4873 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_link_cmn_vals}, 4874 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_link_cmn_vals}, 4875 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_link_cmn_vals}, 4876 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_link_cmn_vals}, 4877 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_link_cmn_vals}, 4878 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_link_cmn_vals}, 4879 4880 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_link_cmn_vals}, 4881 4882 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals}, 4883 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals}, 4884 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_QSGMII), &sgmii_qsgmii_link_cmn_vals}, 4885 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &usb_sgmii_link_cmn_vals}, 4886 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals}, 4887 4888 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_link_cmn_vals}, 4889 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &pcie_sgmii_link_cmn_vals}, 4890 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_SGMII), &sgmii_qsgmii_link_cmn_vals}, 4891 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &usb_sgmii_link_cmn_vals}, 4892 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &usxgmii_sgmii_link_cmn_vals}, 4893 4894 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_link_cmn_vals}, 4895 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &pcie_usb_link_cmn_vals}, 4896 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &ml_pcie_usb_link_cmn_vals}, 4897 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_link_cmn_vals}, 4898 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_link_cmn_vals}, 4899 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_link_cmn_vals}, 4900 4901 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_link_cmn_vals}, 4902 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &pcie_usxgmii_link_cmn_vals}, 4903 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_link_cmn_vals}, 4904 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_link_cmn_vals}, 4905}; 4906 4907static const struct cdns_torrent_vals_entry xcvr_diag_vals_entries[] = { 4908 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_NONE), &sl_dp_xcvr_diag_ln_vals}, 4909 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_PCIE), &dp_pcie_xcvr_diag_ln_vals}, 4910 {CDNS_TORRENT_KEY_ANYCLK(TYPE_DP, TYPE_USB), &dp_usb_xcvr_diag_ln_vals}, 4911 4912 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_NONE), NULL}, 4913 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_PCIE), &ml_pcie_xcvr_diag_ln_vals}, 4914 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_SGMII), &pcie_sgmii_xcvr_diag_ln_vals}, 4915 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_QSGMII), &pcie_sgmii_xcvr_diag_ln_vals}, 4916 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USB), &pcie_usb_xcvr_diag_ln_vals}, 4917 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_DP), &pcie_dp_xcvr_diag_ln_vals}, 4918 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE, TYPE_USXGMII), &pcie_usxgmii_xcvr_diag_ln_vals}, 4919 4920 {CDNS_TORRENT_KEY_ANYCLK(TYPE_PCIE_ML, TYPE_USB), &ml_pcie_usb_xcvr_diag_ln_vals}, 4921 4922 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals}, 4923 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals}, 4924 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_QSGMII), &sgmii_qsgmii_xcvr_diag_ln_vals}, 4925 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals}, 4926 {CDNS_TORRENT_KEY_ANYCLK(TYPE_SGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals}, 4927 4928 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_NONE), &sl_sgmii_xcvr_diag_ln_vals}, 4929 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_PCIE), &sgmii_pcie_xcvr_diag_ln_vals}, 4930 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_SGMII), &sgmii_qsgmii_xcvr_diag_ln_vals}, 4931 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USB), &sgmii_usb_xcvr_diag_ln_vals}, 4932 {CDNS_TORRENT_KEY_ANYCLK(TYPE_QSGMII, TYPE_USXGMII), &sgmii_usxgmii_xcvr_diag_ln_vals}, 4933 4934 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &sl_usb_xcvr_diag_ln_vals}, 4935 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_pcie_xcvr_diag_ln_vals}, 4936 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &usb_ml_pcie_xcvr_diag_ln_vals}, 4937 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_sgmii_xcvr_diag_ln_vals}, 4938 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_sgmii_xcvr_diag_ln_vals}, 4939 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_dp_xcvr_diag_ln_vals}, 4940 4941 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &sl_usxgmii_xcvr_diag_ln_vals}, 4942 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &usxgmii_pcie_xcvr_diag_ln_vals}, 4943 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &usxgmii_sgmii_xcvr_diag_ln_vals}, 4944 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &usxgmii_sgmii_xcvr_diag_ln_vals}, 4945}; 4946 4947static const struct cdns_torrent_vals_entry pcs_cmn_vals_entries[] = { 4948 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_NONE), &usb_phy_pcs_cmn_vals}, 4949 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE), &usb_phy_pcs_cmn_vals}, 4950 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_PCIE_ML), &usb_phy_pcs_cmn_vals}, 4951 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_SGMII), &usb_phy_pcs_cmn_vals}, 4952 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_QSGMII), &usb_phy_pcs_cmn_vals}, 4953 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USB, TYPE_DP), &usb_phy_pcs_cmn_vals}, 4954}; 4955 4956static const struct cdns_torrent_vals_entry cmn_vals_entries[] = { 4957 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals}, 4958 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals}, 4959 4960 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals}, 4961 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals}, 4962 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals}, 4963 4964 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 4965 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 4966 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals}, 4967 4968 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 4969 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 4970 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals}, 4971 4972 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 4973 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 4974 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 4975 4976 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 4977 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 4978 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 4979 4980 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 4981 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 4982 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 4983 4984 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 4985 4986 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 4987 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 4988 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals}, 4989 4990 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals}, 4991 4992 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals}, 4993 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 4994 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals}, 4995 4996 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals}, 4997 4998 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals}, 4999 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 5000 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 5001 5002 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals}, 5003 5004 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5005 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5006 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals}, 5007 5008 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals}, 5009 5010 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5011 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5012 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5013 5014 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5015 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5016 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 5017 5018 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals}, 5019 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 5020 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals}, 5021 5022 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_cmn_vals}, 5023 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 5024 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 5025 5026 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5027 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5028 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 5029 5030 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5031 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5032 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 5033 5034 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals}, 5035 5036 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals}, 5037 5038 /* Dual refclk */ 5039 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL}, 5040 5041 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals}, 5042 5043 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ml_sgmii_pll1_100_no_ssc_cmn_vals}, 5044 5045 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals}, 5046 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals}, 5047 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_pll0_156_25_no_ssc_cmn_vals}, 5048}; 5049 5050static const struct cdns_torrent_vals_entry cdns_tx_ln_vals_entries[] = { 5051 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals}, 5052 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals}, 5053 5054 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals}, 5055 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 5056 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 5057 5058 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 5059 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 5060 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL}, 5061 5062 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL}, 5063 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL}, 5064 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL}, 5065 5066 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL}, 5067 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL}, 5068 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL}, 5069 5070 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL}, 5071 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL}, 5072 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL}, 5073 5074 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL}, 5075 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL}, 5076 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL}, 5077 5078 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 5079 5080 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL}, 5081 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL}, 5082 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL}, 5083 5084 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5085 5086 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5087 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5088 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5089 5090 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5091 5092 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5093 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5094 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5095 5096 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5097 5098 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5099 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5100 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5101 5102 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5103 5104 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5105 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5106 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5107 5108 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5109 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5110 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5111 5112 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5113 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5114 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5115 5116 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5117 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5118 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5119 5120 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5121 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5122 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5123 5124 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5125 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5126 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5127 5128 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5129 5130 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 5131 5132 /* Dual refclk */ 5133 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL}, 5134 5135 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_tx_ln_vals}, 5136 5137 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_tx_ln_vals}, 5138 5139 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5140 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5141 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5142}; 5143 5144static const struct cdns_torrent_vals_entry cdns_rx_ln_vals_entries[] = { 5145 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals}, 5146 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals}, 5147 5148 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals}, 5149 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals}, 5150 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals}, 5151 5152 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5153 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5154 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5155 5156 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals}, 5157 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals}, 5158 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals}, 5159 5160 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5161 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5162 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5163 5164 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5165 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5166 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5167 5168 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5169 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5170 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5171 5172 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5173 5174 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_rx_ln_vals}, 5175 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals}, 5176 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_no_ssc_rx_ln_vals}, 5177 5178 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5179 5180 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5181 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5182 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5183 5184 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5185 5186 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5187 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5188 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5189 5190 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5191 5192 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5193 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5194 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5195 5196 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5197 5198 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5199 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5200 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5201 5202 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5203 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5204 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5205 5206 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5207 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5208 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5209 5210 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5211 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5212 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5213 5214 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5215 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5216 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5217 5218 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5219 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5220 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5221 5222 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5223 5224 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals}, 5225 5226 /* Dual refclk */ 5227 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5228 5229 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5230 5231 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5232 5233 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals}, 5234 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals}, 5235 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals}, 5236}; 5237 5238static const struct cdns_torrent_data cdns_map_torrent = { 5239 .block_offset_shift = 0x2, 5240 .reg_offset_shift = 0x2, 5241 .link_cmn_vals_tbl = { 5242 .entries = link_cmn_vals_entries, 5243 .num_entries = ARRAY_SIZE(link_cmn_vals_entries), 5244 }, 5245 .xcvr_diag_vals_tbl = { 5246 .entries = xcvr_diag_vals_entries, 5247 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries), 5248 }, 5249 .pcs_cmn_vals_tbl = { 5250 .entries = pcs_cmn_vals_entries, 5251 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries), 5252 }, 5253 .cmn_vals_tbl = { 5254 .entries = cmn_vals_entries, 5255 .num_entries = ARRAY_SIZE(cmn_vals_entries), 5256 }, 5257 .tx_ln_vals_tbl = { 5258 .entries = cdns_tx_ln_vals_entries, 5259 .num_entries = ARRAY_SIZE(cdns_tx_ln_vals_entries), 5260 }, 5261 .rx_ln_vals_tbl = { 5262 .entries = cdns_rx_ln_vals_entries, 5263 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries), 5264 }, 5265}; 5266 5267static const struct cdns_torrent_vals_entry j721e_phy_pma_cmn_vals_entries[] = { 5268 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_NONE), &ti_usxgmii_phy_pma_cmn_vals}, 5269 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_PCIE), &ti_usxgmii_phy_pma_cmn_vals}, 5270 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_SGMII), &ti_usxgmii_phy_pma_cmn_vals}, 5271 {CDNS_TORRENT_KEY_ANYCLK(TYPE_USXGMII, TYPE_QSGMII), &ti_usxgmii_phy_pma_cmn_vals}, 5272}; 5273 5274static const struct cdns_torrent_vals_entry ti_tx_ln_vals_entries[] = { 5275 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals}, 5276 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals}, 5277 5278 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals}, 5279 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 5280 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 5281 5282 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 5283 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 5284 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL}, 5285 5286 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL}, 5287 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL}, 5288 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL}, 5289 5290 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL}, 5291 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL}, 5292 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL}, 5293 5294 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL}, 5295 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL}, 5296 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL}, 5297 5298 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL}, 5299 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL}, 5300 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL}, 5301 5302 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 5303 5304 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL}, 5305 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL}, 5306 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL}, 5307 5308 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5309 5310 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5311 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5312 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5313 5314 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5315 5316 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5317 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5318 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5319 5320 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5321 5322 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5323 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5324 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5325 5326 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5327 5328 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5329 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5330 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5331 5332 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5333 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5334 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5335 5336 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5337 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5338 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5339 5340 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5341 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5342 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5343 5344 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5345 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5346 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5347 5348 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5349 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5350 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5351 5352 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5353 5354 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 5355 5356 /* Dual refclk */ 5357 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL}, 5358 5359 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5360 5361 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5362 5363 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5364 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5365 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5366}; 5367 5368static const struct cdns_torrent_data ti_j721e_map_torrent = { 5369 .block_offset_shift = 0x0, 5370 .reg_offset_shift = 0x1, 5371 .link_cmn_vals_tbl = { 5372 .entries = link_cmn_vals_entries, 5373 .num_entries = ARRAY_SIZE(link_cmn_vals_entries), 5374 }, 5375 .xcvr_diag_vals_tbl = { 5376 .entries = xcvr_diag_vals_entries, 5377 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries), 5378 }, 5379 .pcs_cmn_vals_tbl = { 5380 .entries = pcs_cmn_vals_entries, 5381 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries), 5382 }, 5383 .phy_pma_cmn_vals_tbl = { 5384 .entries = j721e_phy_pma_cmn_vals_entries, 5385 .num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries), 5386 }, 5387 .cmn_vals_tbl = { 5388 .entries = cmn_vals_entries, 5389 .num_entries = ARRAY_SIZE(cmn_vals_entries), 5390 }, 5391 .tx_ln_vals_tbl = { 5392 .entries = ti_tx_ln_vals_entries, 5393 .num_entries = ARRAY_SIZE(ti_tx_ln_vals_entries), 5394 }, 5395 .rx_ln_vals_tbl = { 5396 .entries = cdns_rx_ln_vals_entries, 5397 .num_entries = ARRAY_SIZE(cdns_rx_ln_vals_entries), 5398 }, 5399}; 5400 5401/* TI J7200 (Torrent SD0805) */ 5402static const struct cdns_torrent_vals_entry ti_j7200_cmn_vals_entries[] = { 5403 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_cmn_vals}, 5404 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_cmn_vals}, 5405 5406 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_cmn_vals}, 5407 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_cmn_vals}, 5408 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &sl_dp_100_no_ssc_cmn_vals}, 5409 5410 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 5411 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 5412 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &sl_pcie_100_int_ssc_cmn_vals}, 5413 5414 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 5415 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 5416 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals}, 5417 5418 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 5419 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 5420 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 5421 5422 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 5423 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 5424 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 5425 5426 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_cmn_vals}, 5427 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_cmn_vals}, 5428 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_int_ssc_cmn_vals}, 5429 5430 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 5431 5432 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 5433 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &ml_pcie_100_no_ssc_cmn_vals}, 5434 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &ml_pcie_100_int_ssc_cmn_vals}, 5435 5436 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals}, 5437 5438 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_cmn_vals}, 5439 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 5440 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_int_ssc_cmn_vals}, 5441 5442 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sl_sgmii_100_no_ssc_cmn_vals}, 5443 5444 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_cmn_vals}, 5445 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 5446 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_cmn_vals}, 5447 5448 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals}, 5449 5450 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5451 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5452 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_int_ssc_cmn_vals}, 5453 5454 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &sl_qsgmii_100_no_ssc_cmn_vals}, 5455 5456 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5457 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5458 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_cmn_vals}, 5459 5460 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5461 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5462 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 5463 5464 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_cmn_vals}, 5465 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 5466 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_int_ssc_cmn_vals}, 5467 5468 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_cmn_vals}, 5469 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 5470 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_cmn_vals}, 5471 5472 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5473 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5474 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 5475 5476 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5477 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &sl_usb_100_no_ssc_cmn_vals}, 5478 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &sl_usb_100_int_ssc_cmn_vals}, 5479 5480 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_cmn_vals}, 5481 5482 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &sl_usxgmii_156_25_no_ssc_cmn_vals}, 5483 5484 /* Dual refclk */ 5485 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL}, 5486 5487 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals}, 5488 5489 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_ml_sgmii_pll1_100_no_ssc_cmn_vals}, 5490 5491 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_pll1_156_25_no_ssc_cmn_vals}, 5492 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals}, 5493 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &j7200_ml_usxgmii_pll0_156_25_no_ssc_cmn_vals}, 5494}; 5495 5496static const struct cdns_torrent_vals_entry ti_j7200_tx_ln_vals_entries[] = { 5497 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_tx_ln_vals}, 5498 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_tx_ln_vals}, 5499 5500 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_tx_ln_vals}, 5501 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 5502 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_tx_ln_vals}, 5503 5504 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), NULL}, 5505 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), NULL}, 5506 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), NULL}, 5507 5508 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), NULL}, 5509 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), NULL}, 5510 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), NULL}, 5511 5512 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), NULL}, 5513 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), NULL}, 5514 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), NULL}, 5515 5516 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), NULL}, 5517 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), NULL}, 5518 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), NULL}, 5519 5520 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), NULL}, 5521 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), NULL}, 5522 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), NULL}, 5523 5524 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), NULL}, 5525 5526 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), NULL}, 5527 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), NULL}, 5528 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), NULL}, 5529 5530 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5531 5532 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5533 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5534 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5535 5536 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5537 5538 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5539 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5540 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &ti_sgmii_100_no_ssc_tx_ln_vals}, 5541 5542 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5543 5544 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5545 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5546 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5547 5548 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5549 5550 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5551 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5552 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &ti_qsgmii_100_no_ssc_tx_ln_vals}, 5553 5554 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5555 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5556 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5557 5558 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5559 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5560 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5561 5562 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5563 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5564 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5565 5566 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5567 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5568 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5569 5570 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5571 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5572 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_tx_ln_vals}, 5573 5574 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_tx_ln_vals}, 5575 5576 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 5577 5578 /* Dual refclk */ 5579 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), NULL}, 5580 5581 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_tx_ln_vals}, 5582 5583 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_tx_ln_vals}, 5584 5585 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_tx_ln_vals}, 5586 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 5587 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_tx_ln_vals}, 5588}; 5589 5590static const struct cdns_torrent_vals_entry ti_j7200_rx_ln_vals_entries[] = { 5591 {CDNS_TORRENT_KEY(CLK_19_2_MHZ, CLK_19_2_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_19_2_no_ssc_rx_ln_vals}, 5592 {CDNS_TORRENT_KEY(CLK_25_MHZ, CLK_25_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_25_no_ssc_rx_ln_vals}, 5593 5594 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_NONE, NO_SSC), &sl_dp_100_no_ssc_rx_ln_vals}, 5595 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_PCIE, NO_SSC), &dp_100_no_ssc_rx_ln_vals}, 5596 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_DP, TYPE_USB, NO_SSC), &dp_100_no_ssc_rx_ln_vals}, 5597 5598 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5599 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5600 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_NONE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5601 5602 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5603 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5604 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_PCIE, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5605 5606 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5607 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5608 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_SGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5609 5610 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5611 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5612 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_QSGMII, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5613 5614 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5615 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5616 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5617 5618 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE, TYPE_DP, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5619 5620 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5621 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, EXTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5622 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_PCIE_ML, TYPE_USB, INTERNAL_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5623 5624 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_NONE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5625 5626 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5627 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5628 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_PCIE, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5629 5630 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_QSGMII, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5631 5632 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, NO_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5633 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, EXTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5634 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_SGMII, TYPE_USB, INTERNAL_SSC), &sgmii_100_no_ssc_rx_ln_vals}, 5635 5636 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_NONE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5637 5638 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5639 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5640 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_PCIE, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5641 5642 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_SGMII, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5643 5644 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, NO_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5645 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, EXTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5646 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_QSGMII, TYPE_USB, INTERNAL_SSC), &qsgmii_100_no_ssc_rx_ln_vals}, 5647 5648 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5649 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5650 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_NONE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5651 5652 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5653 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5654 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5655 5656 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5657 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5658 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_PCIE_ML, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5659 5660 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5661 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5662 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_SGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5663 5664 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5665 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, EXTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5666 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_QSGMII, INTERNAL_SSC), &usb_100_no_ssc_rx_ln_vals}, 5667 5668 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_100_MHZ, TYPE_USB, TYPE_DP, NO_SSC), &usb_100_no_ssc_rx_ln_vals}, 5669 5670 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_156_25_MHZ, TYPE_USXGMII, TYPE_NONE, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals}, 5671 5672 /* Dual refclk */ 5673 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_PCIE, TYPE_USXGMII, NO_SSC), &pcie_100_no_ssc_rx_ln_vals}, 5674 5675 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_SGMII, TYPE_USXGMII, NO_SSC), &j7200_sgmii_100_no_ssc_rx_ln_vals}, 5676 5677 {CDNS_TORRENT_KEY(CLK_100_MHZ, CLK_156_25_MHZ, TYPE_QSGMII, TYPE_USXGMII, NO_SSC), &j7200_qsgmii_100_no_ssc_rx_ln_vals}, 5678 5679 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_PCIE, NO_SSC), &ml_usxgmii_156_25_no_ssc_rx_ln_vals}, 5680 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_SGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals}, 5681 {CDNS_TORRENT_KEY(CLK_156_25_MHZ, CLK_100_MHZ, TYPE_USXGMII, TYPE_QSGMII, NO_SSC), &usxgmii_156_25_no_ssc_rx_ln_vals}, 5682}; 5683 5684static const struct cdns_torrent_data ti_j7200_map_torrent = { 5685 .block_offset_shift = 0x0, 5686 .reg_offset_shift = 0x1, 5687 .link_cmn_vals_tbl = { 5688 .entries = link_cmn_vals_entries, 5689 .num_entries = ARRAY_SIZE(link_cmn_vals_entries), 5690 }, 5691 .xcvr_diag_vals_tbl = { 5692 .entries = xcvr_diag_vals_entries, 5693 .num_entries = ARRAY_SIZE(xcvr_diag_vals_entries), 5694 }, 5695 .pcs_cmn_vals_tbl = { 5696 .entries = pcs_cmn_vals_entries, 5697 .num_entries = ARRAY_SIZE(pcs_cmn_vals_entries), 5698 }, 5699 .phy_pma_cmn_vals_tbl = { 5700 .entries = j721e_phy_pma_cmn_vals_entries, 5701 .num_entries = ARRAY_SIZE(j721e_phy_pma_cmn_vals_entries), 5702 }, 5703 .cmn_vals_tbl = { 5704 .entries = ti_j7200_cmn_vals_entries, 5705 .num_entries = ARRAY_SIZE(ti_j7200_cmn_vals_entries), 5706 }, 5707 .tx_ln_vals_tbl = { 5708 .entries = ti_j7200_tx_ln_vals_entries, 5709 .num_entries = ARRAY_SIZE(ti_j7200_tx_ln_vals_entries), 5710 }, 5711 .rx_ln_vals_tbl = { 5712 .entries = ti_j7200_rx_ln_vals_entries, 5713 .num_entries = ARRAY_SIZE(ti_j7200_rx_ln_vals_entries), 5714 }, 5715}; 5716 5717static const struct of_device_id cdns_torrent_phy_of_match[] = { 5718 { 5719 .compatible = "cdns,torrent-phy", 5720 .data = &cdns_map_torrent, 5721 }, 5722 { 5723 .compatible = "ti,j721e-serdes-10g", 5724 .data = &ti_j721e_map_torrent, 5725 }, 5726 { 5727 .compatible = "ti,j7200-serdes-10g", 5728 .data = &ti_j7200_map_torrent, 5729 }, 5730 {} 5731}; 5732MODULE_DEVICE_TABLE(of, cdns_torrent_phy_of_match); 5733 5734static struct platform_driver cdns_torrent_phy_driver = { 5735 .probe = cdns_torrent_phy_probe, 5736 .remove = cdns_torrent_phy_remove, 5737 .driver = { 5738 .name = "cdns-torrent-phy", 5739 .of_match_table = cdns_torrent_phy_of_match, 5740 .pm = pm_sleep_ptr(&cdns_torrent_phy_pm_ops), 5741 } 5742}; 5743module_platform_driver(cdns_torrent_phy_driver); 5744 5745MODULE_AUTHOR("Cadence Design Systems, Inc."); 5746MODULE_DESCRIPTION("Cadence Torrent PHY driver"); 5747MODULE_LICENSE("GPL v2");
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