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riscv_pmu_sbi.c
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linux-6.19.14/drivers/perf/riscv_pmu_sbi.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * RISC-V performance counter support. 4 * 5 * Copyright (C) 2021 Western Digital Corporation or its affiliates. 6 * 7 * This code is based on ARM perf event code which is in turn based on 8 * sparc64 and x86 code. 9 */ 10 11#define pr_fmt(fmt) "riscv-pmu-sbi: " fmt 12 13#include <linux/mod_devicetable.h> 14#include <linux/perf/riscv_pmu.h> 15#include <linux/platform_device.h> 16#include <linux/irq.h> 17#include <linux/irqdomain.h> 18#include <linux/of_irq.h> 19#include <linux/of.h> 20#include <linux/cpu_pm.h> 21#include <linux/sched/clock.h> 22#include <linux/soc/andes/irq.h> 23#include <linux/workqueue.h> 24 25#include <asm/errata_list.h> 26#include <asm/sbi.h> 27#include <asm/cpufeature.h> 28#include <asm/vendor_extensions.h> 29#include <asm/vendor_extensions/andes.h> 30 31#define ALT_SBI_PMU_OVERFLOW(__ovl) \ 32asm volatile(ALTERNATIVE_2( \ 33 "csrr %0, " __stringify(CSR_SCOUNTOVF), \ 34 "csrr %0, " __stringify(THEAD_C9XX_CSR_SCOUNTEROF), \ 35 THEAD_VENDOR_ID, ERRATA_THEAD_PMU, \ 36 CONFIG_ERRATA_THEAD_PMU, \ 37 "csrr %0, " __stringify(ANDES_CSR_SCOUNTEROF), \ 38 ANDES_VENDOR_ID, \ 39 RISCV_ISA_VENDOR_EXT_XANDESPMU + RISCV_VENDOR_EXT_ALTERNATIVES_BASE, \ 40 CONFIG_ANDES_CUSTOM_PMU) \ 41 : "=r" (__ovl) : \ 42 : "memory") 43 44#define ALT_SBI_PMU_OVF_CLEAR_PENDING(__irq_mask) \ 45asm volatile(ALTERNATIVE( \ 46 "csrc " __stringify(CSR_IP) ", %0\n\t", \ 47 "csrc " __stringify(ANDES_CSR_SLIP) ", %0\n\t", \ 48 ANDES_VENDOR_ID, \ 49 RISCV_ISA_VENDOR_EXT_XANDESPMU + RISCV_VENDOR_EXT_ALTERNATIVES_BASE, \ 50 CONFIG_ANDES_CUSTOM_PMU) \ 51 : : "r"(__irq_mask) \ 52 : "memory") 53 54#define SYSCTL_NO_USER_ACCESS 0 55#define SYSCTL_USER_ACCESS 1 56#define SYSCTL_LEGACY 2 57 58#define PERF_EVENT_FLAG_NO_USER_ACCESS BIT(SYSCTL_NO_USER_ACCESS) 59#define PERF_EVENT_FLAG_USER_ACCESS BIT(SYSCTL_USER_ACCESS) 60#define PERF_EVENT_FLAG_LEGACY BIT(SYSCTL_LEGACY) 61 62PMU_FORMAT_ATTR(event, "config:0-55"); 63PMU_FORMAT_ATTR(firmware, "config:62-63"); 64 65static bool sbi_v2_available; 66static bool sbi_v3_available; 67static DEFINE_STATIC_KEY_FALSE(sbi_pmu_snapshot_available); 68#define sbi_pmu_snapshot_available() \ 69 static_branch_unlikely(&sbi_pmu_snapshot_available) 70 71static struct attribute *riscv_arch_formats_attr[] = { 72 &format_attr_event.attr, 73 &format_attr_firmware.attr, 74 NULL, 75}; 76 77static struct attribute_group riscv_pmu_format_group = { 78 .name = "format", 79 .attrs = riscv_arch_formats_attr, 80}; 81 82static const struct attribute_group *riscv_pmu_attr_groups[] = { 83 &riscv_pmu_format_group, 84 NULL, 85}; 86 87/* Allow user mode access by default */ 88static int sysctl_perf_user_access __read_mostly = SYSCTL_USER_ACCESS; 89 90/* 91 * RISC-V doesn't have heterogeneous harts yet. This need to be part of 92 * per_cpu in case of harts with different pmu counters 93 */ 94static union sbi_pmu_ctr_info *pmu_ctr_list; 95static bool riscv_pmu_use_irq; 96static unsigned int riscv_pmu_irq_num; 97static unsigned int riscv_pmu_irq_mask; 98static unsigned int riscv_pmu_irq; 99 100/* Cache the available counters in a bitmask */ 101static unsigned long cmask; 102 103static int pmu_event_find_cache(u64 config); 104struct sbi_pmu_event_data { 105 union { 106 union { 107 struct hw_gen_event { 108 uint32_t event_code:16; 109 uint32_t event_type:4; 110 uint32_t reserved:12; 111 } hw_gen_event; 112 struct hw_cache_event { 113 uint32_t result_id:1; 114 uint32_t op_id:2; 115 uint32_t cache_id:13; 116 uint32_t event_type:4; 117 uint32_t reserved:12; 118 } hw_cache_event; 119 }; 120 uint32_t event_idx; 121 }; 122}; 123 124static struct sbi_pmu_event_data pmu_hw_event_map[] = { 125 [PERF_COUNT_HW_CPU_CYCLES] = {.hw_gen_event = { 126 SBI_PMU_HW_CPU_CYCLES, 127 SBI_PMU_EVENT_TYPE_HW, 0}}, 128 [PERF_COUNT_HW_INSTRUCTIONS] = {.hw_gen_event = { 129 SBI_PMU_HW_INSTRUCTIONS, 130 SBI_PMU_EVENT_TYPE_HW, 0}}, 131 [PERF_COUNT_HW_CACHE_REFERENCES] = {.hw_gen_event = { 132 SBI_PMU_HW_CACHE_REFERENCES, 133 SBI_PMU_EVENT_TYPE_HW, 0}}, 134 [PERF_COUNT_HW_CACHE_MISSES] = {.hw_gen_event = { 135 SBI_PMU_HW_CACHE_MISSES, 136 SBI_PMU_EVENT_TYPE_HW, 0}}, 137 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = {.hw_gen_event = { 138 SBI_PMU_HW_BRANCH_INSTRUCTIONS, 139 SBI_PMU_EVENT_TYPE_HW, 0}}, 140 [PERF_COUNT_HW_BRANCH_MISSES] = {.hw_gen_event = { 141 SBI_PMU_HW_BRANCH_MISSES, 142 SBI_PMU_EVENT_TYPE_HW, 0}}, 143 [PERF_COUNT_HW_BUS_CYCLES] = {.hw_gen_event = { 144 SBI_PMU_HW_BUS_CYCLES, 145 SBI_PMU_EVENT_TYPE_HW, 0}}, 146 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = {.hw_gen_event = { 147 SBI_PMU_HW_STALLED_CYCLES_FRONTEND, 148 SBI_PMU_EVENT_TYPE_HW, 0}}, 149 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = {.hw_gen_event = { 150 SBI_PMU_HW_STALLED_CYCLES_BACKEND, 151 SBI_PMU_EVENT_TYPE_HW, 0}}, 152 [PERF_COUNT_HW_REF_CPU_CYCLES] = {.hw_gen_event = { 153 SBI_PMU_HW_REF_CPU_CYCLES, 154 SBI_PMU_EVENT_TYPE_HW, 0}}, 155}; 156 157#define C(x) PERF_COUNT_HW_CACHE_##x 158static struct sbi_pmu_event_data pmu_cache_event_map[PERF_COUNT_HW_CACHE_MAX] 159[PERF_COUNT_HW_CACHE_OP_MAX] 160[PERF_COUNT_HW_CACHE_RESULT_MAX] = { 161 [C(L1D)] = { 162 [C(OP_READ)] = { 163 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 164 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 165 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 166 C(OP_READ), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 167 }, 168 [C(OP_WRITE)] = { 169 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 170 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 171 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 172 C(OP_WRITE), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 173 }, 174 [C(OP_PREFETCH)] = { 175 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 176 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 177 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 178 C(OP_PREFETCH), C(L1D), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 179 }, 180 }, 181 [C(L1I)] = { 182 [C(OP_READ)] = { 183 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 184 C(OP_READ), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 185 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), C(OP_READ), 186 C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 187 }, 188 [C(OP_WRITE)] = { 189 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 190 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 191 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 192 C(OP_WRITE), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 193 }, 194 [C(OP_PREFETCH)] = { 195 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 196 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 197 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 198 C(OP_PREFETCH), C(L1I), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 199 }, 200 }, 201 [C(LL)] = { 202 [C(OP_READ)] = { 203 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 204 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 205 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 206 C(OP_READ), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 207 }, 208 [C(OP_WRITE)] = { 209 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 210 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 211 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 212 C(OP_WRITE), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 213 }, 214 [C(OP_PREFETCH)] = { 215 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 216 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 217 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 218 C(OP_PREFETCH), C(LL), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 219 }, 220 }, 221 [C(DTLB)] = { 222 [C(OP_READ)] = { 223 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 224 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 225 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 226 C(OP_READ), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 227 }, 228 [C(OP_WRITE)] = { 229 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 230 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 231 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 232 C(OP_WRITE), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 233 }, 234 [C(OP_PREFETCH)] = { 235 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 236 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 237 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 238 C(OP_PREFETCH), C(DTLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 239 }, 240 }, 241 [C(ITLB)] = { 242 [C(OP_READ)] = { 243 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 244 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 245 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 246 C(OP_READ), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 247 }, 248 [C(OP_WRITE)] = { 249 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 250 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 251 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 252 C(OP_WRITE), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 253 }, 254 [C(OP_PREFETCH)] = { 255 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 256 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 257 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 258 C(OP_PREFETCH), C(ITLB), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 259 }, 260 }, 261 [C(BPU)] = { 262 [C(OP_READ)] = { 263 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 264 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 265 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 266 C(OP_READ), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 267 }, 268 [C(OP_WRITE)] = { 269 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 270 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 271 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 272 C(OP_WRITE), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 273 }, 274 [C(OP_PREFETCH)] = { 275 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 276 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 277 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 278 C(OP_PREFETCH), C(BPU), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 279 }, 280 }, 281 [C(NODE)] = { 282 [C(OP_READ)] = { 283 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 284 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 285 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 286 C(OP_READ), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 287 }, 288 [C(OP_WRITE)] = { 289 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 290 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 291 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 292 C(OP_WRITE), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 293 }, 294 [C(OP_PREFETCH)] = { 295 [C(RESULT_ACCESS)] = {.hw_cache_event = {C(RESULT_ACCESS), 296 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 297 [C(RESULT_MISS)] = {.hw_cache_event = {C(RESULT_MISS), 298 C(OP_PREFETCH), C(NODE), SBI_PMU_EVENT_TYPE_CACHE, 0}}, 299 }, 300 }, 301}; 302 303static int pmu_sbi_check_event_info(void) 304{ 305 int num_events = ARRAY_SIZE(pmu_hw_event_map) + PERF_COUNT_HW_CACHE_MAX * 306 PERF_COUNT_HW_CACHE_OP_MAX * PERF_COUNT_HW_CACHE_RESULT_MAX; 307 struct riscv_pmu_event_info *event_info_shmem; 308 phys_addr_t base_addr; 309 int i, j, k, result = 0, count = 0; 310 struct sbiret ret; 311 312 event_info_shmem = kcalloc(num_events, sizeof(*event_info_shmem), GFP_KERNEL); 313 if (!event_info_shmem) 314 return -ENOMEM; 315 316 for (i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) 317 event_info_shmem[count++].event_idx = pmu_hw_event_map[i].event_idx; 318 319 for (i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { 320 for (j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) { 321 for (k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) 322 event_info_shmem[count++].event_idx = 323 pmu_cache_event_map[i][j][k].event_idx; 324 } 325 } 326 327 base_addr = __pa(event_info_shmem); 328 if (IS_ENABLED(CONFIG_32BIT)) 329 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO, lower_32_bits(base_addr), 330 upper_32_bits(base_addr), count, 0, 0, 0); 331 else 332 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_EVENT_GET_INFO, base_addr, 0, 333 count, 0, 0, 0); 334 if (ret.error) { 335 result = -EOPNOTSUPP; 336 goto free_mem; 337 } 338 339 for (i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) { 340 if (!(event_info_shmem[i].output & RISCV_PMU_EVENT_INFO_OUTPUT_MASK)) 341 pmu_hw_event_map[i].event_idx = -ENOENT; 342 } 343 344 count = ARRAY_SIZE(pmu_hw_event_map); 345 346 for (i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) { 347 for (j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) { 348 for (k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) { 349 if (!(event_info_shmem[count].output & 350 RISCV_PMU_EVENT_INFO_OUTPUT_MASK)) 351 pmu_cache_event_map[i][j][k].event_idx = -ENOENT; 352 count++; 353 } 354 } 355 } 356 357free_mem: 358 kfree(event_info_shmem); 359 360 return result; 361} 362 363static void pmu_sbi_check_event(struct sbi_pmu_event_data *edata) 364{ 365 struct sbiret ret; 366 367 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, 368 0, cmask, 0, edata->event_idx, 0, 0); 369 if (!ret.error) { 370 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 371 ret.value, 0x1, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); 372 } else if (ret.error == SBI_ERR_NOT_SUPPORTED) { 373 /* This event cannot be monitored by any counter */ 374 edata->event_idx = -ENOENT; 375 } 376} 377 378static void pmu_sbi_check_std_events(struct work_struct *work) 379{ 380 int ret; 381 382 if (sbi_v3_available) { 383 ret = pmu_sbi_check_event_info(); 384 if (ret) 385 pr_err("pmu_sbi_check_event_info failed with error %d\n", ret); 386 return; 387 } 388 389 for (int i = 0; i < ARRAY_SIZE(pmu_hw_event_map); i++) 390 pmu_sbi_check_event(&pmu_hw_event_map[i]); 391 392 for (int i = 0; i < ARRAY_SIZE(pmu_cache_event_map); i++) 393 for (int j = 0; j < ARRAY_SIZE(pmu_cache_event_map[i]); j++) 394 for (int k = 0; k < ARRAY_SIZE(pmu_cache_event_map[i][j]); k++) 395 pmu_sbi_check_event(&pmu_cache_event_map[i][j][k]); 396} 397 398static DECLARE_WORK(check_std_events_work, pmu_sbi_check_std_events); 399 400static int pmu_sbi_ctr_get_width(int idx) 401{ 402 return pmu_ctr_list[idx].width; 403} 404 405static bool pmu_sbi_ctr_is_fw(int cidx) 406{ 407 union sbi_pmu_ctr_info *info; 408 409 info = &pmu_ctr_list[cidx]; 410 if (!info) 411 return false; 412 413 return info->type == SBI_PMU_CTR_TYPE_FW; 414} 415 416int riscv_pmu_get_event_info(u32 type, u64 config, u64 *econfig) 417{ 418 int ret = -ENOENT; 419 420 switch (type) { 421 case PERF_TYPE_HARDWARE: 422 if (config >= PERF_COUNT_HW_MAX) 423 return -EINVAL; 424 ret = pmu_hw_event_map[config].event_idx; 425 break; 426 case PERF_TYPE_HW_CACHE: 427 ret = pmu_event_find_cache(config); 428 break; 429 case PERF_TYPE_RAW: 430 /* 431 * As per SBI v0.3 specification, 432 * -- the upper 16 bits must be unused for a hardware raw event. 433 * As per SBI v2.0 specification, 434 * -- the upper 8 bits must be unused for a hardware raw event. 435 * Bits 63:62 are used to distinguish between raw events 436 * 00 - Hardware raw event 437 * 10 - SBI firmware events 438 * 11 - Risc-V platform specific firmware event 439 */ 440 switch (config >> 62) { 441 case 0: 442 if (sbi_v3_available) { 443 /* Return error any bits [56-63] is set as it is not allowed by the spec */ 444 if (!(config & ~RISCV_PMU_RAW_EVENT_V2_MASK)) { 445 if (econfig) 446 *econfig = config & RISCV_PMU_RAW_EVENT_V2_MASK; 447 ret = RISCV_PMU_RAW_EVENT_V2_IDX; 448 } 449 /* Return error any bits [48-63] is set as it is not allowed by the spec */ 450 } else if (!(config & ~RISCV_PMU_RAW_EVENT_MASK)) { 451 if (econfig) 452 *econfig = config & RISCV_PMU_RAW_EVENT_MASK; 453 ret = RISCV_PMU_RAW_EVENT_IDX; 454 } 455 break; 456 case 2: 457 ret = (config & 0xFFFF) | (SBI_PMU_EVENT_TYPE_FW << 16); 458 break; 459 case 3: 460 /* 461 * For Risc-V platform specific firmware events 462 * Event code - 0xFFFF 463 * Event data - raw event encoding 464 */ 465 ret = SBI_PMU_EVENT_TYPE_FW << 16 | RISCV_PLAT_FW_EVENT; 466 if (econfig) 467 *econfig = config & RISCV_PMU_PLAT_FW_EVENT_MASK; 468 break; 469 default: 470 break; 471 } 472 break; 473 default: 474 break; 475 } 476 477 return ret; 478} 479EXPORT_SYMBOL_GPL(riscv_pmu_get_event_info); 480 481/* 482 * Returns the counter width of a programmable counter and number of hardware 483 * counters. As we don't support heterogeneous CPUs yet, it is okay to just 484 * return the counter width of the first programmable counter. 485 */ 486int riscv_pmu_get_hpm_info(u32 *hw_ctr_width, u32 *num_hw_ctr) 487{ 488 int i; 489 union sbi_pmu_ctr_info *info; 490 u32 hpm_width = 0, hpm_count = 0; 491 492 if (!cmask) 493 return -EINVAL; 494 495 for_each_set_bit(i, &cmask, RISCV_MAX_COUNTERS) { 496 info = &pmu_ctr_list[i]; 497 if (!info) 498 continue; 499 if (!hpm_width && info->csr != CSR_CYCLE && info->csr != CSR_INSTRET) 500 hpm_width = info->width; 501 if (info->type == SBI_PMU_CTR_TYPE_HW) 502 hpm_count++; 503 } 504 505 *hw_ctr_width = hpm_width; 506 *num_hw_ctr = hpm_count; 507 508 return 0; 509} 510EXPORT_SYMBOL_GPL(riscv_pmu_get_hpm_info); 511 512static uint8_t pmu_sbi_csr_index(struct perf_event *event) 513{ 514 return pmu_ctr_list[event->hw.idx].csr - CSR_CYCLE; 515} 516 517static unsigned long pmu_sbi_get_filter_flags(struct perf_event *event) 518{ 519 unsigned long cflags = 0; 520 bool guest_events = false; 521 522 if (event->attr.config1 & RISCV_PMU_CONFIG1_GUEST_EVENTS) 523 guest_events = true; 524 if (event->attr.exclude_kernel) 525 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VSINH : SBI_PMU_CFG_FLAG_SET_SINH; 526 if (event->attr.exclude_user) 527 cflags |= guest_events ? SBI_PMU_CFG_FLAG_SET_VUINH : SBI_PMU_CFG_FLAG_SET_UINH; 528 if (guest_events && event->attr.exclude_hv) 529 cflags |= SBI_PMU_CFG_FLAG_SET_SINH; 530 if (event->attr.exclude_host) 531 cflags |= SBI_PMU_CFG_FLAG_SET_UINH | SBI_PMU_CFG_FLAG_SET_SINH; 532 if (event->attr.exclude_guest) 533 cflags |= SBI_PMU_CFG_FLAG_SET_VSINH | SBI_PMU_CFG_FLAG_SET_VUINH; 534 535 return cflags; 536} 537 538static int pmu_sbi_ctr_get_idx(struct perf_event *event) 539{ 540 struct hw_perf_event *hwc = &event->hw; 541 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); 542 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); 543 struct sbiret ret; 544 int idx; 545 uint64_t cbase = 0, cmask = rvpmu->cmask; 546 unsigned long cflags = 0; 547 548 cflags = pmu_sbi_get_filter_flags(event); 549 550 /* 551 * In legacy mode, we have to force the fixed counters for those events 552 * but not in the user access mode as we want to use the other counters 553 * that support sampling/filtering. 554 */ 555 if ((hwc->flags & PERF_EVENT_FLAG_LEGACY) && (event->attr.type == PERF_TYPE_HARDWARE)) { 556 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES) { 557 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; 558 cmask = 1; 559 } else if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS) { 560 cflags |= SBI_PMU_CFG_FLAG_SKIP_MATCH; 561 cmask = BIT(CSR_INSTRET - CSR_CYCLE); 562 } 563 } 564 565 /* retrieve the available counter index */ 566#if defined(CONFIG_32BIT) 567 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, 568 cmask, cflags, hwc->event_base, hwc->config, 569 hwc->config >> 32); 570#else 571 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_CFG_MATCH, cbase, 572 cmask, cflags, hwc->event_base, hwc->config, 0); 573#endif 574 if (ret.error) { 575 pr_debug("Not able to find a counter for event %lx config %llx\n", 576 hwc->event_base, hwc->config); 577 return sbi_err_map_linux_errno(ret.error); 578 } 579 580 idx = ret.value; 581 if (!test_bit(idx, &rvpmu->cmask) || !pmu_ctr_list[idx].value) 582 return -ENOENT; 583 584 /* Additional sanity check for the counter id */ 585 if (pmu_sbi_ctr_is_fw(idx)) { 586 if (!test_and_set_bit(idx, cpuc->used_fw_ctrs)) 587 return idx; 588 } else { 589 if (!test_and_set_bit(idx, cpuc->used_hw_ctrs)) 590 return idx; 591 } 592 593 return -ENOENT; 594} 595 596static void pmu_sbi_ctr_clear_idx(struct perf_event *event) 597{ 598 599 struct hw_perf_event *hwc = &event->hw; 600 struct riscv_pmu *rvpmu = to_riscv_pmu(event->pmu); 601 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); 602 int idx = hwc->idx; 603 604 if (pmu_sbi_ctr_is_fw(idx)) 605 clear_bit(idx, cpuc->used_fw_ctrs); 606 else 607 clear_bit(idx, cpuc->used_hw_ctrs); 608} 609 610static int pmu_event_find_cache(u64 config) 611{ 612 unsigned int cache_type, cache_op, cache_result, ret; 613 614 cache_type = (config >> 0) & 0xff; 615 if (cache_type >= PERF_COUNT_HW_CACHE_MAX) 616 return -EINVAL; 617 618 cache_op = (config >> 8) & 0xff; 619 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX) 620 return -EINVAL; 621 622 cache_result = (config >> 16) & 0xff; 623 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX) 624 return -EINVAL; 625 626 ret = pmu_cache_event_map[cache_type][cache_op][cache_result].event_idx; 627 628 return ret; 629} 630 631static bool pmu_sbi_is_fw_event(struct perf_event *event) 632{ 633 u32 type = event->attr.type; 634 u64 config = event->attr.config; 635 636 if ((type == PERF_TYPE_RAW) && ((config >> 63) == 1)) 637 return true; 638 else 639 return false; 640} 641 642static int pmu_sbi_event_map(struct perf_event *event, u64 *econfig) 643{ 644 u32 type = event->attr.type; 645 u64 config = event->attr.config; 646 647 /* 648 * Ensure we are finished checking standard hardware events for 649 * validity before allowing userspace to configure any events. 650 */ 651 flush_work(&check_std_events_work); 652 653 return riscv_pmu_get_event_info(type, config, econfig); 654} 655 656static void pmu_sbi_snapshot_free(struct riscv_pmu *pmu) 657{ 658 int cpu; 659 660 for_each_possible_cpu(cpu) { 661 struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu); 662 663 if (!cpu_hw_evt->snapshot_addr) 664 continue; 665 666 free_page((unsigned long)cpu_hw_evt->snapshot_addr); 667 cpu_hw_evt->snapshot_addr = NULL; 668 cpu_hw_evt->snapshot_addr_phys = 0; 669 } 670} 671 672static int pmu_sbi_snapshot_alloc(struct riscv_pmu *pmu) 673{ 674 int cpu; 675 struct page *snapshot_page; 676 677 for_each_possible_cpu(cpu) { 678 struct cpu_hw_events *cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu); 679 680 snapshot_page = alloc_page(GFP_ATOMIC | __GFP_ZERO); 681 if (!snapshot_page) { 682 pmu_sbi_snapshot_free(pmu); 683 return -ENOMEM; 684 } 685 cpu_hw_evt->snapshot_addr = page_to_virt(snapshot_page); 686 cpu_hw_evt->snapshot_addr_phys = page_to_phys(snapshot_page); 687 } 688 689 return 0; 690} 691 692static int pmu_sbi_snapshot_disable(void) 693{ 694 struct sbiret ret; 695 696 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, SBI_SHMEM_DISABLE, 697 SBI_SHMEM_DISABLE, 0, 0, 0, 0); 698 if (ret.error) { 699 pr_warn("failed to disable snapshot shared memory\n"); 700 return sbi_err_map_linux_errno(ret.error); 701 } 702 703 return 0; 704} 705 706static int pmu_sbi_snapshot_setup(struct riscv_pmu *pmu, int cpu) 707{ 708 struct cpu_hw_events *cpu_hw_evt; 709 struct sbiret ret = {0}; 710 711 cpu_hw_evt = per_cpu_ptr(pmu->hw_events, cpu); 712 if (!cpu_hw_evt->snapshot_addr_phys) 713 return -EINVAL; 714 715 if (cpu_hw_evt->snapshot_set_done) 716 return 0; 717 718 if (IS_ENABLED(CONFIG_32BIT)) 719 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, 720 cpu_hw_evt->snapshot_addr_phys, 721 (u64)(cpu_hw_evt->snapshot_addr_phys) >> 32, 0, 0, 0, 0); 722 else 723 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_SNAPSHOT_SET_SHMEM, 724 cpu_hw_evt->snapshot_addr_phys, 0, 0, 0, 0, 0); 725 726 /* Free up the snapshot area memory and fall back to SBI PMU calls without snapshot */ 727 if (ret.error) { 728 if (ret.error != SBI_ERR_NOT_SUPPORTED) 729 pr_warn("pmu snapshot setup failed with error %ld\n", ret.error); 730 return sbi_err_map_linux_errno(ret.error); 731 } 732 733 memset(cpu_hw_evt->snapshot_cval_shcopy, 0, sizeof(u64) * RISCV_MAX_COUNTERS); 734 cpu_hw_evt->snapshot_set_done = true; 735 736 return 0; 737} 738 739static u64 pmu_sbi_ctr_read(struct perf_event *event) 740{ 741 struct hw_perf_event *hwc = &event->hw; 742 int idx = hwc->idx; 743 struct sbiret ret; 744 u64 val = 0; 745 struct riscv_pmu *pmu = to_riscv_pmu(event->pmu); 746 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); 747 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; 748 union sbi_pmu_ctr_info info = pmu_ctr_list[idx]; 749 750 /* Read the value from the shared memory directly only if counter is stopped */ 751 if (sbi_pmu_snapshot_available() && (hwc->state & PERF_HES_STOPPED)) { 752 val = sdata->ctr_values[idx]; 753 return val; 754 } 755 756 if (pmu_sbi_is_fw_event(event)) { 757 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ, 758 hwc->idx, 0, 0, 0, 0, 0); 759 if (ret.error) 760 return 0; 761 762 val = ret.value; 763 if (IS_ENABLED(CONFIG_32BIT) && sbi_v2_available && info.width >= 32) { 764 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_FW_READ_HI, 765 hwc->idx, 0, 0, 0, 0, 0); 766 if (!ret.error) 767 val |= ((u64)ret.value << 32); 768 else 769 WARN_ONCE(1, "Unable to read upper 32 bits of firmware counter error: %ld\n", 770 ret.error); 771 } 772 } else { 773 val = riscv_pmu_ctr_read_csr(info.csr); 774 if (IS_ENABLED(CONFIG_32BIT)) 775 val |= ((u64)riscv_pmu_ctr_read_csr(info.csr + 0x80)) << 32; 776 } 777 778 return val; 779} 780 781static void pmu_sbi_set_scounteren(void *arg) 782{ 783 struct perf_event *event = (struct perf_event *)arg; 784 785 if (event->hw.idx != -1) 786 csr_write(CSR_SCOUNTEREN, 787 csr_read(CSR_SCOUNTEREN) | BIT(pmu_sbi_csr_index(event))); 788} 789 790static void pmu_sbi_reset_scounteren(void *arg) 791{ 792 struct perf_event *event = (struct perf_event *)arg; 793 794 if (event->hw.idx != -1) 795 csr_write(CSR_SCOUNTEREN, 796 csr_read(CSR_SCOUNTEREN) & ~BIT(pmu_sbi_csr_index(event))); 797} 798 799static void pmu_sbi_ctr_start(struct perf_event *event, u64 ival) 800{ 801 struct sbiret ret; 802 struct hw_perf_event *hwc = &event->hw; 803 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; 804 805 /* There is no benefit setting SNAPSHOT FLAG for a single counter */ 806#if defined(CONFIG_32BIT) 807 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 808 1, flag, ival, ival >> 32, 0); 809#else 810 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, hwc->idx, 811 1, flag, ival, 0, 0); 812#endif 813 if (ret.error && (ret.error != SBI_ERR_ALREADY_STARTED)) 814 pr_err("Starting counter idx %d failed with error %d\n", 815 hwc->idx, sbi_err_map_linux_errno(ret.error)); 816 817 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && 818 (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) 819 pmu_sbi_set_scounteren((void *)event); 820} 821 822static void pmu_sbi_ctr_stop(struct perf_event *event, unsigned long flag) 823{ 824 struct sbiret ret; 825 struct hw_perf_event *hwc = &event->hw; 826 struct riscv_pmu *pmu = to_riscv_pmu(event->pmu); 827 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); 828 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; 829 830 if ((hwc->flags & PERF_EVENT_FLAG_USER_ACCESS) && 831 (hwc->flags & PERF_EVENT_FLAG_USER_READ_CNT)) 832 pmu_sbi_reset_scounteren((void *)event); 833 834 if (sbi_pmu_snapshot_available()) 835 flag |= SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; 836 837 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, hwc->idx, 1, flag, 0, 0, 0); 838 if (!ret.error && sbi_pmu_snapshot_available()) { 839 /* 840 * The counter snapshot is based on the index base specified by hwc->idx. 841 * The actual counter value is updated in shared memory at index 0 when counter 842 * mask is 0x01. To ensure accurate counter values, it's necessary to transfer 843 * the counter value to shared memory. However, if hwc->idx is zero, the counter 844 * value is already correctly updated in shared memory, requiring no further 845 * adjustment. 846 */ 847 if (hwc->idx > 0) { 848 sdata->ctr_values[hwc->idx] = sdata->ctr_values[0]; 849 sdata->ctr_values[0] = 0; 850 } 851 } else if (ret.error && (ret.error != SBI_ERR_ALREADY_STOPPED) && 852 flag != SBI_PMU_STOP_FLAG_RESET) { 853 pr_err("Stopping counter idx %d failed with error %d\n", 854 hwc->idx, sbi_err_map_linux_errno(ret.error)); 855 } 856} 857 858static int pmu_sbi_find_num_ctrs(void) 859{ 860 struct sbiret ret; 861 862 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_NUM_COUNTERS, 0, 0, 0, 0, 0, 0); 863 if (!ret.error) 864 return ret.value; 865 else 866 return sbi_err_map_linux_errno(ret.error); 867} 868 869static int pmu_sbi_get_ctrinfo(int nctr, unsigned long *mask) 870{ 871 struct sbiret ret; 872 int i, num_hw_ctr = 0, num_fw_ctr = 0; 873 union sbi_pmu_ctr_info cinfo; 874 875 pmu_ctr_list = kcalloc(nctr, sizeof(*pmu_ctr_list), GFP_KERNEL); 876 if (!pmu_ctr_list) 877 return -ENOMEM; 878 879 for (i = 0; i < nctr; i++) { 880 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_GET_INFO, i, 0, 0, 0, 0, 0); 881 if (ret.error) 882 /* The logical counter ids are not expected to be contiguous */ 883 continue; 884 885 *mask |= BIT(i); 886 887 cinfo.value = ret.value; 888 if (cinfo.type == SBI_PMU_CTR_TYPE_FW) 889 num_fw_ctr++; 890 else 891 num_hw_ctr++; 892 pmu_ctr_list[i].value = cinfo.value; 893 } 894 895 pr_info("%d firmware and %d hardware counters\n", num_fw_ctr, num_hw_ctr); 896 897 return 0; 898} 899 900static inline void pmu_sbi_stop_all(struct riscv_pmu *pmu) 901{ 902 /* 903 * No need to check the error because we are disabling all the counters 904 * which may include counters that are not enabled yet. 905 */ 906 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, 907 0, pmu->cmask, SBI_PMU_STOP_FLAG_RESET, 0, 0, 0); 908} 909 910static inline void pmu_sbi_stop_hw_ctrs(struct riscv_pmu *pmu) 911{ 912 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); 913 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; 914 unsigned long flag = 0; 915 int i, idx; 916 struct sbiret ret; 917 u64 temp_ctr_overflow_mask = 0; 918 919 if (sbi_pmu_snapshot_available()) 920 flag = SBI_PMU_STOP_FLAG_TAKE_SNAPSHOT; 921 922 /* Reset the shadow copy to avoid save/restore any value from previous overflow */ 923 memset(cpu_hw_evt->snapshot_cval_shcopy, 0, sizeof(u64) * RISCV_MAX_COUNTERS); 924 925 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { 926 /* No need to check the error here as we can't do anything about the error */ 927 ret = sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_STOP, i * BITS_PER_LONG, 928 cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0); 929 if (!ret.error && sbi_pmu_snapshot_available()) { 930 /* Save the counter values to avoid clobbering */ 931 for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG) 932 cpu_hw_evt->snapshot_cval_shcopy[i * BITS_PER_LONG + idx] = 933 sdata->ctr_values[idx]; 934 /* Save the overflow mask to avoid clobbering */ 935 temp_ctr_overflow_mask |= sdata->ctr_overflow_mask << (i * BITS_PER_LONG); 936 } 937 } 938 939 /* Restore the counter values to the shared memory for used hw counters */ 940 if (sbi_pmu_snapshot_available()) { 941 for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) 942 sdata->ctr_values[idx] = cpu_hw_evt->snapshot_cval_shcopy[idx]; 943 if (temp_ctr_overflow_mask) 944 sdata->ctr_overflow_mask = temp_ctr_overflow_mask; 945 } 946} 947 948/* 949 * This function starts all the used counters in two step approach. 950 * Any counter that did not overflow can be start in a single step 951 * while the overflowed counters need to be started with updated initialization 952 * value. 953 */ 954static inline void pmu_sbi_start_ovf_ctrs_sbi(struct cpu_hw_events *cpu_hw_evt, 955 u64 ctr_ovf_mask) 956{ 957 int idx = 0, i; 958 struct perf_event *event; 959 unsigned long flag = SBI_PMU_START_FLAG_SET_INIT_VALUE; 960 unsigned long ctr_start_mask = 0; 961 uint64_t max_period; 962 struct hw_perf_event *hwc; 963 u64 init_val = 0; 964 965 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { 966 ctr_start_mask = cpu_hw_evt->used_hw_ctrs[i] & ~ctr_ovf_mask; 967 /* Start all the counters that did not overflow in a single shot */ 968 if (ctr_start_mask) { 969 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, i * BITS_PER_LONG, 970 ctr_start_mask, 0, 0, 0, 0); 971 } 972 } 973 974 /* Reinitialize and start all the counter that overflowed */ 975 while (ctr_ovf_mask) { 976 if (ctr_ovf_mask & 0x01) { 977 event = cpu_hw_evt->events[idx]; 978 hwc = &event->hw; 979 max_period = riscv_pmu_ctr_get_width_mask(event); 980 init_val = local64_read(&hwc->prev_count) & max_period; 981#if defined(CONFIG_32BIT) 982 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, 983 flag, init_val, init_val >> 32, 0); 984#else 985 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx, 1, 986 flag, init_val, 0, 0); 987#endif 988 perf_event_update_userpage(event); 989 } 990 ctr_ovf_mask = ctr_ovf_mask >> 1; 991 idx++; 992 } 993} 994 995static inline void pmu_sbi_start_ovf_ctrs_snapshot(struct cpu_hw_events *cpu_hw_evt, 996 u64 ctr_ovf_mask) 997{ 998 int i, idx = 0; 999 struct perf_event *event; 1000 unsigned long flag = SBI_PMU_START_FLAG_INIT_SNAPSHOT; 1001 u64 max_period, init_val = 0; 1002 struct hw_perf_event *hwc; 1003 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; 1004 1005 for_each_set_bit(idx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { 1006 if (ctr_ovf_mask & BIT(idx)) { 1007 event = cpu_hw_evt->events[idx]; 1008 hwc = &event->hw; 1009 max_period = riscv_pmu_ctr_get_width_mask(event); 1010 init_val = local64_read(&hwc->prev_count) & max_period; 1011 cpu_hw_evt->snapshot_cval_shcopy[idx] = init_val; 1012 } 1013 /* 1014 * We do not need to update the non-overflow counters the previous 1015 * value should have been there already. 1016 */ 1017 } 1018 1019 for (i = 0; i < BITS_TO_LONGS(RISCV_MAX_COUNTERS); i++) { 1020 /* Restore the counter values to relative indices for used hw counters */ 1021 for_each_set_bit(idx, &cpu_hw_evt->used_hw_ctrs[i], BITS_PER_LONG) 1022 sdata->ctr_values[idx] = 1023 cpu_hw_evt->snapshot_cval_shcopy[idx + i * BITS_PER_LONG]; 1024 /* Start all the counters in a single shot */ 1025 sbi_ecall(SBI_EXT_PMU, SBI_EXT_PMU_COUNTER_START, idx * BITS_PER_LONG, 1026 cpu_hw_evt->used_hw_ctrs[i], flag, 0, 0, 0); 1027 } 1028} 1029 1030static void pmu_sbi_start_overflow_mask(struct riscv_pmu *pmu, 1031 u64 ctr_ovf_mask) 1032{ 1033 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); 1034 1035 if (sbi_pmu_snapshot_available()) 1036 pmu_sbi_start_ovf_ctrs_snapshot(cpu_hw_evt, ctr_ovf_mask); 1037 else 1038 pmu_sbi_start_ovf_ctrs_sbi(cpu_hw_evt, ctr_ovf_mask); 1039} 1040 1041static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) 1042{ 1043 struct perf_sample_data data; 1044 struct pt_regs *regs; 1045 struct hw_perf_event *hw_evt; 1046 union sbi_pmu_ctr_info *info; 1047 int lidx, hidx, fidx; 1048 struct riscv_pmu *pmu; 1049 struct perf_event *event; 1050 u64 overflow; 1051 u64 overflowed_ctrs = 0; 1052 struct cpu_hw_events *cpu_hw_evt = dev; 1053 u64 start_clock = sched_clock(); 1054 struct riscv_pmu_snapshot_data *sdata = cpu_hw_evt->snapshot_addr; 1055 1056 if (WARN_ON_ONCE(!cpu_hw_evt)) 1057 return IRQ_NONE; 1058 1059 /* Firmware counter don't support overflow yet */ 1060 fidx = find_first_bit(cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS); 1061 if (fidx == RISCV_MAX_COUNTERS) { 1062 csr_clear(CSR_SIP, BIT(riscv_pmu_irq_num)); 1063 return IRQ_NONE; 1064 } 1065 1066 event = cpu_hw_evt->events[fidx]; 1067 if (!event) { 1068 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); 1069 return IRQ_NONE; 1070 } 1071 1072 pmu = to_riscv_pmu(event->pmu); 1073 pmu_sbi_stop_hw_ctrs(pmu); 1074 1075 /* Overflow status register should only be read after counter are stopped */ 1076 if (sbi_pmu_snapshot_available()) 1077 overflow = sdata->ctr_overflow_mask; 1078 else 1079 ALT_SBI_PMU_OVERFLOW(overflow); 1080 1081 /* 1082 * Overflow interrupt pending bit should only be cleared after stopping 1083 * all the counters to avoid any race condition. 1084 */ 1085 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); 1086 1087 /* No overflow bit is set */ 1088 if (!overflow) 1089 return IRQ_NONE; 1090 1091 regs = get_irq_regs(); 1092 1093 for_each_set_bit(lidx, cpu_hw_evt->used_hw_ctrs, RISCV_MAX_COUNTERS) { 1094 struct perf_event *event = cpu_hw_evt->events[lidx]; 1095 1096 /* Skip if invalid event or user did not request a sampling */ 1097 if (!event || !is_sampling_event(event)) 1098 continue; 1099 1100 info = &pmu_ctr_list[lidx]; 1101 /* Do a sanity check */ 1102 if (!info || info->type != SBI_PMU_CTR_TYPE_HW) 1103 continue; 1104 1105 if (sbi_pmu_snapshot_available()) 1106 /* SBI implementation already updated the logical indicies */ 1107 hidx = lidx; 1108 else 1109 /* compute hardware counter index */ 1110 hidx = info->csr - CSR_CYCLE; 1111 1112 /* check if the corresponding bit is set in scountovf or overflow mask in shmem */ 1113 if (!(overflow & BIT(hidx))) 1114 continue; 1115 1116 /* 1117 * Keep a track of overflowed counters so that they can be started 1118 * with updated initial value. 1119 */ 1120 overflowed_ctrs |= BIT(lidx); 1121 hw_evt = &event->hw; 1122 /* Update the event states here so that we know the state while reading */ 1123 hw_evt->state |= PERF_HES_STOPPED; 1124 riscv_pmu_event_update(event); 1125 hw_evt->state |= PERF_HES_UPTODATE; 1126 perf_sample_data_init(&data, 0, hw_evt->last_period); 1127 if (riscv_pmu_event_set_period(event)) { 1128 /* 1129 * Unlike other ISAs, RISC-V don't have to disable interrupts 1130 * to avoid throttling here. As per the specification, the 1131 * interrupt remains disabled until the OF bit is set. 1132 * Interrupts are enabled again only during the start. 1133 * TODO: We will need to stop the guest counters once 1134 * virtualization support is added. 1135 */ 1136 perf_event_overflow(event, &data, regs); 1137 } 1138 /* Reset the state as we are going to start the counter after the loop */ 1139 hw_evt->state = 0; 1140 } 1141 1142 pmu_sbi_start_overflow_mask(pmu, overflowed_ctrs); 1143 perf_sample_event_took(sched_clock() - start_clock); 1144 1145 return IRQ_HANDLED; 1146} 1147 1148static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) 1149{ 1150 struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); 1151 struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); 1152 1153 /* 1154 * We keep enabling userspace access to CYCLE, TIME and INSTRET via the 1155 * legacy option but that will be removed in the future. 1156 */ 1157 if (sysctl_perf_user_access == SYSCTL_LEGACY) 1158 csr_write(CSR_SCOUNTEREN, 0x7); 1159 else 1160 csr_write(CSR_SCOUNTEREN, 0x2); 1161 1162 /* Stop all the counters so that they can be enabled from perf */ 1163 pmu_sbi_stop_all(pmu); 1164 1165 if (riscv_pmu_use_irq) { 1166 cpu_hw_evt->irq = riscv_pmu_irq; 1167 ALT_SBI_PMU_OVF_CLEAR_PENDING(riscv_pmu_irq_mask); 1168 enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); 1169 } 1170 1171 if (sbi_pmu_snapshot_available()) 1172 return pmu_sbi_snapshot_setup(pmu, cpu); 1173 1174 return 0; 1175} 1176 1177static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) 1178{ 1179 if (riscv_pmu_use_irq) { 1180 disable_percpu_irq(riscv_pmu_irq); 1181 } 1182 1183 /* Disable all counters access for user mode now */ 1184 csr_write(CSR_SCOUNTEREN, 0x0); 1185 1186 if (sbi_pmu_snapshot_available()) 1187 return pmu_sbi_snapshot_disable(); 1188 1189 return 0; 1190} 1191 1192static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pdev) 1193{ 1194 int ret; 1195 struct cpu_hw_events __percpu *hw_events = pmu->hw_events; 1196 struct irq_domain *domain = NULL; 1197 1198 if (riscv_isa_extension_available(NULL, SSCOFPMF)) { 1199 riscv_pmu_irq_num = RV_IRQ_PMU; 1200 riscv_pmu_use_irq = true; 1201 } else if (IS_ENABLED(CONFIG_ERRATA_THEAD_PMU) && 1202 riscv_cached_mvendorid(0) == THEAD_VENDOR_ID && 1203 riscv_cached_marchid(0) == 0 && 1204 riscv_cached_mimpid(0) == 0) { 1205 riscv_pmu_irq_num = THEAD_C9XX_RV_IRQ_PMU; 1206 riscv_pmu_use_irq = true; 1207 } else if (riscv_has_vendor_extension_unlikely(ANDES_VENDOR_ID, 1208 RISCV_ISA_VENDOR_EXT_XANDESPMU) && 1209 IS_ENABLED(CONFIG_ANDES_CUSTOM_PMU)) { 1210 riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMOVI; 1211 riscv_pmu_use_irq = true; 1212 } 1213 1214 riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG); 1215 1216 if (!riscv_pmu_use_irq) 1217 return -EOPNOTSUPP; 1218 1219 domain = irq_find_matching_fwnode(riscv_get_intc_hwnode(), 1220 DOMAIN_BUS_ANY); 1221 if (!domain) { 1222 pr_err("Failed to find INTC IRQ root domain\n"); 1223 return -ENODEV; 1224 } 1225 1226 riscv_pmu_irq = irq_create_mapping(domain, riscv_pmu_irq_num); 1227 if (!riscv_pmu_irq) { 1228 pr_err("Failed to map PMU interrupt for node\n"); 1229 return -ENODEV; 1230 } 1231 1232 ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); 1233 if (ret) { 1234 pr_err("registering percpu irq failed [%d]\n", ret); 1235 return ret; 1236 } 1237 1238 return 0; 1239} 1240 1241#ifdef CONFIG_CPU_PM 1242static int riscv_pm_pmu_notify(struct notifier_block *b, unsigned long cmd, 1243 void *v) 1244{ 1245 struct riscv_pmu *rvpmu = container_of(b, struct riscv_pmu, riscv_pm_nb); 1246 struct cpu_hw_events *cpuc = this_cpu_ptr(rvpmu->hw_events); 1247 int enabled = bitmap_weight(cpuc->used_hw_ctrs, RISCV_MAX_COUNTERS); 1248 struct perf_event *event; 1249 int idx; 1250 1251 if (!enabled) 1252 return NOTIFY_OK; 1253 1254 for (idx = 0; idx < RISCV_MAX_COUNTERS; idx++) { 1255 event = cpuc->events[idx]; 1256 if (!event) 1257 continue; 1258 1259 switch (cmd) { 1260 case CPU_PM_ENTER: 1261 /* 1262 * Stop and update the counter 1263 */ 1264 riscv_pmu_stop(event, PERF_EF_UPDATE); 1265 break; 1266 case CPU_PM_EXIT: 1267 case CPU_PM_ENTER_FAILED: 1268 /* 1269 * Restore and enable the counter. 1270 */ 1271 riscv_pmu_start(event, PERF_EF_RELOAD); 1272 break; 1273 default: 1274 break; 1275 } 1276 } 1277 1278 return NOTIFY_OK; 1279} 1280 1281static int riscv_pm_pmu_register(struct riscv_pmu *pmu) 1282{ 1283 pmu->riscv_pm_nb.notifier_call = riscv_pm_pmu_notify; 1284 return cpu_pm_register_notifier(&pmu->riscv_pm_nb); 1285} 1286 1287static void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) 1288{ 1289 cpu_pm_unregister_notifier(&pmu->riscv_pm_nb); 1290} 1291#else 1292static inline int riscv_pm_pmu_register(struct riscv_pmu *pmu) { return 0; } 1293static inline void riscv_pm_pmu_unregister(struct riscv_pmu *pmu) { } 1294#endif 1295 1296static void riscv_pmu_destroy(struct riscv_pmu *pmu) 1297{ 1298 if (sbi_v2_available) { 1299 if (sbi_pmu_snapshot_available()) { 1300 pmu_sbi_snapshot_disable(); 1301 pmu_sbi_snapshot_free(pmu); 1302 } 1303 } 1304 riscv_pm_pmu_unregister(pmu); 1305 cpuhp_state_remove_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); 1306} 1307 1308static void pmu_sbi_event_init(struct perf_event *event) 1309{ 1310 /* 1311 * The permissions are set at event_init so that we do not depend 1312 * on the sysctl value that can change. 1313 */ 1314 if (sysctl_perf_user_access == SYSCTL_NO_USER_ACCESS) 1315 event->hw.flags |= PERF_EVENT_FLAG_NO_USER_ACCESS; 1316 else if (sysctl_perf_user_access == SYSCTL_USER_ACCESS) 1317 event->hw.flags |= PERF_EVENT_FLAG_USER_ACCESS; 1318 else 1319 event->hw.flags |= PERF_EVENT_FLAG_LEGACY; 1320} 1321 1322static void pmu_sbi_event_mapped(struct perf_event *event, struct mm_struct *mm) 1323{ 1324 if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) 1325 return; 1326 1327 if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) { 1328 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && 1329 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) { 1330 return; 1331 } 1332 } 1333 1334 /* 1335 * The user mmapped the event to directly access it: this is where 1336 * we determine based on sysctl_perf_user_access if we grant userspace 1337 * the direct access to this event. That means that within the same 1338 * task, some events may be directly accessible and some other may not, 1339 * if the user changes the value of sysctl_perf_user_accesss in the 1340 * meantime. 1341 */ 1342 1343 event->hw.flags |= PERF_EVENT_FLAG_USER_READ_CNT; 1344 1345 /* 1346 * We must enable userspace access *before* advertising in the user page 1347 * that it is possible to do so to avoid any race. 1348 * And we must notify all cpus here because threads that currently run 1349 * on other cpus will try to directly access the counter too without 1350 * calling pmu_sbi_ctr_start. 1351 */ 1352 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) 1353 on_each_cpu_mask(mm_cpumask(mm), 1354 pmu_sbi_set_scounteren, (void *)event, 1); 1355} 1356 1357static void pmu_sbi_event_unmapped(struct perf_event *event, struct mm_struct *mm) 1358{ 1359 if (event->hw.flags & PERF_EVENT_FLAG_NO_USER_ACCESS) 1360 return; 1361 1362 if (event->hw.flags & PERF_EVENT_FLAG_LEGACY) { 1363 if (event->attr.config != PERF_COUNT_HW_CPU_CYCLES && 1364 event->attr.config != PERF_COUNT_HW_INSTRUCTIONS) { 1365 return; 1366 } 1367 } 1368 1369 /* 1370 * Here we can directly remove user access since the user does not have 1371 * access to the user page anymore so we avoid the racy window where the 1372 * user could have read cap_user_rdpmc to true right before we disable 1373 * it. 1374 */ 1375 event->hw.flags &= ~PERF_EVENT_FLAG_USER_READ_CNT; 1376 1377 if (event->hw.flags & PERF_EVENT_FLAG_USER_ACCESS) 1378 on_each_cpu_mask(mm_cpumask(mm), 1379 pmu_sbi_reset_scounteren, (void *)event, 1); 1380} 1381 1382static void riscv_pmu_update_counter_access(void *info) 1383{ 1384 if (sysctl_perf_user_access == SYSCTL_LEGACY) 1385 csr_write(CSR_SCOUNTEREN, 0x7); 1386 else 1387 csr_write(CSR_SCOUNTEREN, 0x2); 1388} 1389 1390static int riscv_pmu_proc_user_access_handler(const struct ctl_table *table, 1391 int write, void *buffer, 1392 size_t *lenp, loff_t *ppos) 1393{ 1394 int prev = sysctl_perf_user_access; 1395 int ret = proc_dointvec_minmax(table, write, buffer, lenp, ppos); 1396 1397 /* 1398 * Test against the previous value since we clear SCOUNTEREN when 1399 * sysctl_perf_user_access is set to SYSCTL_USER_ACCESS, but we should 1400 * not do that if that was already the case. 1401 */ 1402 if (ret || !write || prev == sysctl_perf_user_access) 1403 return ret; 1404 1405 on_each_cpu(riscv_pmu_update_counter_access, NULL, 1); 1406 1407 return 0; 1408} 1409 1410static const struct ctl_table sbi_pmu_sysctl_table[] = { 1411 { 1412 .procname = "perf_user_access", 1413 .data = &sysctl_perf_user_access, 1414 .maxlen = sizeof(unsigned int), 1415 .mode = 0644, 1416 .proc_handler = riscv_pmu_proc_user_access_handler, 1417 .extra1 = SYSCTL_ZERO, 1418 .extra2 = SYSCTL_TWO, 1419 }, 1420}; 1421 1422static int pmu_sbi_device_probe(struct platform_device *pdev) 1423{ 1424 struct riscv_pmu *pmu = NULL; 1425 int ret = -ENODEV; 1426 int num_counters; 1427 1428 pr_info("SBI PMU extension is available\n"); 1429 pmu = riscv_pmu_alloc(); 1430 if (!pmu) 1431 return -ENOMEM; 1432 1433 num_counters = pmu_sbi_find_num_ctrs(); 1434 if (num_counters < 0) { 1435 pr_err("SBI PMU extension doesn't provide any counters\n"); 1436 goto out_free; 1437 } 1438 1439 /* It is possible to get from SBI more than max number of counters */ 1440 if (num_counters > RISCV_MAX_COUNTERS) { 1441 num_counters = RISCV_MAX_COUNTERS; 1442 pr_info("SBI returned more than maximum number of counters. Limiting the number of counters to %d\n", num_counters); 1443 } 1444 1445 /* cache all the information about counters now */ 1446 if (pmu_sbi_get_ctrinfo(num_counters, &cmask)) 1447 goto out_free; 1448 1449 ret = pmu_sbi_setup_irqs(pmu, pdev); 1450 if (ret < 0) { 1451 pr_info("Perf sampling/filtering is not supported as sscof extension is not available\n"); 1452 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_INTERRUPT; 1453 pmu->pmu.capabilities |= PERF_PMU_CAP_NO_EXCLUDE; 1454 } 1455 1456 pmu->pmu.attr_groups = riscv_pmu_attr_groups; 1457 pmu->pmu.parent = &pdev->dev; 1458 pmu->cmask = cmask; 1459 pmu->ctr_start = pmu_sbi_ctr_start; 1460 pmu->ctr_stop = pmu_sbi_ctr_stop; 1461 pmu->event_map = pmu_sbi_event_map; 1462 pmu->ctr_get_idx = pmu_sbi_ctr_get_idx; 1463 pmu->ctr_get_width = pmu_sbi_ctr_get_width; 1464 pmu->ctr_clear_idx = pmu_sbi_ctr_clear_idx; 1465 pmu->ctr_read = pmu_sbi_ctr_read; 1466 pmu->event_init = pmu_sbi_event_init; 1467 pmu->event_mapped = pmu_sbi_event_mapped; 1468 pmu->event_unmapped = pmu_sbi_event_unmapped; 1469 pmu->csr_index = pmu_sbi_csr_index; 1470 1471 ret = riscv_pm_pmu_register(pmu); 1472 if (ret) 1473 goto out_unregister; 1474 1475 ret = perf_pmu_register(&pmu->pmu, "cpu", PERF_TYPE_RAW); 1476 if (ret) 1477 goto out_unregister; 1478 1479 /* SBI PMU Snapsphot is only available in SBI v2.0 */ 1480 if (sbi_v2_available) { 1481 int cpu; 1482 1483 ret = pmu_sbi_snapshot_alloc(pmu); 1484 if (ret) 1485 goto out_unregister; 1486 1487 cpu = get_cpu(); 1488 ret = pmu_sbi_snapshot_setup(pmu, cpu); 1489 put_cpu(); 1490 1491 if (ret) { 1492 /* Snapshot is an optional feature. Continue if not available */ 1493 pmu_sbi_snapshot_free(pmu); 1494 } else { 1495 pr_info("SBI PMU snapshot detected\n"); 1496 /* 1497 * We enable it once here for the boot cpu. If snapshot shmem setup 1498 * fails during cpu hotplug process, it will fail to start the cpu 1499 * as we can not handle hetergenous PMUs with different snapshot 1500 * capability. 1501 */ 1502 static_branch_enable(&sbi_pmu_snapshot_available); 1503 } 1504 } 1505 1506 register_sysctl("kernel", sbi_pmu_sysctl_table); 1507 1508 ret = cpuhp_state_add_instance(CPUHP_AP_PERF_RISCV_STARTING, &pmu->node); 1509 if (ret) 1510 goto out_unregister; 1511 1512 /* Asynchronously check which standard events are available */ 1513 schedule_work(&check_std_events_work); 1514 1515 return 0; 1516 1517out_unregister: 1518 riscv_pmu_destroy(pmu); 1519 1520out_free: 1521 kfree(pmu); 1522 return ret; 1523} 1524 1525static struct platform_driver pmu_sbi_driver = { 1526 .probe = pmu_sbi_device_probe, 1527 .driver = { 1528 .name = RISCV_PMU_SBI_PDEV_NAME, 1529 }, 1530}; 1531 1532static int __init pmu_sbi_devinit(void) 1533{ 1534 int ret; 1535 struct platform_device *pdev; 1536 1537 if (sbi_spec_version < sbi_mk_version(0, 3) || 1538 !sbi_probe_extension(SBI_EXT_PMU)) { 1539 return 0; 1540 } 1541 1542 if (sbi_spec_version >= sbi_mk_version(2, 0)) 1543 sbi_v2_available = true; 1544 1545 if (sbi_spec_version >= sbi_mk_version(3, 0)) 1546 sbi_v3_available = true; 1547 1548 ret = cpuhp_setup_state_multi(CPUHP_AP_PERF_RISCV_STARTING, 1549 "perf/riscv/pmu:starting", 1550 pmu_sbi_starting_cpu, pmu_sbi_dying_cpu); 1551 if (ret) { 1552 pr_err("CPU hotplug notifier could not be registered: %d\n", 1553 ret); 1554 return ret; 1555 } 1556 1557 ret = platform_driver_register(&pmu_sbi_driver); 1558 if (ret) 1559 return ret; 1560 1561 pdev = platform_device_register_simple(RISCV_PMU_SBI_PDEV_NAME, -1, NULL, 0); 1562 if (IS_ERR(pdev)) { 1563 platform_driver_unregister(&pmu_sbi_driver); 1564 return PTR_ERR(pdev); 1565 } 1566 1567 /* Notify legacy implementation that SBI pmu is available*/ 1568 riscv_pmu_legacy_skip_init(); 1569 1570 return ret; 1571} 1572device_initcall(pmu_sbi_devinit)
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