hisi_uncore_pmu.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * HiSilicon SoC Hardware event counters support
  4 *
  5 * Copyright (C) 2017 HiSilicon Limited
  6 * Author: Anurup M <anurup.m@huawei.com>
  7 *         Shaokun Zhang <zhangshaokun@hisilicon.com>
  8 *
  9 * This code is based on the uncore PMUs like arm-cci and arm-ccn.
 10 */
 11#include <linux/bitmap.h>
 12#include <linux/bitops.h>
 13#include <linux/bug.h>
 14#include <linux/err.h>
 15#include <linux/errno.h>
 16#include <linux/interrupt.h>
 17#include <linux/property.h>
 18
 19#include <asm/cputype.h>
 20#include <asm/local64.h>
 21
 22#include "hisi_uncore_pmu.h"
 23
 24#define HISI_MAX_PERIOD(nr) (GENMASK_ULL((nr) - 1, 0))
 25
 26/*
 27 * PMU event attributes
 28 */
 29ssize_t hisi_event_sysfs_show(struct device *dev,
 30			      struct device_attribute *attr, char *page)
 31{
 32	struct dev_ext_attribute *eattr;
 33
 34	eattr = container_of(attr, struct dev_ext_attribute, attr);
 35
 36	return sysfs_emit(page, "config=0x%lx\n", (unsigned long)eattr->var);
 37}
 38EXPORT_SYMBOL_NS_GPL(hisi_event_sysfs_show, "HISI_PMU");
 39
 40/*
 41 * sysfs cpumask attributes. For uncore PMU, we only have a single CPU to show
 42 */
 43ssize_t hisi_cpumask_sysfs_show(struct device *dev,
 44				struct device_attribute *attr, char *buf)
 45{
 46	struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
 47
 48	return sysfs_emit(buf, "%d\n", hisi_pmu->on_cpu);
 49}
 50EXPORT_SYMBOL_NS_GPL(hisi_cpumask_sysfs_show, "HISI_PMU");
 51
 52static DEVICE_ATTR(cpumask, 0444, hisi_cpumask_sysfs_show, NULL);
 53
 54static ssize_t hisi_associated_cpus_sysfs_show(struct device *dev,
 55				struct device_attribute *attr, char *buf)
 56{
 57	struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
 58
 59	return cpumap_print_to_pagebuf(true, buf, &hisi_pmu->associated_cpus);
 60}
 61static DEVICE_ATTR(associated_cpus, 0444, hisi_associated_cpus_sysfs_show, NULL);
 62
 63static struct attribute *hisi_pmu_cpumask_attrs[] = {
 64	&dev_attr_cpumask.attr,
 65	&dev_attr_associated_cpus.attr,
 66	NULL
 67};
 68
 69const struct attribute_group hisi_pmu_cpumask_attr_group = {
 70	.attrs = hisi_pmu_cpumask_attrs,
 71};
 72EXPORT_SYMBOL_NS_GPL(hisi_pmu_cpumask_attr_group, "HISI_PMU");
 73
 74ssize_t hisi_uncore_pmu_identifier_attr_show(struct device *dev,
 75					     struct device_attribute *attr,
 76					     char *page)
 77{
 78	struct hisi_pmu *hisi_pmu = to_hisi_pmu(dev_get_drvdata(dev));
 79
 80	return sysfs_emit(page, "0x%08x\n", hisi_pmu->identifier);
 81}
 82EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_identifier_attr_show, "HISI_PMU");
 83
 84static struct device_attribute hisi_pmu_identifier_attr =
 85	__ATTR(identifier, 0444, hisi_uncore_pmu_identifier_attr_show, NULL);
 86
 87static struct attribute *hisi_pmu_identifier_attrs[] = {
 88	&hisi_pmu_identifier_attr.attr,
 89	NULL
 90};
 91
 92const struct attribute_group hisi_pmu_identifier_group = {
 93	.attrs = hisi_pmu_identifier_attrs,
 94};
 95EXPORT_SYMBOL_NS_GPL(hisi_pmu_identifier_group, "HISI_PMU");
 96
 97static bool hisi_validate_event_group(struct perf_event *event)
 98{
 99	struct perf_event *sibling, *leader = event->group_leader;
100	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
101	/* Include count for the event */
102	int counters = 1;
103
104	if (!is_software_event(leader)) {
105		/*
106		 * We must NOT create groups containing mixed PMUs, although
107		 * software events are acceptable
108		 */
109		if (leader->pmu != event->pmu)
110			return false;
111
112		/* Increment counter for the leader */
113		if (leader != event)
114			counters++;
115	}
116
117	for_each_sibling_event(sibling, event->group_leader) {
118		if (is_software_event(sibling))
119			continue;
120		if (sibling->pmu != event->pmu)
121			return false;
122		/* Increment counter for each sibling */
123		counters++;
124	}
125
126	/* The group can not count events more than the counters in the HW */
127	return counters <= hisi_pmu->num_counters;
128}
129
130int hisi_uncore_pmu_get_event_idx(struct perf_event *event)
131{
132	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
133	unsigned long *used_mask = hisi_pmu->pmu_events.used_mask;
134	u32 num_counters = hisi_pmu->num_counters;
135	int idx;
136
137	idx = find_first_zero_bit(used_mask, num_counters);
138	if (idx == num_counters)
139		return -EAGAIN;
140
141	set_bit(idx, used_mask);
142
143	return idx;
144}
145EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_get_event_idx, "HISI_PMU");
146
147static void hisi_uncore_pmu_clear_event_idx(struct hisi_pmu *hisi_pmu, int idx)
148{
149	clear_bit(idx, hisi_pmu->pmu_events.used_mask);
150}
151
152irqreturn_t hisi_uncore_pmu_isr(int irq, void *data)
153{
154	struct hisi_pmu *hisi_pmu = data;
155	struct perf_event *event;
156	unsigned long overflown;
157	int idx;
158
159	overflown = hisi_pmu->ops->get_int_status(hisi_pmu);
160	if (!overflown)
161		return IRQ_NONE;
162
163	/*
164	 * Find the counter index which overflowed if the bit was set
165	 * and handle it.
166	 */
167	for_each_set_bit(idx, &overflown, hisi_pmu->num_counters) {
168		/* Write 1 to clear the IRQ status flag */
169		hisi_pmu->ops->clear_int_status(hisi_pmu, idx);
170		/* Get the corresponding event struct */
171		event = hisi_pmu->pmu_events.hw_events[idx];
172		if (!event)
173			continue;
174
175		hisi_uncore_pmu_event_update(event);
176		hisi_uncore_pmu_set_event_period(event);
177	}
178
179	return IRQ_HANDLED;
180}
181EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_isr, "HISI_PMU");
182
183int hisi_uncore_pmu_init_irq(struct hisi_pmu *hisi_pmu,
184			     struct platform_device *pdev)
185{
186	int irq, ret;
187
188	irq = platform_get_irq(pdev, 0);
189	if (irq < 0)
190		return irq;
191
192	ret = devm_request_irq(&pdev->dev, irq, hisi_uncore_pmu_isr,
193			       IRQF_NOBALANCING | IRQF_NO_THREAD,
194			       dev_name(&pdev->dev), hisi_pmu);
195	if (ret < 0) {
196		dev_err(&pdev->dev,
197			"Fail to request IRQ: %d ret: %d.\n", irq, ret);
198		return ret;
199	}
200
201	hisi_pmu->irq = irq;
202
203	return 0;
204}
205EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_init_irq, "HISI_PMU");
206
207int hisi_uncore_pmu_event_init(struct perf_event *event)
208{
209	struct hw_perf_event *hwc = &event->hw;
210	struct hisi_pmu *hisi_pmu;
211
212	if (event->attr.type != event->pmu->type)
213		return -ENOENT;
214
215	/*
216	 * We do not support sampling as the counters are all
217	 * shared by all CPU cores in a CPU die(SCCL). Also we
218	 * do not support attach to a task(per-process mode)
219	 */
220	if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK)
221		return -EOPNOTSUPP;
222
223	/*
224	 *  The uncore counters not specific to any CPU, so cannot
225	 *  support per-task
226	 */
227	if (event->cpu < 0)
228		return -EINVAL;
229
230	/*
231	 * Validate if the events in group does not exceed the
232	 * available counters in hardware.
233	 */
234	if (!hisi_validate_event_group(event))
235		return -EINVAL;
236
237	hisi_pmu = to_hisi_pmu(event->pmu);
238	if ((event->attr.config & HISI_EVENTID_MASK) > hisi_pmu->check_event)
239		return -EINVAL;
240
241	if (hisi_pmu->on_cpu == -1)
242		return -EINVAL;
243	/*
244	 * We don't assign an index until we actually place the event onto
245	 * hardware. Use -1 to signify that we haven't decided where to put it
246	 * yet.
247	 */
248	hwc->idx		= -1;
249	hwc->config_base	= event->attr.config;
250
251	if (hisi_pmu->ops->check_filter && hisi_pmu->ops->check_filter(event))
252		return -EINVAL;
253
254	/* Enforce to use the same CPU for all events in this PMU */
255	event->cpu = hisi_pmu->on_cpu;
256
257	return 0;
258}
259EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_event_init, "HISI_PMU");
260
261/*
262 * Set the counter to count the event that we're interested in,
263 * and enable interrupt and counter.
264 */
265static void hisi_uncore_pmu_enable_event(struct perf_event *event)
266{
267	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
268	struct hw_perf_event *hwc = &event->hw;
269
270	hisi_pmu->ops->write_evtype(hisi_pmu, hwc->idx,
271				    HISI_GET_EVENTID(event));
272
273	if (hisi_pmu->ops->enable_filter)
274		hisi_pmu->ops->enable_filter(event);
275
276	hisi_pmu->ops->enable_counter_int(hisi_pmu, hwc);
277	hisi_pmu->ops->enable_counter(hisi_pmu, hwc);
278}
279
280/*
281 * Disable counter and interrupt.
282 */
283static void hisi_uncore_pmu_disable_event(struct perf_event *event)
284{
285	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
286	struct hw_perf_event *hwc = &event->hw;
287
288	hisi_pmu->ops->disable_counter(hisi_pmu, hwc);
289	hisi_pmu->ops->disable_counter_int(hisi_pmu, hwc);
290
291	if (hisi_pmu->ops->disable_filter)
292		hisi_pmu->ops->disable_filter(event);
293}
294
295void hisi_uncore_pmu_set_event_period(struct perf_event *event)
296{
297	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
298	struct hw_perf_event *hwc = &event->hw;
299
300	/*
301	 * The HiSilicon PMU counters support 32 bits or 48 bits, depending on
302	 * the PMU. We reduce it to 2^(counter_bits - 1) to account for the
303	 * extreme interrupt latency. So we could hopefully handle the overflow
304	 * interrupt before another 2^(counter_bits - 1) events occur and the
305	 * counter overtakes its previous value.
306	 */
307	u64 val = BIT_ULL(hisi_pmu->counter_bits - 1);
308
309	local64_set(&hwc->prev_count, val);
310	/* Write start value to the hardware event counter */
311	hisi_pmu->ops->write_counter(hisi_pmu, hwc, val);
312}
313EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_set_event_period, "HISI_PMU");
314
315void hisi_uncore_pmu_event_update(struct perf_event *event)
316{
317	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
318	struct hw_perf_event *hwc = &event->hw;
319	u64 delta, prev_raw_count, new_raw_count;
320
321	do {
322		/* Read the count from the counter register */
323		new_raw_count = hisi_pmu->ops->read_counter(hisi_pmu, hwc);
324		prev_raw_count = local64_read(&hwc->prev_count);
325	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
326				 new_raw_count) != prev_raw_count);
327	/*
328	 * compute the delta
329	 */
330	delta = (new_raw_count - prev_raw_count) &
331		HISI_MAX_PERIOD(hisi_pmu->counter_bits);
332	local64_add(delta, &event->count);
333}
334EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_event_update, "HISI_PMU");
335
336void hisi_uncore_pmu_start(struct perf_event *event, int flags)
337{
338	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
339	struct hw_perf_event *hwc = &event->hw;
340
341	if (WARN_ON_ONCE(!(hwc->state & PERF_HES_STOPPED)))
342		return;
343
344	WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
345	hwc->state = 0;
346	hisi_uncore_pmu_set_event_period(event);
347
348	if (flags & PERF_EF_RELOAD) {
349		u64 prev_raw_count =  local64_read(&hwc->prev_count);
350
351		hisi_pmu->ops->write_counter(hisi_pmu, hwc, prev_raw_count);
352	}
353
354	hisi_uncore_pmu_enable_event(event);
355	perf_event_update_userpage(event);
356}
357EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_start, "HISI_PMU");
358
359void hisi_uncore_pmu_stop(struct perf_event *event, int flags)
360{
361	struct hw_perf_event *hwc = &event->hw;
362
363	hisi_uncore_pmu_disable_event(event);
364	WARN_ON_ONCE(hwc->state & PERF_HES_STOPPED);
365	hwc->state |= PERF_HES_STOPPED;
366
367	if (hwc->state & PERF_HES_UPTODATE)
368		return;
369
370	/* Read hardware counter and update the perf counter statistics */
371	hisi_uncore_pmu_event_update(event);
372	hwc->state |= PERF_HES_UPTODATE;
373}
374EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_stop, "HISI_PMU");
375
376int hisi_uncore_pmu_add(struct perf_event *event, int flags)
377{
378	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
379	struct hw_perf_event *hwc = &event->hw;
380	int idx;
381
382	hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
383
384	/* Get an available counter index for counting */
385	idx = hisi_pmu->ops->get_event_idx(event);
386	if (idx < 0)
387		return idx;
388
389	event->hw.idx = idx;
390	hisi_pmu->pmu_events.hw_events[idx] = event;
391
392	if (flags & PERF_EF_START)
393		hisi_uncore_pmu_start(event, PERF_EF_RELOAD);
394
395	return 0;
396}
397EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_add, "HISI_PMU");
398
399void hisi_uncore_pmu_del(struct perf_event *event, int flags)
400{
401	struct hisi_pmu *hisi_pmu = to_hisi_pmu(event->pmu);
402	struct hw_perf_event *hwc = &event->hw;
403
404	hisi_uncore_pmu_stop(event, PERF_EF_UPDATE);
405	hisi_uncore_pmu_clear_event_idx(hisi_pmu, hwc->idx);
406	perf_event_update_userpage(event);
407	hisi_pmu->pmu_events.hw_events[hwc->idx] = NULL;
408}
409EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_del, "HISI_PMU");
410
411void hisi_uncore_pmu_read(struct perf_event *event)
412{
413	/* Read hardware counter and update the perf counter statistics */
414	hisi_uncore_pmu_event_update(event);
415}
416EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_read, "HISI_PMU");
417
418void hisi_uncore_pmu_enable(struct pmu *pmu)
419{
420	struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
421	bool enabled = !bitmap_empty(hisi_pmu->pmu_events.used_mask,
422				    hisi_pmu->num_counters);
423
424	if (!enabled)
425		return;
426
427	hisi_pmu->ops->start_counters(hisi_pmu);
428}
429EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_enable, "HISI_PMU");
430
431void hisi_uncore_pmu_disable(struct pmu *pmu)
432{
433	struct hisi_pmu *hisi_pmu = to_hisi_pmu(pmu);
434
435	hisi_pmu->ops->stop_counters(hisi_pmu);
436}
437EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_disable, "HISI_PMU");
438
439
440/*
441 * The Super CPU Cluster (SCCL) and CPU Cluster (CCL) IDs can be
442 * determined from the MPIDR_EL1, but the encoding varies by CPU:
443 *
444 * - For MT variants of TSV110:
445 *   SCCL is Aff2[7:3], CCL is Aff2[2:0]
446 *
447 * - For other MT parts:
448 *   SCCL is Aff3[7:0], CCL is Aff2[7:0]
449 *
450 * - For non-MT parts:
451 *   SCCL is Aff2[7:0], CCL is Aff1[7:0]
452 */
453static void hisi_read_sccl_and_ccl_id(int *scclp, int *cclp)
454{
455	u64 mpidr = read_cpuid_mpidr();
456	int aff3 = MPIDR_AFFINITY_LEVEL(mpidr, 3);
457	int aff2 = MPIDR_AFFINITY_LEVEL(mpidr, 2);
458	int aff1 = MPIDR_AFFINITY_LEVEL(mpidr, 1);
459	bool mt = mpidr & MPIDR_MT_BITMASK;
460	int sccl, ccl;
461
462	if (mt && read_cpuid_part_number() == HISI_CPU_PART_TSV110) {
463		sccl = aff2 >> 3;
464		ccl = aff2 & 0x7;
465	} else if (mt) {
466		sccl = aff3;
467		ccl = aff2;
468	} else {
469		sccl = aff2;
470		ccl = aff1;
471	}
472
473	if (scclp)
474		*scclp = sccl;
475	if (cclp)
476		*cclp = ccl;
477}
478
479/*
480 * Check whether the CPU is associated with this uncore PMU
481 */
482static bool hisi_pmu_cpu_is_associated_pmu(struct hisi_pmu *hisi_pmu)
483{
484	struct hisi_pmu_topology *topo = &hisi_pmu->topo;
485	int sccl_id, ccl_id;
486
487	if (topo->ccl_id == -1) {
488		/* If CCL_ID is -1, the PMU only shares the same SCCL */
489		hisi_read_sccl_and_ccl_id(&sccl_id, NULL);
490
491		return sccl_id == topo->sccl_id;
492	}
493
494	hisi_read_sccl_and_ccl_id(&sccl_id, &ccl_id);
495
496	return sccl_id == topo->sccl_id && ccl_id == topo->ccl_id;
497}
498
499int hisi_uncore_pmu_online_cpu(unsigned int cpu, struct hlist_node *node)
500{
501	struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
502						     node);
503
504	/*
505	 * If the CPU is not associated to PMU, initialize the hisi_pmu->on_cpu
506	 * based on the locality if it hasn't been initialized yet. For PMUs
507	 * do have associated CPUs, it'll be updated later.
508	 */
509	if (!hisi_pmu_cpu_is_associated_pmu(hisi_pmu)) {
510		if (hisi_pmu->on_cpu != -1)
511			return 0;
512
513		hisi_pmu->on_cpu = cpumask_local_spread(0, dev_to_node(hisi_pmu->dev));
514		if (hisi_pmu->irq > 0)
515			WARN_ON(irq_set_affinity(hisi_pmu->irq,
516						 cpumask_of(hisi_pmu->on_cpu)));
517		return 0;
518	}
519
520	cpumask_set_cpu(cpu, &hisi_pmu->associated_cpus);
521
522	/* If another associated CPU is already managing this PMU, simply return. */
523	if (hisi_pmu->on_cpu != -1 &&
524	    cpumask_test_cpu(hisi_pmu->on_cpu, &hisi_pmu->associated_cpus))
525		return 0;
526
527	/* Use this CPU in cpumask for event counting */
528	hisi_pmu->on_cpu = cpu;
529
530	/* Overflow interrupt also should use the same CPU */
531	if (hisi_pmu->irq > 0)
532		WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(cpu)));
533
534	return 0;
535}
536EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_online_cpu, "HISI_PMU");
537
538int hisi_uncore_pmu_offline_cpu(unsigned int cpu, struct hlist_node *node)
539{
540	struct hisi_pmu *hisi_pmu = hlist_entry_safe(node, struct hisi_pmu,
541						     node);
542	unsigned int target;
543
544	/* Nothing to do if this CPU doesn't own the PMU */
545	if (hisi_pmu->on_cpu != cpu)
546		return 0;
547
548	/* Give up ownership of the PMU */
549	hisi_pmu->on_cpu = -1;
550
551	/*
552	 * Migrate ownership of the PMU to a new CPU chosen from PMU's online
553	 * associated CPUs if possible, if no associated CPU online then
554	 * migrate to one online CPU.
555	 */
556	target = cpumask_any_and_but(&hisi_pmu->associated_cpus,
557				     cpu_online_mask, cpu);
558	if (target >= nr_cpu_ids)
559		target = cpumask_any_but(cpu_online_mask, cpu);
560
561	if (target >= nr_cpu_ids)
562		return 0;
563
564	perf_pmu_migrate_context(&hisi_pmu->pmu, cpu, target);
565	/* Use this CPU for event counting */
566	hisi_pmu->on_cpu = target;
567
568	if (hisi_pmu->irq > 0)
569		WARN_ON(irq_set_affinity(hisi_pmu->irq, cpumask_of(target)));
570
571	return 0;
572}
573EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_offline_cpu, "HISI_PMU");
574
575/*
576 * Retrieve the topology information from the firmware for the hisi_pmu device.
577 * The topology ID will be -1 if we cannot initialize it, it may either due to
578 * the PMU doesn't locate on this certain topology or the firmware needs to be
579 * fixed.
580 */
581void hisi_uncore_pmu_init_topology(struct hisi_pmu *hisi_pmu, struct device *dev)
582{
583	struct hisi_pmu_topology *topo = &hisi_pmu->topo;
584
585	topo->sccl_id = -1;
586	topo->ccl_id = -1;
587	topo->index_id = -1;
588	topo->sub_id = -1;
589
590	if (device_property_read_u32(dev, "hisilicon,scl-id", &topo->sccl_id))
591		dev_dbg(dev, "no scl-id present\n");
592
593	if (device_property_read_u32(dev, "hisilicon,ccl-id", &topo->ccl_id))
594		dev_dbg(dev, "no ccl-id present\n");
595
596	if (device_property_read_u32(dev, "hisilicon,idx-id", &topo->index_id))
597		dev_dbg(dev, "no idx-id present\n");
598
599	if (device_property_read_u32(dev, "hisilicon,sub-id", &topo->sub_id))
600		dev_dbg(dev, "no sub-id present\n");
601}
602EXPORT_SYMBOL_NS_GPL(hisi_uncore_pmu_init_topology, "HISI_PMU");
603
604void hisi_pmu_init(struct hisi_pmu *hisi_pmu, struct module *module)
605{
606	struct pmu *pmu = &hisi_pmu->pmu;
607
608	pmu->module             = module;
609	pmu->parent             = hisi_pmu->dev;
610	pmu->task_ctx_nr        = perf_invalid_context;
611	pmu->event_init         = hisi_uncore_pmu_event_init;
612	pmu->pmu_enable         = hisi_uncore_pmu_enable;
613	pmu->pmu_disable        = hisi_uncore_pmu_disable;
614	pmu->add                = hisi_uncore_pmu_add;
615	pmu->del                = hisi_uncore_pmu_del;
616	pmu->start              = hisi_uncore_pmu_start;
617	pmu->stop               = hisi_uncore_pmu_stop;
618	pmu->read               = hisi_uncore_pmu_read;
619	pmu->attr_groups        = hisi_pmu->pmu_events.attr_groups;
620	pmu->capabilities       = PERF_PMU_CAP_NO_EXCLUDE;
621}
622EXPORT_SYMBOL_NS_GPL(hisi_pmu_init, "HISI_PMU");
623
624MODULE_DESCRIPTION("HiSilicon SoC uncore Performance Monitor driver framework");
625MODULE_LICENSE("GPL v2");