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fsl_imx9_ddr_perf.c
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linux-6.19.14/drivers/perf/fsl_imx9_ddr_perf.c
1// SPDX-License-Identifier: GPL-2.0 2// Copyright 2023 NXP 3 4#include <linux/bitfield.h> 5#include <linux/init.h> 6#include <linux/interrupt.h> 7#include <linux/io.h> 8#include <linux/module.h> 9#include <linux/of.h> 10#include <linux/platform_device.h> 11#include <linux/perf_event.h> 12 13/* Performance monitor configuration */ 14#define PMCFG1 0x00 15#define MX93_PMCFG1_RD_TRANS_FILT_EN BIT(31) 16#define MX93_PMCFG1_WR_TRANS_FILT_EN BIT(30) 17#define MX93_PMCFG1_RD_BT_FILT_EN BIT(29) 18#define MX93_PMCFG1_ID_MASK GENMASK(17, 0) 19 20#define MX95_PMCFG1_WR_BEAT_FILT_EN BIT(31) 21#define MX95_PMCFG1_RD_BEAT_FILT_EN BIT(30) 22 23#define PMCFG2 0x04 24#define MX93_PMCFG2_ID GENMASK(17, 0) 25 26#define PMCFG3 0x08 27#define PMCFG4 0x0C 28#define PMCFG5 0x10 29#define PMCFG6 0x14 30#define MX95_PMCFG_ID_MASK GENMASK(9, 0) 31#define MX95_PMCFG_ID GENMASK(25, 16) 32 33/* Global control register affects all counters and takes priority over local control registers */ 34#define PMGC0 0x40 35/* Global control register bits */ 36#define PMGC0_FAC BIT(31) 37#define PMGC0_PMIE BIT(30) 38#define PMGC0_FCECE BIT(29) 39 40/* 41 * 64bit counter0 exclusively dedicated to counting cycles 42 * 32bit counters monitor counter-specific events in addition to counting reference events 43 */ 44#define PMLCA(n) (0x40 + 0x10 + (0x10 * n)) 45#define PMLCB(n) (0x40 + 0x14 + (0x10 * n)) 46#define PMC(n) (0x40 + 0x18 + (0x10 * n)) 47/* Local control register bits */ 48#define PMLCA_FC BIT(31) 49#define PMLCA_CE BIT(26) 50#define PMLCA_EVENT GENMASK(22, 16) 51 52#define NUM_COUNTERS 11 53#define CYCLES_COUNTER 0 54#define CYCLES_EVENT_ID 0 55 56#define CONFIG_EVENT_MASK GENMASK(7, 0) 57#define CONFIG_COUNTER_MASK GENMASK(23, 16) 58 59#define to_ddr_pmu(p) container_of(p, struct ddr_pmu, pmu) 60 61#define DDR_PERF_DEV_NAME "imx9_ddr" 62#define DDR_CPUHP_CB_NAME DDR_PERF_DEV_NAME "_perf_pmu" 63 64static DEFINE_IDA(ddr_ida); 65 66/* 67 * V1 support 1 read transaction, 1 write transaction and 1 read beats 68 * event which corresponding respecitively to counter 2, 3 and 4. 69 */ 70#define DDR_PERF_AXI_FILTER_V1 0x1 71 72/* 73 * V2 support 1 read beats and 3 write beats events which corresponding 74 * respecitively to counter 2-5. 75 */ 76#define DDR_PERF_AXI_FILTER_V2 0x2 77 78struct imx_ddr_devtype_data { 79 const char *identifier; /* system PMU identifier for userspace */ 80 unsigned int filter_ver; /* AXI filter version */ 81}; 82 83struct ddr_pmu { 84 struct pmu pmu; 85 void __iomem *base; 86 unsigned int cpu; 87 struct hlist_node node; 88 struct device *dev; 89 struct perf_event *events[NUM_COUNTERS]; 90 int active_events; 91 enum cpuhp_state cpuhp_state; 92 const struct imx_ddr_devtype_data *devtype_data; 93 int irq; 94 int id; 95}; 96 97static const struct imx_ddr_devtype_data imx91_devtype_data = { 98 .identifier = "imx91", 99 .filter_ver = DDR_PERF_AXI_FILTER_V1 100}; 101 102static const struct imx_ddr_devtype_data imx93_devtype_data = { 103 .identifier = "imx93", 104 .filter_ver = DDR_PERF_AXI_FILTER_V1 105}; 106 107static const struct imx_ddr_devtype_data imx94_devtype_data = { 108 .identifier = "imx94", 109 .filter_ver = DDR_PERF_AXI_FILTER_V2 110}; 111 112static const struct imx_ddr_devtype_data imx95_devtype_data = { 113 .identifier = "imx95", 114 .filter_ver = DDR_PERF_AXI_FILTER_V2 115}; 116 117static inline bool axi_filter_v1(struct ddr_pmu *pmu) 118{ 119 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V1; 120} 121 122static inline bool axi_filter_v2(struct ddr_pmu *pmu) 123{ 124 return pmu->devtype_data->filter_ver == DDR_PERF_AXI_FILTER_V2; 125} 126 127static const struct of_device_id imx_ddr_pmu_dt_ids[] = { 128 { .compatible = "fsl,imx91-ddr-pmu", .data = &imx91_devtype_data }, 129 { .compatible = "fsl,imx93-ddr-pmu", .data = &imx93_devtype_data }, 130 { .compatible = "fsl,imx94-ddr-pmu", .data = &imx94_devtype_data }, 131 { .compatible = "fsl,imx95-ddr-pmu", .data = &imx95_devtype_data }, 132 { /* sentinel */ } 133}; 134MODULE_DEVICE_TABLE(of, imx_ddr_pmu_dt_ids); 135 136static ssize_t ddr_perf_identifier_show(struct device *dev, 137 struct device_attribute *attr, 138 char *page) 139{ 140 struct ddr_pmu *pmu = dev_get_drvdata(dev); 141 142 return sysfs_emit(page, "%s\n", pmu->devtype_data->identifier); 143} 144 145static struct device_attribute ddr_perf_identifier_attr = 146 __ATTR(identifier, 0444, ddr_perf_identifier_show, NULL); 147 148static struct attribute *ddr_perf_identifier_attrs[] = { 149 &ddr_perf_identifier_attr.attr, 150 NULL, 151}; 152 153static struct attribute_group ddr_perf_identifier_attr_group = { 154 .attrs = ddr_perf_identifier_attrs, 155}; 156 157static ssize_t ddr_perf_cpumask_show(struct device *dev, 158 struct device_attribute *attr, char *buf) 159{ 160 struct ddr_pmu *pmu = dev_get_drvdata(dev); 161 162 return cpumap_print_to_pagebuf(true, buf, cpumask_of(pmu->cpu)); 163} 164 165static struct device_attribute ddr_perf_cpumask_attr = 166 __ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL); 167 168static struct attribute *ddr_perf_cpumask_attrs[] = { 169 &ddr_perf_cpumask_attr.attr, 170 NULL, 171}; 172 173static const struct attribute_group ddr_perf_cpumask_attr_group = { 174 .attrs = ddr_perf_cpumask_attrs, 175}; 176 177struct imx9_pmu_events_attr { 178 struct device_attribute attr; 179 u64 id; 180 const struct imx_ddr_devtype_data *devtype_data; 181}; 182 183static ssize_t ddr_pmu_event_show(struct device *dev, 184 struct device_attribute *attr, char *page) 185{ 186 struct imx9_pmu_events_attr *pmu_attr; 187 188 pmu_attr = container_of(attr, struct imx9_pmu_events_attr, attr); 189 return sysfs_emit(page, "event=0x%02llx\n", pmu_attr->id); 190} 191 192#define COUNTER_OFFSET_IN_EVENT 8 193#define ID(counter, id) ((counter << COUNTER_OFFSET_IN_EVENT) | id) 194 195#define DDR_PMU_EVENT_ATTR_COMM(_name, _id, _data) \ 196 (&((struct imx9_pmu_events_attr[]) { \ 197 { .attr = __ATTR(_name, 0444, ddr_pmu_event_show, NULL),\ 198 .id = _id, \ 199 .devtype_data = _data, } \ 200 })[0].attr.attr) 201 202#define IMX9_DDR_PMU_EVENT_ATTR(_name, _id) \ 203 DDR_PMU_EVENT_ATTR_COMM(_name, _id, NULL) 204 205#define IMX93_DDR_PMU_EVENT_ATTR(_name, _id) \ 206 DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx93_devtype_data) 207 208#define IMX95_DDR_PMU_EVENT_ATTR(_name, _id) \ 209 DDR_PMU_EVENT_ATTR_COMM(_name, _id, &imx95_devtype_data) 210 211static struct attribute *ddr_perf_events_attrs[] = { 212 /* counter0 cycles event */ 213 IMX9_DDR_PMU_EVENT_ATTR(cycles, 0), 214 215 /* reference events for all normal counters, need assert DEBUG19[21] bit */ 216 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ddrc1_rmw_for_ecc, 12), 217 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_rreorder, 13), 218 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_wreorder, 14), 219 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_0, 15), 220 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_1, 16), 221 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_2, 17), 222 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_3, 18), 223 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_4, 19), 224 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_5, 22), 225 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_6, 23), 226 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_7, 24), 227 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_8, 25), 228 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_9, 26), 229 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_10, 27), 230 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_11, 28), 231 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_12, 31), 232 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_13, 59), 233 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_15, 61), 234 IMX9_DDR_PMU_EVENT_ATTR(ddrc_pm_29, 63), 235 236 /* counter1 specific events */ 237 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_0, ID(1, 64)), 238 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_1, ID(1, 65)), 239 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_2, ID(1, 66)), 240 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_3, ID(1, 67)), 241 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_4, ID(1, 68)), 242 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_5, ID(1, 69)), 243 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_6, ID(1, 70)), 244 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_riq_7, ID(1, 71)), 245 246 /* counter2 specific events */ 247 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_0, ID(2, 64)), 248 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_1, ID(2, 65)), 249 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_2, ID(2, 66)), 250 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_3, ID(2, 67)), 251 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_4, ID(2, 68)), 252 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_5, ID(2, 69)), 253 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_6, ID(2, 70)), 254 IMX9_DDR_PMU_EVENT_ATTR(ddrc_ld_wiq_7, ID(2, 71)), 255 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_empty, ID(2, 72)), 256 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_trans_filt, ID(2, 73)), /* imx93 specific*/ 257 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_beat_filt, ID(2, 73)), /* imx95 specific*/ 258 259 /* counter3 specific events */ 260 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_0, ID(3, 64)), 261 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_1, ID(3, 65)), 262 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_2, ID(3, 66)), 263 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_3, ID(3, 67)), 264 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_4, ID(3, 68)), 265 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_5, ID(3, 69)), 266 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_6, ID(3, 70)), 267 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_collision_7, ID(3, 71)), 268 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_full, ID(3, 72)), 269 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_wr_trans_filt, ID(3, 73)), /* imx93 specific*/ 270 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt2, ID(3, 73)), /* imx95 specific*/ 271 272 /* counter4 specific events */ 273 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_0, ID(4, 64)), 274 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_1, ID(4, 65)), 275 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_2, ID(4, 66)), 276 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_3, ID(4, 67)), 277 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_4, ID(4, 68)), 278 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_5, ID(4, 69)), 279 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_6, ID(4, 70)), 280 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_row_open_7, ID(4, 71)), 281 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2_rmw, ID(4, 72)), 282 IMX93_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt, ID(4, 73)), /* imx93 specific*/ 283 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt1, ID(4, 73)), /* imx95 specific*/ 284 285 /* counter5 specific events */ 286 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_0, ID(5, 64)), 287 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_1, ID(5, 65)), 288 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_2, ID(5, 66)), 289 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_3, ID(5, 67)), 290 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_4, ID(5, 68)), 291 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_5, ID(5, 69)), 292 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_6, ID(5, 70)), 293 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_start_7, ID(5, 71)), 294 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq1, ID(5, 72)), 295 IMX95_DDR_PMU_EVENT_ATTR(eddrtq_pm_rd_beat_filt0, ID(5, 73)), /* imx95 specific*/ 296 297 /* counter6 specific events */ 298 IMX9_DDR_PMU_EVENT_ATTR(ddrc_qx_valid_end_0, ID(6, 64)), 299 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq2, ID(6, 72)), 300 301 /* counter7 specific events */ 302 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_2_full, ID(7, 64)), 303 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq0, ID(7, 65)), 304 305 /* counter8 specific events */ 306 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_bias_switched, ID(8, 64)), 307 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_1_4_full, ID(8, 65)), 308 309 /* counter9 specific events */ 310 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_wrq1, ID(9, 65)), 311 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_3_4_full, ID(9, 66)), 312 313 /* counter10 specific events */ 314 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_misc_mrk, ID(10, 65)), 315 IMX9_DDR_PMU_EVENT_ATTR(eddrtq_pmon_ld_rdq0, ID(10, 66)), 316 NULL, 317}; 318 319static umode_t 320ddr_perf_events_attrs_is_visible(struct kobject *kobj, 321 struct attribute *attr, int unused) 322{ 323 struct pmu *pmu = dev_get_drvdata(kobj_to_dev(kobj)); 324 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 325 struct imx9_pmu_events_attr *eattr; 326 327 eattr = container_of(attr, typeof(*eattr), attr.attr); 328 329 if (!eattr->devtype_data) 330 return attr->mode; 331 332 if (eattr->devtype_data != ddr_pmu->devtype_data && 333 eattr->devtype_data->filter_ver != ddr_pmu->devtype_data->filter_ver) 334 return 0; 335 336 return attr->mode; 337} 338 339static const struct attribute_group ddr_perf_events_attr_group = { 340 .name = "events", 341 .attrs = ddr_perf_events_attrs, 342 .is_visible = ddr_perf_events_attrs_is_visible, 343}; 344 345PMU_FORMAT_ATTR(event, "config:0-7,16-23"); 346PMU_FORMAT_ATTR(counter, "config:8-15"); 347PMU_FORMAT_ATTR(axi_id, "config1:0-17"); 348PMU_FORMAT_ATTR(axi_mask, "config2:0-17"); 349 350static struct attribute *ddr_perf_format_attrs[] = { 351 &format_attr_event.attr, 352 &format_attr_counter.attr, 353 &format_attr_axi_id.attr, 354 &format_attr_axi_mask.attr, 355 NULL, 356}; 357 358static const struct attribute_group ddr_perf_format_attr_group = { 359 .name = "format", 360 .attrs = ddr_perf_format_attrs, 361}; 362 363static const struct attribute_group *attr_groups[] = { 364 &ddr_perf_identifier_attr_group, 365 &ddr_perf_cpumask_attr_group, 366 &ddr_perf_events_attr_group, 367 &ddr_perf_format_attr_group, 368 NULL, 369}; 370 371static void ddr_perf_clear_counter(struct ddr_pmu *pmu, int counter) 372{ 373 if (counter == CYCLES_COUNTER) { 374 writel(0, pmu->base + PMC(counter) + 0x4); 375 writel(0, pmu->base + PMC(counter)); 376 } else { 377 writel(0, pmu->base + PMC(counter)); 378 } 379} 380 381static u64 ddr_perf_read_counter(struct ddr_pmu *pmu, int counter) 382{ 383 u32 val_lower, val_upper; 384 u64 val; 385 386 if (counter != CYCLES_COUNTER) { 387 val = readl_relaxed(pmu->base + PMC(counter)); 388 goto out; 389 } 390 391 /* special handling for reading 64bit cycle counter */ 392 do { 393 val_upper = readl_relaxed(pmu->base + PMC(counter) + 0x4); 394 val_lower = readl_relaxed(pmu->base + PMC(counter)); 395 } while (val_upper != readl_relaxed(pmu->base + PMC(counter) + 0x4)); 396 397 val = val_upper; 398 val = (val << 32); 399 val |= val_lower; 400out: 401 return val; 402} 403 404static void ddr_perf_counter_global_config(struct ddr_pmu *pmu, bool enable) 405{ 406 u32 ctrl; 407 408 ctrl = readl_relaxed(pmu->base + PMGC0); 409 410 if (enable) { 411 /* 412 * The performance monitor must be reset before event counting 413 * sequences. The performance monitor can be reset by first freezing 414 * one or more counters and then clearing the freeze condition to 415 * allow the counters to count according to the settings in the 416 * performance monitor registers. Counters can be frozen individually 417 * by setting PMLCAn[FC] bits, or simultaneously by setting PMGC0[FAC]. 418 * Simply clearing these freeze bits will then allow the performance 419 * monitor to begin counting based on the register settings. 420 */ 421 ctrl |= PMGC0_FAC; 422 writel(ctrl, pmu->base + PMGC0); 423 424 /* 425 * Freeze all counters disabled, interrupt enabled, and freeze 426 * counters on condition enabled. 427 */ 428 ctrl &= ~PMGC0_FAC; 429 ctrl |= PMGC0_PMIE | PMGC0_FCECE; 430 writel(ctrl, pmu->base + PMGC0); 431 } else { 432 ctrl |= PMGC0_FAC; 433 ctrl &= ~(PMGC0_PMIE | PMGC0_FCECE); 434 writel(ctrl, pmu->base + PMGC0); 435 } 436} 437 438static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config, 439 int counter, bool enable) 440{ 441 u32 ctrl_a; 442 int event; 443 444 ctrl_a = readl_relaxed(pmu->base + PMLCA(counter)); 445 event = FIELD_GET(CONFIG_EVENT_MASK, config); 446 447 if (enable) { 448 ctrl_a |= PMLCA_FC; 449 writel(ctrl_a, pmu->base + PMLCA(counter)); 450 451 ddr_perf_clear_counter(pmu, counter); 452 453 /* Freeze counter disabled, condition enabled, and program event.*/ 454 ctrl_a &= ~PMLCA_FC; 455 ctrl_a |= PMLCA_CE; 456 ctrl_a &= ~FIELD_PREP(PMLCA_EVENT, 0x7F); 457 ctrl_a |= FIELD_PREP(PMLCA_EVENT, event); 458 writel(ctrl_a, pmu->base + PMLCA(counter)); 459 } else { 460 /* Freeze counter. */ 461 ctrl_a |= PMLCA_FC; 462 writel(ctrl_a, pmu->base + PMLCA(counter)); 463 } 464} 465 466static void imx93_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, 467 int counter, int axi_id, int axi_mask) 468{ 469 u32 pmcfg1, pmcfg2; 470 static const u32 mask[] = { 471 MX93_PMCFG1_RD_TRANS_FILT_EN, 472 MX93_PMCFG1_WR_TRANS_FILT_EN, 473 MX93_PMCFG1_RD_BT_FILT_EN 474 }; 475 476 pmcfg1 = readl_relaxed(pmu->base + PMCFG1); 477 478 if (counter >= 2 && counter <= 4) 479 pmcfg1 = event == 73 ? pmcfg1 | mask[counter - 2] : 480 pmcfg1 & ~mask[counter - 2]; 481 482 pmcfg1 &= ~FIELD_PREP(MX93_PMCFG1_ID_MASK, 0x3FFFF); 483 pmcfg1 |= FIELD_PREP(MX93_PMCFG1_ID_MASK, axi_mask); 484 writel_relaxed(pmcfg1, pmu->base + PMCFG1); 485 486 pmcfg2 = readl_relaxed(pmu->base + PMCFG2); 487 pmcfg2 &= ~FIELD_PREP(MX93_PMCFG2_ID, 0x3FFFF); 488 pmcfg2 |= FIELD_PREP(MX93_PMCFG2_ID, axi_id); 489 writel_relaxed(pmcfg2, pmu->base + PMCFG2); 490} 491 492static void imx95_ddr_perf_monitor_config(struct ddr_pmu *pmu, int event, 493 int counter, int axi_id, int axi_mask) 494{ 495 u32 pmcfg1, pmcfg, offset = 0; 496 497 pmcfg1 = readl_relaxed(pmu->base + PMCFG1); 498 499 if (event == 73) { 500 switch (counter) { 501 case 2: 502 pmcfg1 |= MX95_PMCFG1_WR_BEAT_FILT_EN; 503 offset = PMCFG3; 504 break; 505 case 3: 506 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; 507 offset = PMCFG4; 508 break; 509 case 4: 510 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; 511 offset = PMCFG5; 512 break; 513 case 5: 514 pmcfg1 |= MX95_PMCFG1_RD_BEAT_FILT_EN; 515 offset = PMCFG6; 516 break; 517 } 518 } else { 519 switch (counter) { 520 case 2: 521 pmcfg1 &= ~MX95_PMCFG1_WR_BEAT_FILT_EN; 522 break; 523 case 3: 524 case 4: 525 case 5: 526 pmcfg1 &= ~MX95_PMCFG1_RD_BEAT_FILT_EN; 527 break; 528 } 529 } 530 531 writel_relaxed(pmcfg1, pmu->base + PMCFG1); 532 533 if (offset) { 534 pmcfg = readl_relaxed(pmu->base + offset); 535 pmcfg &= ~(FIELD_PREP(MX95_PMCFG_ID_MASK, 0x3FF) | 536 FIELD_PREP(MX95_PMCFG_ID, 0x3FF)); 537 pmcfg |= (FIELD_PREP(MX95_PMCFG_ID_MASK, axi_mask) | 538 FIELD_PREP(MX95_PMCFG_ID, axi_id)); 539 writel_relaxed(pmcfg, pmu->base + offset); 540 } 541} 542 543static void ddr_perf_event_update(struct perf_event *event) 544{ 545 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 546 struct hw_perf_event *hwc = &event->hw; 547 int counter = hwc->idx; 548 u64 new_raw_count; 549 550 new_raw_count = ddr_perf_read_counter(pmu, counter); 551 local64_add(new_raw_count, &event->count); 552 553 /* clear counter's value every time */ 554 ddr_perf_clear_counter(pmu, counter); 555} 556 557static int ddr_perf_event_init(struct perf_event *event) 558{ 559 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 560 struct hw_perf_event *hwc = &event->hw; 561 struct perf_event *sibling; 562 563 if (event->attr.type != event->pmu->type) 564 return -ENOENT; 565 566 if (is_sampling_event(event) || event->attach_state & PERF_ATTACH_TASK) 567 return -EOPNOTSUPP; 568 569 if (event->cpu < 0) { 570 dev_warn(pmu->dev, "Can't provide per-task data!\n"); 571 return -EOPNOTSUPP; 572 } 573 574 /* 575 * We must NOT create groups containing mixed PMUs, although software 576 * events are acceptable (for example to create a CCN group 577 * periodically read when a hrtimer aka cpu-clock leader triggers). 578 */ 579 if (event->group_leader->pmu != event->pmu && 580 !is_software_event(event->group_leader)) 581 return -EINVAL; 582 583 for_each_sibling_event(sibling, event->group_leader) { 584 if (sibling->pmu != event->pmu && 585 !is_software_event(sibling)) 586 return -EINVAL; 587 } 588 589 event->cpu = pmu->cpu; 590 hwc->idx = -1; 591 592 return 0; 593} 594 595static void ddr_perf_event_start(struct perf_event *event, int flags) 596{ 597 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 598 struct hw_perf_event *hwc = &event->hw; 599 int counter = hwc->idx; 600 601 local64_set(&hwc->prev_count, 0); 602 603 ddr_perf_counter_local_config(pmu, event->attr.config, counter, true); 604 hwc->state = 0; 605} 606 607static int ddr_perf_alloc_counter(struct ddr_pmu *pmu, int event, int counter) 608{ 609 int i; 610 611 if (event == CYCLES_EVENT_ID) { 612 // Cycles counter is dedicated for cycle event. 613 if (pmu->events[CYCLES_COUNTER] == NULL) 614 return CYCLES_COUNTER; 615 } else if (counter != 0) { 616 // Counter specific event use specific counter. 617 if (pmu->events[counter] == NULL) 618 return counter; 619 } else { 620 // Auto allocate counter for referene event. 621 for (i = 1; i < NUM_COUNTERS; i++) 622 if (pmu->events[i] == NULL) 623 return i; 624 } 625 626 return -ENOENT; 627} 628 629static int ddr_perf_event_add(struct perf_event *event, int flags) 630{ 631 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 632 struct hw_perf_event *hwc = &event->hw; 633 int cfg = event->attr.config; 634 int cfg1 = event->attr.config1; 635 int cfg2 = event->attr.config2; 636 int event_id, counter; 637 638 event_id = FIELD_GET(CONFIG_EVENT_MASK, cfg); 639 counter = FIELD_GET(CONFIG_COUNTER_MASK, cfg); 640 641 counter = ddr_perf_alloc_counter(pmu, event_id, counter); 642 if (counter < 0) { 643 dev_dbg(pmu->dev, "There are not enough counters\n"); 644 return -EOPNOTSUPP; 645 } 646 647 pmu->events[counter] = event; 648 pmu->active_events++; 649 hwc->idx = counter; 650 hwc->state |= PERF_HES_STOPPED; 651 652 if (axi_filter_v1(pmu)) 653 /* read trans, write trans, read beat */ 654 imx93_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); 655 656 if (axi_filter_v2(pmu)) 657 /* write beat, read beat2, read beat1, read beat */ 658 imx95_ddr_perf_monitor_config(pmu, event_id, counter, cfg1, cfg2); 659 660 if (flags & PERF_EF_START) 661 ddr_perf_event_start(event, flags); 662 663 return 0; 664} 665 666static void ddr_perf_event_stop(struct perf_event *event, int flags) 667{ 668 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 669 struct hw_perf_event *hwc = &event->hw; 670 int counter = hwc->idx; 671 672 ddr_perf_counter_local_config(pmu, event->attr.config, counter, false); 673 ddr_perf_event_update(event); 674 675 hwc->state |= PERF_HES_STOPPED; 676} 677 678static void ddr_perf_event_del(struct perf_event *event, int flags) 679{ 680 struct ddr_pmu *pmu = to_ddr_pmu(event->pmu); 681 struct hw_perf_event *hwc = &event->hw; 682 int counter = hwc->idx; 683 684 ddr_perf_event_stop(event, PERF_EF_UPDATE); 685 686 pmu->events[counter] = NULL; 687 pmu->active_events--; 688 hwc->idx = -1; 689} 690 691static void ddr_perf_pmu_enable(struct pmu *pmu) 692{ 693 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 694 695 ddr_perf_counter_global_config(ddr_pmu, true); 696} 697 698static void ddr_perf_pmu_disable(struct pmu *pmu) 699{ 700 struct ddr_pmu *ddr_pmu = to_ddr_pmu(pmu); 701 702 ddr_perf_counter_global_config(ddr_pmu, false); 703} 704 705static void ddr_perf_init(struct ddr_pmu *pmu, void __iomem *base, 706 struct device *dev) 707{ 708 *pmu = (struct ddr_pmu) { 709 .pmu = (struct pmu) { 710 .module = THIS_MODULE, 711 .capabilities = PERF_PMU_CAP_NO_EXCLUDE, 712 .task_ctx_nr = perf_invalid_context, 713 .attr_groups = attr_groups, 714 .event_init = ddr_perf_event_init, 715 .add = ddr_perf_event_add, 716 .del = ddr_perf_event_del, 717 .start = ddr_perf_event_start, 718 .stop = ddr_perf_event_stop, 719 .read = ddr_perf_event_update, 720 .pmu_enable = ddr_perf_pmu_enable, 721 .pmu_disable = ddr_perf_pmu_disable, 722 }, 723 .base = base, 724 .dev = dev, 725 }; 726} 727 728static irqreturn_t ddr_perf_irq_handler(int irq, void *p) 729{ 730 struct ddr_pmu *pmu = (struct ddr_pmu *)p; 731 struct perf_event *event; 732 int i; 733 734 /* 735 * Counters can generate an interrupt on an overflow when msb of a 736 * counter changes from 0 to 1. For the interrupt to be signalled, 737 * below condition mush be satisfied: 738 * PMGC0[PMIE] = 1, PMGC0[FCECE] = 1, PMLCAn[CE] = 1 739 * When an interrupt is signalled, PMGC0[FAC] is set by hardware and 740 * all of the registers are frozen. 741 * Software can clear the interrupt condition by resetting the performance 742 * monitor and clearing the most significant bit of the counter that 743 * generate the overflow. 744 */ 745 for (i = 0; i < NUM_COUNTERS; i++) { 746 if (!pmu->events[i]) 747 continue; 748 749 event = pmu->events[i]; 750 751 ddr_perf_event_update(event); 752 } 753 754 ddr_perf_counter_global_config(pmu, true); 755 756 return IRQ_HANDLED; 757} 758 759static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node) 760{ 761 struct ddr_pmu *pmu = hlist_entry_safe(node, struct ddr_pmu, node); 762 int target; 763 764 if (cpu != pmu->cpu) 765 return 0; 766 767 target = cpumask_any_but(cpu_online_mask, cpu); 768 if (target >= nr_cpu_ids) 769 return 0; 770 771 perf_pmu_migrate_context(&pmu->pmu, cpu, target); 772 pmu->cpu = target; 773 774 WARN_ON(irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu))); 775 776 return 0; 777} 778 779static int ddr_perf_probe(struct platform_device *pdev) 780{ 781 struct ddr_pmu *pmu; 782 void __iomem *base; 783 int ret, irq; 784 char *name; 785 786 base = devm_platform_ioremap_resource(pdev, 0); 787 if (IS_ERR(base)) 788 return PTR_ERR(base); 789 790 pmu = devm_kzalloc(&pdev->dev, sizeof(*pmu), GFP_KERNEL); 791 if (!pmu) 792 return -ENOMEM; 793 794 ddr_perf_init(pmu, base, &pdev->dev); 795 796 pmu->devtype_data = of_device_get_match_data(&pdev->dev); 797 798 platform_set_drvdata(pdev, pmu); 799 800 pmu->id = ida_alloc(&ddr_ida, GFP_KERNEL); 801 name = devm_kasprintf(&pdev->dev, GFP_KERNEL, DDR_PERF_DEV_NAME "%d", pmu->id); 802 if (!name) { 803 ret = -ENOMEM; 804 goto format_string_err; 805 } 806 807 pmu->cpu = raw_smp_processor_id(); 808 ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN, DDR_CPUHP_CB_NAME, 809 NULL, ddr_perf_offline_cpu); 810 if (ret < 0) { 811 dev_err(&pdev->dev, "Failed to add callbacks for multi state\n"); 812 goto cpuhp_state_err; 813 } 814 pmu->cpuhp_state = ret; 815 816 /* Register the pmu instance for cpu hotplug */ 817 ret = cpuhp_state_add_instance_nocalls(pmu->cpuhp_state, &pmu->node); 818 if (ret) { 819 dev_err(&pdev->dev, "Error %d registering hotplug\n", ret); 820 goto cpuhp_instance_err; 821 } 822 823 /* Request irq */ 824 irq = platform_get_irq(pdev, 0); 825 if (irq < 0) { 826 ret = irq; 827 goto ddr_perf_err; 828 } 829 830 ret = devm_request_irq(&pdev->dev, irq, ddr_perf_irq_handler, 831 IRQF_NOBALANCING | IRQF_NO_THREAD, 832 DDR_CPUHP_CB_NAME, pmu); 833 if (ret < 0) { 834 dev_err(&pdev->dev, "Request irq failed: %d", ret); 835 goto ddr_perf_err; 836 } 837 838 pmu->irq = irq; 839 ret = irq_set_affinity(pmu->irq, cpumask_of(pmu->cpu)); 840 if (ret) { 841 dev_err(pmu->dev, "Failed to set interrupt affinity\n"); 842 goto ddr_perf_err; 843 } 844 845 ret = perf_pmu_register(&pmu->pmu, name, -1); 846 if (ret) 847 goto ddr_perf_err; 848 849 return 0; 850 851ddr_perf_err: 852 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 853cpuhp_instance_err: 854 cpuhp_remove_multi_state(pmu->cpuhp_state); 855cpuhp_state_err: 856format_string_err: 857 ida_free(&ddr_ida, pmu->id); 858 dev_warn(&pdev->dev, "i.MX9 DDR Perf PMU failed (%d), disabled\n", ret); 859 return ret; 860} 861 862static void ddr_perf_remove(struct platform_device *pdev) 863{ 864 struct ddr_pmu *pmu = platform_get_drvdata(pdev); 865 866 cpuhp_state_remove_instance_nocalls(pmu->cpuhp_state, &pmu->node); 867 cpuhp_remove_multi_state(pmu->cpuhp_state); 868 869 perf_pmu_unregister(&pmu->pmu); 870 871 ida_free(&ddr_ida, pmu->id); 872} 873 874static struct platform_driver imx_ddr_pmu_driver = { 875 .driver = { 876 .name = "imx9-ddr-pmu", 877 .of_match_table = imx_ddr_pmu_dt_ids, 878 .suppress_bind_attrs = true, 879 }, 880 .probe = ddr_perf_probe, 881 .remove = ddr_perf_remove, 882}; 883module_platform_driver(imx_ddr_pmu_driver); 884 885MODULE_AUTHOR("Xu Yang <xu.yang_2@nxp.com>"); 886MODULE_LICENSE("GPL v2"); 887MODULE_DESCRIPTION("DDRC PerfMon for i.MX9 SoCs");
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