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arm_v7_pmu.c
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linux-6.19.14/drivers/perf/arm_v7_pmu.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code. 4 * 5 * ARMv7 support: Jean Pihet <jpihet@mvista.com> 6 * 2010 (c) MontaVista Software, LLC. 7 * 8 * Copied from ARMv6 code, with the low level code inspired 9 * by the ARMv7 Oprofile code. 10 * 11 * Cortex-A8 has up to 4 configurable performance counters and 12 * a single cycle counter. 13 * Cortex-A9 has up to 31 configurable performance counters and 14 * a single cycle counter. 15 * 16 * All counters can be enabled/disabled and IRQ masked separately. The cycle 17 * counter and all 4 performance counters together can be reset separately. 18 */ 19 20#include <asm/cp15.h> 21#include <asm/cputype.h> 22#include <asm/irq_regs.h> 23#include <asm/vfp.h> 24#include "../vfp/vfpinstr.h" 25 26#include <linux/of.h> 27#include <linux/perf/arm_pmu.h> 28#include <linux/platform_device.h> 29 30/* 31 * Common ARMv7 event types 32 * 33 * Note: An implementation may not be able to count all of these events 34 * but the encodings are considered to be `reserved' in the case that 35 * they are not available. 36 */ 37#define ARMV7_PERFCTR_PMNC_SW_INCR 0x00 38#define ARMV7_PERFCTR_L1_ICACHE_REFILL 0x01 39#define ARMV7_PERFCTR_ITLB_REFILL 0x02 40#define ARMV7_PERFCTR_L1_DCACHE_REFILL 0x03 41#define ARMV7_PERFCTR_L1_DCACHE_ACCESS 0x04 42#define ARMV7_PERFCTR_DTLB_REFILL 0x05 43#define ARMV7_PERFCTR_MEM_READ 0x06 44#define ARMV7_PERFCTR_MEM_WRITE 0x07 45#define ARMV7_PERFCTR_INSTR_EXECUTED 0x08 46#define ARMV7_PERFCTR_EXC_TAKEN 0x09 47#define ARMV7_PERFCTR_EXC_EXECUTED 0x0A 48#define ARMV7_PERFCTR_CID_WRITE 0x0B 49 50/* 51 * ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS. 52 * It counts: 53 * - all (taken) branch instructions, 54 * - instructions that explicitly write the PC, 55 * - exception generating instructions. 56 */ 57#define ARMV7_PERFCTR_PC_WRITE 0x0C 58#define ARMV7_PERFCTR_PC_IMM_BRANCH 0x0D 59#define ARMV7_PERFCTR_PC_PROC_RETURN 0x0E 60#define ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS 0x0F 61#define ARMV7_PERFCTR_PC_BRANCH_MIS_PRED 0x10 62#define ARMV7_PERFCTR_CLOCK_CYCLES 0x11 63#define ARMV7_PERFCTR_PC_BRANCH_PRED 0x12 64 65/* These events are defined by the PMUv2 supplement (ARM DDI 0457A). */ 66#define ARMV7_PERFCTR_MEM_ACCESS 0x13 67#define ARMV7_PERFCTR_L1_ICACHE_ACCESS 0x14 68#define ARMV7_PERFCTR_L1_DCACHE_WB 0x15 69#define ARMV7_PERFCTR_L2_CACHE_ACCESS 0x16 70#define ARMV7_PERFCTR_L2_CACHE_REFILL 0x17 71#define ARMV7_PERFCTR_L2_CACHE_WB 0x18 72#define ARMV7_PERFCTR_BUS_ACCESS 0x19 73#define ARMV7_PERFCTR_MEM_ERROR 0x1A 74#define ARMV7_PERFCTR_INSTR_SPEC 0x1B 75#define ARMV7_PERFCTR_TTBR_WRITE 0x1C 76#define ARMV7_PERFCTR_BUS_CYCLES 0x1D 77 78#define ARMV7_PERFCTR_CPU_CYCLES 0xFF 79 80/* ARMv7 Cortex-A8 specific event types */ 81#define ARMV7_A8_PERFCTR_L2_CACHE_ACCESS 0x43 82#define ARMV7_A8_PERFCTR_L2_CACHE_REFILL 0x44 83#define ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS 0x50 84#define ARMV7_A8_PERFCTR_STALL_ISIDE 0x56 85 86/* ARMv7 Cortex-A9 specific event types */ 87#define ARMV7_A9_PERFCTR_INSTR_CORE_RENAME 0x68 88#define ARMV7_A9_PERFCTR_STALL_ICACHE 0x60 89#define ARMV7_A9_PERFCTR_STALL_DISPATCH 0x66 90 91/* ARMv7 Cortex-A5 specific event types */ 92#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL 0xc2 93#define ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP 0xc3 94 95/* ARMv7 Cortex-A15 specific event types */ 96#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 97#define ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 98#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ 0x42 99#define ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE 0x43 100 101#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ 0x4C 102#define ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE 0x4D 103 104#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ 0x50 105#define ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 106#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ 0x52 107#define ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE 0x53 108 109#define ARMV7_A15_PERFCTR_PC_WRITE_SPEC 0x76 110 111/* ARMv7 Cortex-A12 specific event types */ 112#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ 0x40 113#define ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE 0x41 114 115#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ 0x50 116#define ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE 0x51 117 118#define ARMV7_A12_PERFCTR_PC_WRITE_SPEC 0x76 119 120#define ARMV7_A12_PERFCTR_PF_TLB_REFILL 0xe7 121 122/* ARMv7 Krait specific event types */ 123#define KRAIT_PMRESR0_GROUP0 0xcc 124#define KRAIT_PMRESR1_GROUP0 0xd0 125#define KRAIT_PMRESR2_GROUP0 0xd4 126#define KRAIT_VPMRESR0_GROUP0 0xd8 127 128#define KRAIT_PERFCTR_L1_ICACHE_ACCESS 0x10011 129#define KRAIT_PERFCTR_L1_ICACHE_MISS 0x10010 130 131#define KRAIT_PERFCTR_L1_ITLB_ACCESS 0x12222 132#define KRAIT_PERFCTR_L1_DTLB_ACCESS 0x12210 133 134/* ARMv7 Scorpion specific event types */ 135#define SCORPION_LPM0_GROUP0 0x4c 136#define SCORPION_LPM1_GROUP0 0x50 137#define SCORPION_LPM2_GROUP0 0x54 138#define SCORPION_L2LPM_GROUP0 0x58 139#define SCORPION_VLPM_GROUP0 0x5c 140 141#define SCORPION_ICACHE_ACCESS 0x10053 142#define SCORPION_ICACHE_MISS 0x10052 143 144#define SCORPION_DTLB_ACCESS 0x12013 145#define SCORPION_DTLB_MISS 0x12012 146 147#define SCORPION_ITLB_MISS 0x12021 148 149/* 150 * Cortex-A8 HW events mapping 151 * 152 * The hardware events that we support. We do support cache operations but 153 * we have harvard caches and no way to combine instruction and data 154 * accesses/misses in hardware. 155 */ 156static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = { 157 PERF_MAP_ALL_UNSUPPORTED, 158 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 159 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 160 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 161 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 162 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 163 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 164 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A8_PERFCTR_STALL_ISIDE, 165}; 166 167static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 168 [PERF_COUNT_HW_CACHE_OP_MAX] 169 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 170 PERF_CACHE_MAP_ALL_UNSUPPORTED, 171 172 /* 173 * The performance counters don't differentiate between read and write 174 * accesses/misses so this isn't strictly correct, but it's the best we 175 * can do. Writes and reads get combined. 176 */ 177 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 178 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 179 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 180 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 181 182 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L1_ICACHE_ACCESS, 183 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 184 185 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, 186 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, 187 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A8_PERFCTR_L2_CACHE_ACCESS, 188 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A8_PERFCTR_L2_CACHE_REFILL, 189 190 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 191 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 192 193 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 194 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 195 196 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 197 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 198 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 199 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 200}; 201 202/* 203 * Cortex-A9 HW events mapping 204 */ 205static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = { 206 PERF_MAP_ALL_UNSUPPORTED, 207 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 208 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_A9_PERFCTR_INSTR_CORE_RENAME, 209 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 210 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 211 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 212 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 213 [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND] = ARMV7_A9_PERFCTR_STALL_ICACHE, 214 [PERF_COUNT_HW_STALLED_CYCLES_BACKEND] = ARMV7_A9_PERFCTR_STALL_DISPATCH, 215}; 216 217static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 218 [PERF_COUNT_HW_CACHE_OP_MAX] 219 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 220 PERF_CACHE_MAP_ALL_UNSUPPORTED, 221 222 /* 223 * The performance counters don't differentiate between read and write 224 * accesses/misses so this isn't strictly correct, but it's the best we 225 * can do. Writes and reads get combined. 226 */ 227 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 228 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 229 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 230 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 231 232 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 233 234 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 235 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 236 237 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 238 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 239 240 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 241 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 242 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 243 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 244}; 245 246/* 247 * Cortex-A5 HW events mapping 248 */ 249static const unsigned armv7_a5_perf_map[PERF_COUNT_HW_MAX] = { 250 PERF_MAP_ALL_UNSUPPORTED, 251 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 252 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 253 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 254 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 255 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 256 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 257}; 258 259static const unsigned armv7_a5_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 260 [PERF_COUNT_HW_CACHE_OP_MAX] 261 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 262 PERF_CACHE_MAP_ALL_UNSUPPORTED, 263 264 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 265 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 266 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 267 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 268 [C(L1D)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 269 [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 270 271 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 272 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 273 /* 274 * The prefetch counters don't differentiate between the I side and the 275 * D side. 276 */ 277 [C(L1I)][C(OP_PREFETCH)][C(RESULT_ACCESS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL, 278 [C(L1I)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A5_PERFCTR_PREFETCH_LINEFILL_DROP, 279 280 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 281 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 282 283 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 284 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 285 286 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 287 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 288 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 289 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 290}; 291 292/* 293 * Cortex-A15 HW events mapping 294 */ 295static const unsigned armv7_a15_perf_map[PERF_COUNT_HW_MAX] = { 296 PERF_MAP_ALL_UNSUPPORTED, 297 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 298 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 299 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 300 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 301 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A15_PERFCTR_PC_WRITE_SPEC, 302 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 303 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 304}; 305 306static const unsigned armv7_a15_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 307 [PERF_COUNT_HW_CACHE_OP_MAX] 308 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 309 PERF_CACHE_MAP_ALL_UNSUPPORTED, 310 311 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_READ, 312 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_READ, 313 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L1_DCACHE_ACCESS_WRITE, 314 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L1_DCACHE_REFILL_WRITE, 315 316 /* 317 * Not all performance counters differentiate between read and write 318 * accesses/misses so we're not always strictly correct, but it's the 319 * best we can do. Writes and reads get combined in these cases. 320 */ 321 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 322 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 323 324 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_READ, 325 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_READ, 326 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A15_PERFCTR_L2_CACHE_ACCESS_WRITE, 327 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_L2_CACHE_REFILL_WRITE, 328 329 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_READ, 330 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_A15_PERFCTR_DTLB_REFILL_L1_WRITE, 331 332 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 333 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 334 335 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 336 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 337 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 338 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 339}; 340 341/* 342 * Cortex-A7 HW events mapping 343 */ 344static const unsigned armv7_a7_perf_map[PERF_COUNT_HW_MAX] = { 345 PERF_MAP_ALL_UNSUPPORTED, 346 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 347 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 348 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 349 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 350 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 351 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 352 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 353}; 354 355static const unsigned armv7_a7_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 356 [PERF_COUNT_HW_CACHE_OP_MAX] 357 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 358 PERF_CACHE_MAP_ALL_UNSUPPORTED, 359 360 /* 361 * The performance counters don't differentiate between read and write 362 * accesses/misses so this isn't strictly correct, but it's the best we 363 * can do. Writes and reads get combined. 364 */ 365 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 366 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 367 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 368 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 369 370 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 371 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 372 373 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, 374 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 375 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_CACHE_ACCESS, 376 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 377 378 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 379 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 380 381 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 382 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 383 384 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 385 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 386 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 387 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 388}; 389 390/* 391 * Cortex-A12 HW events mapping 392 */ 393static const unsigned armv7_a12_perf_map[PERF_COUNT_HW_MAX] = { 394 PERF_MAP_ALL_UNSUPPORTED, 395 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 396 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 397 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 398 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 399 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_A12_PERFCTR_PC_WRITE_SPEC, 400 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 401 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_BUS_CYCLES, 402}; 403 404static const unsigned armv7_a12_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 405 [PERF_COUNT_HW_CACHE_OP_MAX] 406 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 407 PERF_CACHE_MAP_ALL_UNSUPPORTED, 408 409 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_READ, 410 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 411 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L1_DCACHE_ACCESS_WRITE, 412 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 413 414 /* 415 * Not all performance counters differentiate between read and write 416 * accesses/misses so we're not always strictly correct, but it's the 417 * best we can do. Writes and reads get combined in these cases. 418 */ 419 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_ICACHE_ACCESS, 420 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_ICACHE_REFILL, 421 422 [C(LL)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_READ, 423 [C(LL)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 424 [C(LL)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_A12_PERFCTR_L2_CACHE_ACCESS_WRITE, 425 [C(LL)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACHE_REFILL, 426 427 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 428 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL, 429 [C(DTLB)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV7_A12_PERFCTR_PF_TLB_REFILL, 430 431 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 432 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_REFILL, 433 434 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 435 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 436 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 437 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 438}; 439 440/* 441 * Krait HW events mapping 442 */ 443static const unsigned krait_perf_map[PERF_COUNT_HW_MAX] = { 444 PERF_MAP_ALL_UNSUPPORTED, 445 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 446 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 447 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 448 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 449 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 450}; 451 452static const unsigned krait_perf_map_no_branch[PERF_COUNT_HW_MAX] = { 453 PERF_MAP_ALL_UNSUPPORTED, 454 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 455 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 456 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 457 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 458}; 459 460static const unsigned krait_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 461 [PERF_COUNT_HW_CACHE_OP_MAX] 462 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 463 PERF_CACHE_MAP_ALL_UNSUPPORTED, 464 465 /* 466 * The performance counters don't differentiate between read and write 467 * accesses/misses so this isn't strictly correct, but it's the best we 468 * can do. Writes and reads get combined. 469 */ 470 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 471 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 472 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 473 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 474 475 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ICACHE_ACCESS, 476 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = KRAIT_PERFCTR_L1_ICACHE_MISS, 477 478 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, 479 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_DTLB_ACCESS, 480 481 [C(ITLB)][C(OP_READ)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, 482 [C(ITLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = KRAIT_PERFCTR_L1_ITLB_ACCESS, 483 484 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 485 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 486 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 487 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 488}; 489 490/* 491 * Scorpion HW events mapping 492 */ 493static const unsigned scorpion_perf_map[PERF_COUNT_HW_MAX] = { 494 PERF_MAP_ALL_UNSUPPORTED, 495 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES, 496 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED, 497 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE, 498 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 499 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES, 500}; 501 502static const unsigned scorpion_perf_cache_map[PERF_COUNT_HW_CACHE_MAX] 503 [PERF_COUNT_HW_CACHE_OP_MAX] 504 [PERF_COUNT_HW_CACHE_RESULT_MAX] = { 505 PERF_CACHE_MAP_ALL_UNSUPPORTED, 506 /* 507 * The performance counters don't differentiate between read and write 508 * accesses/misses so this isn't strictly correct, but it's the best we 509 * can do. Writes and reads get combined. 510 */ 511 [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 512 [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 513 [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_DCACHE_ACCESS, 514 [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_L1_DCACHE_REFILL, 515 [C(L1I)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_ICACHE_ACCESS, 516 [C(L1I)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ICACHE_MISS, 517 /* 518 * Only ITLB misses and DTLB refills are supported. If users want the 519 * DTLB refills misses a raw counter must be used. 520 */ 521 [C(DTLB)][C(OP_READ)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, 522 [C(DTLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, 523 [C(DTLB)][C(OP_WRITE)][C(RESULT_ACCESS)] = SCORPION_DTLB_ACCESS, 524 [C(DTLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_DTLB_MISS, 525 [C(ITLB)][C(OP_READ)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, 526 [C(ITLB)][C(OP_WRITE)][C(RESULT_MISS)] = SCORPION_ITLB_MISS, 527 [C(BPU)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 528 [C(BPU)][C(OP_READ)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 529 [C(BPU)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_BRANCH_PRED, 530 [C(BPU)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED, 531}; 532 533PMU_FORMAT_ATTR(event, "config:0-7"); 534 535static struct attribute *armv7_pmu_format_attrs[] = { 536 &format_attr_event.attr, 537 NULL, 538}; 539 540static struct attribute_group armv7_pmu_format_attr_group = { 541 .name = "format", 542 .attrs = armv7_pmu_format_attrs, 543}; 544 545#define ARMV7_EVENT_ATTR_RESOLVE(m) #m 546#define ARMV7_EVENT_ATTR(name, config) \ 547 PMU_EVENT_ATTR_STRING(name, armv7_event_attr_##name, \ 548 "event=" ARMV7_EVENT_ATTR_RESOLVE(config)) 549 550ARMV7_EVENT_ATTR(sw_incr, ARMV7_PERFCTR_PMNC_SW_INCR); 551ARMV7_EVENT_ATTR(l1i_cache_refill, ARMV7_PERFCTR_L1_ICACHE_REFILL); 552ARMV7_EVENT_ATTR(l1i_tlb_refill, ARMV7_PERFCTR_ITLB_REFILL); 553ARMV7_EVENT_ATTR(l1d_cache_refill, ARMV7_PERFCTR_L1_DCACHE_REFILL); 554ARMV7_EVENT_ATTR(l1d_cache, ARMV7_PERFCTR_L1_DCACHE_ACCESS); 555ARMV7_EVENT_ATTR(l1d_tlb_refill, ARMV7_PERFCTR_DTLB_REFILL); 556ARMV7_EVENT_ATTR(ld_retired, ARMV7_PERFCTR_MEM_READ); 557ARMV7_EVENT_ATTR(st_retired, ARMV7_PERFCTR_MEM_WRITE); 558ARMV7_EVENT_ATTR(inst_retired, ARMV7_PERFCTR_INSTR_EXECUTED); 559ARMV7_EVENT_ATTR(exc_taken, ARMV7_PERFCTR_EXC_TAKEN); 560ARMV7_EVENT_ATTR(exc_return, ARMV7_PERFCTR_EXC_EXECUTED); 561ARMV7_EVENT_ATTR(cid_write_retired, ARMV7_PERFCTR_CID_WRITE); 562ARMV7_EVENT_ATTR(pc_write_retired, ARMV7_PERFCTR_PC_WRITE); 563ARMV7_EVENT_ATTR(br_immed_retired, ARMV7_PERFCTR_PC_IMM_BRANCH); 564ARMV7_EVENT_ATTR(br_return_retired, ARMV7_PERFCTR_PC_PROC_RETURN); 565ARMV7_EVENT_ATTR(unaligned_ldst_retired, ARMV7_PERFCTR_MEM_UNALIGNED_ACCESS); 566ARMV7_EVENT_ATTR(br_mis_pred, ARMV7_PERFCTR_PC_BRANCH_MIS_PRED); 567ARMV7_EVENT_ATTR(cpu_cycles, ARMV7_PERFCTR_CLOCK_CYCLES); 568ARMV7_EVENT_ATTR(br_pred, ARMV7_PERFCTR_PC_BRANCH_PRED); 569 570static struct attribute *armv7_pmuv1_event_attrs[] = { 571 &armv7_event_attr_sw_incr.attr.attr, 572 &armv7_event_attr_l1i_cache_refill.attr.attr, 573 &armv7_event_attr_l1i_tlb_refill.attr.attr, 574 &armv7_event_attr_l1d_cache_refill.attr.attr, 575 &armv7_event_attr_l1d_cache.attr.attr, 576 &armv7_event_attr_l1d_tlb_refill.attr.attr, 577 &armv7_event_attr_ld_retired.attr.attr, 578 &armv7_event_attr_st_retired.attr.attr, 579 &armv7_event_attr_inst_retired.attr.attr, 580 &armv7_event_attr_exc_taken.attr.attr, 581 &armv7_event_attr_exc_return.attr.attr, 582 &armv7_event_attr_cid_write_retired.attr.attr, 583 &armv7_event_attr_pc_write_retired.attr.attr, 584 &armv7_event_attr_br_immed_retired.attr.attr, 585 &armv7_event_attr_br_return_retired.attr.attr, 586 &armv7_event_attr_unaligned_ldst_retired.attr.attr, 587 &armv7_event_attr_br_mis_pred.attr.attr, 588 &armv7_event_attr_cpu_cycles.attr.attr, 589 &armv7_event_attr_br_pred.attr.attr, 590 NULL, 591}; 592 593static struct attribute_group armv7_pmuv1_events_attr_group = { 594 .name = "events", 595 .attrs = armv7_pmuv1_event_attrs, 596}; 597 598ARMV7_EVENT_ATTR(mem_access, ARMV7_PERFCTR_MEM_ACCESS); 599ARMV7_EVENT_ATTR(l1i_cache, ARMV7_PERFCTR_L1_ICACHE_ACCESS); 600ARMV7_EVENT_ATTR(l1d_cache_wb, ARMV7_PERFCTR_L1_DCACHE_WB); 601ARMV7_EVENT_ATTR(l2d_cache, ARMV7_PERFCTR_L2_CACHE_ACCESS); 602ARMV7_EVENT_ATTR(l2d_cache_refill, ARMV7_PERFCTR_L2_CACHE_REFILL); 603ARMV7_EVENT_ATTR(l2d_cache_wb, ARMV7_PERFCTR_L2_CACHE_WB); 604ARMV7_EVENT_ATTR(bus_access, ARMV7_PERFCTR_BUS_ACCESS); 605ARMV7_EVENT_ATTR(memory_error, ARMV7_PERFCTR_MEM_ERROR); 606ARMV7_EVENT_ATTR(inst_spec, ARMV7_PERFCTR_INSTR_SPEC); 607ARMV7_EVENT_ATTR(ttbr_write_retired, ARMV7_PERFCTR_TTBR_WRITE); 608ARMV7_EVENT_ATTR(bus_cycles, ARMV7_PERFCTR_BUS_CYCLES); 609 610static struct attribute *armv7_pmuv2_event_attrs[] = { 611 &armv7_event_attr_sw_incr.attr.attr, 612 &armv7_event_attr_l1i_cache_refill.attr.attr, 613 &armv7_event_attr_l1i_tlb_refill.attr.attr, 614 &armv7_event_attr_l1d_cache_refill.attr.attr, 615 &armv7_event_attr_l1d_cache.attr.attr, 616 &armv7_event_attr_l1d_tlb_refill.attr.attr, 617 &armv7_event_attr_ld_retired.attr.attr, 618 &armv7_event_attr_st_retired.attr.attr, 619 &armv7_event_attr_inst_retired.attr.attr, 620 &armv7_event_attr_exc_taken.attr.attr, 621 &armv7_event_attr_exc_return.attr.attr, 622 &armv7_event_attr_cid_write_retired.attr.attr, 623 &armv7_event_attr_pc_write_retired.attr.attr, 624 &armv7_event_attr_br_immed_retired.attr.attr, 625 &armv7_event_attr_br_return_retired.attr.attr, 626 &armv7_event_attr_unaligned_ldst_retired.attr.attr, 627 &armv7_event_attr_br_mis_pred.attr.attr, 628 &armv7_event_attr_cpu_cycles.attr.attr, 629 &armv7_event_attr_br_pred.attr.attr, 630 &armv7_event_attr_mem_access.attr.attr, 631 &armv7_event_attr_l1i_cache.attr.attr, 632 &armv7_event_attr_l1d_cache_wb.attr.attr, 633 &armv7_event_attr_l2d_cache.attr.attr, 634 &armv7_event_attr_l2d_cache_refill.attr.attr, 635 &armv7_event_attr_l2d_cache_wb.attr.attr, 636 &armv7_event_attr_bus_access.attr.attr, 637 &armv7_event_attr_memory_error.attr.attr, 638 &armv7_event_attr_inst_spec.attr.attr, 639 &armv7_event_attr_ttbr_write_retired.attr.attr, 640 &armv7_event_attr_bus_cycles.attr.attr, 641 NULL, 642}; 643 644static struct attribute_group armv7_pmuv2_events_attr_group = { 645 .name = "events", 646 .attrs = armv7_pmuv2_event_attrs, 647}; 648 649/* 650 * Perf Events' indices 651 */ 652#define ARMV7_IDX_CYCLE_COUNTER 31 653#define ARMV7_IDX_COUNTER_MAX 31 654/* 655 * ARMv7 low level PMNC access 656 */ 657 658/* 659 * Per-CPU PMNC: config reg 660 */ 661#define ARMV7_PMNC_E (1 << 0) /* Enable all counters */ 662#define ARMV7_PMNC_P (1 << 1) /* Reset all counters */ 663#define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */ 664#define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */ 665#define ARMV7_PMNC_X (1 << 4) /* Export to ETM */ 666#define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/ 667#define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */ 668#define ARMV7_PMNC_N_MASK 0x1f 669#define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */ 670 671/* 672 * FLAG: counters overflow flag status reg 673 */ 674#define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */ 675#define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK 676 677/* 678 * PMXEVTYPER: Event selection reg 679 */ 680#define ARMV7_EVTYPE_MASK 0xc80000ff /* Mask for writable bits */ 681#define ARMV7_EVTYPE_EVENT 0xff /* Mask for EVENT bits */ 682 683/* 684 * Event filters for PMUv2 685 */ 686#define ARMV7_EXCLUDE_PL1 BIT(31) 687#define ARMV7_EXCLUDE_USER BIT(30) 688#define ARMV7_INCLUDE_HYP BIT(27) 689 690/* 691 * Secure debug enable reg 692 */ 693#define ARMV7_SDER_SUNIDEN BIT(1) /* Permit non-invasive debug */ 694 695static inline u32 armv7_pmnc_read(void) 696{ 697 u32 val; 698 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val)); 699 return val; 700} 701 702static inline void armv7_pmnc_write(u32 val) 703{ 704 val &= ARMV7_PMNC_MASK; 705 isb(); 706 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val)); 707} 708 709static inline int armv7_pmnc_has_overflowed(u32 pmnc) 710{ 711 return pmnc & ARMV7_OVERFLOWED_MASK; 712} 713 714static inline int armv7_pmnc_counter_valid(struct arm_pmu *cpu_pmu, int idx) 715{ 716 return test_bit(idx, cpu_pmu->cntr_mask); 717} 718 719static inline int armv7_pmnc_counter_has_overflowed(u32 pmnc, int idx) 720{ 721 return pmnc & BIT(idx); 722} 723 724static inline void armv7_pmnc_select_counter(int idx) 725{ 726 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (idx)); 727 isb(); 728} 729 730static inline u64 armv7pmu_read_counter(struct perf_event *event) 731{ 732 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 733 struct hw_perf_event *hwc = &event->hw; 734 int idx = hwc->idx; 735 u32 value = 0; 736 737 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 738 pr_err("CPU%u reading wrong counter %d\n", 739 smp_processor_id(), idx); 740 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { 741 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value)); 742 } else { 743 armv7_pmnc_select_counter(idx); 744 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (value)); 745 } 746 747 return value; 748} 749 750static inline void armv7pmu_write_counter(struct perf_event *event, u64 value) 751{ 752 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 753 struct hw_perf_event *hwc = &event->hw; 754 int idx = hwc->idx; 755 756 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 757 pr_err("CPU%u writing wrong counter %d\n", 758 smp_processor_id(), idx); 759 } else if (idx == ARMV7_IDX_CYCLE_COUNTER) { 760 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" ((u32)value)); 761 } else { 762 armv7_pmnc_select_counter(idx); 763 asm volatile("mcr p15, 0, %0, c9, c13, 2" : : "r" ((u32)value)); 764 } 765} 766 767static inline void armv7_pmnc_write_evtsel(int idx, u32 val) 768{ 769 armv7_pmnc_select_counter(idx); 770 val &= ARMV7_EVTYPE_MASK; 771 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val)); 772} 773 774static inline void armv7_pmnc_enable_counter(int idx) 775{ 776 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (BIT(idx))); 777} 778 779static inline void armv7_pmnc_disable_counter(int idx) 780{ 781 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (BIT(idx))); 782} 783 784static inline void armv7_pmnc_enable_intens(int idx) 785{ 786 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (BIT(idx))); 787} 788 789static inline void armv7_pmnc_disable_intens(int idx) 790{ 791 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (BIT(idx))); 792 isb(); 793 /* Clear the overflow flag in case an interrupt is pending. */ 794 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (BIT(idx))); 795 isb(); 796} 797 798static inline u32 armv7_pmnc_getreset_flags(void) 799{ 800 u32 val; 801 802 /* Read */ 803 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); 804 805 /* Write to clear flags */ 806 val &= ARMV7_FLAG_MASK; 807 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val)); 808 809 return val; 810} 811 812#ifdef DEBUG 813static void armv7_pmnc_dump_regs(struct arm_pmu *cpu_pmu) 814{ 815 u32 val; 816 unsigned int cnt; 817 818 pr_info("PMNC registers dump:\n"); 819 820 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val)); 821 pr_info("PMNC =0x%08x\n", val); 822 823 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val)); 824 pr_info("CNTENS=0x%08x\n", val); 825 826 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val)); 827 pr_info("INTENS=0x%08x\n", val); 828 829 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val)); 830 pr_info("FLAGS =0x%08x\n", val); 831 832 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val)); 833 pr_info("SELECT=0x%08x\n", val); 834 835 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val)); 836 pr_info("CCNT =0x%08x\n", val); 837 838 for_each_set_bit(cnt, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 839 armv7_pmnc_select_counter(cnt); 840 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val)); 841 pr_info("CNT[%d] count =0x%08x\n", cnt, val); 842 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val)); 843 pr_info("CNT[%d] evtsel=0x%08x\n", cnt, val); 844 } 845} 846#endif 847 848static void armv7pmu_enable_event(struct perf_event *event) 849{ 850 struct hw_perf_event *hwc = &event->hw; 851 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 852 int idx = hwc->idx; 853 854 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 855 pr_err("CPU%u enabling wrong PMNC counter IRQ enable %d\n", 856 smp_processor_id(), idx); 857 return; 858 } 859 860 /* 861 * Set event (if destined for PMNx counters) 862 * We only need to set the event for the cycle counter if we 863 * have the ability to perform event filtering. 864 */ 865 if (cpu_pmu->set_event_filter || idx != ARMV7_IDX_CYCLE_COUNTER) 866 armv7_pmnc_write_evtsel(idx, hwc->config_base); 867 868 armv7_pmnc_enable_intens(idx); 869 armv7_pmnc_enable_counter(idx); 870} 871 872static void armv7pmu_disable_event(struct perf_event *event) 873{ 874 struct hw_perf_event *hwc = &event->hw; 875 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 876 int idx = hwc->idx; 877 878 if (!armv7_pmnc_counter_valid(cpu_pmu, idx)) { 879 pr_err("CPU%u disabling wrong PMNC counter IRQ enable %d\n", 880 smp_processor_id(), idx); 881 return; 882 } 883 884 armv7_pmnc_disable_counter(idx); 885 armv7_pmnc_disable_intens(idx); 886} 887 888static irqreturn_t armv7pmu_handle_irq(struct arm_pmu *cpu_pmu) 889{ 890 u32 pmnc; 891 struct perf_sample_data data; 892 struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events); 893 struct pt_regs *regs; 894 int idx; 895 896 /* 897 * Get and reset the IRQ flags 898 */ 899 pmnc = armv7_pmnc_getreset_flags(); 900 901 /* 902 * Did an overflow occur? 903 */ 904 if (!armv7_pmnc_has_overflowed(pmnc)) 905 return IRQ_NONE; 906 907 /* 908 * Handle the counter(s) overflow(s) 909 */ 910 regs = get_irq_regs(); 911 912 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { 913 struct perf_event *event = cpuc->events[idx]; 914 struct hw_perf_event *hwc; 915 916 /* Ignore if we don't have an event. */ 917 if (!event) 918 continue; 919 920 /* 921 * We have a single interrupt for all counters. Check that 922 * each counter has overflowed before we process it. 923 */ 924 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx)) 925 continue; 926 927 hwc = &event->hw; 928 armpmu_event_update(event); 929 perf_sample_data_init(&data, 0, hwc->last_period); 930 if (!armpmu_event_set_period(event)) 931 continue; 932 933 perf_event_overflow(event, &data, regs); 934 } 935 936 /* 937 * Handle the pending perf events. 938 * 939 * Note: this call *must* be run with interrupts disabled. For 940 * platforms that can have the PMU interrupts raised as an NMI, this 941 * will not work. 942 */ 943 irq_work_run(); 944 945 return IRQ_HANDLED; 946} 947 948static void armv7pmu_start(struct arm_pmu *cpu_pmu) 949{ 950 /* Enable all counters */ 951 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E); 952} 953 954static void armv7pmu_stop(struct arm_pmu *cpu_pmu) 955{ 956 /* Disable all counters */ 957 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E); 958} 959 960static int armv7pmu_get_event_idx(struct pmu_hw_events *cpuc, 961 struct perf_event *event) 962{ 963 int idx; 964 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 965 struct hw_perf_event *hwc = &event->hw; 966 unsigned long evtype = hwc->config_base & ARMV7_EVTYPE_EVENT; 967 968 /* Always place a cycle counter into the cycle counter. */ 969 if (evtype == ARMV7_PERFCTR_CPU_CYCLES) { 970 if (test_and_set_bit(ARMV7_IDX_CYCLE_COUNTER, cpuc->used_mask)) 971 return -EAGAIN; 972 973 return ARMV7_IDX_CYCLE_COUNTER; 974 } 975 976 /* 977 * For anything other than a cycle counter, try and use 978 * the events counters 979 */ 980 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 981 if (!test_and_set_bit(idx, cpuc->used_mask)) 982 return idx; 983 } 984 985 /* The counters are all in use. */ 986 return -EAGAIN; 987} 988 989static void armv7pmu_clear_event_idx(struct pmu_hw_events *cpuc, 990 struct perf_event *event) 991{ 992 clear_bit(event->hw.idx, cpuc->used_mask); 993} 994 995/* 996 * Add an event filter to a given event. This will only work for PMUv2 PMUs. 997 */ 998static int armv7pmu_set_event_filter(struct hw_perf_event *event, 999 struct perf_event_attr *attr) 1000{ 1001 unsigned long config_base = 0; 1002 1003 if (attr->exclude_idle) { 1004 pr_debug("ARM performance counters do not support mode exclusion\n"); 1005 return -EOPNOTSUPP; 1006 } 1007 if (attr->exclude_user) 1008 config_base |= ARMV7_EXCLUDE_USER; 1009 if (attr->exclude_kernel) 1010 config_base |= ARMV7_EXCLUDE_PL1; 1011 if (!attr->exclude_hv) 1012 config_base |= ARMV7_INCLUDE_HYP; 1013 1014 /* 1015 * Install the filter into config_base as this is used to 1016 * construct the event type. 1017 */ 1018 event->config_base = config_base; 1019 1020 return 0; 1021} 1022 1023static void armv7pmu_reset(void *info) 1024{ 1025 struct arm_pmu *cpu_pmu = (struct arm_pmu *)info; 1026 u32 idx, val; 1027 1028 if (cpu_pmu->secure_access) { 1029 asm volatile("mrc p15, 0, %0, c1, c1, 1" : "=r" (val)); 1030 val |= ARMV7_SDER_SUNIDEN; 1031 asm volatile("mcr p15, 0, %0, c1, c1, 1" : : "r" (val)); 1032 } 1033 1034 /* The counter and interrupt enable registers are unknown at reset. */ 1035 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMPMU_MAX_HWEVENTS) { 1036 armv7_pmnc_disable_counter(idx); 1037 armv7_pmnc_disable_intens(idx); 1038 } 1039 1040 /* Initialize & Reset PMNC: C and P bits */ 1041 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C); 1042} 1043 1044static int armv7_a8_map_event(struct perf_event *event) 1045{ 1046 return armpmu_map_event(event, &armv7_a8_perf_map, 1047 &armv7_a8_perf_cache_map, 0xFF); 1048} 1049 1050static int armv7_a9_map_event(struct perf_event *event) 1051{ 1052 return armpmu_map_event(event, &armv7_a9_perf_map, 1053 &armv7_a9_perf_cache_map, 0xFF); 1054} 1055 1056static int armv7_a5_map_event(struct perf_event *event) 1057{ 1058 return armpmu_map_event(event, &armv7_a5_perf_map, 1059 &armv7_a5_perf_cache_map, 0xFF); 1060} 1061 1062static int armv7_a15_map_event(struct perf_event *event) 1063{ 1064 return armpmu_map_event(event, &armv7_a15_perf_map, 1065 &armv7_a15_perf_cache_map, 0xFF); 1066} 1067 1068static int armv7_a7_map_event(struct perf_event *event) 1069{ 1070 return armpmu_map_event(event, &armv7_a7_perf_map, 1071 &armv7_a7_perf_cache_map, 0xFF); 1072} 1073 1074static int armv7_a12_map_event(struct perf_event *event) 1075{ 1076 return armpmu_map_event(event, &armv7_a12_perf_map, 1077 &armv7_a12_perf_cache_map, 0xFF); 1078} 1079 1080static int krait_map_event(struct perf_event *event) 1081{ 1082 return armpmu_map_event(event, &krait_perf_map, 1083 &krait_perf_cache_map, 0xFFFFF); 1084} 1085 1086static int krait_map_event_no_branch(struct perf_event *event) 1087{ 1088 return armpmu_map_event(event, &krait_perf_map_no_branch, 1089 &krait_perf_cache_map, 0xFFFFF); 1090} 1091 1092static int scorpion_map_event(struct perf_event *event) 1093{ 1094 return armpmu_map_event(event, &scorpion_perf_map, 1095 &scorpion_perf_cache_map, 0xFFFFF); 1096} 1097 1098static void armv7pmu_init(struct arm_pmu *cpu_pmu) 1099{ 1100 cpu_pmu->handle_irq = armv7pmu_handle_irq; 1101 cpu_pmu->enable = armv7pmu_enable_event; 1102 cpu_pmu->disable = armv7pmu_disable_event; 1103 cpu_pmu->read_counter = armv7pmu_read_counter; 1104 cpu_pmu->write_counter = armv7pmu_write_counter; 1105 cpu_pmu->get_event_idx = armv7pmu_get_event_idx; 1106 cpu_pmu->clear_event_idx = armv7pmu_clear_event_idx; 1107 cpu_pmu->start = armv7pmu_start; 1108 cpu_pmu->stop = armv7pmu_stop; 1109 cpu_pmu->reset = armv7pmu_reset; 1110}; 1111 1112static void armv7_read_num_pmnc_events(void *info) 1113{ 1114 int nb_cnt; 1115 struct arm_pmu *cpu_pmu = info; 1116 1117 /* Read the nb of CNTx counters supported from PMNC */ 1118 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK; 1119 bitmap_set(cpu_pmu->cntr_mask, 0, nb_cnt); 1120 1121 /* Add the CPU cycles counter */ 1122 set_bit(ARMV7_IDX_CYCLE_COUNTER, cpu_pmu->cntr_mask); 1123} 1124 1125static int armv7_probe_num_events(struct arm_pmu *arm_pmu) 1126{ 1127 return smp_call_function_any(&arm_pmu->supported_cpus, 1128 armv7_read_num_pmnc_events, 1129 arm_pmu, 1); 1130} 1131 1132static int armv7_a8_pmu_init(struct arm_pmu *cpu_pmu) 1133{ 1134 armv7pmu_init(cpu_pmu); 1135 cpu_pmu->name = "armv7_cortex_a8"; 1136 cpu_pmu->map_event = armv7_a8_map_event; 1137 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1138 &armv7_pmuv1_events_attr_group; 1139 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1140 &armv7_pmu_format_attr_group; 1141 return armv7_probe_num_events(cpu_pmu); 1142} 1143 1144static int armv7_a9_pmu_init(struct arm_pmu *cpu_pmu) 1145{ 1146 armv7pmu_init(cpu_pmu); 1147 cpu_pmu->name = "armv7_cortex_a9"; 1148 cpu_pmu->map_event = armv7_a9_map_event; 1149 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1150 &armv7_pmuv1_events_attr_group; 1151 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1152 &armv7_pmu_format_attr_group; 1153 return armv7_probe_num_events(cpu_pmu); 1154} 1155 1156static int armv7_a5_pmu_init(struct arm_pmu *cpu_pmu) 1157{ 1158 armv7pmu_init(cpu_pmu); 1159 cpu_pmu->name = "armv7_cortex_a5"; 1160 cpu_pmu->map_event = armv7_a5_map_event; 1161 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1162 &armv7_pmuv1_events_attr_group; 1163 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1164 &armv7_pmu_format_attr_group; 1165 return armv7_probe_num_events(cpu_pmu); 1166} 1167 1168static int armv7_a15_pmu_init(struct arm_pmu *cpu_pmu) 1169{ 1170 armv7pmu_init(cpu_pmu); 1171 cpu_pmu->name = "armv7_cortex_a15"; 1172 cpu_pmu->map_event = armv7_a15_map_event; 1173 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1174 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1175 &armv7_pmuv2_events_attr_group; 1176 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1177 &armv7_pmu_format_attr_group; 1178 return armv7_probe_num_events(cpu_pmu); 1179} 1180 1181static int armv7_a7_pmu_init(struct arm_pmu *cpu_pmu) 1182{ 1183 armv7pmu_init(cpu_pmu); 1184 cpu_pmu->name = "armv7_cortex_a7"; 1185 cpu_pmu->map_event = armv7_a7_map_event; 1186 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1187 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1188 &armv7_pmuv2_events_attr_group; 1189 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1190 &armv7_pmu_format_attr_group; 1191 return armv7_probe_num_events(cpu_pmu); 1192} 1193 1194static int armv7_a12_pmu_init(struct arm_pmu *cpu_pmu) 1195{ 1196 armv7pmu_init(cpu_pmu); 1197 cpu_pmu->name = "armv7_cortex_a12"; 1198 cpu_pmu->map_event = armv7_a12_map_event; 1199 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1200 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1201 &armv7_pmuv2_events_attr_group; 1202 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1203 &armv7_pmu_format_attr_group; 1204 return armv7_probe_num_events(cpu_pmu); 1205} 1206 1207static int armv7_a17_pmu_init(struct arm_pmu *cpu_pmu) 1208{ 1209 int ret = armv7_a12_pmu_init(cpu_pmu); 1210 cpu_pmu->name = "armv7_cortex_a17"; 1211 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = 1212 &armv7_pmuv2_events_attr_group; 1213 cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = 1214 &armv7_pmu_format_attr_group; 1215 return ret; 1216} 1217 1218/* 1219 * Krait Performance Monitor Region Event Selection Register (PMRESRn) 1220 * 1221 * 31 30 24 16 8 0 1222 * +--------------------------------+ 1223 * PMRESR0 | EN | CC | CC | CC | CC | N = 1, R = 0 1224 * +--------------------------------+ 1225 * PMRESR1 | EN | CC | CC | CC | CC | N = 1, R = 1 1226 * +--------------------------------+ 1227 * PMRESR2 | EN | CC | CC | CC | CC | N = 1, R = 2 1228 * +--------------------------------+ 1229 * VPMRESR0 | EN | CC | CC | CC | CC | N = 2, R = ? 1230 * +--------------------------------+ 1231 * EN | G=3 | G=2 | G=1 | G=0 1232 * 1233 * Event Encoding: 1234 * 1235 * hwc->config_base = 0xNRCCG 1236 * 1237 * N = prefix, 1 for Krait CPU (PMRESRn), 2 for Venum VFP (VPMRESR) 1238 * R = region register 1239 * CC = class of events the group G is choosing from 1240 * G = group or particular event 1241 * 1242 * Example: 0x12021 is a Krait CPU event in PMRESR2's group 1 with code 2 1243 * 1244 * A region (R) corresponds to a piece of the CPU (execution unit, instruction 1245 * unit, etc.) while the event code (CC) corresponds to a particular class of 1246 * events (interrupts for example). An event code is broken down into 1247 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for 1248 * example). 1249 */ 1250 1251#define KRAIT_EVENT (1 << 16) 1252#define VENUM_EVENT (2 << 16) 1253#define KRAIT_EVENT_MASK (KRAIT_EVENT | VENUM_EVENT) 1254#define PMRESRn_EN BIT(31) 1255 1256#define EVENT_REGION(event) (((event) >> 12) & 0xf) /* R */ 1257#define EVENT_GROUP(event) ((event) & 0xf) /* G */ 1258#define EVENT_CODE(event) (((event) >> 4) & 0xff) /* CC */ 1259#define EVENT_VENUM(event) (!!(event & VENUM_EVENT)) /* N=2 */ 1260#define EVENT_CPU(event) (!!(event & KRAIT_EVENT)) /* N=1 */ 1261 1262static u32 krait_read_pmresrn(int n) 1263{ 1264 u32 val; 1265 1266 switch (n) { 1267 case 0: 1268 asm volatile("mrc p15, 1, %0, c9, c15, 0" : "=r" (val)); 1269 break; 1270 case 1: 1271 asm volatile("mrc p15, 1, %0, c9, c15, 1" : "=r" (val)); 1272 break; 1273 case 2: 1274 asm volatile("mrc p15, 1, %0, c9, c15, 2" : "=r" (val)); 1275 break; 1276 default: 1277 BUG(); /* Should be validated in krait_pmu_get_event_idx() */ 1278 } 1279 1280 return val; 1281} 1282 1283static void krait_write_pmresrn(int n, u32 val) 1284{ 1285 switch (n) { 1286 case 0: 1287 asm volatile("mcr p15, 1, %0, c9, c15, 0" : : "r" (val)); 1288 break; 1289 case 1: 1290 asm volatile("mcr p15, 1, %0, c9, c15, 1" : : "r" (val)); 1291 break; 1292 case 2: 1293 asm volatile("mcr p15, 1, %0, c9, c15, 2" : : "r" (val)); 1294 break; 1295 default: 1296 BUG(); /* Should be validated in krait_pmu_get_event_idx() */ 1297 } 1298} 1299 1300static u32 venum_read_pmresr(void) 1301{ 1302 u32 val; 1303 asm volatile("mrc p10, 7, %0, c11, c0, 0" : "=r" (val)); 1304 return val; 1305} 1306 1307static void venum_write_pmresr(u32 val) 1308{ 1309 asm volatile("mcr p10, 7, %0, c11, c0, 0" : : "r" (val)); 1310} 1311 1312static void venum_pre_pmresr(u32 *venum_orig_val, u32 *fp_orig_val) 1313{ 1314 u32 venum_new_val; 1315 u32 fp_new_val; 1316 1317 BUG_ON(preemptible()); 1318 /* CPACR Enable CP10 and CP11 access */ 1319 *venum_orig_val = get_copro_access(); 1320 venum_new_val = *venum_orig_val | CPACC_SVC(10) | CPACC_SVC(11); 1321 set_copro_access(venum_new_val); 1322 1323 /* Enable FPEXC */ 1324 *fp_orig_val = fmrx(FPEXC); 1325 fp_new_val = *fp_orig_val | FPEXC_EN; 1326 fmxr(FPEXC, fp_new_val); 1327} 1328 1329static void venum_post_pmresr(u32 venum_orig_val, u32 fp_orig_val) 1330{ 1331 BUG_ON(preemptible()); 1332 /* Restore FPEXC */ 1333 fmxr(FPEXC, fp_orig_val); 1334 isb(); 1335 /* Restore CPACR */ 1336 set_copro_access(venum_orig_val); 1337} 1338 1339static u32 krait_get_pmresrn_event(unsigned int region) 1340{ 1341 static const u32 pmresrn_table[] = { KRAIT_PMRESR0_GROUP0, 1342 KRAIT_PMRESR1_GROUP0, 1343 KRAIT_PMRESR2_GROUP0 }; 1344 return pmresrn_table[region]; 1345} 1346 1347static void krait_evt_setup(int idx, u32 config_base) 1348{ 1349 u32 val; 1350 u32 mask; 1351 u32 vval, fval; 1352 unsigned int region = EVENT_REGION(config_base); 1353 unsigned int group = EVENT_GROUP(config_base); 1354 unsigned int code = EVENT_CODE(config_base); 1355 unsigned int group_shift; 1356 bool venum_event = EVENT_VENUM(config_base); 1357 1358 group_shift = group * 8; 1359 mask = 0xff << group_shift; 1360 1361 /* Configure evtsel for the region and group */ 1362 if (venum_event) 1363 val = KRAIT_VPMRESR0_GROUP0; 1364 else 1365 val = krait_get_pmresrn_event(region); 1366 val += group; 1367 /* Mix in mode-exclusion bits */ 1368 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); 1369 armv7_pmnc_write_evtsel(idx, val); 1370 1371 if (venum_event) { 1372 venum_pre_pmresr(&vval, &fval); 1373 val = venum_read_pmresr(); 1374 val &= ~mask; 1375 val |= code << group_shift; 1376 val |= PMRESRn_EN; 1377 venum_write_pmresr(val); 1378 venum_post_pmresr(vval, fval); 1379 } else { 1380 val = krait_read_pmresrn(region); 1381 val &= ~mask; 1382 val |= code << group_shift; 1383 val |= PMRESRn_EN; 1384 krait_write_pmresrn(region, val); 1385 } 1386} 1387 1388static u32 clear_pmresrn_group(u32 val, int group) 1389{ 1390 u32 mask; 1391 int group_shift; 1392 1393 group_shift = group * 8; 1394 mask = 0xff << group_shift; 1395 val &= ~mask; 1396 1397 /* Don't clear enable bit if entire region isn't disabled */ 1398 if (val & ~PMRESRn_EN) 1399 return val |= PMRESRn_EN; 1400 1401 return 0; 1402} 1403 1404static void krait_clearpmu(u32 config_base) 1405{ 1406 u32 val; 1407 u32 vval, fval; 1408 unsigned int region = EVENT_REGION(config_base); 1409 unsigned int group = EVENT_GROUP(config_base); 1410 bool venum_event = EVENT_VENUM(config_base); 1411 1412 if (venum_event) { 1413 venum_pre_pmresr(&vval, &fval); 1414 val = venum_read_pmresr(); 1415 val = clear_pmresrn_group(val, group); 1416 venum_write_pmresr(val); 1417 venum_post_pmresr(vval, fval); 1418 } else { 1419 val = krait_read_pmresrn(region); 1420 val = clear_pmresrn_group(val, group); 1421 krait_write_pmresrn(region, val); 1422 } 1423} 1424 1425static void krait_pmu_disable_event(struct perf_event *event) 1426{ 1427 struct hw_perf_event *hwc = &event->hw; 1428 int idx = hwc->idx; 1429 1430 /* Disable counter and interrupt */ 1431 1432 /* Disable counter */ 1433 armv7_pmnc_disable_counter(idx); 1434 1435 /* 1436 * Clear pmresr code (if destined for PMNx counters) 1437 */ 1438 if (hwc->config_base & KRAIT_EVENT_MASK) 1439 krait_clearpmu(hwc->config_base); 1440 1441 /* Disable interrupt for this counter */ 1442 armv7_pmnc_disable_intens(idx); 1443} 1444 1445static void krait_pmu_enable_event(struct perf_event *event) 1446{ 1447 struct hw_perf_event *hwc = &event->hw; 1448 int idx = hwc->idx; 1449 1450 /* 1451 * Set event (if destined for PMNx counters) 1452 * We set the event for the cycle counter because we 1453 * have the ability to perform event filtering. 1454 */ 1455 if (hwc->config_base & KRAIT_EVENT_MASK) 1456 krait_evt_setup(idx, hwc->config_base); 1457 else 1458 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1459 1460 armv7_pmnc_enable_intens(idx); 1461 armv7_pmnc_enable_counter(idx); 1462} 1463 1464static void krait_pmu_reset(void *info) 1465{ 1466 u32 vval, fval; 1467 struct arm_pmu *cpu_pmu = info; 1468 u32 idx; 1469 1470 armv7pmu_reset(info); 1471 1472 /* Clear all pmresrs */ 1473 krait_write_pmresrn(0, 0); 1474 krait_write_pmresrn(1, 0); 1475 krait_write_pmresrn(2, 0); 1476 1477 venum_pre_pmresr(&vval, &fval); 1478 venum_write_pmresr(0); 1479 venum_post_pmresr(vval, fval); 1480 1481 /* Reset PMxEVNCTCR to sane default */ 1482 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 1483 armv7_pmnc_select_counter(idx); 1484 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1485 } 1486 1487} 1488 1489static int krait_event_to_bit(struct perf_event *event, unsigned int region, 1490 unsigned int group) 1491{ 1492 int bit; 1493 struct hw_perf_event *hwc = &event->hw; 1494 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1495 1496 if (hwc->config_base & VENUM_EVENT) 1497 bit = KRAIT_VPMRESR0_GROUP0; 1498 else 1499 bit = krait_get_pmresrn_event(region); 1500 bit -= krait_get_pmresrn_event(0); 1501 bit += group; 1502 /* 1503 * Lower bits are reserved for use by the counters (see 1504 * armv7pmu_get_event_idx() for more info) 1505 */ 1506 bit += bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); 1507 1508 return bit; 1509} 1510 1511/* 1512 * We check for column exclusion constraints here. 1513 * Two events cant use the same group within a pmresr register. 1514 */ 1515static int krait_pmu_get_event_idx(struct pmu_hw_events *cpuc, 1516 struct perf_event *event) 1517{ 1518 int idx; 1519 int bit = -1; 1520 struct hw_perf_event *hwc = &event->hw; 1521 unsigned int region = EVENT_REGION(hwc->config_base); 1522 unsigned int code = EVENT_CODE(hwc->config_base); 1523 unsigned int group = EVENT_GROUP(hwc->config_base); 1524 bool venum_event = EVENT_VENUM(hwc->config_base); 1525 bool krait_event = EVENT_CPU(hwc->config_base); 1526 1527 if (venum_event || krait_event) { 1528 /* Ignore invalid events */ 1529 if (group > 3 || region > 2) 1530 return -EINVAL; 1531 if (venum_event && (code & 0xe0)) 1532 return -EINVAL; 1533 1534 bit = krait_event_to_bit(event, region, group); 1535 if (test_and_set_bit(bit, cpuc->used_mask)) 1536 return -EAGAIN; 1537 } 1538 1539 idx = armv7pmu_get_event_idx(cpuc, event); 1540 if (idx < 0 && bit >= 0) 1541 clear_bit(bit, cpuc->used_mask); 1542 1543 return idx; 1544} 1545 1546static void krait_pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1547 struct perf_event *event) 1548{ 1549 int bit; 1550 struct hw_perf_event *hwc = &event->hw; 1551 unsigned int region = EVENT_REGION(hwc->config_base); 1552 unsigned int group = EVENT_GROUP(hwc->config_base); 1553 bool venum_event = EVENT_VENUM(hwc->config_base); 1554 bool krait_event = EVENT_CPU(hwc->config_base); 1555 1556 armv7pmu_clear_event_idx(cpuc, event); 1557 if (venum_event || krait_event) { 1558 bit = krait_event_to_bit(event, region, group); 1559 clear_bit(bit, cpuc->used_mask); 1560 } 1561} 1562 1563static int krait_pmu_init(struct arm_pmu *cpu_pmu) 1564{ 1565 armv7pmu_init(cpu_pmu); 1566 cpu_pmu->name = "armv7_krait"; 1567 /* Some early versions of Krait don't support PC write events */ 1568 if (of_property_read_bool(cpu_pmu->plat_device->dev.of_node, 1569 "qcom,no-pc-write")) 1570 cpu_pmu->map_event = krait_map_event_no_branch; 1571 else 1572 cpu_pmu->map_event = krait_map_event; 1573 cpu_pmu->set_event_filter = armv7pmu_set_event_filter; 1574 cpu_pmu->reset = krait_pmu_reset; 1575 cpu_pmu->enable = krait_pmu_enable_event; 1576 cpu_pmu->disable = krait_pmu_disable_event; 1577 cpu_pmu->get_event_idx = krait_pmu_get_event_idx; 1578 cpu_pmu->clear_event_idx = krait_pmu_clear_event_idx; 1579 return armv7_probe_num_events(cpu_pmu); 1580} 1581 1582/* 1583 * Scorpion Local Performance Monitor Register (LPMn) 1584 * 1585 * 31 30 24 16 8 0 1586 * +--------------------------------+ 1587 * LPM0 | EN | CC | CC | CC | CC | N = 1, R = 0 1588 * +--------------------------------+ 1589 * LPM1 | EN | CC | CC | CC | CC | N = 1, R = 1 1590 * +--------------------------------+ 1591 * LPM2 | EN | CC | CC | CC | CC | N = 1, R = 2 1592 * +--------------------------------+ 1593 * L2LPM | EN | CC | CC | CC | CC | N = 1, R = 3 1594 * +--------------------------------+ 1595 * VLPM | EN | CC | CC | CC | CC | N = 2, R = ? 1596 * +--------------------------------+ 1597 * EN | G=3 | G=2 | G=1 | G=0 1598 * 1599 * 1600 * Event Encoding: 1601 * 1602 * hwc->config_base = 0xNRCCG 1603 * 1604 * N = prefix, 1 for Scorpion CPU (LPMn/L2LPM), 2 for Venum VFP (VLPM) 1605 * R = region register 1606 * CC = class of events the group G is choosing from 1607 * G = group or particular event 1608 * 1609 * Example: 0x12021 is a Scorpion CPU event in LPM2's group 1 with code 2 1610 * 1611 * A region (R) corresponds to a piece of the CPU (execution unit, instruction 1612 * unit, etc.) while the event code (CC) corresponds to a particular class of 1613 * events (interrupts for example). An event code is broken down into 1614 * groups (G) that can be mapped into the PMU (irq, fiqs, and irq+fiqs for 1615 * example). 1616 */ 1617 1618static u32 scorpion_read_pmresrn(int n) 1619{ 1620 u32 val; 1621 1622 switch (n) { 1623 case 0: 1624 asm volatile("mrc p15, 0, %0, c15, c0, 0" : "=r" (val)); 1625 break; 1626 case 1: 1627 asm volatile("mrc p15, 1, %0, c15, c0, 0" : "=r" (val)); 1628 break; 1629 case 2: 1630 asm volatile("mrc p15, 2, %0, c15, c0, 0" : "=r" (val)); 1631 break; 1632 case 3: 1633 asm volatile("mrc p15, 3, %0, c15, c2, 0" : "=r" (val)); 1634 break; 1635 default: 1636 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ 1637 } 1638 1639 return val; 1640} 1641 1642static void scorpion_write_pmresrn(int n, u32 val) 1643{ 1644 switch (n) { 1645 case 0: 1646 asm volatile("mcr p15, 0, %0, c15, c0, 0" : : "r" (val)); 1647 break; 1648 case 1: 1649 asm volatile("mcr p15, 1, %0, c15, c0, 0" : : "r" (val)); 1650 break; 1651 case 2: 1652 asm volatile("mcr p15, 2, %0, c15, c0, 0" : : "r" (val)); 1653 break; 1654 case 3: 1655 asm volatile("mcr p15, 3, %0, c15, c2, 0" : : "r" (val)); 1656 break; 1657 default: 1658 BUG(); /* Should be validated in scorpion_pmu_get_event_idx() */ 1659 } 1660} 1661 1662static u32 scorpion_get_pmresrn_event(unsigned int region) 1663{ 1664 static const u32 pmresrn_table[] = { SCORPION_LPM0_GROUP0, 1665 SCORPION_LPM1_GROUP0, 1666 SCORPION_LPM2_GROUP0, 1667 SCORPION_L2LPM_GROUP0 }; 1668 return pmresrn_table[region]; 1669} 1670 1671static void scorpion_evt_setup(int idx, u32 config_base) 1672{ 1673 u32 val; 1674 u32 mask; 1675 u32 vval, fval; 1676 unsigned int region = EVENT_REGION(config_base); 1677 unsigned int group = EVENT_GROUP(config_base); 1678 unsigned int code = EVENT_CODE(config_base); 1679 unsigned int group_shift; 1680 bool venum_event = EVENT_VENUM(config_base); 1681 1682 group_shift = group * 8; 1683 mask = 0xff << group_shift; 1684 1685 /* Configure evtsel for the region and group */ 1686 if (venum_event) 1687 val = SCORPION_VLPM_GROUP0; 1688 else 1689 val = scorpion_get_pmresrn_event(region); 1690 val += group; 1691 /* Mix in mode-exclusion bits */ 1692 val |= config_base & (ARMV7_EXCLUDE_USER | ARMV7_EXCLUDE_PL1); 1693 armv7_pmnc_write_evtsel(idx, val); 1694 1695 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1696 1697 if (venum_event) { 1698 venum_pre_pmresr(&vval, &fval); 1699 val = venum_read_pmresr(); 1700 val &= ~mask; 1701 val |= code << group_shift; 1702 val |= PMRESRn_EN; 1703 venum_write_pmresr(val); 1704 venum_post_pmresr(vval, fval); 1705 } else { 1706 val = scorpion_read_pmresrn(region); 1707 val &= ~mask; 1708 val |= code << group_shift; 1709 val |= PMRESRn_EN; 1710 scorpion_write_pmresrn(region, val); 1711 } 1712} 1713 1714static void scorpion_clearpmu(u32 config_base) 1715{ 1716 u32 val; 1717 u32 vval, fval; 1718 unsigned int region = EVENT_REGION(config_base); 1719 unsigned int group = EVENT_GROUP(config_base); 1720 bool venum_event = EVENT_VENUM(config_base); 1721 1722 if (venum_event) { 1723 venum_pre_pmresr(&vval, &fval); 1724 val = venum_read_pmresr(); 1725 val = clear_pmresrn_group(val, group); 1726 venum_write_pmresr(val); 1727 venum_post_pmresr(vval, fval); 1728 } else { 1729 val = scorpion_read_pmresrn(region); 1730 val = clear_pmresrn_group(val, group); 1731 scorpion_write_pmresrn(region, val); 1732 } 1733} 1734 1735static void scorpion_pmu_disable_event(struct perf_event *event) 1736{ 1737 struct hw_perf_event *hwc = &event->hw; 1738 int idx = hwc->idx; 1739 1740 /* Disable counter and interrupt */ 1741 1742 /* Disable counter */ 1743 armv7_pmnc_disable_counter(idx); 1744 1745 /* 1746 * Clear pmresr code (if destined for PMNx counters) 1747 */ 1748 if (hwc->config_base & KRAIT_EVENT_MASK) 1749 scorpion_clearpmu(hwc->config_base); 1750 1751 /* Disable interrupt for this counter */ 1752 armv7_pmnc_disable_intens(idx); 1753} 1754 1755static void scorpion_pmu_enable_event(struct perf_event *event) 1756{ 1757 struct hw_perf_event *hwc = &event->hw; 1758 int idx = hwc->idx; 1759 1760 /* 1761 * Set event (if destined for PMNx counters) 1762 * We don't set the event for the cycle counter because we 1763 * don't have the ability to perform event filtering. 1764 */ 1765 if (hwc->config_base & KRAIT_EVENT_MASK) 1766 scorpion_evt_setup(idx, hwc->config_base); 1767 else if (idx != ARMV7_IDX_CYCLE_COUNTER) 1768 armv7_pmnc_write_evtsel(idx, hwc->config_base); 1769 1770 armv7_pmnc_enable_intens(idx); 1771 armv7_pmnc_enable_counter(idx); 1772} 1773 1774static void scorpion_pmu_reset(void *info) 1775{ 1776 u32 vval, fval; 1777 struct arm_pmu *cpu_pmu = info; 1778 u32 idx; 1779 1780 armv7pmu_reset(info); 1781 1782 /* Clear all pmresrs */ 1783 scorpion_write_pmresrn(0, 0); 1784 scorpion_write_pmresrn(1, 0); 1785 scorpion_write_pmresrn(2, 0); 1786 scorpion_write_pmresrn(3, 0); 1787 1788 venum_pre_pmresr(&vval, &fval); 1789 venum_write_pmresr(0); 1790 venum_post_pmresr(vval, fval); 1791 1792 /* Reset PMxEVNCTCR to sane default */ 1793 for_each_set_bit(idx, cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX) { 1794 armv7_pmnc_select_counter(idx); 1795 asm volatile("mcr p15, 0, %0, c9, c15, 0" : : "r" (0)); 1796 } 1797} 1798 1799static int scorpion_event_to_bit(struct perf_event *event, unsigned int region, 1800 unsigned int group) 1801{ 1802 int bit; 1803 struct hw_perf_event *hwc = &event->hw; 1804 struct arm_pmu *cpu_pmu = to_arm_pmu(event->pmu); 1805 1806 if (hwc->config_base & VENUM_EVENT) 1807 bit = SCORPION_VLPM_GROUP0; 1808 else 1809 bit = scorpion_get_pmresrn_event(region); 1810 bit -= scorpion_get_pmresrn_event(0); 1811 bit += group; 1812 /* 1813 * Lower bits are reserved for use by the counters (see 1814 * armv7pmu_get_event_idx() for more info) 1815 */ 1816 bit += bitmap_weight(cpu_pmu->cntr_mask, ARMV7_IDX_COUNTER_MAX); 1817 1818 return bit; 1819} 1820 1821/* 1822 * We check for column exclusion constraints here. 1823 * Two events cant use the same group within a pmresr register. 1824 */ 1825static int scorpion_pmu_get_event_idx(struct pmu_hw_events *cpuc, 1826 struct perf_event *event) 1827{ 1828 int idx; 1829 int bit = -1; 1830 struct hw_perf_event *hwc = &event->hw; 1831 unsigned int region = EVENT_REGION(hwc->config_base); 1832 unsigned int group = EVENT_GROUP(hwc->config_base); 1833 bool venum_event = EVENT_VENUM(hwc->config_base); 1834 bool scorpion_event = EVENT_CPU(hwc->config_base); 1835 1836 if (venum_event || scorpion_event) { 1837 /* Ignore invalid events */ 1838 if (group > 3 || region > 3) 1839 return -EINVAL; 1840 1841 bit = scorpion_event_to_bit(event, region, group); 1842 if (test_and_set_bit(bit, cpuc->used_mask)) 1843 return -EAGAIN; 1844 } 1845 1846 idx = armv7pmu_get_event_idx(cpuc, event); 1847 if (idx < 0 && bit >= 0) 1848 clear_bit(bit, cpuc->used_mask); 1849 1850 return idx; 1851} 1852 1853static void scorpion_pmu_clear_event_idx(struct pmu_hw_events *cpuc, 1854 struct perf_event *event) 1855{ 1856 int bit; 1857 struct hw_perf_event *hwc = &event->hw; 1858 unsigned int region = EVENT_REGION(hwc->config_base); 1859 unsigned int group = EVENT_GROUP(hwc->config_base); 1860 bool venum_event = EVENT_VENUM(hwc->config_base); 1861 bool scorpion_event = EVENT_CPU(hwc->config_base); 1862 1863 armv7pmu_clear_event_idx(cpuc, event); 1864 if (venum_event || scorpion_event) { 1865 bit = scorpion_event_to_bit(event, region, group); 1866 clear_bit(bit, cpuc->used_mask); 1867 } 1868} 1869 1870static int scorpion_pmu_init(struct arm_pmu *cpu_pmu) 1871{ 1872 armv7pmu_init(cpu_pmu); 1873 cpu_pmu->name = "armv7_scorpion"; 1874 cpu_pmu->map_event = scorpion_map_event; 1875 cpu_pmu->reset = scorpion_pmu_reset; 1876 cpu_pmu->enable = scorpion_pmu_enable_event; 1877 cpu_pmu->disable = scorpion_pmu_disable_event; 1878 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; 1879 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; 1880 return armv7_probe_num_events(cpu_pmu); 1881} 1882 1883static int scorpion_mp_pmu_init(struct arm_pmu *cpu_pmu) 1884{ 1885 armv7pmu_init(cpu_pmu); 1886 cpu_pmu->name = "armv7_scorpion_mp"; 1887 cpu_pmu->map_event = scorpion_map_event; 1888 cpu_pmu->reset = scorpion_pmu_reset; 1889 cpu_pmu->enable = scorpion_pmu_enable_event; 1890 cpu_pmu->disable = scorpion_pmu_disable_event; 1891 cpu_pmu->get_event_idx = scorpion_pmu_get_event_idx; 1892 cpu_pmu->clear_event_idx = scorpion_pmu_clear_event_idx; 1893 return armv7_probe_num_events(cpu_pmu); 1894} 1895 1896static const struct of_device_id armv7_pmu_of_device_ids[] = { 1897 {.compatible = "arm,cortex-a17-pmu", .data = armv7_a17_pmu_init}, 1898 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init}, 1899 {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init}, 1900 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init}, 1901 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init}, 1902 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init}, 1903 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init}, 1904 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init}, 1905 {.compatible = "qcom,scorpion-pmu", .data = scorpion_pmu_init}, 1906 {.compatible = "qcom,scorpion-mp-pmu", .data = scorpion_mp_pmu_init}, 1907 {}, 1908}; 1909 1910static int armv7_pmu_device_probe(struct platform_device *pdev) 1911{ 1912 return arm_pmu_device_probe(pdev, armv7_pmu_of_device_ids, NULL); 1913} 1914 1915static struct platform_driver armv7_pmu_driver = { 1916 .driver = { 1917 .name = "armv7-pmu", 1918 .of_match_table = armv7_pmu_of_device_ids, 1919 .suppress_bind_attrs = true, 1920 }, 1921 .probe = armv7_pmu_device_probe, 1922}; 1923 1924builtin_platform_driver(armv7_pmu_driver);
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