switchtec.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Microsemi Switchtec(tm) PCIe Management Driver
   4 * Copyright (c) 2017, Microsemi Corporation
   5 */
   6
   7#include <linux/switchtec.h>
   8#include <linux/switchtec_ioctl.h>
   9
  10#include <linux/interrupt.h>
  11#include <linux/module.h>
  12#include <linux/fs.h>
  13#include <linux/uaccess.h>
  14#include <linux/poll.h>
  15#include <linux/wait.h>
  16#include <linux/io-64-nonatomic-lo-hi.h>
  17#include <linux/nospec.h>
  18
  19MODULE_DESCRIPTION("Microsemi Switchtec(tm) PCIe Management Driver");
  20MODULE_VERSION("0.1");
  21MODULE_LICENSE("GPL");
  22MODULE_AUTHOR("Microsemi Corporation");
  23
  24static int max_devices = 16;
  25module_param(max_devices, int, 0644);
  26MODULE_PARM_DESC(max_devices, "max number of switchtec device instances");
  27
  28static bool use_dma_mrpc = true;
  29module_param(use_dma_mrpc, bool, 0644);
  30MODULE_PARM_DESC(use_dma_mrpc,
  31		 "Enable the use of the DMA MRPC feature");
  32
  33static int nirqs = 32;
  34module_param(nirqs, int, 0644);
  35MODULE_PARM_DESC(nirqs, "number of interrupts to allocate (more may be useful for NTB applications)");
  36
  37static dev_t switchtec_devt;
  38static DEFINE_IDA(switchtec_minor_ida);
  39
  40const struct class switchtec_class = {
  41	.name = "switchtec",
  42};
  43EXPORT_SYMBOL_GPL(switchtec_class);
  44
  45enum mrpc_state {
  46	MRPC_IDLE = 0,
  47	MRPC_QUEUED,
  48	MRPC_RUNNING,
  49	MRPC_DONE,
  50	MRPC_IO_ERROR,
  51};
  52
  53struct switchtec_user {
  54	struct switchtec_dev *stdev;
  55
  56	enum mrpc_state state;
  57
  58	wait_queue_head_t cmd_comp;
  59	struct kref kref;
  60	struct list_head list;
  61
  62	bool cmd_done;
  63	u32 cmd;
  64	u32 status;
  65	u32 return_code;
  66	size_t data_len;
  67	size_t read_len;
  68	unsigned char data[SWITCHTEC_MRPC_PAYLOAD_SIZE];
  69	int event_cnt;
  70};
  71
  72/*
  73 * The MMIO reads to the device_id register should always return the device ID
  74 * of the device, otherwise the firmware is probably stuck or unreachable
  75 * due to a firmware reset which clears PCI state including the BARs and Memory
  76 * Space Enable bits.
  77 */
  78static int is_firmware_running(struct switchtec_dev *stdev)
  79{
  80	u32 device = ioread32(&stdev->mmio_sys_info->device_id);
  81
  82	return stdev->pdev->device == device;
  83}
  84
  85static struct switchtec_user *stuser_create(struct switchtec_dev *stdev)
  86{
  87	struct switchtec_user *stuser;
  88
  89	stuser = kzalloc(sizeof(*stuser), GFP_KERNEL);
  90	if (!stuser)
  91		return ERR_PTR(-ENOMEM);
  92
  93	get_device(&stdev->dev);
  94	stuser->stdev = stdev;
  95	kref_init(&stuser->kref);
  96	INIT_LIST_HEAD(&stuser->list);
  97	init_waitqueue_head(&stuser->cmd_comp);
  98	stuser->event_cnt = atomic_read(&stdev->event_cnt);
  99
 100	dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
 101
 102	return stuser;
 103}
 104
 105static void stuser_free(struct kref *kref)
 106{
 107	struct switchtec_user *stuser;
 108
 109	stuser = container_of(kref, struct switchtec_user, kref);
 110
 111	dev_dbg(&stuser->stdev->dev, "%s: %p\n", __func__, stuser);
 112
 113	put_device(&stuser->stdev->dev);
 114	kfree(stuser);
 115}
 116
 117static void stuser_put(struct switchtec_user *stuser)
 118{
 119	kref_put(&stuser->kref, stuser_free);
 120}
 121
 122static void stuser_set_state(struct switchtec_user *stuser,
 123			     enum mrpc_state state)
 124{
 125	/* requires the mrpc_mutex to already be held when called */
 126
 127	static const char * const state_names[] = {
 128		[MRPC_IDLE] = "IDLE",
 129		[MRPC_QUEUED] = "QUEUED",
 130		[MRPC_RUNNING] = "RUNNING",
 131		[MRPC_DONE] = "DONE",
 132		[MRPC_IO_ERROR] = "IO_ERROR",
 133	};
 134
 135	stuser->state = state;
 136
 137	dev_dbg(&stuser->stdev->dev, "stuser state %p -> %s",
 138		stuser, state_names[state]);
 139}
 140
 141static void mrpc_complete_cmd(struct switchtec_dev *stdev);
 142
 143static void flush_wc_buf(struct switchtec_dev *stdev)
 144{
 145	struct ntb_dbmsg_regs __iomem *mmio_dbmsg;
 146
 147	/*
 148	 * odb (outbound doorbell) register is processed by low latency
 149	 * hardware and w/o side effect
 150	 */
 151	mmio_dbmsg = (void __iomem *)stdev->mmio_ntb +
 152		SWITCHTEC_NTB_REG_DBMSG_OFFSET;
 153	ioread32(&mmio_dbmsg->odb);
 154}
 155
 156static void mrpc_cmd_submit(struct switchtec_dev *stdev)
 157{
 158	/* requires the mrpc_mutex to already be held when called */
 159
 160	struct switchtec_user *stuser;
 161
 162	if (stdev->mrpc_busy)
 163		return;
 164
 165	if (list_empty(&stdev->mrpc_queue))
 166		return;
 167
 168	stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
 169			    list);
 170
 171	if (stdev->dma_mrpc) {
 172		stdev->dma_mrpc->status = SWITCHTEC_MRPC_STATUS_INPROGRESS;
 173		memset(stdev->dma_mrpc->data, 0xFF, SWITCHTEC_MRPC_PAYLOAD_SIZE);
 174	}
 175
 176	stuser_set_state(stuser, MRPC_RUNNING);
 177	stdev->mrpc_busy = 1;
 178	memcpy_toio(&stdev->mmio_mrpc->input_data,
 179		    stuser->data, stuser->data_len);
 180	flush_wc_buf(stdev);
 181	iowrite32(stuser->cmd, &stdev->mmio_mrpc->cmd);
 182
 183	schedule_delayed_work(&stdev->mrpc_timeout,
 184			      msecs_to_jiffies(500));
 185}
 186
 187static int mrpc_queue_cmd(struct switchtec_user *stuser)
 188{
 189	/* requires the mrpc_mutex to already be held when called */
 190
 191	struct switchtec_dev *stdev = stuser->stdev;
 192
 193	kref_get(&stuser->kref);
 194	stuser->read_len = sizeof(stuser->data);
 195	stuser_set_state(stuser, MRPC_QUEUED);
 196	stuser->cmd_done = false;
 197	list_add_tail(&stuser->list, &stdev->mrpc_queue);
 198
 199	mrpc_cmd_submit(stdev);
 200
 201	return 0;
 202}
 203
 204static void mrpc_cleanup_cmd(struct switchtec_dev *stdev)
 205{
 206	/* requires the mrpc_mutex to already be held when called */
 207
 208	struct switchtec_user *stuser = list_entry(stdev->mrpc_queue.next,
 209						   struct switchtec_user, list);
 210
 211	stuser->cmd_done = true;
 212	wake_up_interruptible(&stuser->cmd_comp);
 213	list_del_init(&stuser->list);
 214	stuser_put(stuser);
 215	stdev->mrpc_busy = 0;
 216
 217	mrpc_cmd_submit(stdev);
 218}
 219
 220static void mrpc_complete_cmd(struct switchtec_dev *stdev)
 221{
 222	/* requires the mrpc_mutex to already be held when called */
 223
 224	struct switchtec_user *stuser;
 225
 226	if (list_empty(&stdev->mrpc_queue))
 227		return;
 228
 229	stuser = list_entry(stdev->mrpc_queue.next, struct switchtec_user,
 230			    list);
 231
 232	if (stdev->dma_mrpc)
 233		stuser->status = stdev->dma_mrpc->status;
 234	else
 235		stuser->status = ioread32(&stdev->mmio_mrpc->status);
 236
 237	if (stuser->status == SWITCHTEC_MRPC_STATUS_INPROGRESS)
 238		return;
 239
 240	stuser_set_state(stuser, MRPC_DONE);
 241	stuser->return_code = 0;
 242
 243	if (stuser->status != SWITCHTEC_MRPC_STATUS_DONE &&
 244	    stuser->status != SWITCHTEC_MRPC_STATUS_ERROR)
 245		goto out;
 246
 247	if (stdev->dma_mrpc)
 248		stuser->return_code = stdev->dma_mrpc->rtn_code;
 249	else
 250		stuser->return_code = ioread32(&stdev->mmio_mrpc->ret_value);
 251	if (stuser->return_code != 0)
 252		goto out;
 253
 254	if (stdev->dma_mrpc)
 255		memcpy(stuser->data, &stdev->dma_mrpc->data,
 256			      stuser->read_len);
 257	else
 258		memcpy_fromio(stuser->data, &stdev->mmio_mrpc->output_data,
 259			      stuser->read_len);
 260out:
 261	mrpc_cleanup_cmd(stdev);
 262}
 263
 264static void mrpc_event_work(struct work_struct *work)
 265{
 266	struct switchtec_dev *stdev;
 267
 268	stdev = container_of(work, struct switchtec_dev, mrpc_work);
 269
 270	dev_dbg(&stdev->dev, "%s\n", __func__);
 271
 272	guard(mutex)(&stdev->mrpc_mutex);
 273	cancel_delayed_work(&stdev->mrpc_timeout);
 274	mrpc_complete_cmd(stdev);
 275}
 276
 277static void mrpc_error_complete_cmd(struct switchtec_dev *stdev)
 278{
 279	/* requires the mrpc_mutex to already be held when called */
 280
 281	struct switchtec_user *stuser;
 282
 283	if (list_empty(&stdev->mrpc_queue))
 284		return;
 285
 286	stuser = list_entry(stdev->mrpc_queue.next,
 287			    struct switchtec_user, list);
 288
 289	stuser_set_state(stuser, MRPC_IO_ERROR);
 290
 291	mrpc_cleanup_cmd(stdev);
 292}
 293
 294static void mrpc_timeout_work(struct work_struct *work)
 295{
 296	struct switchtec_dev *stdev;
 297	u32 status;
 298
 299	stdev = container_of(work, struct switchtec_dev, mrpc_timeout.work);
 300
 301	dev_dbg(&stdev->dev, "%s\n", __func__);
 302
 303	mutex_lock(&stdev->mrpc_mutex);
 304
 305	if (!is_firmware_running(stdev)) {
 306		mrpc_error_complete_cmd(stdev);
 307		goto out;
 308	}
 309
 310	if (stdev->dma_mrpc)
 311		status = stdev->dma_mrpc->status;
 312	else
 313		status = ioread32(&stdev->mmio_mrpc->status);
 314	if (status == SWITCHTEC_MRPC_STATUS_INPROGRESS) {
 315		schedule_delayed_work(&stdev->mrpc_timeout,
 316				      msecs_to_jiffies(500));
 317		goto out;
 318	}
 319
 320	mrpc_complete_cmd(stdev);
 321out:
 322	mutex_unlock(&stdev->mrpc_mutex);
 323}
 324
 325static ssize_t device_version_show(struct device *dev,
 326	struct device_attribute *attr, char *buf)
 327{
 328	struct switchtec_dev *stdev = to_stdev(dev);
 329	u32 ver;
 330
 331	ver = ioread32(&stdev->mmio_sys_info->device_version);
 332
 333	return sysfs_emit(buf, "%x\n", ver);
 334}
 335static DEVICE_ATTR_RO(device_version);
 336
 337static ssize_t fw_version_show(struct device *dev,
 338	struct device_attribute *attr, char *buf)
 339{
 340	struct switchtec_dev *stdev = to_stdev(dev);
 341	u32 ver;
 342
 343	ver = ioread32(&stdev->mmio_sys_info->firmware_version);
 344
 345	return sysfs_emit(buf, "%08x\n", ver);
 346}
 347static DEVICE_ATTR_RO(fw_version);
 348
 349static ssize_t io_string_show(char *buf, void __iomem *attr, size_t len)
 350{
 351	int i;
 352
 353	memcpy_fromio(buf, attr, len);
 354	buf[len] = '\n';
 355	buf[len + 1] = 0;
 356
 357	for (i = len - 1; i > 0; i--) {
 358		if (buf[i] != ' ')
 359			break;
 360		buf[i] = '\n';
 361		buf[i + 1] = 0;
 362	}
 363
 364	return strlen(buf);
 365}
 366
 367#define DEVICE_ATTR_SYS_INFO_STR(field) \
 368static ssize_t field ## _show(struct device *dev, \
 369	struct device_attribute *attr, char *buf) \
 370{ \
 371	struct switchtec_dev *stdev = to_stdev(dev); \
 372	struct sys_info_regs __iomem *si = stdev->mmio_sys_info; \
 373	if (stdev->gen == SWITCHTEC_GEN3) \
 374		return io_string_show(buf, &si->gen3.field, \
 375				      sizeof(si->gen3.field)); \
 376	else if (stdev->gen >= SWITCHTEC_GEN4) \
 377		return io_string_show(buf, &si->gen4.field, \
 378				      sizeof(si->gen4.field)); \
 379	else \
 380		return -EOPNOTSUPP; \
 381} \
 382\
 383static DEVICE_ATTR_RO(field)
 384
 385DEVICE_ATTR_SYS_INFO_STR(vendor_id);
 386DEVICE_ATTR_SYS_INFO_STR(product_id);
 387DEVICE_ATTR_SYS_INFO_STR(product_revision);
 388
 389static ssize_t component_vendor_show(struct device *dev,
 390				     struct device_attribute *attr, char *buf)
 391{
 392	struct switchtec_dev *stdev = to_stdev(dev);
 393	struct sys_info_regs __iomem *si = stdev->mmio_sys_info;
 394
 395	/* component_vendor field not supported after gen3 */
 396	if (stdev->gen != SWITCHTEC_GEN3)
 397		return sysfs_emit(buf, "none\n");
 398
 399	return io_string_show(buf, &si->gen3.component_vendor,
 400			      sizeof(si->gen3.component_vendor));
 401}
 402static DEVICE_ATTR_RO(component_vendor);
 403
 404static ssize_t component_id_show(struct device *dev,
 405	struct device_attribute *attr, char *buf)
 406{
 407	struct switchtec_dev *stdev = to_stdev(dev);
 408	int id = ioread16(&stdev->mmio_sys_info->gen3.component_id);
 409
 410	/* component_id field not supported after gen3 */
 411	if (stdev->gen != SWITCHTEC_GEN3)
 412		return sysfs_emit(buf, "none\n");
 413
 414	return sysfs_emit(buf, "PM%04X\n", id);
 415}
 416static DEVICE_ATTR_RO(component_id);
 417
 418static ssize_t component_revision_show(struct device *dev,
 419	struct device_attribute *attr, char *buf)
 420{
 421	struct switchtec_dev *stdev = to_stdev(dev);
 422	int rev = ioread8(&stdev->mmio_sys_info->gen3.component_revision);
 423
 424	/* component_revision field not supported after gen3 */
 425	if (stdev->gen != SWITCHTEC_GEN3)
 426		return sysfs_emit(buf, "255\n");
 427
 428	return sysfs_emit(buf, "%d\n", rev);
 429}
 430static DEVICE_ATTR_RO(component_revision);
 431
 432static ssize_t partition_show(struct device *dev,
 433	struct device_attribute *attr, char *buf)
 434{
 435	struct switchtec_dev *stdev = to_stdev(dev);
 436
 437	return sysfs_emit(buf, "%d\n", stdev->partition);
 438}
 439static DEVICE_ATTR_RO(partition);
 440
 441static ssize_t partition_count_show(struct device *dev,
 442	struct device_attribute *attr, char *buf)
 443{
 444	struct switchtec_dev *stdev = to_stdev(dev);
 445
 446	return sysfs_emit(buf, "%d\n", stdev->partition_count);
 447}
 448static DEVICE_ATTR_RO(partition_count);
 449
 450static struct attribute *switchtec_device_attrs[] = {
 451	&dev_attr_device_version.attr,
 452	&dev_attr_fw_version.attr,
 453	&dev_attr_vendor_id.attr,
 454	&dev_attr_product_id.attr,
 455	&dev_attr_product_revision.attr,
 456	&dev_attr_component_vendor.attr,
 457	&dev_attr_component_id.attr,
 458	&dev_attr_component_revision.attr,
 459	&dev_attr_partition.attr,
 460	&dev_attr_partition_count.attr,
 461	NULL,
 462};
 463
 464ATTRIBUTE_GROUPS(switchtec_device);
 465
 466static int switchtec_dev_open(struct inode *inode, struct file *filp)
 467{
 468	struct switchtec_dev *stdev;
 469	struct switchtec_user *stuser;
 470
 471	stdev = container_of(inode->i_cdev, struct switchtec_dev, cdev);
 472
 473	stuser = stuser_create(stdev);
 474	if (IS_ERR(stuser))
 475		return PTR_ERR(stuser);
 476
 477	filp->private_data = stuser;
 478	stream_open(inode, filp);
 479
 480	dev_dbg(&stdev->dev, "%s: %p\n", __func__, stuser);
 481
 482	return 0;
 483}
 484
 485static int switchtec_dev_release(struct inode *inode, struct file *filp)
 486{
 487	struct switchtec_user *stuser = filp->private_data;
 488
 489	stuser_put(stuser);
 490
 491	return 0;
 492}
 493
 494static int lock_mutex_and_test_alive(struct switchtec_dev *stdev)
 495{
 496	if (mutex_lock_interruptible(&stdev->mrpc_mutex))
 497		return -EINTR;
 498
 499	if (!stdev->alive) {
 500		mutex_unlock(&stdev->mrpc_mutex);
 501		return -ENODEV;
 502	}
 503
 504	return 0;
 505}
 506
 507static ssize_t switchtec_dev_write(struct file *filp, const char __user *data,
 508				   size_t size, loff_t *off)
 509{
 510	struct switchtec_user *stuser = filp->private_data;
 511	struct switchtec_dev *stdev = stuser->stdev;
 512	int rc;
 513
 514	if (size < sizeof(stuser->cmd) ||
 515	    size > sizeof(stuser->cmd) + sizeof(stuser->data))
 516		return -EINVAL;
 517
 518	stuser->data_len = size - sizeof(stuser->cmd);
 519
 520	rc = lock_mutex_and_test_alive(stdev);
 521	if (rc)
 522		return rc;
 523
 524	if (stuser->state != MRPC_IDLE) {
 525		rc = -EBADE;
 526		goto out;
 527	}
 528
 529	rc = copy_from_user(&stuser->cmd, data, sizeof(stuser->cmd));
 530	if (rc) {
 531		rc = -EFAULT;
 532		goto out;
 533	}
 534	if (((MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_WRITE) ||
 535	     (MRPC_CMD_ID(stuser->cmd) == MRPC_GAS_READ)) &&
 536	    !capable(CAP_SYS_ADMIN)) {
 537		rc = -EPERM;
 538		goto out;
 539	}
 540
 541	data += sizeof(stuser->cmd);
 542	rc = copy_from_user(&stuser->data, data, size - sizeof(stuser->cmd));
 543	if (rc) {
 544		rc = -EFAULT;
 545		goto out;
 546	}
 547
 548	rc = mrpc_queue_cmd(stuser);
 549
 550out:
 551	mutex_unlock(&stdev->mrpc_mutex);
 552
 553	if (rc)
 554		return rc;
 555
 556	return size;
 557}
 558
 559static ssize_t switchtec_dev_read(struct file *filp, char __user *data,
 560				  size_t size, loff_t *off)
 561{
 562	struct switchtec_user *stuser = filp->private_data;
 563	struct switchtec_dev *stdev = stuser->stdev;
 564	int rc;
 565
 566	if (size < sizeof(stuser->cmd) ||
 567	    size > sizeof(stuser->cmd) + sizeof(stuser->data))
 568		return -EINVAL;
 569
 570	rc = lock_mutex_and_test_alive(stdev);
 571	if (rc)
 572		return rc;
 573
 574	if (stuser->state == MRPC_IDLE) {
 575		mutex_unlock(&stdev->mrpc_mutex);
 576		return -EBADE;
 577	}
 578
 579	stuser->read_len = size - sizeof(stuser->return_code);
 580
 581	mutex_unlock(&stdev->mrpc_mutex);
 582
 583	if (filp->f_flags & O_NONBLOCK) {
 584		if (!stuser->cmd_done)
 585			return -EAGAIN;
 586	} else {
 587		rc = wait_event_interruptible(stuser->cmd_comp,
 588					      stuser->cmd_done);
 589		if (rc < 0)
 590			return rc;
 591	}
 592
 593	rc = lock_mutex_and_test_alive(stdev);
 594	if (rc)
 595		return rc;
 596
 597	if (stuser->state == MRPC_IO_ERROR) {
 598		mutex_unlock(&stdev->mrpc_mutex);
 599		return -EIO;
 600	}
 601
 602	if (stuser->state != MRPC_DONE) {
 603		mutex_unlock(&stdev->mrpc_mutex);
 604		return -EBADE;
 605	}
 606
 607	rc = copy_to_user(data, &stuser->return_code,
 608			  sizeof(stuser->return_code));
 609	if (rc) {
 610		mutex_unlock(&stdev->mrpc_mutex);
 611		return -EFAULT;
 612	}
 613
 614	data += sizeof(stuser->return_code);
 615	rc = copy_to_user(data, &stuser->data,
 616			  size - sizeof(stuser->return_code));
 617	if (rc) {
 618		mutex_unlock(&stdev->mrpc_mutex);
 619		return -EFAULT;
 620	}
 621
 622	stuser_set_state(stuser, MRPC_IDLE);
 623
 624	mutex_unlock(&stdev->mrpc_mutex);
 625
 626	if (stuser->status == SWITCHTEC_MRPC_STATUS_DONE ||
 627	    stuser->status == SWITCHTEC_MRPC_STATUS_ERROR)
 628		return size;
 629	else if (stuser->status == SWITCHTEC_MRPC_STATUS_INTERRUPTED)
 630		return -ENXIO;
 631	else
 632		return -EBADMSG;
 633}
 634
 635static __poll_t switchtec_dev_poll(struct file *filp, poll_table *wait)
 636{
 637	struct switchtec_user *stuser = filp->private_data;
 638	struct switchtec_dev *stdev = stuser->stdev;
 639	__poll_t ret = 0;
 640
 641	poll_wait(filp, &stuser->cmd_comp, wait);
 642	poll_wait(filp, &stdev->event_wq, wait);
 643
 644	if (lock_mutex_and_test_alive(stdev))
 645		return EPOLLIN | EPOLLRDHUP | EPOLLOUT | EPOLLERR | EPOLLHUP;
 646
 647	mutex_unlock(&stdev->mrpc_mutex);
 648
 649	if (stuser->cmd_done)
 650		ret |= EPOLLIN | EPOLLRDNORM;
 651
 652	if (stuser->event_cnt != atomic_read(&stdev->event_cnt))
 653		ret |= EPOLLPRI | EPOLLRDBAND;
 654
 655	return ret;
 656}
 657
 658static int ioctl_flash_info(struct switchtec_dev *stdev,
 659			    struct switchtec_ioctl_flash_info __user *uinfo)
 660{
 661	struct switchtec_ioctl_flash_info info = {0};
 662	struct flash_info_regs __iomem *fi = stdev->mmio_flash_info;
 663
 664	if (stdev->gen == SWITCHTEC_GEN3) {
 665		info.flash_length = ioread32(&fi->gen3.flash_length);
 666		info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN3;
 667	} else if (stdev->gen >= SWITCHTEC_GEN4) {
 668		info.flash_length = ioread32(&fi->gen4.flash_length);
 669		info.num_partitions = SWITCHTEC_NUM_PARTITIONS_GEN4;
 670	} else {
 671		return -EOPNOTSUPP;
 672	}
 673
 674	if (copy_to_user(uinfo, &info, sizeof(info)))
 675		return -EFAULT;
 676
 677	return 0;
 678}
 679
 680static void set_fw_info_part(struct switchtec_ioctl_flash_part_info *info,
 681			     struct partition_info __iomem *pi)
 682{
 683	info->address = ioread32(&pi->address);
 684	info->length = ioread32(&pi->length);
 685}
 686
 687static int flash_part_info_gen3(struct switchtec_dev *stdev,
 688		struct switchtec_ioctl_flash_part_info *info)
 689{
 690	struct flash_info_regs_gen3 __iomem *fi =
 691		&stdev->mmio_flash_info->gen3;
 692	struct sys_info_regs_gen3 __iomem *si = &stdev->mmio_sys_info->gen3;
 693	u32 active_addr = -1;
 694
 695	switch (info->flash_partition) {
 696	case SWITCHTEC_IOCTL_PART_CFG0:
 697		active_addr = ioread32(&fi->active_cfg);
 698		set_fw_info_part(info, &fi->cfg0);
 699		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG0_RUNNING)
 700			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 701		break;
 702	case SWITCHTEC_IOCTL_PART_CFG1:
 703		active_addr = ioread32(&fi->active_cfg);
 704		set_fw_info_part(info, &fi->cfg1);
 705		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN3_CFG1_RUNNING)
 706			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 707		break;
 708	case SWITCHTEC_IOCTL_PART_IMG0:
 709		active_addr = ioread32(&fi->active_img);
 710		set_fw_info_part(info, &fi->img0);
 711		if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG0_RUNNING)
 712			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 713		break;
 714	case SWITCHTEC_IOCTL_PART_IMG1:
 715		active_addr = ioread32(&fi->active_img);
 716		set_fw_info_part(info, &fi->img1);
 717		if (ioread16(&si->img_running) == SWITCHTEC_GEN3_IMG1_RUNNING)
 718			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 719		break;
 720	case SWITCHTEC_IOCTL_PART_NVLOG:
 721		set_fw_info_part(info, &fi->nvlog);
 722		break;
 723	case SWITCHTEC_IOCTL_PART_VENDOR0:
 724		set_fw_info_part(info, &fi->vendor[0]);
 725		break;
 726	case SWITCHTEC_IOCTL_PART_VENDOR1:
 727		set_fw_info_part(info, &fi->vendor[1]);
 728		break;
 729	case SWITCHTEC_IOCTL_PART_VENDOR2:
 730		set_fw_info_part(info, &fi->vendor[2]);
 731		break;
 732	case SWITCHTEC_IOCTL_PART_VENDOR3:
 733		set_fw_info_part(info, &fi->vendor[3]);
 734		break;
 735	case SWITCHTEC_IOCTL_PART_VENDOR4:
 736		set_fw_info_part(info, &fi->vendor[4]);
 737		break;
 738	case SWITCHTEC_IOCTL_PART_VENDOR5:
 739		set_fw_info_part(info, &fi->vendor[5]);
 740		break;
 741	case SWITCHTEC_IOCTL_PART_VENDOR6:
 742		set_fw_info_part(info, &fi->vendor[6]);
 743		break;
 744	case SWITCHTEC_IOCTL_PART_VENDOR7:
 745		set_fw_info_part(info, &fi->vendor[7]);
 746		break;
 747	default:
 748		return -EINVAL;
 749	}
 750
 751	if (info->address == active_addr)
 752		info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 753
 754	return 0;
 755}
 756
 757static int flash_part_info_gen4(struct switchtec_dev *stdev,
 758		struct switchtec_ioctl_flash_part_info *info)
 759{
 760	struct flash_info_regs_gen4 __iomem *fi = &stdev->mmio_flash_info->gen4;
 761	struct sys_info_regs_gen4 __iomem *si = &stdev->mmio_sys_info->gen4;
 762	struct active_partition_info_gen4 __iomem *af = &fi->active_flag;
 763
 764	switch (info->flash_partition) {
 765	case SWITCHTEC_IOCTL_PART_MAP_0:
 766		set_fw_info_part(info, &fi->map0);
 767		break;
 768	case SWITCHTEC_IOCTL_PART_MAP_1:
 769		set_fw_info_part(info, &fi->map1);
 770		break;
 771	case SWITCHTEC_IOCTL_PART_KEY_0:
 772		set_fw_info_part(info, &fi->key0);
 773		if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY0_ACTIVE)
 774			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 775		if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY0_RUNNING)
 776			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 777		break;
 778	case SWITCHTEC_IOCTL_PART_KEY_1:
 779		set_fw_info_part(info, &fi->key1);
 780		if (ioread8(&af->key) == SWITCHTEC_GEN4_KEY1_ACTIVE)
 781			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 782		if (ioread16(&si->key_running) == SWITCHTEC_GEN4_KEY1_RUNNING)
 783			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 784		break;
 785	case SWITCHTEC_IOCTL_PART_BL2_0:
 786		set_fw_info_part(info, &fi->bl2_0);
 787		if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_0_ACTIVE)
 788			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 789		if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_0_RUNNING)
 790			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 791		break;
 792	case SWITCHTEC_IOCTL_PART_BL2_1:
 793		set_fw_info_part(info, &fi->bl2_1);
 794		if (ioread8(&af->bl2) == SWITCHTEC_GEN4_BL2_1_ACTIVE)
 795			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 796		if (ioread16(&si->bl2_running) == SWITCHTEC_GEN4_BL2_1_RUNNING)
 797			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 798		break;
 799	case SWITCHTEC_IOCTL_PART_CFG0:
 800		set_fw_info_part(info, &fi->cfg0);
 801		if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG0_ACTIVE)
 802			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 803		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG0_RUNNING)
 804			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 805		break;
 806	case SWITCHTEC_IOCTL_PART_CFG1:
 807		set_fw_info_part(info, &fi->cfg1);
 808		if (ioread8(&af->cfg) == SWITCHTEC_GEN4_CFG1_ACTIVE)
 809			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 810		if (ioread16(&si->cfg_running) == SWITCHTEC_GEN4_CFG1_RUNNING)
 811			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 812		break;
 813	case SWITCHTEC_IOCTL_PART_IMG0:
 814		set_fw_info_part(info, &fi->img0);
 815		if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG0_ACTIVE)
 816			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 817		if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG0_RUNNING)
 818			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 819		break;
 820	case SWITCHTEC_IOCTL_PART_IMG1:
 821		set_fw_info_part(info, &fi->img1);
 822		if (ioread8(&af->img) == SWITCHTEC_GEN4_IMG1_ACTIVE)
 823			info->active |= SWITCHTEC_IOCTL_PART_ACTIVE;
 824		if (ioread16(&si->img_running) == SWITCHTEC_GEN4_IMG1_RUNNING)
 825			info->active |= SWITCHTEC_IOCTL_PART_RUNNING;
 826		break;
 827	case SWITCHTEC_IOCTL_PART_NVLOG:
 828		set_fw_info_part(info, &fi->nvlog);
 829		break;
 830	case SWITCHTEC_IOCTL_PART_VENDOR0:
 831		set_fw_info_part(info, &fi->vendor[0]);
 832		break;
 833	case SWITCHTEC_IOCTL_PART_VENDOR1:
 834		set_fw_info_part(info, &fi->vendor[1]);
 835		break;
 836	case SWITCHTEC_IOCTL_PART_VENDOR2:
 837		set_fw_info_part(info, &fi->vendor[2]);
 838		break;
 839	case SWITCHTEC_IOCTL_PART_VENDOR3:
 840		set_fw_info_part(info, &fi->vendor[3]);
 841		break;
 842	case SWITCHTEC_IOCTL_PART_VENDOR4:
 843		set_fw_info_part(info, &fi->vendor[4]);
 844		break;
 845	case SWITCHTEC_IOCTL_PART_VENDOR5:
 846		set_fw_info_part(info, &fi->vendor[5]);
 847		break;
 848	case SWITCHTEC_IOCTL_PART_VENDOR6:
 849		set_fw_info_part(info, &fi->vendor[6]);
 850		break;
 851	case SWITCHTEC_IOCTL_PART_VENDOR7:
 852		set_fw_info_part(info, &fi->vendor[7]);
 853		break;
 854	default:
 855		return -EINVAL;
 856	}
 857
 858	return 0;
 859}
 860
 861static int ioctl_flash_part_info(struct switchtec_dev *stdev,
 862		struct switchtec_ioctl_flash_part_info __user *uinfo)
 863{
 864	int ret;
 865	struct switchtec_ioctl_flash_part_info info = {0};
 866
 867	if (copy_from_user(&info, uinfo, sizeof(info)))
 868		return -EFAULT;
 869
 870	if (stdev->gen == SWITCHTEC_GEN3) {
 871		ret = flash_part_info_gen3(stdev, &info);
 872		if (ret)
 873			return ret;
 874	} else if (stdev->gen >= SWITCHTEC_GEN4) {
 875		ret = flash_part_info_gen4(stdev, &info);
 876		if (ret)
 877			return ret;
 878	} else {
 879		return -EOPNOTSUPP;
 880	}
 881
 882	if (copy_to_user(uinfo, &info, sizeof(info)))
 883		return -EFAULT;
 884
 885	return 0;
 886}
 887
 888static int ioctl_event_summary(struct switchtec_dev *stdev,
 889	struct switchtec_user *stuser,
 890	struct switchtec_ioctl_event_summary __user *usum,
 891	size_t size)
 892{
 893	struct switchtec_ioctl_event_summary *s;
 894	int i;
 895	u32 reg;
 896	int ret = 0;
 897
 898	s = kzalloc(sizeof(*s), GFP_KERNEL);
 899	if (!s)
 900		return -ENOMEM;
 901
 902	s->global = ioread32(&stdev->mmio_sw_event->global_summary);
 903	s->part_bitmap = ioread64(&stdev->mmio_sw_event->part_event_bitmap);
 904	s->local_part = ioread32(&stdev->mmio_part_cfg->part_event_summary);
 905
 906	for (i = 0; i < stdev->partition_count; i++) {
 907		reg = ioread32(&stdev->mmio_part_cfg_all[i].part_event_summary);
 908		s->part[i] = reg;
 909	}
 910
 911	for (i = 0; i < stdev->pff_csr_count; i++) {
 912		reg = ioread32(&stdev->mmio_pff_csr[i].pff_event_summary);
 913		s->pff[i] = reg;
 914	}
 915
 916	if (copy_to_user(usum, s, size)) {
 917		ret = -EFAULT;
 918		goto error_case;
 919	}
 920
 921	stuser->event_cnt = atomic_read(&stdev->event_cnt);
 922
 923error_case:
 924	kfree(s);
 925	return ret;
 926}
 927
 928static u32 __iomem *global_ev_reg(struct switchtec_dev *stdev,
 929				  size_t offset, int index)
 930{
 931	return (void __iomem *)stdev->mmio_sw_event + offset;
 932}
 933
 934static u32 __iomem *part_ev_reg(struct switchtec_dev *stdev,
 935				size_t offset, int index)
 936{
 937	return (void __iomem *)&stdev->mmio_part_cfg_all[index] + offset;
 938}
 939
 940static u32 __iomem *pff_ev_reg(struct switchtec_dev *stdev,
 941			       size_t offset, int index)
 942{
 943	return (void __iomem *)&stdev->mmio_pff_csr[index] + offset;
 944}
 945
 946#define EV_GLB(i, r)[i] = {offsetof(struct sw_event_regs, r), global_ev_reg}
 947#define EV_PAR(i, r)[i] = {offsetof(struct part_cfg_regs, r), part_ev_reg}
 948#define EV_PFF(i, r)[i] = {offsetof(struct pff_csr_regs, r), pff_ev_reg}
 949
 950static const struct event_reg {
 951	size_t offset;
 952	u32 __iomem *(*map_reg)(struct switchtec_dev *stdev,
 953				size_t offset, int index);
 954} event_regs[] = {
 955	EV_GLB(SWITCHTEC_IOCTL_EVENT_STACK_ERROR, stack_error_event_hdr),
 956	EV_GLB(SWITCHTEC_IOCTL_EVENT_PPU_ERROR, ppu_error_event_hdr),
 957	EV_GLB(SWITCHTEC_IOCTL_EVENT_ISP_ERROR, isp_error_event_hdr),
 958	EV_GLB(SWITCHTEC_IOCTL_EVENT_SYS_RESET, sys_reset_event_hdr),
 959	EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_EXC, fw_exception_hdr),
 960	EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NMI, fw_nmi_hdr),
 961	EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_NON_FATAL, fw_non_fatal_hdr),
 962	EV_GLB(SWITCHTEC_IOCTL_EVENT_FW_FATAL, fw_fatal_hdr),
 963	EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP, twi_mrpc_comp_hdr),
 964	EV_GLB(SWITCHTEC_IOCTL_EVENT_TWI_MRPC_COMP_ASYNC,
 965	       twi_mrpc_comp_async_hdr),
 966	EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP, cli_mrpc_comp_hdr),
 967	EV_GLB(SWITCHTEC_IOCTL_EVENT_CLI_MRPC_COMP_ASYNC,
 968	       cli_mrpc_comp_async_hdr),
 969	EV_GLB(SWITCHTEC_IOCTL_EVENT_GPIO_INT, gpio_interrupt_hdr),
 970	EV_GLB(SWITCHTEC_IOCTL_EVENT_GFMS, gfms_event_hdr),
 971	EV_PAR(SWITCHTEC_IOCTL_EVENT_PART_RESET, part_reset_hdr),
 972	EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP, mrpc_comp_hdr),
 973	EV_PAR(SWITCHTEC_IOCTL_EVENT_MRPC_COMP_ASYNC, mrpc_comp_async_hdr),
 974	EV_PAR(SWITCHTEC_IOCTL_EVENT_DYN_PART_BIND_COMP, dyn_binding_hdr),
 975	EV_PAR(SWITCHTEC_IOCTL_EVENT_INTERCOMM_REQ_NOTIFY,
 976	       intercomm_notify_hdr),
 977	EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_P2P, aer_in_p2p_hdr),
 978	EV_PFF(SWITCHTEC_IOCTL_EVENT_AER_IN_VEP, aer_in_vep_hdr),
 979	EV_PFF(SWITCHTEC_IOCTL_EVENT_DPC, dpc_hdr),
 980	EV_PFF(SWITCHTEC_IOCTL_EVENT_CTS, cts_hdr),
 981	EV_PFF(SWITCHTEC_IOCTL_EVENT_UEC, uec_hdr),
 982	EV_PFF(SWITCHTEC_IOCTL_EVENT_HOTPLUG, hotplug_hdr),
 983	EV_PFF(SWITCHTEC_IOCTL_EVENT_IER, ier_hdr),
 984	EV_PFF(SWITCHTEC_IOCTL_EVENT_THRESH, threshold_hdr),
 985	EV_PFF(SWITCHTEC_IOCTL_EVENT_POWER_MGMT, power_mgmt_hdr),
 986	EV_PFF(SWITCHTEC_IOCTL_EVENT_TLP_THROTTLING, tlp_throttling_hdr),
 987	EV_PFF(SWITCHTEC_IOCTL_EVENT_FORCE_SPEED, force_speed_hdr),
 988	EV_PFF(SWITCHTEC_IOCTL_EVENT_CREDIT_TIMEOUT, credit_timeout_hdr),
 989	EV_PFF(SWITCHTEC_IOCTL_EVENT_LINK_STATE, link_state_hdr),
 990};
 991
 992static u32 __iomem *event_hdr_addr(struct switchtec_dev *stdev,
 993				   int event_id, int index)
 994{
 995	size_t off;
 996
 997	if (event_id < 0 || event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
 998		return (u32 __iomem *)ERR_PTR(-EINVAL);
 999
1000	off = event_regs[event_id].offset;
1001
1002	if (event_regs[event_id].map_reg == part_ev_reg) {
1003		if (index == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
1004			index = stdev->partition;
1005		else if (index < 0 || index >= stdev->partition_count)
1006			return (u32 __iomem *)ERR_PTR(-EINVAL);
1007	} else if (event_regs[event_id].map_reg == pff_ev_reg) {
1008		if (index < 0 || index >= stdev->pff_csr_count)
1009			return (u32 __iomem *)ERR_PTR(-EINVAL);
1010	}
1011
1012	return event_regs[event_id].map_reg(stdev, off, index);
1013}
1014
1015static int event_ctl(struct switchtec_dev *stdev,
1016		     struct switchtec_ioctl_event_ctl *ctl)
1017{
1018	int i;
1019	u32 __iomem *reg;
1020	u32 hdr;
1021
1022	reg = event_hdr_addr(stdev, ctl->event_id, ctl->index);
1023	if (IS_ERR(reg))
1024		return PTR_ERR(reg);
1025
1026	hdr = ioread32(reg);
1027	if (hdr & SWITCHTEC_EVENT_NOT_SUPP)
1028		return -EOPNOTSUPP;
1029
1030	for (i = 0; i < ARRAY_SIZE(ctl->data); i++)
1031		ctl->data[i] = ioread32(&reg[i + 1]);
1032
1033	ctl->occurred = hdr & SWITCHTEC_EVENT_OCCURRED;
1034	ctl->count = (hdr >> 5) & 0xFF;
1035
1036	if (!(ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_CLEAR))
1037		hdr &= ~SWITCHTEC_EVENT_CLEAR;
1038	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL)
1039		hdr |= SWITCHTEC_EVENT_EN_IRQ;
1040	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_POLL)
1041		hdr &= ~SWITCHTEC_EVENT_EN_IRQ;
1042	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG)
1043		hdr |= SWITCHTEC_EVENT_EN_LOG;
1044	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_LOG)
1045		hdr &= ~SWITCHTEC_EVENT_EN_LOG;
1046	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI)
1047		hdr |= SWITCHTEC_EVENT_EN_CLI;
1048	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_CLI)
1049		hdr &= ~SWITCHTEC_EVENT_EN_CLI;
1050	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL)
1051		hdr |= SWITCHTEC_EVENT_FATAL;
1052	if (ctl->flags & SWITCHTEC_IOCTL_EVENT_FLAG_DIS_FATAL)
1053		hdr &= ~SWITCHTEC_EVENT_FATAL;
1054
1055	if (ctl->flags)
1056		iowrite32(hdr, reg);
1057
1058	ctl->flags = 0;
1059	if (hdr & SWITCHTEC_EVENT_EN_IRQ)
1060		ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_POLL;
1061	if (hdr & SWITCHTEC_EVENT_EN_LOG)
1062		ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_LOG;
1063	if (hdr & SWITCHTEC_EVENT_EN_CLI)
1064		ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_CLI;
1065	if (hdr & SWITCHTEC_EVENT_FATAL)
1066		ctl->flags |= SWITCHTEC_IOCTL_EVENT_FLAG_EN_FATAL;
1067
1068	return 0;
1069}
1070
1071static int ioctl_event_ctl(struct switchtec_dev *stdev,
1072	struct switchtec_ioctl_event_ctl __user *uctl)
1073{
1074	int ret;
1075	int nr_idxs;
1076	unsigned int event_flags;
1077	struct switchtec_ioctl_event_ctl ctl;
1078
1079	if (copy_from_user(&ctl, uctl, sizeof(ctl)))
1080		return -EFAULT;
1081
1082	if (ctl.event_id >= SWITCHTEC_IOCTL_MAX_EVENTS)
1083		return -EINVAL;
1084
1085	if (ctl.flags & SWITCHTEC_IOCTL_EVENT_FLAG_UNUSED)
1086		return -EINVAL;
1087
1088	if (ctl.index == SWITCHTEC_IOCTL_EVENT_IDX_ALL) {
1089		if (event_regs[ctl.event_id].map_reg == global_ev_reg)
1090			nr_idxs = 1;
1091		else if (event_regs[ctl.event_id].map_reg == part_ev_reg)
1092			nr_idxs = stdev->partition_count;
1093		else if (event_regs[ctl.event_id].map_reg == pff_ev_reg)
1094			nr_idxs = stdev->pff_csr_count;
1095		else
1096			return -EINVAL;
1097
1098		event_flags = ctl.flags;
1099		for (ctl.index = 0; ctl.index < nr_idxs; ctl.index++) {
1100			ctl.flags = event_flags;
1101			ret = event_ctl(stdev, &ctl);
1102			if (ret < 0 && ret != -EOPNOTSUPP)
1103				return ret;
1104		}
1105	} else {
1106		ret = event_ctl(stdev, &ctl);
1107		if (ret < 0)
1108			return ret;
1109	}
1110
1111	if (copy_to_user(uctl, &ctl, sizeof(ctl)))
1112		return -EFAULT;
1113
1114	return 0;
1115}
1116
1117static int ioctl_pff_to_port(struct switchtec_dev *stdev,
1118			     struct switchtec_ioctl_pff_port __user *up)
1119{
1120	int i, part;
1121	u32 reg;
1122	struct part_cfg_regs __iomem *pcfg;
1123	struct switchtec_ioctl_pff_port p;
1124
1125	if (copy_from_user(&p, up, sizeof(p)))
1126		return -EFAULT;
1127
1128	p.port = -1;
1129	for (part = 0; part < stdev->partition_count; part++) {
1130		pcfg = &stdev->mmio_part_cfg_all[part];
1131		p.partition = part;
1132
1133		reg = ioread32(&pcfg->usp_pff_inst_id);
1134		if (reg == p.pff) {
1135			p.port = 0;
1136			break;
1137		}
1138
1139		reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;
1140		if (reg == p.pff) {
1141			p.port = SWITCHTEC_IOCTL_PFF_VEP;
1142			break;
1143		}
1144
1145		for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1146			reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1147			if (reg != p.pff)
1148				continue;
1149
1150			p.port = i + 1;
1151			break;
1152		}
1153
1154		if (p.port != -1)
1155			break;
1156	}
1157
1158	if (copy_to_user(up, &p, sizeof(p)))
1159		return -EFAULT;
1160
1161	return 0;
1162}
1163
1164static int ioctl_port_to_pff(struct switchtec_dev *stdev,
1165			     struct switchtec_ioctl_pff_port __user *up)
1166{
1167	struct switchtec_ioctl_pff_port p;
1168	struct part_cfg_regs __iomem *pcfg;
1169
1170	if (copy_from_user(&p, up, sizeof(p)))
1171		return -EFAULT;
1172
1173	if (p.partition == SWITCHTEC_IOCTL_EVENT_LOCAL_PART_IDX)
1174		pcfg = stdev->mmio_part_cfg;
1175	else if (p.partition < stdev->partition_count)
1176		pcfg = &stdev->mmio_part_cfg_all[p.partition];
1177	else
1178		return -EINVAL;
1179
1180	switch (p.port) {
1181	case 0:
1182		p.pff = ioread32(&pcfg->usp_pff_inst_id);
1183		break;
1184	case SWITCHTEC_IOCTL_PFF_VEP:
1185		p.pff = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;
1186		break;
1187	default:
1188		if (p.port > ARRAY_SIZE(pcfg->dsp_pff_inst_id))
1189			return -EINVAL;
1190		p.port = array_index_nospec(p.port,
1191					ARRAY_SIZE(pcfg->dsp_pff_inst_id) + 1);
1192		p.pff = ioread32(&pcfg->dsp_pff_inst_id[p.port - 1]);
1193		break;
1194	}
1195
1196	if (copy_to_user(up, &p, sizeof(p)))
1197		return -EFAULT;
1198
1199	return 0;
1200}
1201
1202static long switchtec_dev_ioctl(struct file *filp, unsigned int cmd,
1203				unsigned long arg)
1204{
1205	struct switchtec_user *stuser = filp->private_data;
1206	struct switchtec_dev *stdev = stuser->stdev;
1207	int rc;
1208	void __user *argp = (void __user *)arg;
1209
1210	rc = lock_mutex_and_test_alive(stdev);
1211	if (rc)
1212		return rc;
1213
1214	switch (cmd) {
1215	case SWITCHTEC_IOCTL_FLASH_INFO:
1216		rc = ioctl_flash_info(stdev, argp);
1217		break;
1218	case SWITCHTEC_IOCTL_FLASH_PART_INFO:
1219		rc = ioctl_flash_part_info(stdev, argp);
1220		break;
1221	case SWITCHTEC_IOCTL_EVENT_SUMMARY_LEGACY:
1222		rc = ioctl_event_summary(stdev, stuser, argp,
1223					 sizeof(struct switchtec_ioctl_event_summary_legacy));
1224		break;
1225	case SWITCHTEC_IOCTL_EVENT_CTL:
1226		rc = ioctl_event_ctl(stdev, argp);
1227		break;
1228	case SWITCHTEC_IOCTL_PFF_TO_PORT:
1229		rc = ioctl_pff_to_port(stdev, argp);
1230		break;
1231	case SWITCHTEC_IOCTL_PORT_TO_PFF:
1232		rc = ioctl_port_to_pff(stdev, argp);
1233		break;
1234	case SWITCHTEC_IOCTL_EVENT_SUMMARY:
1235		rc = ioctl_event_summary(stdev, stuser, argp,
1236					 sizeof(struct switchtec_ioctl_event_summary));
1237		break;
1238	default:
1239		rc = -ENOTTY;
1240		break;
1241	}
1242
1243	mutex_unlock(&stdev->mrpc_mutex);
1244	return rc;
1245}
1246
1247static const struct file_operations switchtec_fops = {
1248	.owner = THIS_MODULE,
1249	.open = switchtec_dev_open,
1250	.release = switchtec_dev_release,
1251	.write = switchtec_dev_write,
1252	.read = switchtec_dev_read,
1253	.poll = switchtec_dev_poll,
1254	.unlocked_ioctl = switchtec_dev_ioctl,
1255	.compat_ioctl = compat_ptr_ioctl,
1256};
1257
1258static void link_event_work(struct work_struct *work)
1259{
1260	struct switchtec_dev *stdev;
1261
1262	stdev = container_of(work, struct switchtec_dev, link_event_work);
1263
1264	if (stdev->link_notifier)
1265		stdev->link_notifier(stdev);
1266}
1267
1268static void check_link_state_events(struct switchtec_dev *stdev)
1269{
1270	int idx;
1271	u32 reg;
1272	int count;
1273	int occurred = 0;
1274
1275	for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1276		reg = ioread32(&stdev->mmio_pff_csr[idx].link_state_hdr);
1277		dev_dbg(&stdev->dev, "link_state: %d->%08x\n", idx, reg);
1278		count = (reg >> 5) & 0xFF;
1279
1280		if (count != stdev->link_event_count[idx]) {
1281			occurred = 1;
1282			stdev->link_event_count[idx] = count;
1283		}
1284	}
1285
1286	if (occurred)
1287		schedule_work(&stdev->link_event_work);
1288}
1289
1290static void enable_link_state_events(struct switchtec_dev *stdev)
1291{
1292	int idx;
1293
1294	for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1295		iowrite32(SWITCHTEC_EVENT_CLEAR |
1296			  SWITCHTEC_EVENT_EN_IRQ,
1297			  &stdev->mmio_pff_csr[idx].link_state_hdr);
1298	}
1299}
1300
1301static void enable_dma_mrpc(struct switchtec_dev *stdev)
1302{
1303	writeq(stdev->dma_mrpc_dma_addr, &stdev->mmio_mrpc->dma_addr);
1304	flush_wc_buf(stdev);
1305	iowrite32(SWITCHTEC_DMA_MRPC_EN, &stdev->mmio_mrpc->dma_en);
1306}
1307
1308static void stdev_release(struct device *dev)
1309{
1310	struct switchtec_dev *stdev = to_stdev(dev);
1311
1312	kfree(stdev);
1313}
1314
1315static void stdev_kill(struct switchtec_dev *stdev)
1316{
1317	struct switchtec_user *stuser, *tmpuser;
1318
1319	pci_clear_master(stdev->pdev);
1320
1321	cancel_delayed_work_sync(&stdev->mrpc_timeout);
1322
1323	/* Mark the hardware as unavailable and complete all completions */
1324	scoped_guard (mutex, &stdev->mrpc_mutex) {
1325		stdev->alive = false;
1326
1327		/* Wake up and kill any users waiting on an MRPC request */
1328		list_for_each_entry_safe(stuser, tmpuser, &stdev->mrpc_queue, list) {
1329			stuser->cmd_done = true;
1330			wake_up_interruptible(&stuser->cmd_comp);
1331			list_del_init(&stuser->list);
1332			stuser_put(stuser);
1333		}
1334
1335	}
1336
1337	/* Wake up any users waiting on event_wq */
1338	wake_up_interruptible(&stdev->event_wq);
1339}
1340
1341static struct switchtec_dev *stdev_create(struct pci_dev *pdev)
1342{
1343	struct switchtec_dev *stdev;
1344	int minor;
1345	struct device *dev;
1346	struct cdev *cdev;
1347	int rc;
1348
1349	stdev = kzalloc_node(sizeof(*stdev), GFP_KERNEL,
1350			     dev_to_node(&pdev->dev));
1351	if (!stdev)
1352		return ERR_PTR(-ENOMEM);
1353
1354	stdev->alive = true;
1355	stdev->pdev = pci_dev_get(pdev);
1356	INIT_LIST_HEAD(&stdev->mrpc_queue);
1357	mutex_init(&stdev->mrpc_mutex);
1358	stdev->mrpc_busy = 0;
1359	INIT_WORK(&stdev->mrpc_work, mrpc_event_work);
1360	INIT_DELAYED_WORK(&stdev->mrpc_timeout, mrpc_timeout_work);
1361	INIT_WORK(&stdev->link_event_work, link_event_work);
1362	init_waitqueue_head(&stdev->event_wq);
1363	atomic_set(&stdev->event_cnt, 0);
1364
1365	dev = &stdev->dev;
1366	device_initialize(dev);
1367	dev->class = &switchtec_class;
1368	dev->parent = &pdev->dev;
1369	dev->groups = switchtec_device_groups;
1370	dev->release = stdev_release;
1371
1372	minor = ida_alloc(&switchtec_minor_ida, GFP_KERNEL);
1373	if (minor < 0) {
1374		rc = minor;
1375		goto err_put;
1376	}
1377
1378	dev->devt = MKDEV(MAJOR(switchtec_devt), minor);
1379	dev_set_name(dev, "switchtec%d", minor);
1380
1381	cdev = &stdev->cdev;
1382	cdev_init(cdev, &switchtec_fops);
1383	cdev->owner = THIS_MODULE;
1384
1385	return stdev;
1386
1387err_put:
1388	pci_dev_put(stdev->pdev);
1389	put_device(&stdev->dev);
1390	return ERR_PTR(rc);
1391}
1392
1393static int mask_event(struct switchtec_dev *stdev, int eid, int idx)
1394{
1395	size_t off = event_regs[eid].offset;
1396	u32 __iomem *hdr_reg;
1397	u32 hdr;
1398
1399	hdr_reg = event_regs[eid].map_reg(stdev, off, idx);
1400	hdr = ioread32(hdr_reg);
1401
1402	if (hdr & SWITCHTEC_EVENT_NOT_SUPP)
1403		return 0;
1404
1405	if (!(hdr & SWITCHTEC_EVENT_OCCURRED && hdr & SWITCHTEC_EVENT_EN_IRQ))
1406		return 0;
1407
1408	dev_dbg(&stdev->dev, "%s: %d %d %x\n", __func__, eid, idx, hdr);
1409	hdr &= ~(SWITCHTEC_EVENT_EN_IRQ | SWITCHTEC_EVENT_OCCURRED);
1410	iowrite32(hdr, hdr_reg);
1411
1412	return 1;
1413}
1414
1415static int mask_all_events(struct switchtec_dev *stdev, int eid)
1416{
1417	int idx;
1418	int count = 0;
1419
1420	if (event_regs[eid].map_reg == part_ev_reg) {
1421		for (idx = 0; idx < stdev->partition_count; idx++)
1422			count += mask_event(stdev, eid, idx);
1423	} else if (event_regs[eid].map_reg == pff_ev_reg) {
1424		for (idx = 0; idx < stdev->pff_csr_count; idx++) {
1425			if (!stdev->pff_local[idx])
1426				continue;
1427
1428			count += mask_event(stdev, eid, idx);
1429		}
1430	} else {
1431		count += mask_event(stdev, eid, 0);
1432	}
1433
1434	return count;
1435}
1436
1437static irqreturn_t switchtec_event_isr(int irq, void *dev)
1438{
1439	struct switchtec_dev *stdev = dev;
1440	u32 reg;
1441	irqreturn_t ret = IRQ_NONE;
1442	int eid, event_count = 0;
1443
1444	reg = ioread32(&stdev->mmio_part_cfg->mrpc_comp_hdr);
1445	if (reg & SWITCHTEC_EVENT_OCCURRED) {
1446		dev_dbg(&stdev->dev, "%s: mrpc comp\n", __func__);
1447		ret = IRQ_HANDLED;
1448		schedule_work(&stdev->mrpc_work);
1449		iowrite32(reg, &stdev->mmio_part_cfg->mrpc_comp_hdr);
1450	}
1451
1452	check_link_state_events(stdev);
1453
1454	for (eid = 0; eid < SWITCHTEC_IOCTL_MAX_EVENTS; eid++) {
1455		if (eid == SWITCHTEC_IOCTL_EVENT_LINK_STATE ||
1456		    eid == SWITCHTEC_IOCTL_EVENT_MRPC_COMP)
1457			continue;
1458
1459		event_count += mask_all_events(stdev, eid);
1460	}
1461
1462	if (event_count) {
1463		atomic_inc(&stdev->event_cnt);
1464		wake_up_interruptible(&stdev->event_wq);
1465		dev_dbg(&stdev->dev, "%s: %d events\n", __func__,
1466			event_count);
1467		return IRQ_HANDLED;
1468	}
1469
1470	return ret;
1471}
1472
1473
1474static irqreturn_t switchtec_dma_mrpc_isr(int irq, void *dev)
1475{
1476	struct switchtec_dev *stdev = dev;
1477
1478	iowrite32(SWITCHTEC_EVENT_CLEAR |
1479		  SWITCHTEC_EVENT_EN_IRQ,
1480		  &stdev->mmio_part_cfg->mrpc_comp_hdr);
1481	schedule_work(&stdev->mrpc_work);
1482
1483	return IRQ_HANDLED;
1484}
1485
1486static int switchtec_init_isr(struct switchtec_dev *stdev)
1487{
1488	int nvecs;
1489	int event_irq;
1490	int dma_mrpc_irq;
1491	int rc;
1492
1493	if (nirqs < 4)
1494		nirqs = 4;
1495
1496	nvecs = pci_alloc_irq_vectors(stdev->pdev, 1, nirqs,
1497				      PCI_IRQ_MSIX | PCI_IRQ_MSI |
1498				      PCI_IRQ_VIRTUAL);
1499	if (nvecs < 0)
1500		return nvecs;
1501
1502	event_irq = ioread16(&stdev->mmio_part_cfg->vep_vector_number);
1503	if (event_irq < 0 || event_irq >= nvecs)
1504		return -EFAULT;
1505
1506	event_irq = pci_irq_vector(stdev->pdev, event_irq);
1507	if (event_irq < 0)
1508		return event_irq;
1509
1510	rc = devm_request_irq(&stdev->pdev->dev, event_irq,
1511				switchtec_event_isr, 0,
1512				KBUILD_MODNAME, stdev);
1513
1514	if (rc)
1515		return rc;
1516
1517	if (!stdev->dma_mrpc)
1518		return rc;
1519
1520	dma_mrpc_irq = ioread32(&stdev->mmio_mrpc->dma_vector);
1521	if (dma_mrpc_irq < 0 || dma_mrpc_irq >= nvecs)
1522		return -EFAULT;
1523
1524	dma_mrpc_irq  = pci_irq_vector(stdev->pdev, dma_mrpc_irq);
1525	if (dma_mrpc_irq < 0)
1526		return dma_mrpc_irq;
1527
1528	rc = devm_request_irq(&stdev->pdev->dev, dma_mrpc_irq,
1529				switchtec_dma_mrpc_isr, 0,
1530				KBUILD_MODNAME, stdev);
1531
1532	return rc;
1533}
1534
1535static void init_pff(struct switchtec_dev *stdev)
1536{
1537	int i;
1538	u32 reg;
1539	struct part_cfg_regs __iomem *pcfg = stdev->mmio_part_cfg;
1540
1541	for (i = 0; i < SWITCHTEC_MAX_PFF_CSR; i++) {
1542		reg = ioread16(&stdev->mmio_pff_csr[i].vendor_id);
1543		if (reg != PCI_VENDOR_ID_MICROSEMI)
1544			break;
1545	}
1546
1547	stdev->pff_csr_count = i;
1548
1549	reg = ioread32(&pcfg->usp_pff_inst_id);
1550	if (reg < stdev->pff_csr_count)
1551		stdev->pff_local[reg] = 1;
1552
1553	reg = ioread32(&pcfg->vep_pff_inst_id) & 0xFF;
1554	if (reg < stdev->pff_csr_count)
1555		stdev->pff_local[reg] = 1;
1556
1557	for (i = 0; i < ARRAY_SIZE(pcfg->dsp_pff_inst_id); i++) {
1558		reg = ioread32(&pcfg->dsp_pff_inst_id[i]);
1559		if (reg < stdev->pff_csr_count)
1560			stdev->pff_local[reg] = 1;
1561	}
1562}
1563
1564static int switchtec_init_pci(struct switchtec_dev *stdev,
1565			      struct pci_dev *pdev)
1566{
1567	int rc;
1568	void __iomem *map;
1569	unsigned long res_start, res_len;
1570	u32 __iomem *part_id;
1571
1572	rc = pcim_enable_device(pdev);
1573	if (rc)
1574		return rc;
1575
1576	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1577	if (rc)
1578		return rc;
1579
1580	pci_set_master(pdev);
1581
1582	res_start = pci_resource_start(pdev, 0);
1583	res_len = pci_resource_len(pdev, 0);
1584
1585	if (!devm_request_mem_region(&pdev->dev, res_start,
1586				     res_len, KBUILD_MODNAME))
1587		return -EBUSY;
1588
1589	stdev->mmio_mrpc = devm_ioremap_wc(&pdev->dev, res_start,
1590					   SWITCHTEC_GAS_TOP_CFG_OFFSET);
1591	if (!stdev->mmio_mrpc)
1592		return -ENOMEM;
1593
1594	map = devm_ioremap(&pdev->dev,
1595			   res_start + SWITCHTEC_GAS_TOP_CFG_OFFSET,
1596			   res_len - SWITCHTEC_GAS_TOP_CFG_OFFSET);
1597	if (!map)
1598		return -ENOMEM;
1599
1600	stdev->mmio = map - SWITCHTEC_GAS_TOP_CFG_OFFSET;
1601	stdev->mmio_sw_event = stdev->mmio + SWITCHTEC_GAS_SW_EVENT_OFFSET;
1602	stdev->mmio_sys_info = stdev->mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
1603	stdev->mmio_flash_info = stdev->mmio + SWITCHTEC_GAS_FLASH_INFO_OFFSET;
1604	stdev->mmio_ntb = stdev->mmio + SWITCHTEC_GAS_NTB_OFFSET;
1605
1606	if (stdev->gen == SWITCHTEC_GEN3)
1607		part_id = &stdev->mmio_sys_info->gen3.partition_id;
1608	else if (stdev->gen >= SWITCHTEC_GEN4)
1609		part_id = &stdev->mmio_sys_info->gen4.partition_id;
1610	else
1611		return -EOPNOTSUPP;
1612
1613	stdev->partition = ioread8(part_id);
1614	stdev->partition_count = ioread8(&stdev->mmio_ntb->partition_count);
1615	stdev->mmio_part_cfg_all = stdev->mmio + SWITCHTEC_GAS_PART_CFG_OFFSET;
1616	stdev->mmio_part_cfg = &stdev->mmio_part_cfg_all[stdev->partition];
1617	stdev->mmio_pff_csr = stdev->mmio + SWITCHTEC_GAS_PFF_CSR_OFFSET;
1618
1619	if (stdev->partition_count < 1)
1620		stdev->partition_count = 1;
1621
1622	init_pff(stdev);
1623
1624	pci_set_drvdata(pdev, stdev);
1625
1626	if (!use_dma_mrpc)
1627		return 0;
1628
1629	if (ioread32(&stdev->mmio_mrpc->dma_ver) == 0)
1630		return 0;
1631
1632	stdev->dma_mrpc = dma_alloc_coherent(&stdev->pdev->dev,
1633					     sizeof(*stdev->dma_mrpc),
1634					     &stdev->dma_mrpc_dma_addr,
1635					     GFP_KERNEL);
1636	if (stdev->dma_mrpc == NULL)
1637		return -ENOMEM;
1638
1639	return 0;
1640}
1641
1642static void switchtec_exit_pci(struct switchtec_dev *stdev)
1643{
1644	if (stdev->dma_mrpc) {
1645		iowrite32(0, &stdev->mmio_mrpc->dma_en);
1646		flush_wc_buf(stdev);
1647		writeq(0, &stdev->mmio_mrpc->dma_addr);
1648		dma_free_coherent(&stdev->pdev->dev, sizeof(*stdev->dma_mrpc),
1649				  stdev->dma_mrpc, stdev->dma_mrpc_dma_addr);
1650		stdev->dma_mrpc = NULL;
1651	}
1652}
1653
1654static int switchtec_pci_probe(struct pci_dev *pdev,
1655			       const struct pci_device_id *id)
1656{
1657	struct switchtec_dev *stdev;
1658	int rc;
1659
1660	if (pdev->class == (PCI_CLASS_BRIDGE_OTHER << 8))
1661		request_module_nowait("ntb_hw_switchtec");
1662
1663	stdev = stdev_create(pdev);
1664	if (IS_ERR(stdev))
1665		return PTR_ERR(stdev);
1666
1667	stdev->gen = id->driver_data;
1668
1669	rc = switchtec_init_pci(stdev, pdev);
1670	if (rc)
1671		goto err_put;
1672
1673	rc = switchtec_init_isr(stdev);
1674	if (rc) {
1675		dev_err(&stdev->dev, "failed to init isr.\n");
1676		goto err_exit_pci;
1677	}
1678
1679	iowrite32(SWITCHTEC_EVENT_CLEAR |
1680		  SWITCHTEC_EVENT_EN_IRQ,
1681		  &stdev->mmio_part_cfg->mrpc_comp_hdr);
1682	enable_link_state_events(stdev);
1683
1684	if (stdev->dma_mrpc)
1685		enable_dma_mrpc(stdev);
1686
1687	rc = cdev_device_add(&stdev->cdev, &stdev->dev);
1688	if (rc)
1689		goto err_devadd;
1690
1691	dev_info(&stdev->dev, "Management device registered.\n");
1692
1693	return 0;
1694
1695err_devadd:
1696	stdev_kill(stdev);
1697err_exit_pci:
1698	switchtec_exit_pci(stdev);
1699err_put:
1700	ida_free(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1701	put_device(&stdev->dev);
1702	return rc;
1703}
1704
1705static void switchtec_pci_remove(struct pci_dev *pdev)
1706{
1707	struct switchtec_dev *stdev = pci_get_drvdata(pdev);
1708
1709	pci_set_drvdata(pdev, NULL);
1710
1711	cdev_device_del(&stdev->cdev, &stdev->dev);
1712	ida_free(&switchtec_minor_ida, MINOR(stdev->dev.devt));
1713	dev_info(&stdev->dev, "unregistered.\n");
1714	stdev_kill(stdev);
1715	switchtec_exit_pci(stdev);
1716	pci_dev_put(stdev->pdev);
1717	stdev->pdev = NULL;
1718	put_device(&stdev->dev);
1719}
1720
1721#define SWITCHTEC_PCI_DEVICE(device_id, gen) \
1722	{ \
1723		.vendor     = PCI_VENDOR_ID_MICROSEMI, \
1724		.device     = device_id, \
1725		.subvendor  = PCI_ANY_ID, \
1726		.subdevice  = PCI_ANY_ID, \
1727		.class      = (PCI_CLASS_MEMORY_OTHER << 8), \
1728		.class_mask = 0xFFFFFFFF, \
1729		.driver_data = gen, \
1730	}, \
1731	{ \
1732		.vendor     = PCI_VENDOR_ID_MICROSEMI, \
1733		.device     = device_id, \
1734		.subvendor  = PCI_ANY_ID, \
1735		.subdevice  = PCI_ANY_ID, \
1736		.class      = (PCI_CLASS_BRIDGE_OTHER << 8), \
1737		.class_mask = 0xFFFFFFFF, \
1738		.driver_data = gen, \
1739	}
1740
1741#define SWITCHTEC_PCI100X_DEVICE(device_id, gen) \
1742	{ \
1743		.vendor     = PCI_VENDOR_ID_EFAR, \
1744		.device     = device_id, \
1745		.subvendor  = PCI_ANY_ID, \
1746		.subdevice  = PCI_ANY_ID, \
1747		.class      = (PCI_CLASS_MEMORY_OTHER << 8), \
1748		.class_mask = 0xFFFFFFFF, \
1749		.driver_data = gen, \
1750	}, \
1751	{ \
1752		.vendor     = PCI_VENDOR_ID_EFAR, \
1753		.device     = device_id, \
1754		.subvendor  = PCI_ANY_ID, \
1755		.subdevice  = PCI_ANY_ID, \
1756		.class      = (PCI_CLASS_BRIDGE_OTHER << 8), \
1757		.class_mask = 0xFFFFFFFF, \
1758		.driver_data = gen, \
1759	}
1760
1761static const struct pci_device_id switchtec_pci_tbl[] = {
1762	SWITCHTEC_PCI_DEVICE(0x8531, SWITCHTEC_GEN3),  /* PFX 24xG3 */
1763	SWITCHTEC_PCI_DEVICE(0x8532, SWITCHTEC_GEN3),  /* PFX 32xG3 */
1764	SWITCHTEC_PCI_DEVICE(0x8533, SWITCHTEC_GEN3),  /* PFX 48xG3 */
1765	SWITCHTEC_PCI_DEVICE(0x8534, SWITCHTEC_GEN3),  /* PFX 64xG3 */
1766	SWITCHTEC_PCI_DEVICE(0x8535, SWITCHTEC_GEN3),  /* PFX 80xG3 */
1767	SWITCHTEC_PCI_DEVICE(0x8536, SWITCHTEC_GEN3),  /* PFX 96xG3 */
1768	SWITCHTEC_PCI_DEVICE(0x8541, SWITCHTEC_GEN3),  /* PSX 24xG3 */
1769	SWITCHTEC_PCI_DEVICE(0x8542, SWITCHTEC_GEN3),  /* PSX 32xG3 */
1770	SWITCHTEC_PCI_DEVICE(0x8543, SWITCHTEC_GEN3),  /* PSX 48xG3 */
1771	SWITCHTEC_PCI_DEVICE(0x8544, SWITCHTEC_GEN3),  /* PSX 64xG3 */
1772	SWITCHTEC_PCI_DEVICE(0x8545, SWITCHTEC_GEN3),  /* PSX 80xG3 */
1773	SWITCHTEC_PCI_DEVICE(0x8546, SWITCHTEC_GEN3),  /* PSX 96xG3 */
1774	SWITCHTEC_PCI_DEVICE(0x8551, SWITCHTEC_GEN3),  /* PAX 24XG3 */
1775	SWITCHTEC_PCI_DEVICE(0x8552, SWITCHTEC_GEN3),  /* PAX 32XG3 */
1776	SWITCHTEC_PCI_DEVICE(0x8553, SWITCHTEC_GEN3),  /* PAX 48XG3 */
1777	SWITCHTEC_PCI_DEVICE(0x8554, SWITCHTEC_GEN3),  /* PAX 64XG3 */
1778	SWITCHTEC_PCI_DEVICE(0x8555, SWITCHTEC_GEN3),  /* PAX 80XG3 */
1779	SWITCHTEC_PCI_DEVICE(0x8556, SWITCHTEC_GEN3),  /* PAX 96XG3 */
1780	SWITCHTEC_PCI_DEVICE(0x8561, SWITCHTEC_GEN3),  /* PFXL 24XG3 */
1781	SWITCHTEC_PCI_DEVICE(0x8562, SWITCHTEC_GEN3),  /* PFXL 32XG3 */
1782	SWITCHTEC_PCI_DEVICE(0x8563, SWITCHTEC_GEN3),  /* PFXL 48XG3 */
1783	SWITCHTEC_PCI_DEVICE(0x8564, SWITCHTEC_GEN3),  /* PFXL 64XG3 */
1784	SWITCHTEC_PCI_DEVICE(0x8565, SWITCHTEC_GEN3),  /* PFXL 80XG3 */
1785	SWITCHTEC_PCI_DEVICE(0x8566, SWITCHTEC_GEN3),  /* PFXL 96XG3 */
1786	SWITCHTEC_PCI_DEVICE(0x8571, SWITCHTEC_GEN3),  /* PFXI 24XG3 */
1787	SWITCHTEC_PCI_DEVICE(0x8572, SWITCHTEC_GEN3),  /* PFXI 32XG3 */
1788	SWITCHTEC_PCI_DEVICE(0x8573, SWITCHTEC_GEN3),  /* PFXI 48XG3 */
1789	SWITCHTEC_PCI_DEVICE(0x8574, SWITCHTEC_GEN3),  /* PFXI 64XG3 */
1790	SWITCHTEC_PCI_DEVICE(0x8575, SWITCHTEC_GEN3),  /* PFXI 80XG3 */
1791	SWITCHTEC_PCI_DEVICE(0x8576, SWITCHTEC_GEN3),  /* PFXI 96XG3 */
1792	SWITCHTEC_PCI_DEVICE(0x4000, SWITCHTEC_GEN4),  /* PFX 100XG4 */
1793	SWITCHTEC_PCI_DEVICE(0x4084, SWITCHTEC_GEN4),  /* PFX 84XG4 */
1794	SWITCHTEC_PCI_DEVICE(0x4068, SWITCHTEC_GEN4),  /* PFX 68XG4 */
1795	SWITCHTEC_PCI_DEVICE(0x4052, SWITCHTEC_GEN4),  /* PFX 52XG4 */
1796	SWITCHTEC_PCI_DEVICE(0x4036, SWITCHTEC_GEN4),  /* PFX 36XG4 */
1797	SWITCHTEC_PCI_DEVICE(0x4028, SWITCHTEC_GEN4),  /* PFX 28XG4 */
1798	SWITCHTEC_PCI_DEVICE(0x4100, SWITCHTEC_GEN4),  /* PSX 100XG4 */
1799	SWITCHTEC_PCI_DEVICE(0x4184, SWITCHTEC_GEN4),  /* PSX 84XG4 */
1800	SWITCHTEC_PCI_DEVICE(0x4168, SWITCHTEC_GEN4),  /* PSX 68XG4 */
1801	SWITCHTEC_PCI_DEVICE(0x4152, SWITCHTEC_GEN4),  /* PSX 52XG4 */
1802	SWITCHTEC_PCI_DEVICE(0x4136, SWITCHTEC_GEN4),  /* PSX 36XG4 */
1803	SWITCHTEC_PCI_DEVICE(0x4128, SWITCHTEC_GEN4),  /* PSX 28XG4 */
1804	SWITCHTEC_PCI_DEVICE(0x4200, SWITCHTEC_GEN4),  /* PAX 100XG4 */
1805	SWITCHTEC_PCI_DEVICE(0x4284, SWITCHTEC_GEN4),  /* PAX 84XG4 */
1806	SWITCHTEC_PCI_DEVICE(0x4268, SWITCHTEC_GEN4),  /* PAX 68XG4 */
1807	SWITCHTEC_PCI_DEVICE(0x4252, SWITCHTEC_GEN4),  /* PAX 52XG4 */
1808	SWITCHTEC_PCI_DEVICE(0x4236, SWITCHTEC_GEN4),  /* PAX 36XG4 */
1809	SWITCHTEC_PCI_DEVICE(0x4228, SWITCHTEC_GEN4),  /* PAX 28XG4 */
1810	SWITCHTEC_PCI_DEVICE(0x4352, SWITCHTEC_GEN4),  /* PFXA 52XG4 */
1811	SWITCHTEC_PCI_DEVICE(0x4336, SWITCHTEC_GEN4),  /* PFXA 36XG4 */
1812	SWITCHTEC_PCI_DEVICE(0x4328, SWITCHTEC_GEN4),  /* PFXA 28XG4 */
1813	SWITCHTEC_PCI_DEVICE(0x4452, SWITCHTEC_GEN4),  /* PSXA 52XG4 */
1814	SWITCHTEC_PCI_DEVICE(0x4436, SWITCHTEC_GEN4),  /* PSXA 36XG4 */
1815	SWITCHTEC_PCI_DEVICE(0x4428, SWITCHTEC_GEN4),  /* PSXA 28XG4 */
1816	SWITCHTEC_PCI_DEVICE(0x4552, SWITCHTEC_GEN4),  /* PAXA 52XG4 */
1817	SWITCHTEC_PCI_DEVICE(0x4536, SWITCHTEC_GEN4),  /* PAXA 36XG4 */
1818	SWITCHTEC_PCI_DEVICE(0x4528, SWITCHTEC_GEN4),  /* PAXA 28XG4 */
1819	SWITCHTEC_PCI_DEVICE(0x5000, SWITCHTEC_GEN5),  /* PFX 100XG5 */
1820	SWITCHTEC_PCI_DEVICE(0x5084, SWITCHTEC_GEN5),  /* PFX 84XG5 */
1821	SWITCHTEC_PCI_DEVICE(0x5068, SWITCHTEC_GEN5),  /* PFX 68XG5 */
1822	SWITCHTEC_PCI_DEVICE(0x5052, SWITCHTEC_GEN5),  /* PFX 52XG5 */
1823	SWITCHTEC_PCI_DEVICE(0x5036, SWITCHTEC_GEN5),  /* PFX 36XG5 */
1824	SWITCHTEC_PCI_DEVICE(0x5028, SWITCHTEC_GEN5),  /* PFX 28XG5 */
1825	SWITCHTEC_PCI_DEVICE(0x5100, SWITCHTEC_GEN5),  /* PSX 100XG5 */
1826	SWITCHTEC_PCI_DEVICE(0x5184, SWITCHTEC_GEN5),  /* PSX 84XG5 */
1827	SWITCHTEC_PCI_DEVICE(0x5168, SWITCHTEC_GEN5),  /* PSX 68XG5 */
1828	SWITCHTEC_PCI_DEVICE(0x5152, SWITCHTEC_GEN5),  /* PSX 52XG5 */
1829	SWITCHTEC_PCI_DEVICE(0x5136, SWITCHTEC_GEN5),  /* PSX 36XG5 */
1830	SWITCHTEC_PCI_DEVICE(0x5128, SWITCHTEC_GEN5),  /* PSX 28XG5 */
1831	SWITCHTEC_PCI_DEVICE(0x5200, SWITCHTEC_GEN5),  /* PAX 100XG5 */
1832	SWITCHTEC_PCI_DEVICE(0x5284, SWITCHTEC_GEN5),  /* PAX 84XG5 */
1833	SWITCHTEC_PCI_DEVICE(0x5268, SWITCHTEC_GEN5),  /* PAX 68XG5 */
1834	SWITCHTEC_PCI_DEVICE(0x5252, SWITCHTEC_GEN5),  /* PAX 52XG5 */
1835	SWITCHTEC_PCI_DEVICE(0x5236, SWITCHTEC_GEN5),  /* PAX 36XG5 */
1836	SWITCHTEC_PCI_DEVICE(0x5228, SWITCHTEC_GEN5),  /* PAX 28XG5 */
1837	SWITCHTEC_PCI_DEVICE(0x5300, SWITCHTEC_GEN5),  /* PFXA 100XG5 */
1838	SWITCHTEC_PCI_DEVICE(0x5384, SWITCHTEC_GEN5),  /* PFXA 84XG5 */
1839	SWITCHTEC_PCI_DEVICE(0x5368, SWITCHTEC_GEN5),  /* PFXA 68XG5 */
1840	SWITCHTEC_PCI_DEVICE(0x5352, SWITCHTEC_GEN5),  /* PFXA 52XG5 */
1841	SWITCHTEC_PCI_DEVICE(0x5336, SWITCHTEC_GEN5),  /* PFXA 36XG5 */
1842	SWITCHTEC_PCI_DEVICE(0x5328, SWITCHTEC_GEN5),  /* PFXA 28XG5 */
1843	SWITCHTEC_PCI_DEVICE(0x5400, SWITCHTEC_GEN5),  /* PSXA 100XG5 */
1844	SWITCHTEC_PCI_DEVICE(0x5484, SWITCHTEC_GEN5),  /* PSXA 84XG5 */
1845	SWITCHTEC_PCI_DEVICE(0x5468, SWITCHTEC_GEN5),  /* PSXA 68XG5 */
1846	SWITCHTEC_PCI_DEVICE(0x5452, SWITCHTEC_GEN5),  /* PSXA 52XG5 */
1847	SWITCHTEC_PCI_DEVICE(0x5436, SWITCHTEC_GEN5),  /* PSXA 36XG5 */
1848	SWITCHTEC_PCI_DEVICE(0x5428, SWITCHTEC_GEN5),  /* PSXA 28XG5 */
1849	SWITCHTEC_PCI_DEVICE(0x5500, SWITCHTEC_GEN5),  /* PAXA 100XG5 */
1850	SWITCHTEC_PCI_DEVICE(0x5584, SWITCHTEC_GEN5),  /* PAXA 84XG5 */
1851	SWITCHTEC_PCI_DEVICE(0x5568, SWITCHTEC_GEN5),  /* PAXA 68XG5 */
1852	SWITCHTEC_PCI_DEVICE(0x5552, SWITCHTEC_GEN5),  /* PAXA 52XG5 */
1853	SWITCHTEC_PCI_DEVICE(0x5536, SWITCHTEC_GEN5),  /* PAXA 36XG5 */
1854	SWITCHTEC_PCI_DEVICE(0x5528, SWITCHTEC_GEN5),  /* PAXA 28XG5 */
1855	SWITCHTEC_PCI100X_DEVICE(0x1001, SWITCHTEC_GEN4),  /* PCI1001 16XG4 */
1856	SWITCHTEC_PCI100X_DEVICE(0x1002, SWITCHTEC_GEN4),  /* PCI1002 12XG4 */
1857	SWITCHTEC_PCI100X_DEVICE(0x1003, SWITCHTEC_GEN4),  /* PCI1003 16XG4 */
1858	SWITCHTEC_PCI100X_DEVICE(0x1004, SWITCHTEC_GEN4),  /* PCI1004 16XG4 */
1859	SWITCHTEC_PCI100X_DEVICE(0x1005, SWITCHTEC_GEN4),  /* PCI1005 16XG4 */
1860	SWITCHTEC_PCI100X_DEVICE(0x1006, SWITCHTEC_GEN4),  /* PCI1006 16XG4 */
1861	{0}
1862};
1863MODULE_DEVICE_TABLE(pci, switchtec_pci_tbl);
1864
1865static struct pci_driver switchtec_pci_driver = {
1866	.name		= KBUILD_MODNAME,
1867	.id_table	= switchtec_pci_tbl,
1868	.probe		= switchtec_pci_probe,
1869	.remove		= switchtec_pci_remove,
1870};
1871
1872static int __init switchtec_init(void)
1873{
1874	int rc;
1875
1876	rc = alloc_chrdev_region(&switchtec_devt, 0, max_devices,
1877				 "switchtec");
1878	if (rc)
1879		return rc;
1880
1881	rc = class_register(&switchtec_class);
1882	if (rc)
1883		goto err_create_class;
1884
1885	rc = pci_register_driver(&switchtec_pci_driver);
1886	if (rc)
1887		goto err_pci_register;
1888
1889	pr_info(KBUILD_MODNAME ": loaded.\n");
1890
1891	return 0;
1892
1893err_pci_register:
1894	class_unregister(&switchtec_class);
1895
1896err_create_class:
1897	unregister_chrdev_region(switchtec_devt, max_devices);
1898
1899	return rc;
1900}
1901module_init(switchtec_init);
1902
1903static void __exit switchtec_exit(void)
1904{
1905	pci_unregister_driver(&switchtec_pci_driver);
1906	class_unregister(&switchtec_class);
1907	unregister_chrdev_region(switchtec_devt, max_devices);
1908	ida_destroy(&switchtec_minor_ida);
1909
1910	pr_info(KBUILD_MODNAME ": unloaded.\n");
1911}
1912module_exit(switchtec_exit);