setup-bus.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Support routines for initializing a PCI subsystem
   4 *
   5 * Extruded from code written by
   6 *      Dave Rusling (david.rusling@reo.mts.dec.com)
   7 *      David Mosberger (davidm@cs.arizona.edu)
   8 *	David Miller (davem@redhat.com)
   9 *
  10 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  11 *	     PCI-PCI bridges cleanup, sorted resource allocation.
  12 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
  13 *	     Converted to allocation in 3 passes, which gives
  14 *	     tighter packing. Prefetchable range support.
  15 */
  16
  17#include <linux/align.h>
  18#include <linux/bitops.h>
  19#include <linux/bug.h>
  20#include <linux/init.h>
  21#include <linux/kernel.h>
  22#include <linux/module.h>
  23#include <linux/pci.h>
  24#include <linux/errno.h>
  25#include <linux/ioport.h>
  26#include <linux/cache.h>
  27#include <linux/limits.h>
  28#include <linux/sizes.h>
  29#include <linux/slab.h>
  30#include <linux/acpi.h>
  31#include "pci.h"
  32
  33#define PCI_RES_TYPE_MASK \
  34	(IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH |\
  35	 IORESOURCE_MEM_64)
  36
  37unsigned int pci_flags;
  38EXPORT_SYMBOL_GPL(pci_flags);
  39
  40struct pci_dev_resource {
  41	struct list_head list;
  42	struct resource *res;
  43	struct pci_dev *dev;
  44	resource_size_t start;
  45	resource_size_t end;
  46	resource_size_t add_size;
  47	resource_size_t min_align;
  48	unsigned long flags;
  49};
  50
  51static void free_list(struct list_head *head)
  52{
  53	struct pci_dev_resource *dev_res, *tmp;
  54
  55	list_for_each_entry_safe(dev_res, tmp, head, list) {
  56		list_del(&dev_res->list);
  57		kfree(dev_res);
  58	}
  59}
  60
  61/**
  62 * add_to_list() - Add a new resource tracker to the list
  63 * @head:	Head of the list
  64 * @dev:	Device to which the resource belongs
  65 * @res:	Resource to be tracked
  66 * @add_size:	Additional size to be optionally added to the resource
  67 * @min_align:	Minimum memory window alignment
  68 */
  69static int add_to_list(struct list_head *head, struct pci_dev *dev,
  70		       struct resource *res, resource_size_t add_size,
  71		       resource_size_t min_align)
  72{
  73	struct pci_dev_resource *tmp;
  74
  75	tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
  76	if (!tmp)
  77		return -ENOMEM;
  78
  79	tmp->res = res;
  80	tmp->dev = dev;
  81	tmp->start = res->start;
  82	tmp->end = res->end;
  83	tmp->flags = res->flags;
  84	tmp->add_size = add_size;
  85	tmp->min_align = min_align;
  86
  87	list_add(&tmp->list, head);
  88
  89	return 0;
  90}
  91
  92static void remove_from_list(struct list_head *head, struct resource *res)
  93{
  94	struct pci_dev_resource *dev_res, *tmp;
  95
  96	list_for_each_entry_safe(dev_res, tmp, head, list) {
  97		if (dev_res->res == res) {
  98			list_del(&dev_res->list);
  99			kfree(dev_res);
 100			break;
 101		}
 102	}
 103}
 104
 105static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
 106					       struct resource *res)
 107{
 108	struct pci_dev_resource *dev_res;
 109
 110	list_for_each_entry(dev_res, head, list) {
 111		if (dev_res->res == res)
 112			return dev_res;
 113	}
 114
 115	return NULL;
 116}
 117
 118static resource_size_t get_res_add_size(struct list_head *head,
 119					struct resource *res)
 120{
 121	struct pci_dev_resource *dev_res;
 122
 123	dev_res = res_to_dev_res(head, res);
 124	return dev_res ? dev_res->add_size : 0;
 125}
 126
 127static resource_size_t get_res_add_align(struct list_head *head,
 128					 struct resource *res)
 129{
 130	struct pci_dev_resource *dev_res;
 131
 132	dev_res = res_to_dev_res(head, res);
 133	return dev_res ? dev_res->min_align : 0;
 134}
 135
 136static void restore_dev_resource(struct pci_dev_resource *dev_res)
 137{
 138	struct resource *res = dev_res->res;
 139
 140	if (WARN_ON_ONCE(res->parent))
 141		return;
 142
 143	res->start = dev_res->start;
 144	res->end = dev_res->end;
 145	res->flags = dev_res->flags;
 146}
 147
 148/*
 149 * Helper function for sizing routines.  Assigned resources have non-NULL
 150 * parent resource.
 151 *
 152 * Return first unassigned resource of the correct type.  If there is none,
 153 * return first assigned resource of the correct type.  If none of the
 154 * above, return NULL.
 155 *
 156 * Returning an assigned resource of the correct type allows the caller to
 157 * distinguish between already assigned and no resource of the correct type.
 158 */
 159static struct resource *find_bus_resource_of_type(struct pci_bus *bus,
 160						  unsigned long type_mask,
 161						  unsigned long type)
 162{
 163	struct resource *r, *r_assigned = NULL;
 164
 165	pci_bus_for_each_resource(bus, r) {
 166		if (!r || r == &ioport_resource || r == &iomem_resource)
 167			continue;
 168
 169		if ((r->flags & type_mask) != type)
 170			continue;
 171
 172		if (!r->parent)
 173			return r;
 174		if (!r_assigned)
 175			r_assigned = r;
 176	}
 177	return r_assigned;
 178}
 179
 180/**
 181 * pbus_select_window_for_type - Select bridge window for a resource type
 182 * @bus: PCI bus
 183 * @type: Resource type (resource flags can be passed as is)
 184 *
 185 * Select the bridge window based on a resource @type.
 186 *
 187 * For memory resources, the selection is done as follows:
 188 *
 189 * Any non-prefetchable resource is put into the non-prefetchable window.
 190 *
 191 * If there is no prefetchable MMIO window, put all memory resources into the
 192 * non-prefetchable window.
 193 *
 194 * If there's a 64-bit prefetchable MMIO window, put all 64-bit prefetchable
 195 * resources into it and place 32-bit prefetchable memory into the
 196 * non-prefetchable window.
 197 *
 198 * Otherwise, put all prefetchable resources into the prefetchable window.
 199 *
 200 * Return: the bridge window resource or NULL if no bridge window is found.
 201 */
 202static struct resource *pbus_select_window_for_type(struct pci_bus *bus,
 203						    unsigned long type)
 204{
 205	int iores_type = type & IORESOURCE_TYPE_BITS;	/* w/o 64bit & pref */
 206	struct resource *mmio, *mmio_pref, *win;
 207
 208	type &= PCI_RES_TYPE_MASK;			/* with 64bit & pref */
 209
 210	if ((iores_type != IORESOURCE_IO) && (iores_type != IORESOURCE_MEM))
 211		return NULL;
 212
 213	if (pci_is_root_bus(bus)) {
 214		win = find_bus_resource_of_type(bus, type, type);
 215		if (win)
 216			return win;
 217
 218		type &= ~IORESOURCE_MEM_64;
 219		win = find_bus_resource_of_type(bus, type, type);
 220		if (win)
 221			return win;
 222
 223		type &= ~IORESOURCE_PREFETCH;
 224		return find_bus_resource_of_type(bus, type, type);
 225	}
 226
 227	switch (iores_type) {
 228	case IORESOURCE_IO:
 229		win = pci_bus_resource_n(bus, PCI_BUS_BRIDGE_IO_WINDOW);
 230		if (win && (win->flags & IORESOURCE_IO))
 231			return win;
 232		return NULL;
 233
 234	case IORESOURCE_MEM:
 235		mmio = pci_bus_resource_n(bus, PCI_BUS_BRIDGE_MEM_WINDOW);
 236		mmio_pref = pci_bus_resource_n(bus, PCI_BUS_BRIDGE_PREF_MEM_WINDOW);
 237
 238		if (mmio && !(mmio->flags & IORESOURCE_MEM))
 239			mmio = NULL;
 240		if (mmio_pref && !(mmio_pref->flags & IORESOURCE_MEM))
 241			mmio_pref = NULL;
 242
 243		if (!(type & IORESOURCE_PREFETCH) || !mmio_pref)
 244			return mmio;
 245
 246		if ((type & IORESOURCE_MEM_64) ||
 247		    !(mmio_pref->flags & IORESOURCE_MEM_64))
 248			return mmio_pref;
 249
 250		return mmio;
 251	default:
 252		return NULL;
 253	}
 254}
 255
 256/**
 257 * pbus_select_window - Select bridge window for a resource
 258 * @bus: PCI bus
 259 * @res: Resource
 260 *
 261 * Select the bridge window for @res. If the resource is already assigned,
 262 * return the current bridge window.
 263 *
 264 * For memory resources, the selection is done as follows:
 265 *
 266 * Any non-prefetchable resource is put into the non-prefetchable window.
 267 *
 268 * If there is no prefetchable MMIO window, put all memory resources into the
 269 * non-prefetchable window.
 270 *
 271 * If there's a 64-bit prefetchable MMIO window, put all 64-bit prefetchable
 272 * resources into it and place 32-bit prefetchable memory into the
 273 * non-prefetchable window.
 274 *
 275 * Otherwise, put all prefetchable resources into the prefetchable window.
 276 *
 277 * Return: the bridge window resource or NULL if no bridge window is found.
 278 */
 279struct resource *pbus_select_window(struct pci_bus *bus,
 280				    const struct resource *res)
 281{
 282	if (res->parent)
 283		return res->parent;
 284
 285	return pbus_select_window_for_type(bus, res->flags);
 286}
 287
 288static bool pdev_resources_assignable(struct pci_dev *dev)
 289{
 290	u16 class = dev->class >> 8, command;
 291
 292	/* Don't touch classless devices or host bridges or IOAPICs */
 293	if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
 294		return false;
 295
 296	/* Don't touch IOAPIC devices already enabled by firmware */
 297	if (class == PCI_CLASS_SYSTEM_PIC) {
 298		pci_read_config_word(dev, PCI_COMMAND, &command);
 299		if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
 300			return false;
 301	}
 302
 303	return true;
 304}
 305
 306static bool pdev_resource_assignable(struct pci_dev *dev, struct resource *res)
 307{
 308	int idx = pci_resource_num(dev, res);
 309
 310	if (!res->flags)
 311		return false;
 312
 313	if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END &&
 314	    res->flags & IORESOURCE_DISABLED)
 315		return false;
 316
 317	return true;
 318}
 319
 320static bool pdev_resource_should_fit(struct pci_dev *dev, struct resource *res)
 321{
 322	if (res->parent)
 323		return false;
 324
 325	if (res->flags & IORESOURCE_PCI_FIXED)
 326		return false;
 327
 328	return pdev_resource_assignable(dev, res);
 329}
 330
 331/* Sort resources by alignment */
 332static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
 333{
 334	struct resource *r;
 335	int i;
 336
 337	if (!pdev_resources_assignable(dev))
 338		return;
 339
 340	pci_dev_for_each_resource(dev, r, i) {
 341		const char *r_name = pci_resource_name(dev, i);
 342		struct pci_dev_resource *dev_res, *tmp;
 343		resource_size_t r_align;
 344		struct list_head *n;
 345
 346		if (!pdev_resource_should_fit(dev, r))
 347			continue;
 348
 349		r_align = pci_resource_alignment(dev, r);
 350		if (!r_align) {
 351			pci_warn(dev, "%s %pR: alignment must not be zero\n",
 352				 r_name, r);
 353			continue;
 354		}
 355
 356		tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
 357		if (!tmp)
 358			panic("%s: kzalloc() failed!\n", __func__);
 359		tmp->res = r;
 360		tmp->dev = dev;
 361		tmp->start = r->start;
 362		tmp->end = r->end;
 363		tmp->flags = r->flags;
 364
 365		/* Fallback is smallest one or list is empty */
 366		n = head;
 367		list_for_each_entry(dev_res, head, list) {
 368			resource_size_t align;
 369
 370			align = pci_resource_alignment(dev_res->dev,
 371							 dev_res->res);
 372
 373			if (r_align > align) {
 374				n = &dev_res->list;
 375				break;
 376			}
 377		}
 378		/* Insert it just before n */
 379		list_add_tail(&tmp->list, n);
 380	}
 381}
 382
 383bool pci_resource_is_optional(const struct pci_dev *dev, int resno)
 384{
 385	const struct resource *res = pci_resource_n(dev, resno);
 386
 387	if (pci_resource_is_iov(resno))
 388		return true;
 389	if (resno == PCI_ROM_RESOURCE && !(res->flags & IORESOURCE_ROM_ENABLE))
 390		return true;
 391
 392	return false;
 393}
 394
 395static inline void reset_resource(struct pci_dev *dev, struct resource *res)
 396{
 397	int idx = pci_resource_num(dev, res);
 398
 399	if (idx >= PCI_BRIDGE_RESOURCES && idx <= PCI_BRIDGE_RESOURCE_END) {
 400		res->flags |= IORESOURCE_UNSET;
 401		return;
 402	}
 403
 404	res->start = 0;
 405	res->end = 0;
 406	res->flags = 0;
 407}
 408
 409/**
 410 * reassign_resources_sorted() - Satisfy any additional resource requests
 411 *
 412 * @realloc_head:	Head of the list tracking requests requiring
 413 *			additional resources
 414 * @head:		Head of the list tracking requests with allocated
 415 *			resources
 416 *
 417 * Walk through each element of the realloc_head and try to procure additional
 418 * resources for the element, provided the element is in the head list.
 419 */
 420static void reassign_resources_sorted(struct list_head *realloc_head,
 421				      struct list_head *head)
 422{
 423	struct pci_dev_resource *add_res, *tmp;
 424	struct pci_dev_resource *dev_res;
 425	struct pci_dev *dev;
 426	struct resource *res;
 427	const char *res_name;
 428	resource_size_t add_size, align;
 429	int idx;
 430
 431	list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
 432		bool found_match = false;
 433
 434		res = add_res->res;
 435		dev = add_res->dev;
 436		idx = pci_resource_num(dev, res);
 437
 438		/*
 439		 * Skip resource that failed the earlier assignment and is
 440		 * not optional as it would just fail again.
 441		 */
 442		if (!res->parent && resource_size(res) &&
 443		    !pci_resource_is_optional(dev, idx))
 444			goto out;
 445
 446		/* Skip this resource if not found in head list */
 447		list_for_each_entry(dev_res, head, list) {
 448			if (dev_res->res == res) {
 449				found_match = true;
 450				break;
 451			}
 452		}
 453		if (!found_match) /* Just skip */
 454			continue;
 455
 456		res_name = pci_resource_name(dev, idx);
 457		add_size = add_res->add_size;
 458		align = add_res->min_align;
 459		if (!res->parent) {
 460			resource_set_range(res, align,
 461					   resource_size(res) + add_size);
 462			if (pci_assign_resource(dev, idx)) {
 463				pci_dbg(dev,
 464					"%s %pR: ignoring failure in optional allocation\n",
 465					res_name, res);
 466			}
 467		} else if (add_size > 0 || !IS_ALIGNED(res->start, align)) {
 468			res->flags |= add_res->flags &
 469				 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
 470			if (pci_reassign_resource(dev, idx, add_size, align))
 471				pci_info(dev, "%s %pR: failed to add optional %llx\n",
 472					 res_name, res,
 473					 (unsigned long long) add_size);
 474		}
 475out:
 476		list_del(&add_res->list);
 477		kfree(add_res);
 478	}
 479}
 480
 481/**
 482 * assign_requested_resources_sorted() - Satisfy resource requests
 483 *
 484 * @head:	Head of the list tracking requests for resources
 485 * @fail_head:	Head of the list tracking requests that could not be
 486 *		allocated
 487 * @optional:	Assign also optional resources
 488 *
 489 * Satisfy resource requests of each element in the list.  Add requests that
 490 * could not be satisfied to the failed_list.
 491 */
 492static void assign_requested_resources_sorted(struct list_head *head,
 493					      struct list_head *fail_head,
 494					      bool optional)
 495{
 496	struct pci_dev_resource *dev_res;
 497	struct resource *res;
 498	struct pci_dev *dev;
 499	bool optional_res;
 500	int idx;
 501
 502	list_for_each_entry(dev_res, head, list) {
 503		res = dev_res->res;
 504		dev = dev_res->dev;
 505		idx = pci_resource_num(dev, res);
 506		optional_res = pci_resource_is_optional(dev, idx);
 507
 508		if (!resource_size(res))
 509			continue;
 510
 511		if (!optional && optional_res)
 512			continue;
 513
 514		if (pci_assign_resource(dev, idx)) {
 515			if (fail_head) {
 516				add_to_list(fail_head, dev, res,
 517					    0 /* don't care */,
 518					    0 /* don't care */);
 519			}
 520		}
 521	}
 522}
 523
 524static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
 525{
 526	struct pci_dev_resource *fail_res;
 527	unsigned long mask = 0;
 528
 529	/* Check failed type */
 530	list_for_each_entry(fail_res, fail_head, list)
 531		mask |= fail_res->flags;
 532
 533	/*
 534	 * One pref failed resource will set IORESOURCE_MEM, as we can
 535	 * allocate pref in non-pref range.  Will release all assigned
 536	 * non-pref sibling resources according to that bit.
 537	 */
 538	return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
 539}
 540
 541static bool pci_need_to_release(unsigned long mask, struct resource *res)
 542{
 543	if (res->flags & IORESOURCE_IO)
 544		return !!(mask & IORESOURCE_IO);
 545
 546	/* Check pref at first */
 547	if (res->flags & IORESOURCE_PREFETCH) {
 548		if (mask & IORESOURCE_PREFETCH)
 549			return true;
 550		/* Count pref if its parent is non-pref */
 551		else if ((mask & IORESOURCE_MEM) &&
 552			 !(res->parent->flags & IORESOURCE_PREFETCH))
 553			return true;
 554		else
 555			return false;
 556	}
 557
 558	if (res->flags & IORESOURCE_MEM)
 559		return !!(mask & IORESOURCE_MEM);
 560
 561	return false;	/* Should not get here */
 562}
 563
 564/* Return: @true if assignment of a required resource failed. */
 565static bool pci_required_resource_failed(struct list_head *fail_head,
 566					 unsigned long type)
 567{
 568	struct pci_dev_resource *fail_res;
 569
 570	type &= PCI_RES_TYPE_MASK;
 571
 572	list_for_each_entry(fail_res, fail_head, list) {
 573		int idx = pci_resource_num(fail_res->dev, fail_res->res);
 574
 575		if (type && (fail_res->flags & PCI_RES_TYPE_MASK) != type)
 576			continue;
 577
 578		if (!pci_resource_is_optional(fail_res->dev, idx))
 579			return true;
 580	}
 581	return false;
 582}
 583
 584static void __assign_resources_sorted(struct list_head *head,
 585				      struct list_head *realloc_head,
 586				      struct list_head *fail_head)
 587{
 588	/*
 589	 * Should not assign requested resources at first.  They could be
 590	 * adjacent, so later reassign can not reallocate them one by one in
 591	 * parent resource window.
 592	 *
 593	 * Try to assign required and any optional resources at beginning
 594	 * (add_size included). If all required resources were successfully
 595	 * assigned, get out early. If could not do that, we still try to
 596	 * assign required at first, then try to reassign some optional
 597	 * resources.
 598	 *
 599	 * Separate three resource type checking if we need to release
 600	 * assigned resource after requested + add_size try.
 601	 *
 602	 *	1. If IO port assignment fails, will release assigned IO
 603	 *	   port.
 604	 *	2. If pref MMIO assignment fails, release assigned pref
 605	 *	   MMIO.  If assigned pref MMIO's parent is non-pref MMIO
 606	 *	   and non-pref MMIO assignment fails, will release that
 607	 *	   assigned pref MMIO.
 608	 *	3. If non-pref MMIO assignment fails or pref MMIO
 609	 *	   assignment fails, will release assigned non-pref MMIO.
 610	 */
 611	LIST_HEAD(save_head);
 612	LIST_HEAD(local_fail_head);
 613	LIST_HEAD(dummy_head);
 614	struct pci_dev_resource *save_res;
 615	struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
 616	struct resource *res;
 617	struct pci_dev *dev;
 618	unsigned long fail_type;
 619	resource_size_t add_align, align;
 620
 621	if (!realloc_head)
 622		realloc_head = &dummy_head;
 623
 624	/* Check if optional add_size is there */
 625	if (list_empty(realloc_head))
 626		goto assign;
 627
 628	/* Save original start, end, flags etc at first */
 629	list_for_each_entry(dev_res, head, list) {
 630		if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
 631			free_list(&save_head);
 632			goto assign;
 633		}
 634	}
 635
 636	/* Update res in head list with add_size in realloc_head list */
 637	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
 638		res = dev_res->res;
 639
 640		res->end += get_res_add_size(realloc_head, res);
 641
 642		/*
 643		 * There are two kinds of additional resources in the list:
 644		 * 1. bridge resource  -- IORESOURCE_STARTALIGN
 645		 * 2. SR-IOV resource  -- IORESOURCE_SIZEALIGN
 646		 * Here just fix the additional alignment for bridge
 647		 */
 648		if (!(res->flags & IORESOURCE_STARTALIGN))
 649			continue;
 650
 651		add_align = get_res_add_align(realloc_head, res);
 652
 653		/*
 654		 * The "head" list is sorted by alignment so resources with
 655		 * bigger alignment will be assigned first.  After we
 656		 * change the alignment of a dev_res in "head" list, we
 657		 * need to reorder the list by alignment to make it
 658		 * consistent.
 659		 */
 660		if (add_align > res->start) {
 661			resource_set_range(res, add_align, resource_size(res));
 662
 663			list_for_each_entry(dev_res2, head, list) {
 664				align = pci_resource_alignment(dev_res2->dev,
 665							       dev_res2->res);
 666				if (add_align > align) {
 667					list_move_tail(&dev_res->list,
 668						       &dev_res2->list);
 669					break;
 670				}
 671			}
 672		}
 673
 674	}
 675
 676assign:
 677	assign_requested_resources_sorted(head, &local_fail_head, true);
 678
 679	/* All non-optional resources assigned? */
 680	if (list_empty(&local_fail_head)) {
 681		/* Remove head list from realloc_head list */
 682		list_for_each_entry(dev_res, head, list)
 683			remove_from_list(realloc_head, dev_res->res);
 684		free_list(&save_head);
 685		goto out;
 686	}
 687
 688	/* Without realloc_head and only optional fails, nothing more to do. */
 689	if (!pci_required_resource_failed(&local_fail_head, 0) &&
 690	    list_empty(realloc_head)) {
 691		list_for_each_entry(save_res, &save_head, list) {
 692			struct resource *res = save_res->res;
 693
 694			if (res->parent)
 695				continue;
 696
 697			restore_dev_resource(save_res);
 698		}
 699		free_list(&local_fail_head);
 700		free_list(&save_head);
 701		goto out;
 702	}
 703
 704	/* Check failed type */
 705	fail_type = pci_fail_res_type_mask(&local_fail_head);
 706	/* Remove not need to be released assigned res from head list etc */
 707	list_for_each_entry_safe(dev_res, tmp_res, head, list) {
 708		res = dev_res->res;
 709
 710		if (res->parent && !pci_need_to_release(fail_type, res)) {
 711			/* Remove it from realloc_head list */
 712			remove_from_list(realloc_head, res);
 713			remove_from_list(&save_head, res);
 714			list_del(&dev_res->list);
 715			kfree(dev_res);
 716		}
 717	}
 718
 719	free_list(&local_fail_head);
 720	/* Release assigned resource */
 721	list_for_each_entry(dev_res, head, list) {
 722		res = dev_res->res;
 723		dev = dev_res->dev;
 724
 725		pci_release_resource(dev, pci_resource_num(dev, res));
 726		restore_dev_resource(dev_res);
 727	}
 728	/* Restore start/end/flags from saved list */
 729	list_for_each_entry(save_res, &save_head, list)
 730		restore_dev_resource(save_res);
 731	free_list(&save_head);
 732
 733	/* Satisfy the must-have resource requests */
 734	assign_requested_resources_sorted(head, NULL, false);
 735
 736	/* Try to satisfy any additional optional resource requests */
 737	if (!list_empty(realloc_head))
 738		reassign_resources_sorted(realloc_head, head);
 739
 740out:
 741	/* Reset any failed resource, cannot use fail_head as it can be NULL. */
 742	list_for_each_entry(dev_res, head, list) {
 743		res = dev_res->res;
 744		dev = dev_res->dev;
 745
 746		if (res->parent)
 747			continue;
 748
 749		if (fail_head) {
 750			add_to_list(fail_head, dev, res,
 751				    0 /* don't care */,
 752				    0 /* don't care */);
 753		}
 754
 755		reset_resource(dev, res);
 756	}
 757
 758	free_list(head);
 759}
 760
 761static void pdev_assign_resources_sorted(struct pci_dev *dev,
 762					 struct list_head *add_head,
 763					 struct list_head *fail_head)
 764{
 765	LIST_HEAD(head);
 766
 767	pdev_sort_resources(dev, &head);
 768	__assign_resources_sorted(&head, add_head, fail_head);
 769
 770}
 771
 772static void pbus_assign_resources_sorted(const struct pci_bus *bus,
 773					 struct list_head *realloc_head,
 774					 struct list_head *fail_head)
 775{
 776	struct pci_dev *dev;
 777	LIST_HEAD(head);
 778
 779	list_for_each_entry(dev, &bus->devices, bus_list)
 780		pdev_sort_resources(dev, &head);
 781
 782	__assign_resources_sorted(&head, realloc_head, fail_head);
 783}
 784
 785void pci_setup_cardbus(struct pci_bus *bus)
 786{
 787	struct pci_dev *bridge = bus->self;
 788	struct resource *res;
 789	struct pci_bus_region region;
 790
 791	pci_info(bridge, "CardBus bridge to %pR\n",
 792		 &bus->busn_res);
 793
 794	res = bus->resource[0];
 795	pcibios_resource_to_bus(bridge->bus, &region, res);
 796	if (res->parent && res->flags & IORESOURCE_IO) {
 797		/*
 798		 * The IO resource is allocated a range twice as large as it
 799		 * would normally need.  This allows us to set both IO regs.
 800		 */
 801		pci_info(bridge, "  bridge window %pR\n", res);
 802		pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
 803					region.start);
 804		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
 805					region.end);
 806	}
 807
 808	res = bus->resource[1];
 809	pcibios_resource_to_bus(bridge->bus, &region, res);
 810	if (res->parent && res->flags & IORESOURCE_IO) {
 811		pci_info(bridge, "  bridge window %pR\n", res);
 812		pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
 813					region.start);
 814		pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
 815					region.end);
 816	}
 817
 818	res = bus->resource[2];
 819	pcibios_resource_to_bus(bridge->bus, &region, res);
 820	if (res->parent && res->flags & IORESOURCE_MEM) {
 821		pci_info(bridge, "  bridge window %pR\n", res);
 822		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
 823					region.start);
 824		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
 825					region.end);
 826	}
 827
 828	res = bus->resource[3];
 829	pcibios_resource_to_bus(bridge->bus, &region, res);
 830	if (res->parent && res->flags & IORESOURCE_MEM) {
 831		pci_info(bridge, "  bridge window %pR\n", res);
 832		pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
 833					region.start);
 834		pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
 835					region.end);
 836	}
 837}
 838EXPORT_SYMBOL(pci_setup_cardbus);
 839
 840/*
 841 * Initialize bridges with base/limit values we have collected.  PCI-to-PCI
 842 * Bridge Architecture Specification rev. 1.1 (1998) requires that if there
 843 * are no I/O ports or memory behind the bridge, the corresponding range
 844 * must be turned off by writing base value greater than limit to the
 845 * bridge's base/limit registers.
 846 *
 847 * Note: care must be taken when updating I/O base/limit registers of
 848 * bridges which support 32-bit I/O.  This update requires two config space
 849 * writes, so it's quite possible that an I/O window of the bridge will
 850 * have some undesirable address (e.g. 0) after the first write.  Ditto
 851 * 64-bit prefetchable MMIO.
 852 */
 853static void pci_setup_bridge_io(struct pci_dev *bridge)
 854{
 855	struct resource *res;
 856	const char *res_name;
 857	struct pci_bus_region region;
 858	unsigned long io_mask;
 859	u8 io_base_lo, io_limit_lo;
 860	u16 l;
 861	u32 io_upper16;
 862
 863	io_mask = PCI_IO_RANGE_MASK;
 864	if (bridge->io_window_1k)
 865		io_mask = PCI_IO_1K_RANGE_MASK;
 866
 867	/* Set up the top and bottom of the PCI I/O segment for this bus */
 868	res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
 869	res_name = pci_resource_name(bridge, PCI_BRIDGE_IO_WINDOW);
 870	pcibios_resource_to_bus(bridge->bus, &region, res);
 871	if (res->parent && res->flags & IORESOURCE_IO) {
 872		pci_read_config_word(bridge, PCI_IO_BASE, &l);
 873		io_base_lo = (region.start >> 8) & io_mask;
 874		io_limit_lo = (region.end >> 8) & io_mask;
 875		l = ((u16) io_limit_lo << 8) | io_base_lo;
 876		/* Set up upper 16 bits of I/O base/limit */
 877		io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
 878		pci_info(bridge, "  %s %pR\n", res_name, res);
 879	} else {
 880		/* Clear upper 16 bits of I/O base/limit */
 881		io_upper16 = 0;
 882		l = 0x00f0;
 883	}
 884	/* Temporarily disable the I/O range before updating PCI_IO_BASE */
 885	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
 886	/* Update lower 16 bits of I/O base/limit */
 887	pci_write_config_word(bridge, PCI_IO_BASE, l);
 888	/* Update upper 16 bits of I/O base/limit */
 889	pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
 890}
 891
 892static void pci_setup_bridge_mmio(struct pci_dev *bridge)
 893{
 894	struct resource *res;
 895	const char *res_name;
 896	struct pci_bus_region region;
 897	u32 l;
 898
 899	/* Set up the top and bottom of the PCI Memory segment for this bus */
 900	res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
 901	res_name = pci_resource_name(bridge, PCI_BRIDGE_MEM_WINDOW);
 902	pcibios_resource_to_bus(bridge->bus, &region, res);
 903	if (res->parent && res->flags & IORESOURCE_MEM) {
 904		l = (region.start >> 16) & 0xfff0;
 905		l |= region.end & 0xfff00000;
 906		pci_info(bridge, "  %s %pR\n", res_name, res);
 907	} else {
 908		l = 0x0000fff0;
 909	}
 910	pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
 911}
 912
 913static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
 914{
 915	struct resource *res;
 916	const char *res_name;
 917	struct pci_bus_region region;
 918	u32 l, bu, lu;
 919
 920	/*
 921	 * Clear out the upper 32 bits of PREF limit.  If
 922	 * PCI_PREF_BASE_UPPER32 was non-zero, this temporarily disables
 923	 * PREF range, which is ok.
 924	 */
 925	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
 926
 927	/* Set up PREF base/limit */
 928	bu = lu = 0;
 929	res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
 930	res_name = pci_resource_name(bridge, PCI_BRIDGE_PREF_MEM_WINDOW);
 931	pcibios_resource_to_bus(bridge->bus, &region, res);
 932	if (res->parent && res->flags & IORESOURCE_PREFETCH) {
 933		l = (region.start >> 16) & 0xfff0;
 934		l |= region.end & 0xfff00000;
 935		if (res->flags & IORESOURCE_MEM_64) {
 936			bu = upper_32_bits(region.start);
 937			lu = upper_32_bits(region.end);
 938		}
 939		pci_info(bridge, "  %s %pR\n", res_name, res);
 940	} else {
 941		l = 0x0000fff0;
 942	}
 943	pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
 944
 945	/* Set the upper 32 bits of PREF base & limit */
 946	pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
 947	pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
 948}
 949
 950static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
 951{
 952	struct pci_dev *bridge = bus->self;
 953
 954	pci_info(bridge, "PCI bridge to %pR\n", &bus->busn_res);
 955
 956	if (type & IORESOURCE_IO)
 957		pci_setup_bridge_io(bridge);
 958
 959	if (type & IORESOURCE_MEM)
 960		pci_setup_bridge_mmio(bridge);
 961
 962	if (type & IORESOURCE_PREFETCH)
 963		pci_setup_bridge_mmio_pref(bridge);
 964
 965	pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
 966}
 967
 968static void pci_setup_one_bridge_window(struct pci_dev *bridge, int resno)
 969{
 970	switch (resno) {
 971	case PCI_BRIDGE_IO_WINDOW:
 972		pci_setup_bridge_io(bridge);
 973		break;
 974	case PCI_BRIDGE_MEM_WINDOW:
 975		pci_setup_bridge_mmio(bridge);
 976		break;
 977	case PCI_BRIDGE_PREF_MEM_WINDOW:
 978		pci_setup_bridge_mmio_pref(bridge);
 979		break;
 980	default:
 981		return;
 982	}
 983}
 984
 985void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
 986{
 987}
 988
 989static void pci_setup_bridge(struct pci_bus *bus)
 990{
 991	unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
 992				  IORESOURCE_PREFETCH;
 993
 994	pcibios_setup_bridge(bus, type);
 995	__pci_setup_bridge(bus, type);
 996}
 997
 998
 999int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
1000{
1001	int ret = -EINVAL;
1002
1003	if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
1004		return 0;
1005
1006	if (pci_claim_resource(bridge, i) == 0)
1007		return 0;	/* Claimed the window */
1008
1009	if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1010		return 0;
1011
1012	if (i > PCI_BRIDGE_PREF_MEM_WINDOW)
1013		return -EINVAL;
1014
1015	/* Try to clip the resource and claim the smaller window */
1016	if (pci_bus_clip_resource(bridge, i))
1017		ret = pci_claim_resource(bridge, i);
1018
1019	pci_setup_one_bridge_window(bridge, i);
1020
1021	return ret;
1022}
1023
1024/*
1025 * Check whether the bridge supports optional I/O and prefetchable memory
1026 * ranges.  If not, the respective base/limit registers must be read-only
1027 * and read as 0.
1028 */
1029static void pci_bridge_check_ranges(struct pci_bus *bus)
1030{
1031	struct pci_dev *bridge = bus->self;
1032	struct resource *b_res;
1033
1034	b_res = &bridge->resource[PCI_BRIDGE_MEM_WINDOW];
1035	b_res->flags |= IORESOURCE_MEM;
1036
1037	if (bridge->io_window) {
1038		b_res = &bridge->resource[PCI_BRIDGE_IO_WINDOW];
1039		b_res->flags |= IORESOURCE_IO;
1040	}
1041
1042	if (bridge->pref_window) {
1043		b_res = &bridge->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1044		b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
1045		if (bridge->pref_64_window) {
1046			b_res->flags |= IORESOURCE_MEM_64 |
1047					PCI_PREF_RANGE_TYPE_64;
1048		}
1049	}
1050}
1051
1052static resource_size_t calculate_iosize(resource_size_t size,
1053					resource_size_t min_size,
1054					resource_size_t size1,
1055					resource_size_t add_size,
1056					resource_size_t children_add_size,
1057					resource_size_t old_size,
1058					resource_size_t align)
1059{
1060	if (size < min_size)
1061		size = min_size;
1062	if (old_size == 1)
1063		old_size = 0;
1064	/*
1065	 * To be fixed in 2.5: we should have sort of HAVE_ISA flag in the
1066	 * struct pci_bus.
1067	 */
1068#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
1069	size = (size & 0xff) + ((size & ~0xffUL) << 2);
1070#endif
1071	size = size + size1;
1072
1073	size = max(size, add_size) + children_add_size;
1074	return ALIGN(max(size, old_size), align);
1075}
1076
1077static resource_size_t calculate_memsize(resource_size_t size,
1078					 resource_size_t min_size,
1079					 resource_size_t add_size,
1080					 resource_size_t children_add_size,
1081					 resource_size_t align)
1082{
1083	if (size < min_size)
1084		size = min_size;
1085
1086	size = max(size, add_size) + children_add_size;
1087	return ALIGN(size, align);
1088}
1089
1090resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
1091						unsigned long type)
1092{
1093	return 1;
1094}
1095
1096#define PCI_P2P_DEFAULT_MEM_ALIGN	SZ_1M
1097#define PCI_P2P_DEFAULT_IO_ALIGN	SZ_4K
1098#define PCI_P2P_DEFAULT_IO_ALIGN_1K	SZ_1K
1099
1100static resource_size_t window_alignment(struct pci_bus *bus, unsigned long type)
1101{
1102	resource_size_t align = 1, arch_align;
1103
1104	if (type & IORESOURCE_MEM)
1105		align = PCI_P2P_DEFAULT_MEM_ALIGN;
1106	else if (type & IORESOURCE_IO) {
1107		/*
1108		 * Per spec, I/O windows are 4K-aligned, but some bridges have
1109		 * an extension to support 1K alignment.
1110		 */
1111		if (bus->self && bus->self->io_window_1k)
1112			align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
1113		else
1114			align = PCI_P2P_DEFAULT_IO_ALIGN;
1115	}
1116
1117	arch_align = pcibios_window_alignment(bus, type);
1118	return max(align, arch_align);
1119}
1120
1121/**
1122 * pbus_size_io() - Size the I/O window of a given bus
1123 *
1124 * @bus:		The bus
1125 * @min_size:		The minimum I/O window that must be allocated
1126 * @add_size:		Additional optional I/O window
1127 * @realloc_head:	Track the additional I/O window on this list
1128 *
1129 * Sizing the I/O windows of the PCI-PCI bridge is trivial, since these
1130 * windows have 1K or 4K granularity and the I/O ranges of non-bridge PCI
1131 * devices are limited to 256 bytes.  We must be careful with the ISA
1132 * aliasing though.
1133 */
1134static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
1135			 resource_size_t add_size,
1136			 struct list_head *realloc_head)
1137{
1138	struct pci_dev *dev;
1139	struct resource *b_res = pbus_select_window_for_type(bus, IORESOURCE_IO);
1140	resource_size_t size = 0, size0 = 0, size1 = 0;
1141	resource_size_t children_add_size = 0;
1142	resource_size_t min_align, align;
1143
1144	if (!b_res)
1145		return;
1146
1147	/* If resource is already assigned, nothing more to do */
1148	if (b_res->parent)
1149		return;
1150
1151	min_align = window_alignment(bus, IORESOURCE_IO);
1152	list_for_each_entry(dev, &bus->devices, bus_list) {
1153		struct resource *r;
1154
1155		pci_dev_for_each_resource(dev, r) {
1156			unsigned long r_size;
1157
1158			if (r->parent || !(r->flags & IORESOURCE_IO))
1159				continue;
1160
1161			if (!pdev_resource_assignable(dev, r))
1162				continue;
1163
1164			r_size = resource_size(r);
1165			if (r_size < SZ_1K)
1166				/* Might be re-aligned for ISA */
1167				size += r_size;
1168			else
1169				size1 += r_size;
1170
1171			align = pci_resource_alignment(dev, r);
1172			if (align > min_align)
1173				min_align = align;
1174
1175			if (realloc_head)
1176				children_add_size += get_res_add_size(realloc_head, r);
1177		}
1178	}
1179
1180	size0 = calculate_iosize(size, min_size, size1, 0, 0,
1181			resource_size(b_res), min_align);
1182
1183	if (size0)
1184		b_res->flags &= ~IORESOURCE_DISABLED;
1185
1186	size1 = size0;
1187	if (realloc_head && (add_size > 0 || children_add_size > 0)) {
1188		size1 = calculate_iosize(size, min_size, size1, add_size,
1189					 children_add_size, resource_size(b_res),
1190					 min_align);
1191	}
1192
1193	if (!size0 && !size1) {
1194		if (bus->self && (b_res->start || b_res->end))
1195			pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1196				 b_res, &bus->busn_res);
1197		b_res->flags |= IORESOURCE_DISABLED;
1198		return;
1199	}
1200
1201	resource_set_range(b_res, min_align, size0);
1202	b_res->flags |= IORESOURCE_STARTALIGN;
1203	if (bus->self && size1 > size0 && realloc_head) {
1204		b_res->flags &= ~IORESOURCE_DISABLED;
1205		add_to_list(realloc_head, bus->self, b_res, size1-size0,
1206			    min_align);
1207		pci_info(bus->self, "bridge window %pR to %pR add_size %llx\n",
1208			 b_res, &bus->busn_res,
1209			 (unsigned long long) size1 - size0);
1210	}
1211}
1212
1213static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
1214						  int max_order)
1215{
1216	resource_size_t align = 0;
1217	resource_size_t min_align = 0;
1218	int order;
1219
1220	for (order = 0; order <= max_order; order++) {
1221		resource_size_t align1 = 1;
1222
1223		align1 <<= order + __ffs(SZ_1M);
1224
1225		if (!align)
1226			min_align = align1;
1227		else if (ALIGN(align + min_align, min_align) < align1)
1228			min_align = align1 >> 1;
1229		align += aligns[order];
1230	}
1231
1232	return min_align;
1233}
1234
1235/*
1236 * Calculate bridge window head alignment that leaves no gaps in between
1237 * resources.
1238 */
1239static resource_size_t calculate_head_align(resource_size_t *aligns,
1240					    int max_order)
1241{
1242	resource_size_t head_align = 1;
1243	resource_size_t remainder = 0;
1244	int order;
1245
1246	/* Take the largest alignment as the starting point. */
1247	head_align <<= max_order + __ffs(SZ_1M);
1248
1249	for (order = max_order - 1; order >= 0; order--) {
1250		resource_size_t align1 = 1;
1251
1252		align1 <<= order + __ffs(SZ_1M);
1253
1254		/*
1255		 * Account smaller resources with alignment < max_order that
1256		 * could be used to fill head room if alignment less than
1257		 * max_order is used.
1258		 */
1259		remainder += aligns[order];
1260
1261		/*
1262		 * Test if head fill is enough to satisfy the alignment of
1263		 * the larger resources after reducing the alignment.
1264		 */
1265		while ((head_align > align1) && (remainder >= head_align / 2)) {
1266			head_align /= 2;
1267			remainder -= head_align;
1268		}
1269	}
1270
1271	return head_align;
1272}
1273
1274/**
1275 * pbus_size_mem() - Size the memory window of a given bus
1276 *
1277 * @bus:		The bus
1278 * @type:		The type of bridge resource
1279 * @min_size:		The minimum memory window that must be allocated
1280 * @add_size:		Additional optional memory window
1281 * @realloc_head:	Track the additional memory window on this list
1282 *
1283 * Calculate the size of the bus resource for @type and minimal alignment
1284 * which guarantees that all child resources fit in this size.
1285 *
1286 * Set the bus resource start/end to indicate the required size if there an
1287 * available unassigned bus resource of the desired @type.
1288 *
1289 * Add optional resource requests to the @realloc_head list if it is
1290 * supplied.
1291 */
1292static void pbus_size_mem(struct pci_bus *bus, unsigned long type,
1293			 resource_size_t min_size,
1294			 resource_size_t add_size,
1295			 struct list_head *realloc_head)
1296{
1297	struct pci_dev *dev;
1298	resource_size_t min_align, win_align, align, size, size0, size1 = 0;
1299	resource_size_t aligns[28] = {}; /* Alignments from 1MB to 128TB */
1300	int order, max_order;
1301	struct resource *b_res = pbus_select_window_for_type(bus, type);
1302	resource_size_t children_add_size = 0;
1303	resource_size_t children_add_align = 0;
1304	resource_size_t add_align = 0;
1305
1306	if (!b_res)
1307		return;
1308
1309	/* If resource is already assigned, nothing more to do */
1310	if (b_res->parent)
1311		return;
1312
1313	max_order = 0;
1314	size = 0;
1315
1316	list_for_each_entry(dev, &bus->devices, bus_list) {
1317		struct resource *r;
1318		int i;
1319
1320		pci_dev_for_each_resource(dev, r, i) {
1321			const char *r_name = pci_resource_name(dev, i);
1322			resource_size_t r_size;
1323
1324			if (!pdev_resources_assignable(dev) ||
1325			    !pdev_resource_should_fit(dev, r))
1326				continue;
1327			if (b_res != pbus_select_window(bus, r))
1328				continue;
1329
1330			r_size = resource_size(r);
1331
1332			/* Put SRIOV requested res to the optional list */
1333			if (realloc_head && pci_resource_is_optional(dev, i)) {
1334				add_align = max(pci_resource_alignment(dev, r), add_align);
1335				add_to_list(realloc_head, dev, r, 0, 0 /* Don't care */);
1336				children_add_size += r_size;
1337				continue;
1338			}
1339
1340			/*
1341			 * aligns[0] is for 1MB (since bridge memory
1342			 * windows are always at least 1MB aligned), so
1343			 * keep "order" from being negative for smaller
1344			 * resources.
1345			 */
1346			align = pci_resource_alignment(dev, r);
1347			order = __ffs(align) - __ffs(SZ_1M);
1348			if (order < 0)
1349				order = 0;
1350			if (order >= ARRAY_SIZE(aligns)) {
1351				pci_warn(dev, "%s %pR: disabling; bad alignment %#llx\n",
1352					 r_name, r, (unsigned long long) align);
1353				r->flags = 0;
1354				continue;
1355			}
1356			size += max(r_size, align);
1357
1358			aligns[order] += align;
1359			if (order > max_order)
1360				max_order = order;
1361
1362			if (realloc_head) {
1363				children_add_size += get_res_add_size(realloc_head, r);
1364				children_add_align = get_res_add_align(realloc_head, r);
1365				add_align = max(add_align, children_add_align);
1366			}
1367		}
1368	}
1369
1370	win_align = window_alignment(bus, b_res->flags);
1371	min_align = calculate_head_align(aligns, max_order);
1372	min_align = max(min_align, win_align);
1373	size0 = calculate_memsize(size, min_size, 0, 0, win_align);
1374
1375	if (size0) {
1376		resource_set_range(b_res, min_align, size0);
1377		b_res->flags &= ~IORESOURCE_DISABLED;
1378	}
1379
1380	if (realloc_head && (add_size > 0 || children_add_size > 0)) {
1381		add_align = max(min_align, add_align);
1382		size1 = calculate_memsize(size, min_size, add_size, children_add_size,
1383					  win_align);
1384	}
1385
1386	if (!size0 && !size1) {
1387		if (bus->self && (b_res->start || b_res->end))
1388			pci_info(bus->self, "disabling bridge window %pR to %pR (unused)\n",
1389				 b_res, &bus->busn_res);
1390		b_res->flags |= IORESOURCE_DISABLED;
1391		return;
1392	}
1393
1394	resource_set_range(b_res, min_align, size0);
1395	b_res->flags |= IORESOURCE_STARTALIGN;
1396	if (bus->self && realloc_head && (size1 > size0 || add_align > min_align)) {
1397		b_res->flags &= ~IORESOURCE_DISABLED;
1398		add_size = size1 > size0 ? size1 - size0 : 0;
1399		add_to_list(realloc_head, bus->self, b_res, add_size, add_align);
1400		pci_info(bus->self, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1401			   b_res, &bus->busn_res,
1402			   (unsigned long long) add_size,
1403			   (unsigned long long) add_align);
1404	}
1405}
1406
1407unsigned long pci_cardbus_resource_alignment(struct resource *res)
1408{
1409	if (res->flags & IORESOURCE_IO)
1410		return pci_cardbus_io_size;
1411	if (res->flags & IORESOURCE_MEM)
1412		return pci_cardbus_mem_size;
1413	return 0;
1414}
1415
1416static void pci_bus_size_cardbus(struct pci_bus *bus,
1417				 struct list_head *realloc_head)
1418{
1419	struct pci_dev *bridge = bus->self;
1420	struct resource *b_res;
1421	resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1422	u16 ctrl;
1423
1424	b_res = &bridge->resource[PCI_CB_BRIDGE_IO_0_WINDOW];
1425	if (b_res->parent)
1426		goto handle_b_res_1;
1427	/*
1428	 * Reserve some resources for CardBus.  We reserve a fixed amount
1429	 * of bus space for CardBus bridges.
1430	 */
1431	resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size);
1432	b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1433	if (realloc_head) {
1434		b_res->end -= pci_cardbus_io_size;
1435		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1436			    pci_cardbus_io_size);
1437	}
1438
1439handle_b_res_1:
1440	b_res = &bridge->resource[PCI_CB_BRIDGE_IO_1_WINDOW];
1441	if (b_res->parent)
1442		goto handle_b_res_2;
1443	resource_set_range(b_res, pci_cardbus_io_size, pci_cardbus_io_size);
1444	b_res->flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1445	if (realloc_head) {
1446		b_res->end -= pci_cardbus_io_size;
1447		add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1448			    pci_cardbus_io_size);
1449	}
1450
1451handle_b_res_2:
1452	/* MEM1 must not be pref MMIO */
1453	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1454	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1455		ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1456		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1457		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1458	}
1459
1460	/* Check whether prefetchable memory is supported by this bridge. */
1461	pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1462	if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1463		ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1464		pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1465		pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1466	}
1467
1468	b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_0_WINDOW];
1469	if (b_res->parent)
1470		goto handle_b_res_3;
1471	/*
1472	 * If we have prefetchable memory support, allocate two regions.
1473	 * Otherwise, allocate one region of twice the size.
1474	 */
1475	if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1476		resource_set_range(b_res, pci_cardbus_mem_size,
1477				   pci_cardbus_mem_size);
1478		b_res->flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1479				    IORESOURCE_STARTALIGN;
1480		if (realloc_head) {
1481			b_res->end -= pci_cardbus_mem_size;
1482			add_to_list(realloc_head, bridge, b_res,
1483				    pci_cardbus_mem_size, pci_cardbus_mem_size);
1484		}
1485
1486		/* Reduce that to half */
1487		b_res_3_size = pci_cardbus_mem_size;
1488	}
1489
1490handle_b_res_3:
1491	b_res = &bridge->resource[PCI_CB_BRIDGE_MEM_1_WINDOW];
1492	if (b_res->parent)
1493		goto handle_done;
1494	resource_set_range(b_res, pci_cardbus_mem_size, b_res_3_size);
1495	b_res->flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1496	if (realloc_head) {
1497		b_res->end -= b_res_3_size;
1498		add_to_list(realloc_head, bridge, b_res, b_res_3_size,
1499			    pci_cardbus_mem_size);
1500	}
1501
1502handle_done:
1503	;
1504}
1505
1506void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1507{
1508	struct pci_dev *dev;
1509	resource_size_t additional_io_size = 0, additional_mmio_size = 0,
1510			additional_mmio_pref_size = 0;
1511	struct resource *pref;
1512	struct pci_host_bridge *host;
1513	int hdr_type;
1514
1515	list_for_each_entry(dev, &bus->devices, bus_list) {
1516		struct pci_bus *b = dev->subordinate;
1517		if (!b)
1518			continue;
1519
1520		switch (dev->hdr_type) {
1521		case PCI_HEADER_TYPE_CARDBUS:
1522			pci_bus_size_cardbus(b, realloc_head);
1523			break;
1524
1525		case PCI_HEADER_TYPE_BRIDGE:
1526		default:
1527			__pci_bus_size_bridges(b, realloc_head);
1528			break;
1529		}
1530	}
1531
1532	/* The root bus? */
1533	if (pci_is_root_bus(bus)) {
1534		host = to_pci_host_bridge(bus->bridge);
1535		if (!host->size_windows)
1536			return;
1537		pci_bus_for_each_resource(bus, pref)
1538			if (pref && (pref->flags & IORESOURCE_PREFETCH))
1539				break;
1540		hdr_type = -1;	/* Intentionally invalid - not a PCI device. */
1541	} else {
1542		pref = &bus->self->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
1543		hdr_type = bus->self->hdr_type;
1544	}
1545
1546	switch (hdr_type) {
1547	case PCI_HEADER_TYPE_CARDBUS:
1548		/* Don't size CardBuses yet */
1549		break;
1550
1551	case PCI_HEADER_TYPE_BRIDGE:
1552		pci_bridge_check_ranges(bus);
1553		if (bus->self->is_hotplug_bridge) {
1554			additional_io_size  = pci_hotplug_io_size;
1555			additional_mmio_size = pci_hotplug_mmio_size;
1556			additional_mmio_pref_size = pci_hotplug_mmio_pref_size;
1557		}
1558		fallthrough;
1559	default:
1560		pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1561			     additional_io_size, realloc_head);
1562
1563		if (pref && (pref->flags & IORESOURCE_PREFETCH)) {
1564			pbus_size_mem(bus,
1565				      IORESOURCE_MEM | IORESOURCE_PREFETCH |
1566				      (pref->flags & IORESOURCE_MEM_64),
1567				      realloc_head ? 0 : additional_mmio_pref_size,
1568				      additional_mmio_pref_size, realloc_head);
1569		}
1570
1571		pbus_size_mem(bus, IORESOURCE_MEM,
1572			      realloc_head ? 0 : additional_mmio_size,
1573			      additional_mmio_size, realloc_head);
1574		break;
1575	}
1576}
1577
1578void pci_bus_size_bridges(struct pci_bus *bus)
1579{
1580	__pci_bus_size_bridges(bus, NULL);
1581}
1582EXPORT_SYMBOL(pci_bus_size_bridges);
1583
1584static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1585{
1586	struct resource *parent_r;
1587	unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1588			     IORESOURCE_PREFETCH;
1589
1590	pci_bus_for_each_resource(b, parent_r) {
1591		if (!parent_r)
1592			continue;
1593
1594		if ((r->flags & mask) == (parent_r->flags & mask) &&
1595		    resource_contains(parent_r, r))
1596			request_resource(parent_r, r);
1597	}
1598}
1599
1600/*
1601 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they are
1602 * skipped by pbus_assign_resources_sorted().
1603 */
1604static void pdev_assign_fixed_resources(struct pci_dev *dev)
1605{
1606	struct resource *r;
1607
1608	pci_dev_for_each_resource(dev, r) {
1609		struct pci_bus *b;
1610
1611		if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1612		    !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1613			continue;
1614
1615		b = dev->bus;
1616		while (b && !r->parent) {
1617			assign_fixed_resource_on_bus(b, r);
1618			b = b->parent;
1619		}
1620	}
1621}
1622
1623void __pci_bus_assign_resources(const struct pci_bus *bus,
1624				struct list_head *realloc_head,
1625				struct list_head *fail_head)
1626{
1627	struct pci_bus *b;
1628	struct pci_dev *dev;
1629
1630	pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1631
1632	list_for_each_entry(dev, &bus->devices, bus_list) {
1633		pdev_assign_fixed_resources(dev);
1634
1635		b = dev->subordinate;
1636		if (!b)
1637			continue;
1638
1639		__pci_bus_assign_resources(b, realloc_head, fail_head);
1640
1641		switch (dev->hdr_type) {
1642		case PCI_HEADER_TYPE_BRIDGE:
1643			if (!pci_is_enabled(dev))
1644				pci_setup_bridge(b);
1645			break;
1646
1647		case PCI_HEADER_TYPE_CARDBUS:
1648			pci_setup_cardbus(b);
1649			break;
1650
1651		default:
1652			pci_info(dev, "not setting up bridge for bus %04x:%02x\n",
1653				 pci_domain_nr(b), b->number);
1654			break;
1655		}
1656	}
1657}
1658
1659void pci_bus_assign_resources(const struct pci_bus *bus)
1660{
1661	__pci_bus_assign_resources(bus, NULL, NULL);
1662}
1663EXPORT_SYMBOL(pci_bus_assign_resources);
1664
1665static void pci_claim_device_resources(struct pci_dev *dev)
1666{
1667	int i;
1668
1669	for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1670		struct resource *r = &dev->resource[i];
1671
1672		if (!r->flags || r->parent)
1673			continue;
1674
1675		pci_claim_resource(dev, i);
1676	}
1677}
1678
1679static void pci_claim_bridge_resources(struct pci_dev *dev)
1680{
1681	int i;
1682
1683	for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1684		struct resource *r = &dev->resource[i];
1685
1686		if (!r->flags || r->parent)
1687			continue;
1688		if (r->flags & IORESOURCE_DISABLED)
1689			continue;
1690
1691		pci_claim_bridge_resource(dev, i);
1692	}
1693}
1694
1695static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1696{
1697	struct pci_dev *dev;
1698	struct pci_bus *child;
1699
1700	list_for_each_entry(dev, &b->devices, bus_list) {
1701		pci_claim_device_resources(dev);
1702
1703		child = dev->subordinate;
1704		if (child)
1705			pci_bus_allocate_dev_resources(child);
1706	}
1707}
1708
1709static void pci_bus_allocate_resources(struct pci_bus *b)
1710{
1711	struct pci_bus *child;
1712
1713	/*
1714	 * Carry out a depth-first search on the PCI bus tree to allocate
1715	 * bridge apertures.  Read the programmed bridge bases and
1716	 * recursively claim the respective bridge resources.
1717	 */
1718	if (b->self) {
1719		pci_read_bridge_bases(b);
1720		pci_claim_bridge_resources(b->self);
1721	}
1722
1723	list_for_each_entry(child, &b->children, node)
1724		pci_bus_allocate_resources(child);
1725}
1726
1727void pci_bus_claim_resources(struct pci_bus *b)
1728{
1729	pci_bus_allocate_resources(b);
1730	pci_bus_allocate_dev_resources(b);
1731}
1732EXPORT_SYMBOL(pci_bus_claim_resources);
1733
1734static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1735					  struct list_head *add_head,
1736					  struct list_head *fail_head)
1737{
1738	struct pci_bus *b;
1739
1740	pdev_assign_resources_sorted((struct pci_dev *)bridge,
1741					 add_head, fail_head);
1742
1743	b = bridge->subordinate;
1744	if (!b)
1745		return;
1746
1747	__pci_bus_assign_resources(b, add_head, fail_head);
1748
1749	switch (bridge->class >> 8) {
1750	case PCI_CLASS_BRIDGE_PCI:
1751		pci_setup_bridge(b);
1752		break;
1753
1754	case PCI_CLASS_BRIDGE_CARDBUS:
1755		pci_setup_cardbus(b);
1756		break;
1757
1758	default:
1759		pci_info(bridge, "not setting up bridge for bus %04x:%02x\n",
1760			 pci_domain_nr(b), b->number);
1761		break;
1762	}
1763}
1764
1765static void pci_bridge_release_resources(struct pci_bus *bus,
1766					 struct resource *b_win)
1767{
1768	struct pci_dev *dev = bus->self;
1769	int idx, ret;
1770
1771	if (!b_win->parent)
1772		return;
1773
1774	idx = pci_resource_num(dev, b_win);
1775
1776	/* If there are children, release them all */
1777	release_child_resources(b_win);
1778
1779	ret = pci_release_resource(dev, idx);
1780	if (ret)
1781		return;
1782
1783	pci_setup_one_bridge_window(dev, idx);
1784}
1785
1786enum release_type {
1787	leaf_only,
1788	whole_subtree,
1789};
1790
1791/*
1792 * Try to release PCI bridge resources from leaf bridge, so we can allocate
1793 * a larger window later.
1794 */
1795static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1796					     struct resource *b_win,
1797					     enum release_type rel_type)
1798{
1799	struct pci_dev *dev;
1800	bool is_leaf_bridge = true;
1801
1802	list_for_each_entry(dev, &bus->devices, bus_list) {
1803		struct pci_bus *b = dev->subordinate;
1804		struct resource *res;
1805
1806		if (!b)
1807			continue;
1808
1809		is_leaf_bridge = false;
1810
1811		if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1812			continue;
1813
1814		if (rel_type != whole_subtree)
1815			continue;
1816
1817		pci_bus_for_each_resource(b, res) {
1818			if (res->parent != b_win)
1819				continue;
1820
1821			pci_bus_release_bridge_resources(b, res, rel_type);
1822		}
1823	}
1824
1825	if (pci_is_root_bus(bus))
1826		return;
1827
1828	if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1829		return;
1830
1831	if ((rel_type == whole_subtree) || is_leaf_bridge)
1832		pci_bridge_release_resources(bus, b_win);
1833}
1834
1835static void pci_bus_dump_res(struct pci_bus *bus)
1836{
1837	struct resource *res;
1838	int i;
1839
1840	pci_bus_for_each_resource(bus, res, i) {
1841		if (!res || !res->end || !res->flags)
1842			continue;
1843
1844		dev_info(&bus->dev, "resource %d %pR\n", i, res);
1845	}
1846}
1847
1848static void pci_bus_dump_resources(struct pci_bus *bus)
1849{
1850	struct pci_bus *b;
1851	struct pci_dev *dev;
1852
1853
1854	pci_bus_dump_res(bus);
1855
1856	list_for_each_entry(dev, &bus->devices, bus_list) {
1857		b = dev->subordinate;
1858		if (!b)
1859			continue;
1860
1861		pci_bus_dump_resources(b);
1862	}
1863}
1864
1865static int pci_bus_get_depth(struct pci_bus *bus)
1866{
1867	int depth = 0;
1868	struct pci_bus *child_bus;
1869
1870	list_for_each_entry(child_bus, &bus->children, node) {
1871		int ret;
1872
1873		ret = pci_bus_get_depth(child_bus);
1874		if (ret + 1 > depth)
1875			depth = ret + 1;
1876	}
1877
1878	return depth;
1879}
1880
1881/*
1882 * -1: undefined, will auto detect later
1883 *  0: disabled by user
1884 *  1: disabled by auto detect
1885 *  2: enabled by user
1886 *  3: enabled by auto detect
1887 */
1888enum enable_type {
1889	undefined = -1,
1890	user_disabled,
1891	auto_disabled,
1892	user_enabled,
1893	auto_enabled,
1894};
1895
1896static enum enable_type pci_realloc_enable = undefined;
1897void __init pci_realloc_get_opt(char *str)
1898{
1899	if (!strncmp(str, "off", 3))
1900		pci_realloc_enable = user_disabled;
1901	else if (!strncmp(str, "on", 2))
1902		pci_realloc_enable = user_enabled;
1903}
1904static bool pci_realloc_enabled(enum enable_type enable)
1905{
1906	return enable >= user_enabled;
1907}
1908
1909#if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1910static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1911{
1912	int i;
1913	bool *unassigned = data;
1914
1915	for (i = 0; i < PCI_SRIOV_NUM_BARS; i++) {
1916		int idx = pci_resource_num_from_vf_bar(i);
1917		struct resource *r = &dev->resource[idx];
1918		struct pci_bus_region region;
1919
1920		/* Not assigned or rejected by kernel? */
1921		if (!r->flags)
1922			continue;
1923
1924		pcibios_resource_to_bus(dev->bus, &region, r);
1925		if (!region.start) {
1926			*unassigned = true;
1927			return 1; /* Return early from pci_walk_bus() */
1928		}
1929	}
1930
1931	return 0;
1932}
1933
1934static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1935					   enum enable_type enable_local)
1936{
1937	bool unassigned = false;
1938	struct pci_host_bridge *host;
1939
1940	if (enable_local != undefined)
1941		return enable_local;
1942
1943	host = pci_find_host_bridge(bus);
1944	if (host->preserve_config)
1945		return auto_disabled;
1946
1947	pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1948	if (unassigned)
1949		return auto_enabled;
1950
1951	return enable_local;
1952}
1953#else
1954static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1955					   enum enable_type enable_local)
1956{
1957	return enable_local;
1958}
1959#endif
1960
1961static void adjust_bridge_window(struct pci_dev *bridge, struct resource *res,
1962				 struct list_head *add_list,
1963				 resource_size_t new_size)
1964{
1965	resource_size_t add_size, size = resource_size(res);
1966
1967	if (res->parent)
1968		return;
1969
1970	if (!new_size)
1971		return;
1972
1973	if (new_size > size) {
1974		add_size = new_size - size;
1975		pci_dbg(bridge, "bridge window %pR extended by %pa\n", res,
1976			&add_size);
1977	} else if (new_size < size) {
1978		add_size = size - new_size;
1979		pci_dbg(bridge, "bridge window %pR shrunken by %pa\n", res,
1980			&add_size);
1981	} else {
1982		return;
1983	}
1984
1985	resource_set_size(res, new_size);
1986
1987	/* If the resource is part of the add_list, remove it now */
1988	if (add_list)
1989		remove_from_list(add_list, res);
1990}
1991
1992static void remove_dev_resource(struct resource *avail, struct pci_dev *dev,
1993				struct resource *res)
1994{
1995	resource_size_t size, align, tmp;
1996
1997	size = resource_size(res);
1998	if (!size)
1999		return;
2000
2001	align = pci_resource_alignment(dev, res);
2002	align = align ? ALIGN(avail->start, align) - avail->start : 0;
2003	tmp = align + size;
2004	avail->start = min(avail->start + tmp, avail->end + 1);
2005}
2006
2007static void remove_dev_resources(struct pci_dev *dev,
2008				 struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM])
2009{
2010	struct resource *res, *b_win;
2011	int idx;
2012
2013	pci_dev_for_each_resource(dev, res) {
2014		b_win = pbus_select_window(dev->bus, res);
2015		if (!b_win)
2016			continue;
2017
2018		idx = pci_resource_num(dev->bus->self, b_win);
2019		idx -= PCI_BRIDGE_RESOURCES;
2020
2021		remove_dev_resource(&available[idx], dev, res);
2022	}
2023}
2024
2025#define ALIGN_DOWN_IF_NONZERO(addr, align) \
2026			((align) ? ALIGN_DOWN((addr), (align)) : (addr))
2027
2028/*
2029 * io, mmio and mmio_pref contain the total amount of bridge window space
2030 * available. This includes the minimal space needed to cover all the
2031 * existing devices on the bus and the possible extra space that can be
2032 * shared with the bridges.
2033 */
2034static void pci_bus_distribute_available_resources(struct pci_bus *bus,
2035		    struct list_head *add_list,
2036		    struct resource available_in[PCI_P2P_BRIDGE_RESOURCE_NUM])
2037{
2038	struct resource available[PCI_P2P_BRIDGE_RESOURCE_NUM];
2039	unsigned int normal_bridges = 0, hotplug_bridges = 0;
2040	struct pci_dev *dev, *bridge = bus->self;
2041	resource_size_t per_bridge[PCI_P2P_BRIDGE_RESOURCE_NUM];
2042	resource_size_t align;
2043	int i;
2044
2045	for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) {
2046		struct resource *res =
2047			pci_resource_n(bridge, PCI_BRIDGE_RESOURCES + i);
2048
2049		available[i] = available_in[i];
2050
2051		/*
2052		 * The alignment of this bridge is yet to be considered,
2053		 * hence it must be done now before extending its bridge
2054		 * window.
2055		 */
2056		align = pci_resource_alignment(bridge, res);
2057		if (!res->parent && align)
2058			available[i].start = min(ALIGN(available[i].start, align),
2059						 available[i].end + 1);
2060
2061		/*
2062		 * Now that we have adjusted for alignment, update the
2063		 * bridge window resources to fill as much remaining
2064		 * resource space as possible.
2065		 */
2066		adjust_bridge_window(bridge, res, add_list,
2067				     resource_size(&available[i]));
2068	}
2069
2070	/*
2071	 * Calculate how many hotplug bridges and normal bridges there
2072	 * are on this bus.  We will distribute the additional available
2073	 * resources between hotplug bridges.
2074	 */
2075	for_each_pci_bridge(dev, bus) {
2076		if (dev->is_hotplug_bridge)
2077			hotplug_bridges++;
2078		else
2079			normal_bridges++;
2080	}
2081
2082	if (!(hotplug_bridges + normal_bridges))
2083		return;
2084
2085	/*
2086	 * Calculate the amount of space we can forward from "bus" to any
2087	 * downstream buses, i.e., the space left over after assigning the
2088	 * BARs and windows on "bus".
2089	 */
2090	list_for_each_entry(dev, &bus->devices, bus_list) {
2091		if (!dev->is_virtfn)
2092			remove_dev_resources(dev, available);
2093	}
2094
2095	/*
2096	 * If there is at least one hotplug bridge on this bus it gets all
2097	 * the extra resource space that was left after the reductions
2098	 * above.
2099	 *
2100	 * If there are no hotplug bridges the extra resource space is
2101	 * split between non-hotplug bridges. This is to allow possible
2102	 * hotplug bridges below them to get the extra space as well.
2103	 */
2104	for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) {
2105		per_bridge[i] = div64_ul(resource_size(&available[i]),
2106					 hotplug_bridges ?: normal_bridges);
2107	}
2108
2109	for_each_pci_bridge(dev, bus) {
2110		struct resource *res;
2111		struct pci_bus *b;
2112
2113		b = dev->subordinate;
2114		if (!b)
2115			continue;
2116		if (hotplug_bridges && !dev->is_hotplug_bridge)
2117			continue;
2118
2119		for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) {
2120			res = pci_resource_n(dev, PCI_BRIDGE_RESOURCES + i);
2121
2122			/*
2123			 * Make sure the split resource space is properly
2124			 * aligned for bridge windows (align it down to
2125			 * avoid going above what is available).
2126			 */
2127			align = pci_resource_alignment(dev, res);
2128			resource_set_size(&available[i],
2129					  ALIGN_DOWN_IF_NONZERO(per_bridge[i],
2130								align));
2131
2132			/*
2133			 * The per_bridge holds the extra resource space
2134			 * that can be added for each bridge but there is
2135			 * the minimal already reserved as well so adjust
2136			 * x.start down accordingly to cover the whole
2137			 * space.
2138			 */
2139			available[i].start -= resource_size(res);
2140		}
2141
2142		pci_bus_distribute_available_resources(b, add_list, available);
2143
2144		for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++)
2145			available[i].start += available[i].end + 1;
2146	}
2147}
2148
2149static void pci_bridge_distribute_available_resources(struct pci_dev *bridge,
2150						      struct list_head *add_list)
2151{
2152	struct resource *res, available[PCI_P2P_BRIDGE_RESOURCE_NUM];
2153	unsigned int i;
2154
2155	if (!bridge->is_hotplug_bridge)
2156		return;
2157
2158	pci_dbg(bridge, "distributing available resources\n");
2159
2160	/* Take the initial extra resources from the hotplug port */
2161	for (i = 0; i < PCI_P2P_BRIDGE_RESOURCE_NUM; i++) {
2162		res = pci_resource_n(bridge, PCI_BRIDGE_RESOURCES + i);
2163		available[i] = *res;
2164	}
2165
2166	pci_bus_distribute_available_resources(bridge->subordinate,
2167					       add_list, available);
2168}
2169
2170static bool pci_bridge_resources_not_assigned(struct pci_dev *dev)
2171{
2172	const struct resource *r;
2173
2174	/*
2175	 * If the child device's resources are not yet assigned it means we
2176	 * are configuring them (not the boot firmware), so we should be
2177	 * able to extend the upstream bridge resources in the same way we
2178	 * do with the normal hotplug case.
2179	 */
2180	r = &dev->resource[PCI_BRIDGE_IO_WINDOW];
2181	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2182		return false;
2183	r = &dev->resource[PCI_BRIDGE_MEM_WINDOW];
2184	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2185		return false;
2186	r = &dev->resource[PCI_BRIDGE_PREF_MEM_WINDOW];
2187	if (r->flags && !(r->flags & IORESOURCE_STARTALIGN))
2188		return false;
2189
2190	return true;
2191}
2192
2193static void
2194pci_root_bus_distribute_available_resources(struct pci_bus *bus,
2195					    struct list_head *add_list)
2196{
2197	struct pci_dev *dev, *bridge = bus->self;
2198
2199	for_each_pci_bridge(dev, bus) {
2200		struct pci_bus *b;
2201
2202		b = dev->subordinate;
2203		if (!b)
2204			continue;
2205
2206		/*
2207		 * Need to check "bridge" here too because it is NULL
2208		 * in case of root bus.
2209		 */
2210		if (bridge && pci_bridge_resources_not_assigned(dev))
2211			pci_bridge_distribute_available_resources(dev, add_list);
2212		else
2213			pci_root_bus_distribute_available_resources(b, add_list);
2214	}
2215}
2216
2217static void pci_prepare_next_assign_round(struct list_head *fail_head,
2218					  int tried_times,
2219					  enum release_type rel_type)
2220{
2221	struct pci_dev_resource *fail_res;
2222
2223	pr_info("PCI: No. %d try to assign unassigned res\n", tried_times + 1);
2224
2225	/*
2226	 * Try to release leaf bridge's resources that aren't big
2227	 * enough to contain child device resources.
2228	 */
2229	list_for_each_entry(fail_res, fail_head, list) {
2230		struct pci_bus *bus = fail_res->dev->bus;
2231		struct resource *b_win;
2232
2233		b_win = pbus_select_window_for_type(bus, fail_res->flags);
2234		if (!b_win)
2235			continue;
2236		pci_bus_release_bridge_resources(bus, b_win, rel_type);
2237	}
2238
2239	/* Restore size and flags */
2240	list_for_each_entry(fail_res, fail_head, list)
2241		restore_dev_resource(fail_res);
2242
2243	free_list(fail_head);
2244}
2245
2246/*
2247 * First try will not touch PCI bridge res.
2248 * Second and later try will clear small leaf bridge res.
2249 * Will stop till to the max depth if can not find good one.
2250 */
2251void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
2252{
2253	LIST_HEAD(realloc_head);
2254	/* List of resources that want additional resources */
2255	struct list_head *add_list = NULL;
2256	int tried_times = 0;
2257	enum release_type rel_type = leaf_only;
2258	LIST_HEAD(fail_head);
2259	int pci_try_num = 1;
2260	enum enable_type enable_local;
2261
2262	/* Don't realloc if asked to do so */
2263	enable_local = pci_realloc_detect(bus, pci_realloc_enable);
2264	if (pci_realloc_enabled(enable_local)) {
2265		int max_depth = pci_bus_get_depth(bus);
2266
2267		pci_try_num = max_depth + 1;
2268		dev_info(&bus->dev, "max bus depth: %d pci_try_num: %d\n",
2269			 max_depth, pci_try_num);
2270	}
2271
2272	while (1) {
2273		/*
2274		 * Last try will use add_list, otherwise will try good to
2275		 * have as must have, so can realloc parent bridge resource
2276		 */
2277		if (tried_times + 1 == pci_try_num)
2278			add_list = &realloc_head;
2279		/*
2280		 * Depth first, calculate sizes and alignments of all
2281		 * subordinate buses.
2282		 */
2283		__pci_bus_size_bridges(bus, add_list);
2284
2285		pci_root_bus_distribute_available_resources(bus, add_list);
2286
2287		/* Depth last, allocate resources and update the hardware. */
2288		__pci_bus_assign_resources(bus, add_list, &fail_head);
2289		if (WARN_ON_ONCE(add_list && !list_empty(add_list)))
2290			free_list(add_list);
2291		tried_times++;
2292
2293		/* Any device complain? */
2294		if (list_empty(&fail_head))
2295			break;
2296
2297		if (tried_times >= pci_try_num) {
2298			if (enable_local == undefined) {
2299				dev_info(&bus->dev,
2300					 "Some PCI device resources are unassigned, try booting with pci=realloc\n");
2301			} else if (enable_local == auto_enabled) {
2302				dev_info(&bus->dev,
2303					 "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
2304			}
2305			free_list(&fail_head);
2306			break;
2307		}
2308
2309		/* Third times and later will not check if it is leaf */
2310		if (tried_times + 1 > 2)
2311			rel_type = whole_subtree;
2312
2313		pci_prepare_next_assign_round(&fail_head, tried_times, rel_type);
2314	}
2315
2316	pci_bus_dump_resources(bus);
2317}
2318
2319void pci_assign_unassigned_resources(void)
2320{
2321	struct pci_bus *root_bus;
2322
2323	list_for_each_entry(root_bus, &pci_root_buses, node) {
2324		pci_assign_unassigned_root_bus_resources(root_bus);
2325
2326		/* Make sure the root bridge has a companion ACPI device */
2327		if (ACPI_HANDLE(root_bus->bridge))
2328			acpi_ioapic_add(ACPI_HANDLE(root_bus->bridge));
2329	}
2330}
2331
2332void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
2333{
2334	struct pci_bus *parent = bridge->subordinate;
2335	/* List of resources that want additional resources */
2336	LIST_HEAD(add_list);
2337	int tried_times = 0;
2338	LIST_HEAD(fail_head);
2339	int ret;
2340
2341	while (1) {
2342		__pci_bus_size_bridges(parent, &add_list);
2343
2344		/*
2345		 * Distribute remaining resources (if any) equally between
2346		 * hotplug bridges below. This makes it possible to extend
2347		 * the hierarchy later without running out of resources.
2348		 */
2349		pci_bridge_distribute_available_resources(bridge, &add_list);
2350
2351		__pci_bridge_assign_resources(bridge, &add_list, &fail_head);
2352		if (WARN_ON_ONCE(!list_empty(&add_list)))
2353			free_list(&add_list);
2354		tried_times++;
2355
2356		if (list_empty(&fail_head))
2357			break;
2358
2359		if (tried_times >= 2) {
2360			/* Still fail, don't need to try more */
2361			free_list(&fail_head);
2362			break;
2363		}
2364
2365		pci_prepare_next_assign_round(&fail_head, tried_times,
2366					      whole_subtree);
2367	}
2368
2369	ret = pci_reenable_device(bridge);
2370	if (ret)
2371		pci_err(bridge, "Error reenabling bridge (%d)\n", ret);
2372	pci_set_master(bridge);
2373}
2374EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
2375
2376/*
2377 * Walk to the root bus, find the bridge window relevant for @res and
2378 * release it when possible. If the bridge window contains assigned
2379 * resources, it cannot be released.
2380 */
2381static int pbus_reassign_bridge_resources(struct pci_bus *bus, struct resource *res,
2382					  struct list_head *saved)
2383{
2384	unsigned long type = res->flags;
2385	struct pci_dev_resource *dev_res;
2386	struct pci_dev *bridge = NULL;
2387	LIST_HEAD(added);
2388	LIST_HEAD(failed);
2389	unsigned int i;
2390	int ret = 0;
2391
2392	while (!pci_is_root_bus(bus)) {
2393		bridge = bus->self;
2394		res = pbus_select_window(bus, res);
2395		if (!res)
2396			break;
2397
2398		i = pci_resource_num(bridge, res);
2399
2400		/* Ignore BARs which are still in use */
2401		if (!res->child) {
2402			ret = add_to_list(saved, bridge, res, 0, 0);
2403			if (ret)
2404				return ret;
2405
2406			pci_release_resource(bridge, i);
2407		} else {
2408			const char *res_name = pci_resource_name(bridge, i);
2409
2410			pci_warn(bridge,
2411				 "%s %pR: was not released (still contains assigned resources)\n",
2412				 res_name, res);
2413		}
2414
2415		bus = bus->parent;
2416	}
2417
2418	if (!bridge)
2419		return -ENOENT;
2420
2421	__pci_bus_size_bridges(bridge->subordinate, &added);
2422	__pci_bridge_assign_resources(bridge, &added, &failed);
2423	if (WARN_ON_ONCE(!list_empty(&added)))
2424		free_list(&added);
2425
2426	if (!list_empty(&failed)) {
2427		if (pci_required_resource_failed(&failed, type))
2428			ret = -ENOSPC;
2429		free_list(&failed);
2430		if (ret)
2431			return ret;
2432
2433		/* Only resources with unrelated types failed (again) */
2434	}
2435
2436	list_for_each_entry(dev_res, saved, list) {
2437		struct pci_dev *dev = dev_res->dev;
2438
2439		/* Skip the bridge we just assigned resources for */
2440		if (bridge == dev)
2441			continue;
2442
2443		if (!dev->subordinate)
2444			continue;
2445
2446		pci_setup_bridge(dev->subordinate);
2447	}
2448
2449	return 0;
2450}
2451
2452int pci_do_resource_release_and_resize(struct pci_dev *pdev, int resno, int size,
2453				       int exclude_bars)
2454{
2455	struct resource *res = pci_resource_n(pdev, resno);
2456	struct pci_dev_resource *dev_res;
2457	struct pci_bus *bus = pdev->bus;
2458	struct resource *b_win, *r;
2459	LIST_HEAD(saved);
2460	unsigned int i;
2461	int old, ret;
2462
2463	b_win = pbus_select_window(bus, res);
2464	if (!b_win)
2465		return -EINVAL;
2466
2467	old = pci_rebar_get_current_size(pdev, resno);
2468	if (old < 0)
2469		return old;
2470
2471	ret = pci_rebar_set_size(pdev, resno, size);
2472	if (ret)
2473		return ret;
2474
2475	pci_dev_for_each_resource(pdev, r, i) {
2476		if (i >= PCI_BRIDGE_RESOURCES)
2477			break;
2478
2479		if (exclude_bars & BIT(i))
2480			continue;
2481
2482		if (b_win != pbus_select_window(bus, r))
2483			continue;
2484
2485		ret = add_to_list(&saved, pdev, r, 0, 0);
2486		if (ret)
2487			goto restore;
2488		pci_release_resource(pdev, i);
2489	}
2490
2491	pci_resize_resource_set_size(pdev, resno, size);
2492
2493	if (!bus->self)
2494		goto out;
2495
2496	down_read(&pci_bus_sem);
2497	ret = pbus_reassign_bridge_resources(bus, res, &saved);
2498	if (ret)
2499		goto restore;
2500
2501out:
2502	up_read(&pci_bus_sem);
2503	free_list(&saved);
2504	return ret;
2505
2506restore:
2507	/*
2508	 * Revert to the old configuration.
2509	 *
2510	 * BAR Size must be restored first because it affects the read-only
2511	 * bits in BAR (the old address might not be restorable otherwise
2512	 * due to low address bits).
2513	 */
2514	pci_rebar_set_size(pdev, resno, old);
2515
2516	list_for_each_entry(dev_res, &saved, list) {
2517		struct resource *res = dev_res->res;
2518		struct pci_dev *dev = dev_res->dev;
2519
2520		i = pci_resource_num(dev, res);
2521
2522		if (res->parent) {
2523			release_child_resources(res);
2524			pci_release_resource(dev, i);
2525		}
2526
2527		restore_dev_resource(dev_res);
2528
2529		if (pci_claim_resource(dev, i))
2530			continue;
2531
2532		if (i < PCI_BRIDGE_RESOURCES) {
2533			const char *res_name = pci_resource_name(dev, i);
2534
2535			pci_update_resource(dev, i);
2536			pci_info(dev, "%s %pR: old value restored\n",
2537				 res_name, res);
2538		}
2539		if (dev->subordinate)
2540			pci_setup_bridge(dev->subordinate);
2541	}
2542	goto out;
2543}
2544
2545void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
2546{
2547	struct pci_dev *dev;
2548	/* List of resources that want additional resources */
2549	LIST_HEAD(add_list);
2550
2551	down_read(&pci_bus_sem);
2552	for_each_pci_bridge(dev, bus)
2553		if (pci_has_subordinate(dev))
2554			__pci_bus_size_bridges(dev->subordinate, &add_list);
2555	up_read(&pci_bus_sem);
2556	__pci_bus_assign_resources(bus, &add_list, NULL);
2557	if (WARN_ON_ONCE(!list_empty(&add_list)))
2558		free_list(&add_list);
2559}
2560EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);