FILE
quirks.c
File preview with syntax highlighting.
linux-6.19.14/drivers/pci/quirks.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15#include <linux/aer.h> 16#include <linux/align.h> 17#include <linux/bitfield.h> 18#include <linux/types.h> 19#include <linux/kernel.h> 20#include <linux/export.h> 21#include <linux/pci.h> 22#include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23#include <linux/init.h> 24#include <linux/delay.h> 25#include <linux/acpi.h> 26#include <linux/dmi.h> 27#include <linux/ioport.h> 28#include <linux/sched.h> 29#include <linux/ktime.h> 30#include <linux/mm.h> 31#include <linux/nvme.h> 32#include <linux/platform_data/x86/apple.h> 33#include <linux/pm_runtime.h> 34#include <linux/sizes.h> 35#include <linux/suspend.h> 36#include <linux/switchtec.h> 37#include "pci.h" 38 39static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 40{ 41 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) 42 return true; 43 44 return lnksta & PCI_EXP_LNKSTA_LBMS; 45} 46 47/* 48 * Retrain the link of a downstream PCIe port by hand if necessary. 49 * 50 * This is needed at least where a downstream port of the ASMedia ASM2824 51 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 52 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 53 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 54 * board. 55 * 56 * In such a configuration the switches are supposed to negotiate the link 57 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 58 * continues switching between the two speeds indefinitely and the data 59 * link layer never reaches the active state, with link training reported 60 * repeatedly active ~84% of the time. Forcing the target link speed to 61 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 62 * each other correctly however. And more interestingly retraining with a 63 * higher target link speed afterwards lets the two successfully negotiate 64 * 5.0GT/s. 65 * 66 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 67 * Link Active status bit and in the failed link training scenario it will 68 * be off along with the Link Bandwidth Management Status indicating that 69 * hardware has changed the link speed or width in an attempt to correct 70 * unreliable link operation. For a port that has been left unconnected 71 * both bits will be clear. So use this information to detect the problem 72 * rather than polling the Link Training bit and watching out for flips or 73 * at least the active status. 74 * 75 * Since the exact nature of the problem isn't known and in principle this 76 * could trigger where an ASM2824 device is downstream rather upstream, 77 * apply this erratum workaround to any downstream ports as long as they 78 * support Link Active reporting and have the Link Control 2 register. 79 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 80 * request a retrain and check the result. 81 * 82 * If this turns out successful and we know by the Vendor:Device ID it is 83 * safe to do so, then lift the restriction, letting the devices negotiate 84 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 85 * firmware may have already arranged and lift it with ports that already 86 * report their data link being up. 87 * 88 * Otherwise revert the speed to the original setting and request a retrain 89 * again to remove any residual state, ignoring the result as it's supposed 90 * to fail anyway. 91 * 92 * Return 0 if the link has been successfully retrained. Return an error 93 * if retraining was not needed or we attempted a retrain and it failed. 94 */ 95int pcie_failed_link_retrain(struct pci_dev *dev) 96{ 97 static const struct pci_device_id ids[] = { 98 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 99 {} 100 }; 101 u16 lnksta, lnkctl2; 102 int ret = -ENOTTY; 103 104 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 105 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 106 return ret; 107 108 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 109 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 110 u16 oldlnkctl2; 111 112 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 113 114 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); 115 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 116 if (ret) { 117 pci_info(dev, "retraining failed\n"); 118 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), 119 true); 120 return ret; 121 } 122 123 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 124 } 125 126 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 127 128 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 129 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 130 pci_match_id(ids, dev)) { 131 u32 lnkcap; 132 133 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 134 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 135 ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false); 136 if (ret) { 137 pci_info(dev, "retraining failed\n"); 138 return ret; 139 } 140 } 141 142 return ret; 143} 144 145static ktime_t fixup_debug_start(struct pci_dev *dev, 146 void (*fn)(struct pci_dev *dev)) 147{ 148 if (initcall_debug) 149 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 150 151 return ktime_get(); 152} 153 154static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 155 void (*fn)(struct pci_dev *dev)) 156{ 157 ktime_t delta, rettime; 158 unsigned long long duration; 159 160 rettime = ktime_get(); 161 delta = ktime_sub(rettime, calltime); 162 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 163 if (initcall_debug || duration > 10000) 164 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 165} 166 167static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 168 struct pci_fixup *end) 169{ 170 ktime_t calltime; 171 172 for (; f < end; f++) 173 if ((f->class == (u32) (dev->class >> f->class_shift) || 174 f->class == (u32) PCI_ANY_ID) && 175 (f->vendor == dev->vendor || 176 f->vendor == (u16) PCI_ANY_ID) && 177 (f->device == dev->device || 178 f->device == (u16) PCI_ANY_ID)) { 179 void (*hook)(struct pci_dev *dev); 180#ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 181 hook = offset_to_ptr(&f->hook_offset); 182#else 183 hook = f->hook; 184#endif 185 calltime = fixup_debug_start(dev, hook); 186 hook(dev); 187 fixup_debug_report(dev, calltime, hook); 188 } 189} 190 191extern struct pci_fixup __start_pci_fixups_early[]; 192extern struct pci_fixup __end_pci_fixups_early[]; 193extern struct pci_fixup __start_pci_fixups_header[]; 194extern struct pci_fixup __end_pci_fixups_header[]; 195extern struct pci_fixup __start_pci_fixups_final[]; 196extern struct pci_fixup __end_pci_fixups_final[]; 197extern struct pci_fixup __start_pci_fixups_enable[]; 198extern struct pci_fixup __end_pci_fixups_enable[]; 199extern struct pci_fixup __start_pci_fixups_resume[]; 200extern struct pci_fixup __end_pci_fixups_resume[]; 201extern struct pci_fixup __start_pci_fixups_resume_early[]; 202extern struct pci_fixup __end_pci_fixups_resume_early[]; 203extern struct pci_fixup __start_pci_fixups_suspend[]; 204extern struct pci_fixup __end_pci_fixups_suspend[]; 205extern struct pci_fixup __start_pci_fixups_suspend_late[]; 206extern struct pci_fixup __end_pci_fixups_suspend_late[]; 207 208static bool pci_apply_fixup_final_quirks; 209 210void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 211{ 212 struct pci_fixup *start, *end; 213 214 switch (pass) { 215 case pci_fixup_early: 216 start = __start_pci_fixups_early; 217 end = __end_pci_fixups_early; 218 break; 219 220 case pci_fixup_header: 221 start = __start_pci_fixups_header; 222 end = __end_pci_fixups_header; 223 break; 224 225 case pci_fixup_final: 226 if (!pci_apply_fixup_final_quirks) 227 return; 228 start = __start_pci_fixups_final; 229 end = __end_pci_fixups_final; 230 break; 231 232 case pci_fixup_enable: 233 start = __start_pci_fixups_enable; 234 end = __end_pci_fixups_enable; 235 break; 236 237 case pci_fixup_resume: 238 start = __start_pci_fixups_resume; 239 end = __end_pci_fixups_resume; 240 break; 241 242 case pci_fixup_resume_early: 243 start = __start_pci_fixups_resume_early; 244 end = __end_pci_fixups_resume_early; 245 break; 246 247 case pci_fixup_suspend: 248 start = __start_pci_fixups_suspend; 249 end = __end_pci_fixups_suspend; 250 break; 251 252 case pci_fixup_suspend_late: 253 start = __start_pci_fixups_suspend_late; 254 end = __end_pci_fixups_suspend_late; 255 break; 256 257 default: 258 /* stupid compiler warning, you would think with an enum... */ 259 return; 260 } 261 pci_do_fixups(dev, start, end); 262} 263EXPORT_SYMBOL(pci_fixup_device); 264 265static int __init pci_apply_final_quirks(void) 266{ 267 struct pci_dev *dev = NULL; 268 u8 cls = 0; 269 u8 tmp; 270 271 if (pci_cache_line_size) 272 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 273 274 pci_apply_fixup_final_quirks = true; 275 for_each_pci_dev(dev) { 276 pci_fixup_device(pci_fixup_final, dev); 277 /* 278 * If arch hasn't set it explicitly yet, use the CLS 279 * value shared by all PCI devices. If there's a 280 * mismatch, fall back to the default value. 281 */ 282 if (!pci_cache_line_size) { 283 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 284 if (!cls) 285 cls = tmp; 286 if (!tmp || cls == tmp) 287 continue; 288 289 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 290 cls << 2, tmp << 2, 291 pci_dfl_cache_line_size << 2); 292 pci_cache_line_size = pci_dfl_cache_line_size; 293 } 294 } 295 296 if (!pci_cache_line_size) { 297 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 298 pci_dfl_cache_line_size << 2); 299 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 300 } 301 302 return 0; 303} 304fs_initcall_sync(pci_apply_final_quirks); 305 306/* 307 * Decoding should be disabled for a PCI device during BAR sizing to avoid 308 * conflict. But doing so may cause problems on host bridge and perhaps other 309 * key system devices. For devices that need to have mmio decoding always-on, 310 * we need to set the dev->mmio_always_on bit. 311 */ 312static void quirk_mmio_always_on(struct pci_dev *dev) 313{ 314 dev->mmio_always_on = 1; 315} 316DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 317 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 318 319/* 320 * The Mellanox Tavor device gives false positive parity errors. Disable 321 * parity error reporting. 322 */ 323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 325 326/* 327 * Deal with broken BIOSes that neglect to enable passive release, 328 * which can cause problems in combination with the 82441FX/PPro MTRRs 329 */ 330static void quirk_passive_release(struct pci_dev *dev) 331{ 332 struct pci_dev *d = NULL; 333 unsigned char dlc; 334 335 /* 336 * We have to make sure a particular bit is set in the PIIX3 337 * ISA bridge, so we have to go out and find it. 338 */ 339 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 340 pci_read_config_byte(d, 0x82, &dlc); 341 if (!(dlc & 1<<1)) { 342 pci_info(d, "PIIX3: Enabling Passive Release\n"); 343 dlc |= 1<<1; 344 pci_write_config_byte(d, 0x82, dlc); 345 } 346 } 347} 348DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 349DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 350 351#ifdef CONFIG_X86_32 352/* 353 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 354 * workaround but VIA don't answer queries. If you happen to have good 355 * contacts at VIA ask them for me please -- Alan 356 * 357 * This appears to be BIOS not version dependent. So presumably there is a 358 * chipset level fix. 359 */ 360static void quirk_isa_dma_hangs(struct pci_dev *dev) 361{ 362 if (!isa_dma_bridge_buggy) { 363 isa_dma_bridge_buggy = 1; 364 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 365 } 366} 367/* 368 * It's not totally clear which chipsets are the problematic ones. We know 369 * 82C586 and 82C596 variants are affected. 370 */ 371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 372DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 373DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 374DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 375DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 376DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 378#endif 379 380#ifdef CONFIG_HAS_IOPORT 381/* 382 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 383 * for some HT machines to use C4 w/o hanging. 384 */ 385static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 386{ 387 u32 pmbase; 388 u16 pm1a; 389 390 pci_read_config_dword(dev, 0x40, &pmbase); 391 pmbase = pmbase & 0xff80; 392 pm1a = inw(pmbase); 393 394 if (pm1a & 0x10) { 395 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 396 outw(0x10, pmbase); 397 } 398} 399DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 400#endif 401 402/* Chipsets where PCI->PCI transfers vanish or hang */ 403static void quirk_nopcipci(struct pci_dev *dev) 404{ 405 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 406 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 407 pci_pci_problems |= PCIPCI_FAIL; 408 } 409} 410DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 412 413static void quirk_nopciamd(struct pci_dev *dev) 414{ 415 u8 rev; 416 pci_read_config_byte(dev, 0x08, &rev); 417 if (rev == 0x13) { 418 /* Erratum 24 */ 419 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 420 pci_pci_problems |= PCIAGP_FAIL; 421 } 422} 423DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 424 425/* Triton requires workarounds to be used by the drivers */ 426static void quirk_triton(struct pci_dev *dev) 427{ 428 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 429 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 430 pci_pci_problems |= PCIPCI_TRITON; 431 } 432} 433DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 434DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 435DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 436DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 437 438/* 439 * VIA Apollo KT133 needs PCI latency patch 440 * Made according to a Windows driver-based patch by George E. Breese; 441 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 442 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 443 * which Mr Breese based his work. 444 * 445 * Updated based on further information from the site and also on 446 * information provided by VIA 447 */ 448static void quirk_vialatency(struct pci_dev *dev) 449{ 450 struct pci_dev *p; 451 u8 busarb; 452 453 /* 454 * Ok, we have a potential problem chipset here. Now see if we have 455 * a buggy southbridge. 456 */ 457 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 458 if (p != NULL) { 459 460 /* 461 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 462 * thanks Dan Hollis. 463 * Check for buggy part revisions 464 */ 465 if (p->revision < 0x40 || p->revision > 0x42) 466 goto exit; 467 } else { 468 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 469 if (p == NULL) /* No problem parts */ 470 goto exit; 471 472 /* Check for buggy part revisions */ 473 if (p->revision < 0x10 || p->revision > 0x12) 474 goto exit; 475 } 476 477 /* 478 * Ok we have the problem. Now set the PCI master grant to occur 479 * every master grant. The apparent bug is that under high PCI load 480 * (quite common in Linux of course) you can get data loss when the 481 * CPU is held off the bus for 3 bus master requests. This happens 482 * to include the IDE controllers.... 483 * 484 * VIA only apply this fix when an SB Live! is present but under 485 * both Linux and Windows this isn't enough, and we have seen 486 * corruption without SB Live! but with things like 3 UDMA IDE 487 * controllers. So we ignore that bit of the VIA recommendation.. 488 */ 489 pci_read_config_byte(dev, 0x76, &busarb); 490 491 /* 492 * Set bit 4 and bit 5 of byte 76 to 0x01 493 * "Master priority rotation on every PCI master grant" 494 */ 495 busarb &= ~(1<<5); 496 busarb |= (1<<4); 497 pci_write_config_byte(dev, 0x76, busarb); 498 pci_info(dev, "Applying VIA southbridge workaround\n"); 499exit: 500 pci_dev_put(p); 501} 502DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 503DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 504DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 505/* Must restore this on a resume from RAM */ 506DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 507DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 508DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 509 510/* VIA Apollo VP3 needs ETBF on BT848/878 */ 511static void quirk_viaetbf(struct pci_dev *dev) 512{ 513 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 514 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 515 pci_pci_problems |= PCIPCI_VIAETBF; 516 } 517} 518DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 519 520static void quirk_vsfx(struct pci_dev *dev) 521{ 522 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 523 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 524 pci_pci_problems |= PCIPCI_VSFX; 525 } 526} 527DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 528 529/* 530 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 531 * space. Latency must be set to 0xA and Triton workaround applied too. 532 * [Info kindly provided by ALi] 533 */ 534static void quirk_alimagik(struct pci_dev *dev) 535{ 536 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 537 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 538 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 539 } 540} 541DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 542DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 543 544/* Natoma has some interesting boundary conditions with Zoran stuff at least */ 545static void quirk_natoma(struct pci_dev *dev) 546{ 547 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 548 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 549 pci_pci_problems |= PCIPCI_NATOMA; 550 } 551} 552DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 553DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 554DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 555DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 556DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 557DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 558 559/* 560 * This chip can cause PCI parity errors if config register 0xA0 is read 561 * while DMAs are occurring. 562 */ 563static void quirk_citrine(struct pci_dev *dev) 564{ 565 dev->cfg_size = 0xA0; 566} 567DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 568 569/* 570 * This chip can cause bus lockups if config addresses above 0x600 571 * are read or written. 572 */ 573static void quirk_nfp6000(struct pci_dev *dev) 574{ 575 dev->cfg_size = 0x600; 576} 577DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 578DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 579DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 580DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 581 582/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 583static void quirk_extend_bar_to_page(struct pci_dev *dev) 584{ 585 int i; 586 587 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 588 struct resource *r = &dev->resource[i]; 589 const char *r_name = pci_resource_name(dev, i); 590 591 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 592 resource_set_range(r, 0, PAGE_SIZE); 593 r->flags |= IORESOURCE_UNSET; 594 pci_info(dev, "%s %pR: expanded to page size\n", 595 r_name, r); 596 } 597 } 598} 599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 600 601/* 602 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 603 * If it's needed, re-allocate the region. 604 */ 605static void quirk_s3_64M(struct pci_dev *dev) 606{ 607 struct resource *r = &dev->resource[0]; 608 609 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 610 r->flags |= IORESOURCE_UNSET; 611 resource_set_range(r, 0, SZ_64M); 612 } 613} 614DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 615DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 616 617static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 618 const char *name) 619{ 620 u32 region; 621 struct pci_bus_region bus_region; 622 struct resource *res = pci_resource_n(dev, pos); 623 const char *res_name = pci_resource_name(dev, pos); 624 625 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 626 627 if (!region) 628 return; 629 630 res->name = pci_name(dev); 631 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 632 res->flags |= 633 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 634 region &= ~(size - 1); 635 636 /* Convert from PCI bus to resource space */ 637 bus_region.start = region; 638 bus_region.end = region + size - 1; 639 pcibios_bus_to_resource(dev->bus, res, &bus_region); 640 641 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 642} 643 644/* 645 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 646 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 647 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 648 * (which conflicts w/ BAR1's memory range). 649 * 650 * CS553x's ISA PCI BARs may also be read-only (ref: 651 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 652 */ 653static void quirk_cs5536_vsa(struct pci_dev *dev) 654{ 655 static char *name = "CS5536 ISA bridge"; 656 657 if (pci_resource_len(dev, 0) != 8) { 658 quirk_io(dev, 0, 8, name); /* SMB */ 659 quirk_io(dev, 1, 256, name); /* GPIO */ 660 quirk_io(dev, 2, 64, name); /* MFGPT */ 661 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 662 name); 663 } 664} 665DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 666 667static void quirk_io_region(struct pci_dev *dev, int port, 668 unsigned int size, int nr, const char *name) 669{ 670 u16 region; 671 struct pci_bus_region bus_region; 672 struct resource *res = pci_resource_n(dev, nr); 673 674 pci_read_config_word(dev, port, ®ion); 675 region &= ~(size - 1); 676 677 if (!region) 678 return; 679 680 res->name = pci_name(dev); 681 res->flags = IORESOURCE_IO; 682 683 /* Convert from PCI bus to resource space */ 684 bus_region.start = region; 685 bus_region.end = region + size - 1; 686 pcibios_bus_to_resource(dev->bus, res, &bus_region); 687 688 /* 689 * "res" is typically a bridge window resource that's not being 690 * used for a bridge window, so it's just a place to stash this 691 * non-standard resource. Printing "nr" or pci_resource_name() of 692 * it doesn't really make sense. 693 */ 694 if (!pci_claim_resource(dev, nr)) 695 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 696} 697 698/* 699 * ATI Northbridge setups MCE the processor if you even read somewhere 700 * between 0x3b0->0x3bb or read 0x3d3 701 */ 702static void quirk_ati_exploding_mce(struct pci_dev *dev) 703{ 704 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 705 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 706 request_region(0x3b0, 0x0C, "RadeonIGP"); 707 request_region(0x3d3, 0x01, "RadeonIGP"); 708} 709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 710 711/* 712 * In the AMD NL platform, this device ([1022:7912]) has a class code of 713 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 714 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 715 * 716 * But the dwc3 driver is a more specific driver for this device, and we'd 717 * prefer to use it instead of xhci. To prevent xhci from claiming the 718 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 719 * defines as "USB device (not host controller)". The dwc3 driver can then 720 * claim it based on its Vendor and Device ID. 721 */ 722static void quirk_amd_dwc_class(struct pci_dev *pdev) 723{ 724 u32 class = pdev->class; 725 726 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 727 /* Use "USB Device (not host controller)" class */ 728 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 729 pci_info(pdev, 730 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 731 class, pdev->class); 732 } 733} 734DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 735 quirk_amd_dwc_class); 736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 737 quirk_amd_dwc_class); 738 739/* 740 * Synopsys USB 3.x host HAPS platform has a class code of 741 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 742 * devices should use dwc3-haps driver. Change these devices' class code to 743 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 744 * them. 745 */ 746static void quirk_synopsys_haps(struct pci_dev *pdev) 747{ 748 u32 class = pdev->class; 749 750 switch (pdev->device) { 751 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 752 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 754 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 755 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 756 class, pdev->class); 757 break; 758 } 759} 760DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 761 PCI_CLASS_SERIAL_USB_XHCI, 0, 762 quirk_synopsys_haps); 763 764/* 765 * Let's make the southbridge information explicit instead of having to 766 * worry about people probing the ACPI areas, for example.. (Yes, it 767 * happens, and if you read the wrong ACPI register it will put the machine 768 * to sleep with no way of waking it up again. Bummer). 769 * 770 * ALI M7101: Two IO regions pointed to by words at 771 * 0xE0 (64 bytes of ACPI registers) 772 * 0xE2 (32 bytes of SMB registers) 773 */ 774static void quirk_ali7101_acpi(struct pci_dev *dev) 775{ 776 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 777 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 778} 779DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 780 781static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 782{ 783 u32 devres; 784 u32 mask, size, base; 785 786 pci_read_config_dword(dev, port, &devres); 787 if ((devres & enable) != enable) 788 return; 789 mask = (devres >> 16) & 15; 790 base = devres & 0xffff; 791 size = 16; 792 for (;;) { 793 unsigned int bit = size >> 1; 794 if ((bit & mask) == bit) 795 break; 796 size = bit; 797 } 798 /* 799 * For now we only print it out. Eventually we'll want to 800 * reserve it (at least if it's in the 0x1000+ range), but 801 * let's get enough confirmation reports first. 802 */ 803 base &= -size; 804 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 805} 806 807static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 808{ 809 u32 devres; 810 u32 mask, size, base; 811 812 pci_read_config_dword(dev, port, &devres); 813 if ((devres & enable) != enable) 814 return; 815 base = devres & 0xffff0000; 816 mask = (devres & 0x3f) << 16; 817 size = 128 << 16; 818 for (;;) { 819 unsigned int bit = size >> 1; 820 if ((bit & mask) == bit) 821 break; 822 size = bit; 823 } 824 825 /* 826 * For now we only print it out. Eventually we'll want to 827 * reserve it, but let's get enough confirmation reports first. 828 */ 829 base &= -size; 830 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 831} 832 833/* 834 * PIIX4 ACPI: Two IO regions pointed to by longwords at 835 * 0x40 (64 bytes of ACPI registers) 836 * 0x90 (16 bytes of SMB registers) 837 * and a few strange programmable PIIX4 device resources. 838 */ 839static void quirk_piix4_acpi(struct pci_dev *dev) 840{ 841 u32 res_a; 842 843 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 844 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 845 846 /* Device resource A has enables for some of the other ones */ 847 pci_read_config_dword(dev, 0x5c, &res_a); 848 849 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 850 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 851 852 /* Device resource D is just bitfields for static resources */ 853 854 /* Device 12 enabled? */ 855 if (res_a & (1 << 29)) { 856 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 857 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 858 } 859 /* Device 13 enabled? */ 860 if (res_a & (1 << 30)) { 861 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 862 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 863 } 864 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 865 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 866} 867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 868DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 869 870#define ICH_PMBASE 0x40 871#define ICH_ACPI_CNTL 0x44 872#define ICH4_ACPI_EN 0x10 873#define ICH6_ACPI_EN 0x80 874#define ICH4_GPIOBASE 0x58 875#define ICH4_GPIO_CNTL 0x5c 876#define ICH4_GPIO_EN 0x10 877#define ICH6_GPIOBASE 0x48 878#define ICH6_GPIO_CNTL 0x4c 879#define ICH6_GPIO_EN 0x10 880 881/* 882 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 883 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 884 * 0x58 (64 bytes of GPIO I/O space) 885 */ 886static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 887{ 888 u8 enable; 889 890 /* 891 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 892 * with low legacy (and fixed) ports. We don't know the decoding 893 * priority and can't tell whether the legacy device or the one created 894 * here is really at that address. This happens on boards with broken 895 * BIOSes. 896 */ 897 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 898 if (enable & ICH4_ACPI_EN) 899 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 900 "ICH4 ACPI/GPIO/TCO"); 901 902 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 903 if (enable & ICH4_GPIO_EN) 904 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 905 "ICH4 GPIO"); 906} 907DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 908DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 909DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 910DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 911DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 912DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 913DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 914DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 915DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 916DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 917 918static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 919{ 920 u8 enable; 921 922 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 923 if (enable & ICH6_ACPI_EN) 924 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 925 "ICH6 ACPI/GPIO/TCO"); 926 927 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 928 if (enable & ICH6_GPIO_EN) 929 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 930 "ICH6 GPIO"); 931} 932 933static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 934 const char *name, int dynsize) 935{ 936 u32 val; 937 u32 size, base; 938 939 pci_read_config_dword(dev, reg, &val); 940 941 /* Enabled? */ 942 if (!(val & 1)) 943 return; 944 base = val & 0xfffc; 945 if (dynsize) { 946 /* 947 * This is not correct. It is 16, 32 or 64 bytes depending on 948 * register D31:F0:ADh bits 5:4. 949 * 950 * But this gets us at least _part_ of it. 951 */ 952 size = 16; 953 } else { 954 size = 128; 955 } 956 base &= ~(size-1); 957 958 /* 959 * Just print it out for now. We should reserve it after more 960 * debugging. 961 */ 962 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 963} 964 965static void quirk_ich6_lpc(struct pci_dev *dev) 966{ 967 /* Shared ACPI/GPIO decode with all ICH6+ */ 968 ich6_lpc_acpi_gpio(dev); 969 970 /* ICH6-specific generic IO decode */ 971 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 972 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 973} 974DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 975DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 976 977static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 978 const char *name) 979{ 980 u32 val; 981 u32 mask, base; 982 983 pci_read_config_dword(dev, reg, &val); 984 985 /* Enabled? */ 986 if (!(val & 1)) 987 return; 988 989 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 990 base = val & 0xfffc; 991 mask = (val >> 16) & 0xfc; 992 mask |= 3; 993 994 /* 995 * Just print it out for now. We should reserve it after more 996 * debugging. 997 */ 998 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 999} 1000 1001/* ICH7-10 has the same common LPC generic IO decode registers */ 1002static void quirk_ich7_lpc(struct pci_dev *dev) 1003{ 1004 /* We share the common ACPI/GPIO decode with ICH6 */ 1005 ich6_lpc_acpi_gpio(dev); 1006 1007 /* And have 4 ICH7+ generic decodes */ 1008 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1009 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1010 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1011 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1012} 1013DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1015DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1016DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1019DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1020DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1021DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1022DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1024DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1025DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1026 1027/* 1028 * VIA ACPI: One IO region pointed to by longword at 1029 * 0x48 or 0x20 (256 bytes of ACPI registers) 1030 */ 1031static void quirk_vt82c586_acpi(struct pci_dev *dev) 1032{ 1033 if (dev->revision & 0x10) 1034 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1035 "vt82c586 ACPI"); 1036} 1037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1038 1039/* 1040 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1041 * 0x48 (256 bytes of ACPI registers) 1042 * 0x70 (128 bytes of hardware monitoring register) 1043 * 0x90 (16 bytes of SMB registers) 1044 */ 1045static void quirk_vt82c686_acpi(struct pci_dev *dev) 1046{ 1047 quirk_vt82c586_acpi(dev); 1048 1049 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1050 "vt82c686 HW-mon"); 1051 1052 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1053} 1054DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1055 1056/* 1057 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1058 * 0x88 (128 bytes of power management registers) 1059 * 0xd0 (16 bytes of SMB registers) 1060 */ 1061static void quirk_vt8235_acpi(struct pci_dev *dev) 1062{ 1063 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1064 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1065} 1066DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1067 1068/* 1069 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1070 * back-to-back: Disable fast back-to-back on the secondary bus segment 1071 */ 1072static void quirk_xio2000a(struct pci_dev *dev) 1073{ 1074 struct pci_dev *pdev; 1075 u16 command; 1076 1077 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1078 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1079 pci_read_config_word(pdev, PCI_COMMAND, &command); 1080 if (command & PCI_COMMAND_FAST_BACK) 1081 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1082 } 1083} 1084DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1085 quirk_xio2000a); 1086 1087#ifdef CONFIG_X86_IO_APIC 1088 1089#include <asm/io_apic.h> 1090 1091/* 1092 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1093 * devices to the external APIC. 1094 * 1095 * TODO: When we have device-specific interrupt routers, this code will go 1096 * away from quirks. 1097 */ 1098static void quirk_via_ioapic(struct pci_dev *dev) 1099{ 1100 u8 tmp; 1101 1102 if (nr_ioapics < 1) 1103 tmp = 0; /* nothing routed to external APIC */ 1104 else 1105 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1106 1107 pci_info(dev, "%s VIA external APIC routing\n", 1108 tmp ? "Enabling" : "Disabling"); 1109 1110 /* Offset 0x58: External APIC IRQ output control */ 1111 pci_write_config_byte(dev, 0x58, tmp); 1112} 1113DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1114DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1115 1116/* 1117 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1118 * This leads to doubled level interrupt rates. 1119 * Set this bit to get rid of cycle wastage. 1120 * Otherwise uncritical. 1121 */ 1122static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1123{ 1124 u8 misc_control2; 1125#define BYPASS_APIC_DEASSERT 8 1126 1127 pci_read_config_byte(dev, 0x5B, &misc_control2); 1128 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1129 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1130 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1131 } 1132} 1133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1134DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1135 1136/* 1137 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1138 * We check all revs >= B0 (yet not in the pre production!) as the bug 1139 * is currently marked NoFix 1140 * 1141 * We have multiple reports of hangs with this chipset that went away with 1142 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1143 * of course. However the advice is demonstrably good even if so. 1144 */ 1145static void quirk_amd_ioapic(struct pci_dev *dev) 1146{ 1147 if (dev->revision >= 0x02) { 1148 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1149 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1150 } 1151} 1152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1153#endif /* CONFIG_X86_IO_APIC */ 1154 1155#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1156 1157static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1158{ 1159 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1160 if (dev->subsystem_device == 0xa118) 1161 dev->sriov->link = dev->devfn; 1162} 1163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1164#endif 1165 1166/* 1167 * Some settings of MMRBC can lead to data corruption so block changes. 1168 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1169 */ 1170static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1171{ 1172 if (dev->subordinate && dev->revision <= 0x12) { 1173 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1174 dev->revision); 1175 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1176 } 1177} 1178DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1179 1180/* 1181 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1182 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1183 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1184 * of the ACPI SCI interrupt is only done for convenience. 1185 * -jgarzik 1186 */ 1187static void quirk_via_acpi(struct pci_dev *d) 1188{ 1189 u8 irq; 1190 1191 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1192 pci_read_config_byte(d, 0x42, &irq); 1193 irq &= 0xf; 1194 if (irq && (irq != 2)) 1195 d->irq = irq; 1196} 1197DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1198DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1199 1200/* VIA bridges which have VLink */ 1201static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1202 1203static void quirk_via_bridge(struct pci_dev *dev) 1204{ 1205 /* See what bridge we have and find the device ranges */ 1206 switch (dev->device) { 1207 case PCI_DEVICE_ID_VIA_82C686: 1208 /* 1209 * The VT82C686 is special; it attaches to PCI and can have 1210 * any device number. All its subdevices are functions of 1211 * that single device. 1212 */ 1213 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1214 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1215 break; 1216 case PCI_DEVICE_ID_VIA_8237: 1217 case PCI_DEVICE_ID_VIA_8237A: 1218 via_vlink_dev_lo = 15; 1219 break; 1220 case PCI_DEVICE_ID_VIA_8235: 1221 via_vlink_dev_lo = 16; 1222 break; 1223 case PCI_DEVICE_ID_VIA_8231: 1224 case PCI_DEVICE_ID_VIA_8233_0: 1225 case PCI_DEVICE_ID_VIA_8233A: 1226 case PCI_DEVICE_ID_VIA_8233C_0: 1227 via_vlink_dev_lo = 17; 1228 break; 1229 } 1230} 1231DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1232DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1233DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1234DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1235DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1239 1240/* 1241 * quirk_via_vlink - VIA VLink IRQ number update 1242 * @dev: PCI device 1243 * 1244 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1245 * the IRQ line register which usually is not relevant for PCI cards, is 1246 * actually written so that interrupts get sent to the right place. 1247 * 1248 * We only do this on systems where a VIA south bridge was detected, and 1249 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1250 */ 1251static void quirk_via_vlink(struct pci_dev *dev) 1252{ 1253 u8 irq, new_irq; 1254 1255 /* Check if we have VLink at all */ 1256 if (via_vlink_dev_lo == -1) 1257 return; 1258 1259 new_irq = dev->irq; 1260 1261 /* Don't quirk interrupts outside the legacy IRQ range */ 1262 if (!new_irq || new_irq > 15) 1263 return; 1264 1265 /* Internal device ? */ 1266 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1267 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1268 return; 1269 1270 /* 1271 * This is an internal VLink device on a PIC interrupt. The BIOS 1272 * ought to have set this but may not have, so we redo it. 1273 */ 1274 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1275 if (new_irq != irq) { 1276 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1277 irq, new_irq); 1278 udelay(15); /* unknown if delay really needed */ 1279 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1280 } 1281} 1282DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1283 1284/* 1285 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1286 * of VT82C597 for backward compatibility. We need to switch it off to be 1287 * able to recognize the real type of the chip. 1288 */ 1289static void quirk_vt82c598_id(struct pci_dev *dev) 1290{ 1291 pci_write_config_byte(dev, 0xfc, 0); 1292 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1293} 1294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1295 1296/* 1297 * CardBus controllers have a legacy base address that enables them to 1298 * respond as i82365 pcmcia controllers. We don't want them to do this 1299 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1300 * driver does not (and should not) handle CardBus. 1301 */ 1302static void quirk_cardbus_legacy(struct pci_dev *dev) 1303{ 1304 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1305} 1306DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1307 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1308DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1309 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1310 1311/* 1312 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1313 * what the designers were smoking but let's not inhale... 1314 * 1315 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1316 * turn it off! 1317 */ 1318static void quirk_amd_ordering(struct pci_dev *dev) 1319{ 1320 u32 pcic; 1321 pci_read_config_dword(dev, 0x4C, &pcic); 1322 if ((pcic & 6) != 6) { 1323 pcic |= 6; 1324 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1325 pci_write_config_dword(dev, 0x4C, pcic); 1326 pci_read_config_dword(dev, 0x84, &pcic); 1327 pcic |= (1 << 23); /* Required in this mode */ 1328 pci_write_config_dword(dev, 0x84, pcic); 1329 } 1330} 1331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1332DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1333 1334/* 1335 * DreamWorks-provided workaround for Dunord I-3000 problem 1336 * 1337 * This card decodes and responds to addresses not apparently assigned to 1338 * it. We force a larger allocation to ensure that nothing gets put too 1339 * close to it. 1340 */ 1341static void quirk_dunord(struct pci_dev *dev) 1342{ 1343 struct resource *r = &dev->resource[1]; 1344 1345 r->flags |= IORESOURCE_UNSET; 1346 resource_set_range(r, 0, SZ_16M); 1347} 1348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1349 1350/* 1351 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1352 * decoding (transparent), and does indicate this in the ProgIf. 1353 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1354 */ 1355static void quirk_transparent_bridge(struct pci_dev *dev) 1356{ 1357 dev->transparent = 1; 1358} 1359DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1360DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1361 1362/* 1363 * Enabling Link Bandwidth Management Interrupts (BW notifications) can cause 1364 * boot hangs on P45. 1365 */ 1366static void quirk_p45_bw_notifications(struct pci_dev *dev) 1367{ 1368 dev->no_bw_notif = 1; 1369} 1370DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e21, quirk_p45_bw_notifications); 1371 1372/* 1373 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1374 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1375 * found at http://www.national.com/analog for info on what these bits do. 1376 * <christer@weinigel.se> 1377 */ 1378static void quirk_mediagx_master(struct pci_dev *dev) 1379{ 1380 u8 reg; 1381 1382 pci_read_config_byte(dev, 0x41, ®); 1383 if (reg & 2) { 1384 reg &= ~2; 1385 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1386 reg); 1387 pci_write_config_byte(dev, 0x41, reg); 1388 } 1389} 1390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1391DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1392 1393/* 1394 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1395 * in the odd case it is not the results are corruption hence the presence 1396 * of a Linux check. 1397 */ 1398static void quirk_disable_pxb(struct pci_dev *pdev) 1399{ 1400 u16 config; 1401 1402 if (pdev->revision != 0x04) /* Only C0 requires this */ 1403 return; 1404 pci_read_config_word(pdev, 0x40, &config); 1405 if (config & (1<<6)) { 1406 config &= ~(1<<6); 1407 pci_write_config_word(pdev, 0x40, config); 1408 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1409 } 1410} 1411DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1412DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1413 1414static void quirk_amd_ide_mode(struct pci_dev *pdev) 1415{ 1416 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1417 u8 tmp; 1418 1419 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1420 if (tmp == 0x01) { 1421 pci_read_config_byte(pdev, 0x40, &tmp); 1422 pci_write_config_byte(pdev, 0x40, tmp|1); 1423 pci_write_config_byte(pdev, 0x9, 1); 1424 pci_write_config_byte(pdev, 0xa, 6); 1425 pci_write_config_byte(pdev, 0x40, tmp); 1426 1427 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1428 pci_info(pdev, "set SATA to AHCI mode\n"); 1429 } 1430} 1431DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1432DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1433DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1434DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1435DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1436DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1437DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1438DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1439 1440/* Serverworks CSB5 IDE does not fully support native mode */ 1441static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1442{ 1443 u8 prog; 1444 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1445 if (prog & 5) { 1446 prog &= ~5; 1447 pdev->class &= ~5; 1448 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1449 /* PCI layer will sort out resources */ 1450 } 1451} 1452DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1453 1454/* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1455static void quirk_ide_samemode(struct pci_dev *pdev) 1456{ 1457 u8 prog; 1458 1459 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1460 1461 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1462 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1463 prog &= ~5; 1464 pdev->class &= ~5; 1465 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1466 } 1467} 1468DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1469 1470/* Some ATA devices break if put into D3 */ 1471static void quirk_no_ata_d3(struct pci_dev *pdev) 1472{ 1473 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1474} 1475/* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1476DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1477 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1478DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1479 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1480/* ALi loses some register settings that we cannot then restore */ 1481DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1482 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1483/* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1484 occur when mode detecting */ 1485DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1486 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1487 1488/* 1489 * This was originally an Alpha-specific thing, but it really fits here. 1490 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1491 */ 1492static void quirk_eisa_bridge(struct pci_dev *dev) 1493{ 1494 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1495} 1496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1497 1498/* 1499 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1500 * is not activated. The myth is that Asus said that they do not want the 1501 * users to be irritated by just another PCI Device in the Win98 device 1502 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1503 * package 2.7.0 for details) 1504 * 1505 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1506 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1507 * becomes necessary to do this tweak in two steps -- the chosen trigger 1508 * is either the Host bridge (preferred) or on-board VGA controller. 1509 * 1510 * Note that we used to unhide the SMBus that way on Toshiba laptops 1511 * (Satellite A40 and Tecra M2) but then found that the thermal management 1512 * was done by SMM code, which could cause unsynchronized concurrent 1513 * accesses to the SMBus registers, with potentially bad effects. Thus you 1514 * should be very careful when adding new entries: if SMM is accessing the 1515 * Intel SMBus, this is a very good reason to leave it hidden. 1516 * 1517 * Likewise, many recent laptops use ACPI for thermal management. If the 1518 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1519 * natively, and keeping the SMBus hidden is the right thing to do. If you 1520 * are about to add an entry in the table below, please first disassemble 1521 * the DSDT and double-check that there is no code accessing the SMBus. 1522 */ 1523static int asus_hides_smbus; 1524 1525static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1526{ 1527 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1528 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1529 switch (dev->subsystem_device) { 1530 case 0x8025: /* P4B-LX */ 1531 case 0x8070: /* P4B */ 1532 case 0x8088: /* P4B533 */ 1533 case 0x1626: /* L3C notebook */ 1534 asus_hides_smbus = 1; 1535 } 1536 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1537 switch (dev->subsystem_device) { 1538 case 0x80b1: /* P4GE-V */ 1539 case 0x80b2: /* P4PE */ 1540 case 0x8093: /* P4B533-V */ 1541 asus_hides_smbus = 1; 1542 } 1543 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1544 switch (dev->subsystem_device) { 1545 case 0x8030: /* P4T533 */ 1546 asus_hides_smbus = 1; 1547 } 1548 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1549 switch (dev->subsystem_device) { 1550 case 0x8070: /* P4G8X Deluxe */ 1551 asus_hides_smbus = 1; 1552 } 1553 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1554 switch (dev->subsystem_device) { 1555 case 0x80c9: /* PU-DLS */ 1556 asus_hides_smbus = 1; 1557 } 1558 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1559 switch (dev->subsystem_device) { 1560 case 0x1751: /* M2N notebook */ 1561 case 0x1821: /* M5N notebook */ 1562 case 0x1897: /* A6L notebook */ 1563 asus_hides_smbus = 1; 1564 } 1565 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1566 switch (dev->subsystem_device) { 1567 case 0x184b: /* W1N notebook */ 1568 case 0x186a: /* M6Ne notebook */ 1569 asus_hides_smbus = 1; 1570 } 1571 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1572 switch (dev->subsystem_device) { 1573 case 0x80f2: /* P4P800-X */ 1574 asus_hides_smbus = 1; 1575 } 1576 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1577 switch (dev->subsystem_device) { 1578 case 0x1882: /* M6V notebook */ 1579 case 0x1977: /* A6VA notebook */ 1580 asus_hides_smbus = 1; 1581 } 1582 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1583 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1584 switch (dev->subsystem_device) { 1585 case 0x088C: /* HP Compaq nc8000 */ 1586 case 0x0890: /* HP Compaq nc6000 */ 1587 asus_hides_smbus = 1; 1588 } 1589 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1590 switch (dev->subsystem_device) { 1591 case 0x12bc: /* HP D330L */ 1592 case 0x12bd: /* HP D530 */ 1593 case 0x006a: /* HP Compaq nx9500 */ 1594 asus_hides_smbus = 1; 1595 } 1596 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1597 switch (dev->subsystem_device) { 1598 case 0x12bf: /* HP xw4100 */ 1599 asus_hides_smbus = 1; 1600 } 1601 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1602 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1603 switch (dev->subsystem_device) { 1604 case 0xC00C: /* Samsung P35 notebook */ 1605 asus_hides_smbus = 1; 1606 } 1607 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1608 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1609 switch (dev->subsystem_device) { 1610 case 0x0058: /* Compaq Evo N620c */ 1611 asus_hides_smbus = 1; 1612 } 1613 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1614 switch (dev->subsystem_device) { 1615 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1616 /* Motherboard doesn't have Host bridge 1617 * subvendor/subdevice IDs, therefore checking 1618 * its on-board VGA controller */ 1619 asus_hides_smbus = 1; 1620 } 1621 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1622 switch (dev->subsystem_device) { 1623 case 0x00b8: /* Compaq Evo D510 CMT */ 1624 case 0x00b9: /* Compaq Evo D510 SFF */ 1625 case 0x00ba: /* Compaq Evo D510 USDT */ 1626 /* Motherboard doesn't have Host bridge 1627 * subvendor/subdevice IDs and on-board VGA 1628 * controller is disabled if an AGP card is 1629 * inserted, therefore checking USB UHCI 1630 * Controller #1 */ 1631 asus_hides_smbus = 1; 1632 } 1633 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1634 switch (dev->subsystem_device) { 1635 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1636 /* Motherboard doesn't have host bridge 1637 * subvendor/subdevice IDs, therefore checking 1638 * its on-board VGA controller */ 1639 asus_hides_smbus = 1; 1640 } 1641 } 1642} 1643DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1644DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1645DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1646DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1647DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1648DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1650DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1651DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1652DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1653 1654DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1655DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1656DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1657 1658static void asus_hides_smbus_lpc(struct pci_dev *dev) 1659{ 1660 u16 val; 1661 1662 if (likely(!asus_hides_smbus)) 1663 return; 1664 1665 pci_read_config_word(dev, 0xF2, &val); 1666 if (val & 0x8) { 1667 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1668 pci_read_config_word(dev, 0xF2, &val); 1669 if (val & 0x8) 1670 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1671 val); 1672 else 1673 pci_info(dev, "Enabled i801 SMBus device\n"); 1674 } 1675} 1676DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1677DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1678DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1679DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1680DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1681DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1682DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1683DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1684DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1685DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1686DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1687DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1688DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1689DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1690 1691/* It appears we just have one such device. If not, we have a warning */ 1692static void __iomem *asus_rcba_base; 1693static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1694{ 1695 u32 rcba; 1696 1697 if (likely(!asus_hides_smbus)) 1698 return; 1699 WARN_ON(asus_rcba_base); 1700 1701 pci_read_config_dword(dev, 0xF0, &rcba); 1702 /* use bits 31:14, 16 kB aligned */ 1703 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1704 if (asus_rcba_base == NULL) 1705 return; 1706} 1707 1708static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1709{ 1710 u32 val; 1711 1712 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1713 return; 1714 1715 /* read the Function Disable register, dword mode only */ 1716 val = readl(asus_rcba_base + 0x3418); 1717 1718 /* enable the SMBus device */ 1719 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1720} 1721 1722static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1723{ 1724 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1725 return; 1726 1727 iounmap(asus_rcba_base); 1728 asus_rcba_base = NULL; 1729 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1730} 1731 1732static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1733{ 1734 asus_hides_smbus_lpc_ich6_suspend(dev); 1735 asus_hides_smbus_lpc_ich6_resume_early(dev); 1736 asus_hides_smbus_lpc_ich6_resume(dev); 1737} 1738DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1739DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1740DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1741DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1742 1743/* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1744static void quirk_sis_96x_smbus(struct pci_dev *dev) 1745{ 1746 u8 val = 0; 1747 pci_read_config_byte(dev, 0x77, &val); 1748 if (val & 0x10) { 1749 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1750 pci_write_config_byte(dev, 0x77, val & ~0x10); 1751 } 1752} 1753DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1754DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1755DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1756DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1757DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1758DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1759DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1760DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1761 1762/* 1763 * ... This is further complicated by the fact that some SiS96x south 1764 * bridges pretend to be 85C503/5513 instead. In that case see if we 1765 * spotted a compatible north bridge to make sure. 1766 * (pci_find_device() doesn't work yet) 1767 * 1768 * We can also enable the sis96x bit in the discovery register.. 1769 */ 1770#define SIS_DETECT_REGISTER 0x40 1771 1772static void quirk_sis_503(struct pci_dev *dev) 1773{ 1774 u8 reg; 1775 u16 devid; 1776 1777 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1778 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1779 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1780 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1781 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1782 return; 1783 } 1784 1785 /* 1786 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1787 * it has already been processed. (Depends on link order, which is 1788 * apparently not guaranteed) 1789 */ 1790 dev->device = devid; 1791 quirk_sis_96x_smbus(dev); 1792} 1793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1794DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1795 1796/* 1797 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1798 * and MC97 modem controller are disabled when a second PCI soundcard is 1799 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1800 * -- bjd 1801 */ 1802static void asus_hides_ac97_lpc(struct pci_dev *dev) 1803{ 1804 u8 val; 1805 int asus_hides_ac97 = 0; 1806 1807 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1808 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1809 asus_hides_ac97 = 1; 1810 } 1811 1812 if (!asus_hides_ac97) 1813 return; 1814 1815 pci_read_config_byte(dev, 0x50, &val); 1816 if (val & 0xc0) { 1817 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1818 pci_read_config_byte(dev, 0x50, &val); 1819 if (val & 0xc0) 1820 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1821 val); 1822 else 1823 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1824 } 1825} 1826DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1827DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1828 1829#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1830 1831/* 1832 * If we are using libata we can drive this chip properly but must do this 1833 * early on to make the additional device appear during the PCI scanning. 1834 */ 1835static void quirk_jmicron_ata(struct pci_dev *pdev) 1836{ 1837 u32 conf1, conf5, class; 1838 u8 hdr; 1839 1840 /* Only poke fn 0 */ 1841 if (PCI_FUNC(pdev->devfn)) 1842 return; 1843 1844 pci_read_config_dword(pdev, 0x40, &conf1); 1845 pci_read_config_dword(pdev, 0x80, &conf5); 1846 1847 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1848 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1849 1850 switch (pdev->device) { 1851 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1852 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1853 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1854 /* The controller should be in single function ahci mode */ 1855 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1856 break; 1857 1858 case PCI_DEVICE_ID_JMICRON_JMB365: 1859 case PCI_DEVICE_ID_JMICRON_JMB366: 1860 /* Redirect IDE second PATA port to the right spot */ 1861 conf5 |= (1 << 24); 1862 fallthrough; 1863 case PCI_DEVICE_ID_JMICRON_JMB361: 1864 case PCI_DEVICE_ID_JMICRON_JMB363: 1865 case PCI_DEVICE_ID_JMICRON_JMB369: 1866 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1867 /* Set the class codes correctly and then direct IDE 0 */ 1868 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1869 break; 1870 1871 case PCI_DEVICE_ID_JMICRON_JMB368: 1872 /* The controller should be in single function IDE mode */ 1873 conf1 |= 0x00C00000; /* Set 22, 23 */ 1874 break; 1875 } 1876 1877 pci_write_config_dword(pdev, 0x40, conf1); 1878 pci_write_config_dword(pdev, 0x80, conf5); 1879 1880 /* Update pdev accordingly */ 1881 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1882 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1883 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1884 1885 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1886 pdev->class = class >> 8; 1887} 1888DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1889DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1890DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1891DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1892DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1893DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1894DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1895DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1896DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1897DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1898DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1899DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1900DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1901DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1902DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1903DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1904DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1905DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1906 1907#endif 1908 1909static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1910{ 1911 if (dev->multifunction) { 1912 device_disable_async_suspend(&dev->dev); 1913 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1914 } 1915} 1916DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1917DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1918DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1919DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1920 1921#ifdef CONFIG_X86_IO_APIC 1922static void quirk_alder_ioapic(struct pci_dev *pdev) 1923{ 1924 int i; 1925 1926 if ((pdev->class >> 8) != 0xff00) 1927 return; 1928 1929 /* 1930 * The first BAR is the location of the IO-APIC... we must 1931 * not touch this (and it's already covered by the fixmap), so 1932 * forcibly insert it into the resource tree. 1933 */ 1934 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1935 insert_resource(&iomem_resource, &pdev->resource[0]); 1936 1937 /* 1938 * The next five BARs all seem to be rubbish, so just clean 1939 * them out. 1940 */ 1941 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1942 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1943} 1944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1945#endif 1946 1947static void quirk_no_msi(struct pci_dev *dev) 1948{ 1949 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1950 dev->no_msi = 1; 1951} 1952DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1953DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1954DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1955DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1956DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1957DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1958 1959static void quirk_pcie_mch(struct pci_dev *pdev) 1960{ 1961 pdev->no_msi = 1; 1962} 1963DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1964DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1965DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1966 1967DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1968 1969/* 1970 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1971 * actually on the AMBA bus. These fake PCI devices can support SVA via 1972 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1973 * 1974 * Normally stalling must not be enabled for PCI devices, since it would 1975 * break the PCI requirement for free-flowing writes and may lead to 1976 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1977 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1978 * even when a "PCI" device turns out to be a regular old SoC device 1979 * dressed up as a RCiEP and normal rules don't apply. 1980 */ 1981static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1982{ 1983 struct property_entry properties[] = { 1984 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1985 {}, 1986 }; 1987 1988 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1989 return; 1990 1991 pdev->pasid_no_tlp = 1; 1992 1993 /* 1994 * Set the dma-can-stall property on ACPI platforms. Device tree 1995 * can set it directly. 1996 */ 1997 if (!pdev->dev.of_node && 1998 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1999 pci_warn(pdev, "could not add stall property"); 2000} 2001DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 2002DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 2003DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 2004DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 2005DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 2006DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 2007 2008/* 2009 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2010 * together on certain PXH-based systems. 2011 */ 2012static void quirk_pcie_pxh(struct pci_dev *dev) 2013{ 2014 dev->no_msi = 1; 2015 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2016} 2017DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2018DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2019DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2020DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2021DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2022 2023/* 2024 * Some Intel PCI Express chipsets have trouble with downstream device 2025 * power management. 2026 */ 2027static void quirk_intel_pcie_pm(struct pci_dev *dev) 2028{ 2029 pci_pm_d3hot_delay = 120; 2030 dev->no_d1d2 = 1; 2031} 2032DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2033DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2045DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2046DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2048DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2049DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2051DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2053 2054static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2055{ 2056 if (dev->d3hot_delay >= delay) 2057 return; 2058 2059 dev->d3hot_delay = delay; 2060 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2061 dev->d3hot_delay); 2062} 2063 2064static void quirk_radeon_pm(struct pci_dev *dev) 2065{ 2066 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2067 dev->subsystem_device == 0x00e2) 2068 quirk_d3hot_delay(dev, 20); 2069} 2070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2071 2072/* 2073 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2074 * reset is performed too soon after transition to D0, extend d3hot_delay 2075 * to previous effective default for all NVIDIA HDA controllers. 2076 */ 2077static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2078{ 2079 quirk_d3hot_delay(dev, 20); 2080} 2081DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2082 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2083 quirk_nvidia_hda_pm); 2084 2085/* 2086 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2087 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2088 * 2089 * The kernel attempts to transition these devices to D3cold, but that seems 2090 * to be ineffective on the platforms in question; the PCI device appears to 2091 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2092 * extended delay in order to succeed. 2093 */ 2094static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2095{ 2096 quirk_d3hot_delay(dev, 20); 2097} 2098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2099DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2101 2102#ifdef CONFIG_X86_IO_APIC 2103static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2104{ 2105 noioapicreroute = 1; 2106 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2107 2108 return 0; 2109} 2110 2111static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2112 /* 2113 * Systems to exclude from boot interrupt reroute quirks 2114 */ 2115 { 2116 .callback = dmi_disable_ioapicreroute, 2117 .ident = "ASUSTek Computer INC. M2N-LR", 2118 .matches = { 2119 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2120 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2121 }, 2122 }, 2123 {} 2124}; 2125 2126/* 2127 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2128 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2129 * that a PCI device's interrupt handler is installed on the boot interrupt 2130 * line instead. 2131 */ 2132static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2133{ 2134 dmi_check_system(boot_interrupt_dmi_table); 2135 if (noioapicquirk || noioapicreroute) 2136 return; 2137 2138 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2139 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2140 dev->vendor, dev->device); 2141} 2142DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2143DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2150DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2151DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2152DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2153DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2154DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2155DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2156DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2157DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2158 2159/* 2160 * On some chipsets we can disable the generation of legacy INTx boot 2161 * interrupts. 2162 */ 2163 2164/* 2165 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2166 * 300641-004US, section 5.7.3. 2167 * 2168 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2169 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2170 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2171 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2172 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2173 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2174 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2175 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2176 * Core IO on Xeon Scalable, see Intel order no 610950. 2177 */ 2178#define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2179#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2180 2181#define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2182#define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2183 2184static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2185{ 2186 u16 pci_config_word; 2187 u32 pci_config_dword; 2188 2189 if (noioapicquirk) 2190 return; 2191 2192 switch (dev->device) { 2193 case PCI_DEVICE_ID_INTEL_ESB_10: 2194 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2195 &pci_config_word); 2196 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2197 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2198 pci_config_word); 2199 break; 2200 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2201 case 0x0e28: /* Xeon E5/E7 V2 */ 2202 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2203 case 0x6f28: /* Xeon D-1500 */ 2204 case 0x2034: /* Xeon Scalable Family */ 2205 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2206 &pci_config_dword); 2207 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2208 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2209 pci_config_dword); 2210 break; 2211 default: 2212 return; 2213 } 2214 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2215 dev->vendor, dev->device); 2216} 2217/* 2218 * Device 29 Func 5 Device IDs of IO-APIC 2219 * containing ABAR—APIC1 Alternate Base Address Register 2220 */ 2221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2222 quirk_disable_intel_boot_interrupt); 2223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2224 quirk_disable_intel_boot_interrupt); 2225 2226/* 2227 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2228 * containing Coherent Interface Protocol Interrupt Control 2229 * 2230 * Device IDs obtained from volume 2 datasheets of commented 2231 * families above. 2232 */ 2233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2234 quirk_disable_intel_boot_interrupt); 2235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2236 quirk_disable_intel_boot_interrupt); 2237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2238 quirk_disable_intel_boot_interrupt); 2239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2240 quirk_disable_intel_boot_interrupt); 2241DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2242 quirk_disable_intel_boot_interrupt); 2243DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2244 quirk_disable_intel_boot_interrupt); 2245DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2246 quirk_disable_intel_boot_interrupt); 2247DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2248 quirk_disable_intel_boot_interrupt); 2249DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2250 quirk_disable_intel_boot_interrupt); 2251DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2252 quirk_disable_intel_boot_interrupt); 2253 2254/* Disable boot interrupts on HT-1000 */ 2255#define BC_HT1000_FEATURE_REG 0x64 2256#define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2257#define BC_HT1000_MAP_IDX 0xC00 2258#define BC_HT1000_MAP_DATA 0xC01 2259 2260static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2261{ 2262 u32 pci_config_dword; 2263 u8 irq; 2264 2265 if (noioapicquirk) 2266 return; 2267 2268 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2269 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2270 BC_HT1000_PIC_REGS_ENABLE); 2271 2272 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2273 outb(irq, BC_HT1000_MAP_IDX); 2274 outb(0x00, BC_HT1000_MAP_DATA); 2275 } 2276 2277 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2278 2279 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2280 dev->vendor, dev->device); 2281} 2282DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2283DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2284 2285/* Disable boot interrupts on AMD and ATI chipsets */ 2286 2287/* 2288 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2289 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2290 * (due to an erratum). 2291 */ 2292#define AMD_813X_MISC 0x40 2293#define AMD_813X_NOIOAMODE (1<<0) 2294#define AMD_813X_REV_B1 0x12 2295#define AMD_813X_REV_B2 0x13 2296 2297static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2298{ 2299 u32 pci_config_dword; 2300 2301 if (noioapicquirk) 2302 return; 2303 if ((dev->revision == AMD_813X_REV_B1) || 2304 (dev->revision == AMD_813X_REV_B2)) 2305 return; 2306 2307 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2308 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2309 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2310 2311 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2312 dev->vendor, dev->device); 2313} 2314DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2315DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2317DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2318 2319#define AMD_8111_PCI_IRQ_ROUTING 0x56 2320 2321static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2322{ 2323 u16 pci_config_word; 2324 2325 if (noioapicquirk) 2326 return; 2327 2328 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2329 if (!pci_config_word) { 2330 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2331 dev->vendor, dev->device); 2332 return; 2333 } 2334 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2335 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2336 dev->vendor, dev->device); 2337} 2338DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2339DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2340#endif /* CONFIG_X86_IO_APIC */ 2341 2342/* 2343 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2344 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2345 * Re-allocate the region if needed... 2346 */ 2347static void quirk_tc86c001_ide(struct pci_dev *dev) 2348{ 2349 struct resource *r = &dev->resource[0]; 2350 2351 if (r->start & 0x8) { 2352 r->flags |= IORESOURCE_UNSET; 2353 resource_set_range(r, 0, SZ_16); 2354 } 2355} 2356DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2357 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2358 quirk_tc86c001_ide); 2359 2360/* 2361 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2362 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2363 * being read correctly if bit 7 of the base address is set. 2364 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2365 * Re-allocate the regions to a 256-byte boundary if necessary. 2366 */ 2367static void quirk_plx_pci9050(struct pci_dev *dev) 2368{ 2369 unsigned int bar; 2370 2371 /* Fixed in revision 2 (PCI 9052). */ 2372 if (dev->revision >= 2) 2373 return; 2374 for (bar = 0; bar <= 1; bar++) 2375 if (pci_resource_len(dev, bar) == 0x80 && 2376 (pci_resource_start(dev, bar) & 0x80)) { 2377 struct resource *r = &dev->resource[bar]; 2378 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2379 bar); 2380 r->flags |= IORESOURCE_UNSET; 2381 resource_set_range(r, 0, SZ_256); 2382 } 2383} 2384DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2385 quirk_plx_pci9050); 2386/* 2387 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2388 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2389 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2390 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2391 * 2392 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2393 * driver. 2394 */ 2395DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2396DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2397 2398static void quirk_netmos(struct pci_dev *dev) 2399{ 2400 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2401 unsigned int num_serial = dev->subsystem_device & 0xf; 2402 2403 /* 2404 * These Netmos parts are multiport serial devices with optional 2405 * parallel ports. Even when parallel ports are present, they 2406 * are identified as class SERIAL, which means the serial driver 2407 * will claim them. To prevent this, mark them as class OTHER. 2408 * These combo devices should be claimed by parport_serial. 2409 * 2410 * The subdevice ID is of the form 0x00PS, where <P> is the number 2411 * of parallel ports and <S> is the number of serial ports. 2412 */ 2413 switch (dev->device) { 2414 case PCI_DEVICE_ID_NETMOS_9835: 2415 /* Well, this rule doesn't hold for the following 9835 device */ 2416 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2417 dev->subsystem_device == 0x0299) 2418 return; 2419 fallthrough; 2420 case PCI_DEVICE_ID_NETMOS_9735: 2421 case PCI_DEVICE_ID_NETMOS_9745: 2422 case PCI_DEVICE_ID_NETMOS_9845: 2423 case PCI_DEVICE_ID_NETMOS_9855: 2424 if (num_parallel) { 2425 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2426 dev->device, num_parallel, num_serial); 2427 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2428 (dev->class & 0xff); 2429 } 2430 } 2431} 2432DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2433 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2434 2435static void quirk_e100_interrupt(struct pci_dev *dev) 2436{ 2437 u16 command, pmcsr; 2438 u8 __iomem *csr; 2439 u8 cmd_hi; 2440 2441 switch (dev->device) { 2442 /* PCI IDs taken from drivers/net/e100.c */ 2443 case 0x1029: 2444 case 0x1030 ... 0x1034: 2445 case 0x1038 ... 0x103E: 2446 case 0x1050 ... 0x1057: 2447 case 0x1059: 2448 case 0x1064 ... 0x106B: 2449 case 0x1091 ... 0x1095: 2450 case 0x1209: 2451 case 0x1229: 2452 case 0x2449: 2453 case 0x2459: 2454 case 0x245D: 2455 case 0x27DC: 2456 break; 2457 default: 2458 return; 2459 } 2460 2461 /* 2462 * Some firmware hands off the e100 with interrupts enabled, 2463 * which can cause a flood of interrupts if packets are 2464 * received before the driver attaches to the device. So 2465 * disable all e100 interrupts here. The driver will 2466 * re-enable them when it's ready. 2467 */ 2468 pci_read_config_word(dev, PCI_COMMAND, &command); 2469 2470 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2471 return; 2472 2473 /* 2474 * Check that the device is in the D0 power state. If it's not, 2475 * there is no point to look any further. 2476 */ 2477 if (dev->pm_cap) { 2478 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2479 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2480 return; 2481 } 2482 2483 /* Convert from PCI bus to resource space. */ 2484 csr = ioremap(pci_resource_start(dev, 0), 8); 2485 if (!csr) { 2486 pci_warn(dev, "Can't map e100 registers\n"); 2487 return; 2488 } 2489 2490 cmd_hi = readb(csr + 3); 2491 if (cmd_hi == 0) { 2492 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2493 writeb(1, csr + 3); 2494 } 2495 2496 iounmap(csr); 2497} 2498DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2499 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2500 2501/* 2502 * The 82575 and 82598 may experience data corruption issues when transitioning 2503 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2504 */ 2505static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2506{ 2507 pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S); 2508} 2509DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2521DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2522DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2523 2524static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2525{ 2526 pcie_aspm_remove_cap(dev, 2527 PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); 2528} 2529 2530/* 2531 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2532 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2533 * disable both L0s and L1 for now to be safe. 2534 */ 2535DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2536DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); 2537DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); 2538DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); 2539 2540/* 2541 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2542 * Link bit cleared after starting the link retrain process to allow this 2543 * process to finish. 2544 * 2545 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2546 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2547 */ 2548static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2549{ 2550 dev->clear_retrain_link = 1; 2551 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2552} 2553DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2554DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2555DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2556 2557static void fixup_rev1_53c810(struct pci_dev *dev) 2558{ 2559 u32 class = dev->class; 2560 2561 /* 2562 * rev 1 ncr53c810 chips don't set the class at all which means 2563 * they don't get their resources remapped. Fix that here. 2564 */ 2565 if (class) 2566 return; 2567 2568 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2569 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2570 class, dev->class); 2571} 2572DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2573 2574/* Enable 1k I/O space granularity on the Intel P64H2 */ 2575static void quirk_p64h2_1k_io(struct pci_dev *dev) 2576{ 2577 u16 en1k; 2578 2579 pci_read_config_word(dev, 0x40, &en1k); 2580 2581 if (en1k & 0x200) { 2582 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2583 dev->io_window_1k = 1; 2584 } 2585} 2586DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2587 2588/* 2589 * Under some circumstances, AER is not linked with extended capabilities. 2590 * Force it to be linked by setting the corresponding control bit in the 2591 * config space. 2592 */ 2593static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2594{ 2595 uint8_t b; 2596 2597 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2598 if (!(b & 0x20)) { 2599 pci_write_config_byte(dev, 0xf41, b | 0x20); 2600 pci_info(dev, "Linking AER extended capability\n"); 2601 } 2602 } 2603} 2604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2605 quirk_nvidia_ck804_pcie_aer_ext_cap); 2606DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2607 quirk_nvidia_ck804_pcie_aer_ext_cap); 2608 2609static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2610{ 2611 /* 2612 * Disable PCI Bus Parking and PCI Master read caching on CX700 2613 * which causes unspecified timing errors with a VT6212L on the PCI 2614 * bus leading to USB2.0 packet loss. 2615 * 2616 * This quirk is only enabled if a second (on the external PCI bus) 2617 * VT6212L is found -- the CX700 core itself also contains a USB 2618 * host controller with the same PCI ID as the VT6212L. 2619 */ 2620 2621 /* Count VT6212L instances */ 2622 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2623 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2624 uint8_t b; 2625 2626 /* 2627 * p should contain the first (internal) VT6212L -- see if we have 2628 * an external one by searching again. 2629 */ 2630 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2631 if (!p) 2632 return; 2633 pci_dev_put(p); 2634 2635 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2636 if (b & 0x40) { 2637 /* Turn off PCI Bus Parking */ 2638 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2639 2640 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2641 } 2642 } 2643 2644 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2645 if (b != 0) { 2646 /* Turn off PCI Master read caching */ 2647 pci_write_config_byte(dev, 0x72, 0x0); 2648 2649 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2650 pci_write_config_byte(dev, 0x75, 0x1); 2651 2652 /* Disable "Read FIFO Timer" */ 2653 pci_write_config_byte(dev, 0x77, 0x0); 2654 2655 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2656 } 2657 } 2658} 2659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2660 2661static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2662{ 2663 u32 rev; 2664 2665 pci_read_config_dword(dev, 0xf4, &rev); 2666 2667 /* Only CAP the MRRS if the device is a 5719 A0 */ 2668 if (rev == 0x05719000) { 2669 int readrq = pcie_get_readrq(dev); 2670 if (readrq > 2048) 2671 pcie_set_readrq(dev, 2048); 2672 } 2673} 2674DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2675 PCI_DEVICE_ID_TIGON3_5719, 2676 quirk_brcm_5719_limit_mrrs); 2677 2678/* 2679 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2680 * hide device 6 which configures the overflow device access containing the 2681 * DRBs - this is where we expose device 6. 2682 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2683 */ 2684static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2685{ 2686 u8 reg; 2687 2688 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2689 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2690 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2691 } 2692} 2693DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2694 quirk_unhide_mch_dev6); 2695DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2696 quirk_unhide_mch_dev6); 2697 2698#ifdef CONFIG_PCI_MSI 2699/* 2700 * Some chipsets do not support MSI. We cannot easily rely on setting 2701 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2702 * other buses controlled by the chipset even if Linux is not aware of it. 2703 * Instead of setting the flag on all buses in the machine, simply disable 2704 * MSI globally. 2705 */ 2706static void quirk_disable_all_msi(struct pci_dev *dev) 2707{ 2708 pci_no_msi(); 2709 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2710} 2711DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2712DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2713DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2714DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2715DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2716DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2717DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2718DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2719DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2720 2721/* Disable MSI on chipsets that are known to not support it */ 2722static void quirk_disable_msi(struct pci_dev *dev) 2723{ 2724 if (dev->subordinate) { 2725 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2726 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2727 } 2728} 2729DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2730DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2731DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2732DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); 2733 2734/* 2735 * The APC bridge device in AMD 780 family northbridges has some random 2736 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2737 * we use the possible vendor/device IDs of the host bridge for the 2738 * declared quirk, and search for the APC bridge by slot number. 2739 */ 2740static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2741{ 2742 struct pci_dev *apc_bridge; 2743 2744 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2745 if (apc_bridge) { 2746 if (apc_bridge->device == 0x9602) 2747 quirk_disable_msi(apc_bridge); 2748 pci_dev_put(apc_bridge); 2749 } 2750} 2751DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2752DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2753 2754/* 2755 * Go through the list of HyperTransport capabilities and return 1 if a HT 2756 * MSI capability is found and enabled. 2757 */ 2758static int msi_ht_cap_enabled(struct pci_dev *dev) 2759{ 2760 int pos, ttl = PCI_FIND_CAP_TTL; 2761 2762 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2763 while (pos && ttl--) { 2764 u8 flags; 2765 2766 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2767 &flags) == 0) { 2768 pci_info(dev, "Found %s HT MSI Mapping\n", 2769 flags & HT_MSI_FLAGS_ENABLE ? 2770 "enabled" : "disabled"); 2771 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2772 } 2773 2774 pos = pci_find_next_ht_capability(dev, pos, 2775 HT_CAPTYPE_MSI_MAPPING); 2776 } 2777 return 0; 2778} 2779 2780/* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2781static void quirk_msi_ht_cap(struct pci_dev *dev) 2782{ 2783 if (!msi_ht_cap_enabled(dev)) 2784 quirk_disable_msi(dev); 2785} 2786DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2787 quirk_msi_ht_cap); 2788 2789/* 2790 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2791 * if the MSI capability is set in any of these mappings. 2792 */ 2793static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2794{ 2795 struct pci_dev *pdev; 2796 2797 /* 2798 * Check HT MSI cap on this chipset and the root one. A single one 2799 * having MSI is enough to be sure that MSI is supported. 2800 */ 2801 pdev = pci_get_slot(dev->bus, 0); 2802 if (!pdev) 2803 return; 2804 if (!msi_ht_cap_enabled(pdev)) 2805 quirk_msi_ht_cap(dev); 2806 pci_dev_put(pdev); 2807} 2808DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2809 quirk_nvidia_ck804_msi_ht_cap); 2810 2811/* Force enable MSI mapping capability on HT bridges */ 2812static void ht_enable_msi_mapping(struct pci_dev *dev) 2813{ 2814 int pos, ttl = PCI_FIND_CAP_TTL; 2815 2816 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2817 while (pos && ttl--) { 2818 u8 flags; 2819 2820 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2821 &flags) == 0) { 2822 pci_info(dev, "Enabling HT MSI Mapping\n"); 2823 2824 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2825 flags | HT_MSI_FLAGS_ENABLE); 2826 } 2827 pos = pci_find_next_ht_capability(dev, pos, 2828 HT_CAPTYPE_MSI_MAPPING); 2829 } 2830} 2831DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2832 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2833 ht_enable_msi_mapping); 2834DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2835 ht_enable_msi_mapping); 2836 2837/* 2838 * The P5N32-SLI motherboards from Asus have a problem with MSI 2839 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2840 * also affects other devices. As for now, turn off MSI for this device. 2841 */ 2842static void nvenet_msi_disable(struct pci_dev *dev) 2843{ 2844 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2845 2846 if (board_name && 2847 (strstr(board_name, "P5N32-SLI PREMIUM") || 2848 strstr(board_name, "P5N32-E SLI"))) { 2849 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2850 dev->no_msi = 1; 2851 } 2852} 2853DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2854 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2855 nvenet_msi_disable); 2856 2857/* 2858 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2859 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2860 * interrupts for PME and AER events; instead only INTx interrupts are 2861 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2862 * for other events, since PCIe specification doesn't support using a mix of 2863 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2864 * service drivers registering their respective ISRs for MSIs. 2865 */ 2866static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2867{ 2868 dev->no_msi = 1; 2869} 2870DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2871 PCI_CLASS_BRIDGE_PCI, 8, 2872 pci_quirk_nvidia_tegra_disable_rp_msi); 2873DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2874 PCI_CLASS_BRIDGE_PCI, 8, 2875 pci_quirk_nvidia_tegra_disable_rp_msi); 2876DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2877 PCI_CLASS_BRIDGE_PCI, 8, 2878 pci_quirk_nvidia_tegra_disable_rp_msi); 2879DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2880 PCI_CLASS_BRIDGE_PCI, 8, 2881 pci_quirk_nvidia_tegra_disable_rp_msi); 2882DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2883 PCI_CLASS_BRIDGE_PCI, 8, 2884 pci_quirk_nvidia_tegra_disable_rp_msi); 2885DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2886 PCI_CLASS_BRIDGE_PCI, 8, 2887 pci_quirk_nvidia_tegra_disable_rp_msi); 2888DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2889 PCI_CLASS_BRIDGE_PCI, 8, 2890 pci_quirk_nvidia_tegra_disable_rp_msi); 2891DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2892 PCI_CLASS_BRIDGE_PCI, 8, 2893 pci_quirk_nvidia_tegra_disable_rp_msi); 2894DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2895 PCI_CLASS_BRIDGE_PCI, 8, 2896 pci_quirk_nvidia_tegra_disable_rp_msi); 2897DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2898 PCI_CLASS_BRIDGE_PCI, 8, 2899 pci_quirk_nvidia_tegra_disable_rp_msi); 2900DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2901 PCI_CLASS_BRIDGE_PCI, 8, 2902 pci_quirk_nvidia_tegra_disable_rp_msi); 2903DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2904 PCI_CLASS_BRIDGE_PCI, 8, 2905 pci_quirk_nvidia_tegra_disable_rp_msi); 2906DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2907 PCI_CLASS_BRIDGE_PCI, 8, 2908 pci_quirk_nvidia_tegra_disable_rp_msi); 2909DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2910 PCI_CLASS_BRIDGE_PCI, 8, 2911 pci_quirk_nvidia_tegra_disable_rp_msi); 2912DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2913 PCI_CLASS_BRIDGE_PCI, 8, 2914 pci_quirk_nvidia_tegra_disable_rp_msi); 2915DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2916 PCI_CLASS_BRIDGE_PCI, 8, 2917 pci_quirk_nvidia_tegra_disable_rp_msi); 2918 2919/* 2920 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2921 * config register. This register controls the routing of legacy 2922 * interrupts from devices that route through the MCP55. If this register 2923 * is misprogrammed, interrupts are only sent to the BSP, unlike 2924 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2925 * having this register set properly prevents kdump from booting up 2926 * properly, so let's make sure that we have it set correctly. 2927 * Note that this is an undocumented register. 2928 */ 2929static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2930{ 2931 u32 cfg; 2932 2933 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2934 return; 2935 2936 pci_read_config_dword(dev, 0x74, &cfg); 2937 2938 if (cfg & ((1 << 2) | (1 << 15))) { 2939 pr_info("Rewriting IRQ routing register on MCP55\n"); 2940 cfg &= ~((1 << 2) | (1 << 15)); 2941 pci_write_config_dword(dev, 0x74, cfg); 2942 } 2943} 2944DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2945 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2946 nvbridge_check_legacy_irq_routing); 2947DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2948 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2949 nvbridge_check_legacy_irq_routing); 2950 2951static int ht_check_msi_mapping(struct pci_dev *dev) 2952{ 2953 int pos, ttl = PCI_FIND_CAP_TTL; 2954 int found = 0; 2955 2956 /* Check if there is HT MSI cap or enabled on this device */ 2957 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2958 while (pos && ttl--) { 2959 u8 flags; 2960 2961 if (found < 1) 2962 found = 1; 2963 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2964 &flags) == 0) { 2965 if (flags & HT_MSI_FLAGS_ENABLE) { 2966 if (found < 2) { 2967 found = 2; 2968 break; 2969 } 2970 } 2971 } 2972 pos = pci_find_next_ht_capability(dev, pos, 2973 HT_CAPTYPE_MSI_MAPPING); 2974 } 2975 2976 return found; 2977} 2978 2979static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2980{ 2981 struct pci_dev *dev; 2982 int pos; 2983 int i, dev_no; 2984 int found = 0; 2985 2986 dev_no = host_bridge->devfn >> 3; 2987 for (i = dev_no + 1; i < 0x20; i++) { 2988 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2989 if (!dev) 2990 continue; 2991 2992 /* found next host bridge? */ 2993 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2994 if (pos != 0) { 2995 pci_dev_put(dev); 2996 break; 2997 } 2998 2999 if (ht_check_msi_mapping(dev)) { 3000 found = 1; 3001 pci_dev_put(dev); 3002 break; 3003 } 3004 pci_dev_put(dev); 3005 } 3006 3007 return found; 3008} 3009 3010#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3011#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3012 3013static int is_end_of_ht_chain(struct pci_dev *dev) 3014{ 3015 int pos, ctrl_off; 3016 int end = 0; 3017 u16 flags, ctrl; 3018 3019 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3020 3021 if (!pos) 3022 goto out; 3023 3024 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3025 3026 ctrl_off = ((flags >> 10) & 1) ? 3027 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3028 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3029 3030 if (ctrl & (1 << 6)) 3031 end = 1; 3032 3033out: 3034 return end; 3035} 3036 3037static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3038{ 3039 struct pci_dev *host_bridge; 3040 int pos; 3041 int i, dev_no; 3042 int found = 0; 3043 3044 dev_no = dev->devfn >> 3; 3045 for (i = dev_no; i >= 0; i--) { 3046 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3047 if (!host_bridge) 3048 continue; 3049 3050 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3051 if (pos != 0) { 3052 found = 1; 3053 break; 3054 } 3055 pci_dev_put(host_bridge); 3056 } 3057 3058 if (!found) 3059 return; 3060 3061 /* don't enable end_device/host_bridge with leaf directly here */ 3062 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3063 host_bridge_with_leaf(host_bridge)) 3064 goto out; 3065 3066 /* root did that ! */ 3067 if (msi_ht_cap_enabled(host_bridge)) 3068 goto out; 3069 3070 ht_enable_msi_mapping(dev); 3071 3072out: 3073 pci_dev_put(host_bridge); 3074} 3075 3076static void ht_disable_msi_mapping(struct pci_dev *dev) 3077{ 3078 int pos, ttl = PCI_FIND_CAP_TTL; 3079 3080 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3081 while (pos && ttl--) { 3082 u8 flags; 3083 3084 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3085 &flags) == 0) { 3086 pci_info(dev, "Disabling HT MSI Mapping\n"); 3087 3088 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3089 flags & ~HT_MSI_FLAGS_ENABLE); 3090 } 3091 pos = pci_find_next_ht_capability(dev, pos, 3092 HT_CAPTYPE_MSI_MAPPING); 3093 } 3094} 3095 3096static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3097{ 3098 struct pci_dev *host_bridge; 3099 int pos; 3100 int found; 3101 3102 if (!pci_msi_enabled()) 3103 return; 3104 3105 /* check if there is HT MSI cap or enabled on this device */ 3106 found = ht_check_msi_mapping(dev); 3107 3108 /* no HT MSI CAP */ 3109 if (found == 0) 3110 return; 3111 3112 /* 3113 * HT MSI mapping should be disabled on devices that are below 3114 * a non-HyperTransport host bridge. Locate the host bridge. 3115 */ 3116 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3117 PCI_DEVFN(0, 0)); 3118 if (host_bridge == NULL) { 3119 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3120 return; 3121 } 3122 3123 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3124 if (pos != 0) { 3125 /* Host bridge is to HT */ 3126 if (found == 1) { 3127 /* it is not enabled, try to enable it */ 3128 if (all) 3129 ht_enable_msi_mapping(dev); 3130 else 3131 nv_ht_enable_msi_mapping(dev); 3132 } 3133 goto out; 3134 } 3135 3136 /* HT MSI is not enabled */ 3137 if (found == 1) 3138 goto out; 3139 3140 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3141 ht_disable_msi_mapping(dev); 3142 3143out: 3144 pci_dev_put(host_bridge); 3145} 3146 3147static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3148{ 3149 return __nv_msi_ht_cap_quirk(dev, 1); 3150} 3151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3152DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3153 3154static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3155{ 3156 return __nv_msi_ht_cap_quirk(dev, 0); 3157} 3158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3159DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3160 3161static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3162{ 3163 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3164} 3165 3166static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3167{ 3168 struct pci_dev *p; 3169 3170 /* 3171 * SB700 MSI issue will be fixed at HW level from revision A21; 3172 * we need check PCI REVISION ID of SMBus controller to get SB700 3173 * revision. 3174 */ 3175 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3176 NULL); 3177 if (!p) 3178 return; 3179 3180 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3181 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3182 pci_dev_put(p); 3183} 3184 3185static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3186{ 3187 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3188 if (dev->revision < 0x18) { 3189 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3190 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3191 } 3192} 3193DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3194 PCI_DEVICE_ID_TIGON3_5780, 3195 quirk_msi_intx_disable_bug); 3196DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3197 PCI_DEVICE_ID_TIGON3_5780S, 3198 quirk_msi_intx_disable_bug); 3199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3200 PCI_DEVICE_ID_TIGON3_5714, 3201 quirk_msi_intx_disable_bug); 3202DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3203 PCI_DEVICE_ID_TIGON3_5714S, 3204 quirk_msi_intx_disable_bug); 3205DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3206 PCI_DEVICE_ID_TIGON3_5715, 3207 quirk_msi_intx_disable_bug); 3208DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3209 PCI_DEVICE_ID_TIGON3_5715S, 3210 quirk_msi_intx_disable_bug); 3211 3212DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3213 quirk_msi_intx_disable_ati_bug); 3214DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3215 quirk_msi_intx_disable_ati_bug); 3216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3217 quirk_msi_intx_disable_ati_bug); 3218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3219 quirk_msi_intx_disable_ati_bug); 3220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3221 quirk_msi_intx_disable_ati_bug); 3222 3223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3224 quirk_msi_intx_disable_bug); 3225DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3226 quirk_msi_intx_disable_bug); 3227DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3228 quirk_msi_intx_disable_bug); 3229 3230DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3231 quirk_msi_intx_disable_bug); 3232DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3233 quirk_msi_intx_disable_bug); 3234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3235 quirk_msi_intx_disable_bug); 3236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3237 quirk_msi_intx_disable_bug); 3238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3239 quirk_msi_intx_disable_bug); 3240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3241 quirk_msi_intx_disable_bug); 3242DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3243 quirk_msi_intx_disable_qca_bug); 3244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3245 quirk_msi_intx_disable_qca_bug); 3246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3247 quirk_msi_intx_disable_qca_bug); 3248DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3249 quirk_msi_intx_disable_qca_bug); 3250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3251 quirk_msi_intx_disable_qca_bug); 3252 3253/* 3254 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3255 * should be disabled on platforms where the device (mistakenly) advertises it. 3256 * 3257 * Notice that this quirk also disables MSI (which may work, but hasn't been 3258 * tested), since currently there is no standard way to disable only MSI-X. 3259 * 3260 * The 0031 device id is reused for other non Root Port device types, 3261 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3262 */ 3263static void quirk_al_msi_disable(struct pci_dev *dev) 3264{ 3265 dev->no_msi = 1; 3266 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3267} 3268DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3269 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3270#endif /* CONFIG_PCI_MSI */ 3271 3272/* 3273 * Allow manual resource allocation for PCI hotplug bridges via 3274 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3275 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3276 * allocate resources when hotplug device is inserted and PCI bus is 3277 * rescanned. 3278 */ 3279static void quirk_hotplug_bridge(struct pci_dev *dev) 3280{ 3281 dev->is_hotplug_bridge = 1; 3282} 3283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3284 3285/* 3286 * This is a quirk for the Ricoh MMC controller found as a part of some 3287 * multifunction chips. 3288 * 3289 * This is very similar and based on the ricoh_mmc driver written by 3290 * Philip Langdale. Thank you for these magic sequences. 3291 * 3292 * These chips implement the four main memory card controllers (SD, MMC, 3293 * MS, xD) and one or both of CardBus or FireWire. 3294 * 3295 * It happens that they implement SD and MMC support as separate 3296 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3297 * cards but the chip detects MMC cards in hardware and directs them to the 3298 * MMC controller - so the SDHCI driver never sees them. 3299 * 3300 * To get around this, we must disable the useless MMC controller. At that 3301 * point, the SDHCI controller will start seeing them. It seems to be the 3302 * case that the relevant PCI registers to deactivate the MMC controller 3303 * live on PCI function 0, which might be the CardBus controller or the 3304 * FireWire controller, depending on the particular chip in question 3305 * 3306 * This has to be done early, because as soon as we disable the MMC controller 3307 * other PCI functions shift up one level, e.g. function #2 becomes function 3308 * #1, and this will confuse the PCI core. 3309 */ 3310#ifdef CONFIG_MMC_RICOH_MMC 3311static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3312{ 3313 u8 write_enable; 3314 u8 write_target; 3315 u8 disable; 3316 3317 /* 3318 * Disable via CardBus interface 3319 * 3320 * This must be done via function #0 3321 */ 3322 if (PCI_FUNC(dev->devfn)) 3323 return; 3324 3325 pci_read_config_byte(dev, 0xB7, &disable); 3326 if (disable & 0x02) 3327 return; 3328 3329 pci_read_config_byte(dev, 0x8E, &write_enable); 3330 pci_write_config_byte(dev, 0x8E, 0xAA); 3331 pci_read_config_byte(dev, 0x8D, &write_target); 3332 pci_write_config_byte(dev, 0x8D, 0xB7); 3333 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3334 pci_write_config_byte(dev, 0x8E, write_enable); 3335 pci_write_config_byte(dev, 0x8D, write_target); 3336 3337 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3338 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3339} 3340DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3341DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3342 3343static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3344{ 3345 u8 write_enable; 3346 u8 disable; 3347 3348 /* 3349 * Disable via FireWire interface 3350 * 3351 * This must be done via function #0 3352 */ 3353 if (PCI_FUNC(dev->devfn)) 3354 return; 3355 /* 3356 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3357 * certain types of SD/MMC cards. Lowering the SD base clock 3358 * frequency from 200Mhz to 50Mhz fixes this issue. 3359 * 3360 * 0x150 - SD2.0 mode enable for changing base clock 3361 * frequency to 50Mhz 3362 * 0xe1 - Base clock frequency 3363 * 0x32 - 50Mhz new clock frequency 3364 * 0xf9 - Key register for 0x150 3365 * 0xfc - key register for 0xe1 3366 */ 3367 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3368 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3369 pci_write_config_byte(dev, 0xf9, 0xfc); 3370 pci_write_config_byte(dev, 0x150, 0x10); 3371 pci_write_config_byte(dev, 0xf9, 0x00); 3372 pci_write_config_byte(dev, 0xfc, 0x01); 3373 pci_write_config_byte(dev, 0xe1, 0x32); 3374 pci_write_config_byte(dev, 0xfc, 0x00); 3375 3376 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3377 } 3378 3379 pci_read_config_byte(dev, 0xCB, &disable); 3380 3381 if (disable & 0x02) 3382 return; 3383 3384 pci_read_config_byte(dev, 0xCA, &write_enable); 3385 pci_write_config_byte(dev, 0xCA, 0x57); 3386 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3387 pci_write_config_byte(dev, 0xCA, write_enable); 3388 3389 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3390 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3391 3392} 3393DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3394DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3395DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3396DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3397DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3398DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3399#endif /*CONFIG_MMC_RICOH_MMC*/ 3400 3401#ifdef CONFIG_DMAR_TABLE 3402#define VTUNCERRMSK_REG 0x1ac 3403#define VTD_MSK_SPEC_ERRORS (1 << 31) 3404/* 3405 * This is a quirk for masking VT-d spec-defined errors to platform error 3406 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3407 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3408 * on the RAS config settings of the platform) when a VT-d fault happens. 3409 * The resulting SMI caused the system to hang. 3410 * 3411 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3412 * need to report the same error through other channels. 3413 */ 3414static void vtd_mask_spec_errors(struct pci_dev *dev) 3415{ 3416 u32 word; 3417 3418 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3419 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3420} 3421DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3422DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3423#endif 3424 3425static void fixup_ti816x_class(struct pci_dev *dev) 3426{ 3427 u32 class = dev->class; 3428 3429 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3430 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3431 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3432 class, dev->class); 3433} 3434DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3435 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3436 3437/* 3438 * Some PCIe devices do not work reliably with the claimed maximum 3439 * payload size supported. 3440 */ 3441static void fixup_mpss_256(struct pci_dev *dev) 3442{ 3443 dev->pcie_mpss = 1; /* 256 bytes */ 3444} 3445DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3446 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3447DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3448 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3449DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3450 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3451DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3452 3453/* 3454 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3455 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3456 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3457 * until all of the devices are discovered and buses walked, read completion 3458 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3459 * it is possible to hotplug a device with MPS of 256B. 3460 */ 3461static void quirk_intel_mc_errata(struct pci_dev *dev) 3462{ 3463 int err; 3464 u16 rcc; 3465 3466 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3467 pcie_bus_config == PCIE_BUS_DEFAULT) 3468 return; 3469 3470 /* 3471 * Intel erratum specifies bits to change but does not say what 3472 * they are. Keeping them magical until such time as the registers 3473 * and values can be explained. 3474 */ 3475 err = pci_read_config_word(dev, 0x48, &rcc); 3476 if (err) { 3477 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3478 return; 3479 } 3480 3481 if (!(rcc & (1 << 10))) 3482 return; 3483 3484 rcc &= ~(1 << 10); 3485 3486 err = pci_write_config_word(dev, 0x48, rcc); 3487 if (err) { 3488 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3489 return; 3490 } 3491 3492 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3493} 3494/* Intel 5000 series memory controllers and ports 2-7 */ 3495DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3496DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3497DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3498DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3499DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3500DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3501DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3502DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3503DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3504DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3505DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3506DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3507DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3508DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3509/* Intel 5100 series memory controllers and ports 2-7 */ 3510DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3511DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3513DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3514DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3515DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3516DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3517DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3518DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3519DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3520DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3521 3522/* 3523 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3524 * To work around this, query the size it should be configured to by the 3525 * device and modify the resource end to correspond to this new size. 3526 */ 3527static void quirk_intel_ntb(struct pci_dev *dev) 3528{ 3529 int rc; 3530 u8 val; 3531 3532 rc = pci_read_config_byte(dev, 0x00D0, &val); 3533 if (rc) 3534 return; 3535 3536 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3537 3538 rc = pci_read_config_byte(dev, 0x00D1, &val); 3539 if (rc) 3540 return; 3541 3542 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3543} 3544DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3545DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3546 3547/* 3548 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3549 * though no one is handling them (e.g., if the i915 driver is never 3550 * loaded). Additionally the interrupt destination is not set up properly 3551 * and the interrupt ends up -somewhere-. 3552 * 3553 * These spurious interrupts are "sticky" and the kernel disables the 3554 * (shared) interrupt line after 100,000+ generated interrupts. 3555 * 3556 * Fix it by disabling the still enabled interrupts. This resolves crashes 3557 * often seen on monitor unplug. 3558 */ 3559#define I915_DEIER_REG 0x4400c 3560static void disable_igfx_irq(struct pci_dev *dev) 3561{ 3562 void __iomem *regs = pci_iomap(dev, 0, 0); 3563 if (regs == NULL) { 3564 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3565 return; 3566 } 3567 3568 /* Check if any interrupt line is still enabled */ 3569 if (readl(regs + I915_DEIER_REG) != 0) { 3570 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3571 3572 writel(0, regs + I915_DEIER_REG); 3573 } 3574 3575 pci_iounmap(dev, regs); 3576} 3577DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3578DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3579DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3580DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3581DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3582DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3583DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3584 3585/* 3586 * PCI devices which are on Intel chips can skip the 10ms delay 3587 * before entering D3 mode. 3588 */ 3589static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3590{ 3591 dev->d3hot_delay = 0; 3592} 3593/* C600 Series devices do not need 10ms d3hot_delay */ 3594DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3595DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3596DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3597/* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3598DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3599DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3600DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3601DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3602DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3603DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3604DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3607DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3608DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3609/* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3610DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3611DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3612DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3613DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3614DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3615DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3616DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3617DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3618DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3619 3620/* 3621 * Some devices may pass our check in pci_intx_mask_supported() if 3622 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3623 * support this feature. 3624 */ 3625static void quirk_broken_intx_masking(struct pci_dev *dev) 3626{ 3627 dev->broken_intx_masking = 1; 3628} 3629DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3630 quirk_broken_intx_masking); 3631DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3632 quirk_broken_intx_masking); 3633DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3634 quirk_broken_intx_masking); 3635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3636 quirk_broken_intx_masking); 3637 3638/* 3639 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3640 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3641 * 3642 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3643 */ 3644DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3645 quirk_broken_intx_masking); 3646 3647/* 3648 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3649 * DisINTx can be set but the interrupt status bit is non-functional. 3650 */ 3651DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3653DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3667 3668static u16 mellanox_broken_intx_devs[] = { 3669 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3670 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3671 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3672 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3673 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3674 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3675 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3676 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3677 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3678 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3679 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3680 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3681 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3682 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3683}; 3684 3685#define CONNECTX_4_CURR_MAX_MINOR 99 3686#define CONNECTX_4_INTX_SUPPORT_MINOR 14 3687 3688/* 3689 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3690 * If so, don't mark it as broken. 3691 * FW minor > 99 means older FW version format and no INTx masking support. 3692 * FW minor < 14 means new FW version format and no INTx masking support. 3693 */ 3694static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3695{ 3696 __be32 __iomem *fw_ver; 3697 u16 fw_major; 3698 u16 fw_minor; 3699 u16 fw_subminor; 3700 u32 fw_maj_min; 3701 u32 fw_sub_min; 3702 int i; 3703 3704 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3705 if (pdev->device == mellanox_broken_intx_devs[i]) { 3706 pdev->broken_intx_masking = 1; 3707 return; 3708 } 3709 } 3710 3711 /* 3712 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3713 * support so shouldn't be checked further 3714 */ 3715 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3716 return; 3717 3718 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3719 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3720 return; 3721 3722 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3723 if (pci_enable_device_mem(pdev)) { 3724 pci_warn(pdev, "Can't enable device memory\n"); 3725 return; 3726 } 3727 3728 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3729 if (!fw_ver) { 3730 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3731 goto out; 3732 } 3733 3734 /* Reading from resource space should be 32b aligned */ 3735 fw_maj_min = ioread32be(fw_ver); 3736 fw_sub_min = ioread32be(fw_ver + 1); 3737 fw_major = fw_maj_min & 0xffff; 3738 fw_minor = fw_maj_min >> 16; 3739 fw_subminor = fw_sub_min & 0xffff; 3740 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3741 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3742 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3743 fw_major, fw_minor, fw_subminor, pdev->device == 3744 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3745 pdev->broken_intx_masking = 1; 3746 } 3747 3748 iounmap(fw_ver); 3749 3750out: 3751 pci_disable_device(pdev); 3752} 3753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3754 mellanox_check_broken_intx_masking); 3755 3756static void quirk_no_bus_reset(struct pci_dev *dev) 3757{ 3758 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3759} 3760 3761/* 3762 * After asserting Secondary Bus Reset to downstream devices via a GB10 3763 * Root Port, the link may not retrain correctly. 3764 * https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com 3765 */ 3766DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset); 3767DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset); 3768 3769/* 3770 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3771 * prevented for those affected devices. 3772 */ 3773static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3774{ 3775 if ((dev->device & 0xffc0) == 0x2340) 3776 quirk_no_bus_reset(dev); 3777} 3778DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3779 quirk_nvidia_no_bus_reset); 3780 3781/* 3782 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3783 * The device will throw a Link Down error on AER-capable systems and 3784 * regardless of AER, config space of the device is never accessible again 3785 * and typically causes the system to hang or reset when access is attempted. 3786 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3787 */ 3788DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3789DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3790DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3791DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3792DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3793DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3794 3795/* 3796 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3797 * reset when used with certain child devices. After the reset, config 3798 * accesses to the child may fail. 3799 */ 3800DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3801 3802/* 3803 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3804 * automatically disables LTSSM when Secondary Bus Reset is received and 3805 * the device stops working. Prevent bus reset for these devices. With 3806 * this change, the device can be assigned to VMs with VFIO, but it will 3807 * leak state between VMs. Reference 3808 * https://e2e.ti.com/support/processors/f/791/t/954382 3809 */ 3810DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3811 3812/* 3813 * Reports from users making use of PCI device assignment with ASM1164 3814 * controllers indicate an issue with bus reset where the device fails to 3815 * retrain. The issue appears more common in configurations with multiple 3816 * controllers. The device does indicate PM reset support (NoSoftRst-), 3817 * therefore this still leaves a viable reset method. 3818 * https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/ 3819 */ 3820DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset); 3821 3822static void quirk_no_pm_reset(struct pci_dev *dev) 3823{ 3824 /* 3825 * We can't do a bus reset on root bus devices, but an ineffective 3826 * PM reset may be better than nothing. 3827 */ 3828 if (!pci_is_root_bus(dev->bus)) 3829 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3830} 3831 3832/* 3833 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3834 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3835 * to have no effect on the device: it retains the framebuffer contents and 3836 * monitor sync. Advertising this support makes other layers, like VFIO, 3837 * assume pci_reset_function() is viable for this device. Mark it as 3838 * unavailable to skip it when testing reset methods. 3839 */ 3840DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3841 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3842 3843/* 3844 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3845 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3846 * any effect on the device: It continues to be operational and network ports 3847 * remain up. Advertising this support makes it seem as if a PM reset is viable 3848 * for these devices. Mark it as unavailable to skip it when testing reset 3849 * methods. 3850 */ 3851DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3852DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3853DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3854DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3855 3856/* 3857 * Thunderbolt controllers with broken MSI hotplug signaling: 3858 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3859 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3860 */ 3861static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3862{ 3863 if (pdev->is_pciehp && 3864 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3865 pdev->revision <= 1)) 3866 pdev->no_msi = 1; 3867} 3868DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3869 quirk_thunderbolt_hotplug_msi); 3870DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3871 quirk_thunderbolt_hotplug_msi); 3872DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3873 quirk_thunderbolt_hotplug_msi); 3874DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3875 quirk_thunderbolt_hotplug_msi); 3876DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3877 quirk_thunderbolt_hotplug_msi); 3878 3879#ifdef CONFIG_ACPI 3880/* 3881 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3882 * 3883 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3884 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3885 * be present after resume if a device was plugged in before suspend. 3886 * 3887 * The Thunderbolt controller consists of a PCIe switch with downstream 3888 * bridges leading to the NHI and to the tunnel PCI bridges. 3889 * 3890 * This quirk cuts power to the whole chip. Therefore we have to apply it 3891 * during suspend_noirq of the upstream bridge. 3892 * 3893 * Power is automagically restored before resume. No action is needed. 3894 */ 3895static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3896{ 3897 acpi_handle bridge, SXIO, SXFP, SXLV; 3898 3899 if (!x86_apple_machine) 3900 return; 3901 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3902 return; 3903 3904 /* 3905 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3906 * We don't know how to turn it back on again, but firmware does, 3907 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3908 * firmware. 3909 */ 3910 if (!pm_suspend_via_firmware()) 3911 return; 3912 3913 bridge = ACPI_HANDLE(&dev->dev); 3914 if (!bridge) 3915 return; 3916 3917 /* 3918 * SXIO and SXLV are present only on machines requiring this quirk. 3919 * Thunderbolt bridges in external devices might have the same 3920 * device ID as those on the host, but they will not have the 3921 * associated ACPI methods. This implicitly checks that we are at 3922 * the right bridge. 3923 */ 3924 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3925 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3926 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3927 return; 3928 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3929 3930 /* magic sequence */ 3931 acpi_execute_simple_method(SXIO, NULL, 1); 3932 acpi_execute_simple_method(SXFP, NULL, 0); 3933 msleep(300); 3934 acpi_execute_simple_method(SXLV, NULL, 0); 3935 acpi_execute_simple_method(SXIO, NULL, 0); 3936 acpi_execute_simple_method(SXLV, NULL, 0); 3937} 3938DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3939 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3940 quirk_apple_poweroff_thunderbolt); 3941#endif 3942 3943/* 3944 * Following are device-specific reset methods which can be used to 3945 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3946 * not available. 3947 */ 3948static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3949{ 3950 /* 3951 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3952 * 3953 * The 82599 supports FLR on VFs, but FLR support is reported only 3954 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3955 * Thus we must call pcie_flr() directly without first checking if it is 3956 * supported. 3957 */ 3958 if (!probe) 3959 pcie_flr(dev); 3960 return 0; 3961} 3962 3963#define SOUTH_CHICKEN2 0xc2004 3964#define PCH_PP_STATUS 0xc7200 3965#define PCH_PP_CONTROL 0xc7204 3966#define MSG_CTL 0x45010 3967#define NSDE_PWR_STATE 0xd0100 3968#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3969 3970static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3971{ 3972 void __iomem *mmio_base; 3973 unsigned long timeout; 3974 u32 val; 3975 3976 if (probe) 3977 return 0; 3978 3979 mmio_base = pci_iomap(dev, 0, 0); 3980 if (!mmio_base) 3981 return -ENOMEM; 3982 3983 iowrite32(0x00000002, mmio_base + MSG_CTL); 3984 3985 /* 3986 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3987 * driver loaded sets the right bits. However, this's a reset and 3988 * the bits have been set by i915 previously, so we clobber 3989 * SOUTH_CHICKEN2 register directly here. 3990 */ 3991 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3992 3993 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3994 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3995 3996 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3997 do { 3998 val = ioread32(mmio_base + PCH_PP_STATUS); 3999 if ((val & 0xb0000000) == 0) 4000 goto reset_complete; 4001 msleep(10); 4002 } while (time_before(jiffies, timeout)); 4003 pci_warn(dev, "timeout during reset\n"); 4004 4005reset_complete: 4006 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 4007 4008 pci_iounmap(dev, mmio_base); 4009 return 0; 4010} 4011 4012/* Device-specific reset method for Chelsio T4-based adapters */ 4013static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 4014{ 4015 u16 old_command; 4016 u16 msix_flags; 4017 4018 /* 4019 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 4020 * that we have no device-specific reset method. 4021 */ 4022 if ((dev->device & 0xf000) != 0x4000) 4023 return -ENOTTY; 4024 4025 /* 4026 * If this is the "probe" phase, return 0 indicating that we can 4027 * reset this device. 4028 */ 4029 if (probe) 4030 return 0; 4031 4032 /* 4033 * T4 can wedge if there are DMAs in flight within the chip and Bus 4034 * Master has been disabled. We need to have it on till the Function 4035 * Level Reset completes. (BUS_MASTER is disabled in 4036 * pci_reset_function()). 4037 */ 4038 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4039 pci_write_config_word(dev, PCI_COMMAND, 4040 old_command | PCI_COMMAND_MASTER); 4041 4042 /* 4043 * Perform the actual device function reset, saving and restoring 4044 * configuration information around the reset. 4045 */ 4046 pci_save_state(dev); 4047 4048 /* 4049 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4050 * are disabled when an MSI-X interrupt message needs to be delivered. 4051 * So we briefly re-enable MSI-X interrupts for the duration of the 4052 * FLR. The pci_restore_state() below will restore the original 4053 * MSI-X state. 4054 */ 4055 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4056 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4057 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4058 msix_flags | 4059 PCI_MSIX_FLAGS_ENABLE | 4060 PCI_MSIX_FLAGS_MASKALL); 4061 4062 pcie_flr(dev); 4063 4064 /* 4065 * Restore the configuration information (BAR values, etc.) including 4066 * the original PCI Configuration Space Command word, and return 4067 * success. 4068 */ 4069 pci_restore_state(dev); 4070 pci_write_config_word(dev, PCI_COMMAND, old_command); 4071 return 0; 4072} 4073 4074#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4075#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4076#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4077 4078/* 4079 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4080 * FLR where config space reads from the device return -1. We seem to be 4081 * able to avoid this condition if we disable the NVMe controller prior to 4082 * FLR. This quirk is generic for any NVMe class device requiring similar 4083 * assistance to quiesce the device prior to FLR. 4084 * 4085 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4086 * Revision 1.0e: 4087 * Chapter 2: Required and optional PCI config registers 4088 * Chapter 3: NVMe control registers 4089 * Chapter 7.3: Reset behavior 4090 */ 4091static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4092{ 4093 void __iomem *bar; 4094 u16 cmd; 4095 u32 cfg; 4096 4097 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4098 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4099 return -ENOTTY; 4100 4101 if (probe) 4102 return 0; 4103 4104 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4105 if (!bar) 4106 return -ENOTTY; 4107 4108 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4109 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4110 4111 cfg = readl(bar + NVME_REG_CC); 4112 4113 /* Disable controller if enabled */ 4114 if (cfg & NVME_CC_ENABLE) { 4115 u32 cap = readl(bar + NVME_REG_CAP); 4116 unsigned long timeout; 4117 4118 /* 4119 * Per nvme_disable_ctrl() skip shutdown notification as it 4120 * could complete commands to the admin queue. We only intend 4121 * to quiesce the device before reset. 4122 */ 4123 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4124 4125 writel(cfg, bar + NVME_REG_CC); 4126 4127 /* 4128 * Some controllers require an additional delay here, see 4129 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4130 * supported by this quirk. 4131 */ 4132 4133 /* Cap register provides max timeout in 500ms increments */ 4134 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4135 4136 for (;;) { 4137 u32 status = readl(bar + NVME_REG_CSTS); 4138 4139 /* Ready status becomes zero on disable complete */ 4140 if (!(status & NVME_CSTS_RDY)) 4141 break; 4142 4143 msleep(100); 4144 4145 if (time_after(jiffies, timeout)) { 4146 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4147 break; 4148 } 4149 } 4150 } 4151 4152 pci_iounmap(dev, bar); 4153 4154 pcie_flr(dev); 4155 4156 return 0; 4157} 4158 4159/* 4160 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4161 * timeout waiting for ready status to change after NVMe enable if the driver 4162 * starts interacting with the device too soon after FLR. A 250ms delay after 4163 * FLR has heuristically proven to produce reliably working results for device 4164 * assignment cases. 4165 */ 4166static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4167{ 4168 if (probe) 4169 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4170 4171 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4172 4173 msleep(250); 4174 4175 return 0; 4176} 4177 4178#define PCI_DEVICE_ID_HINIC_VF 0x375E 4179#define HINIC_VF_FLR_TYPE 0x1000 4180#define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4181#define HINIC_VF_OP 0xE80 4182#define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4183#define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4184 4185/* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4186static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4187{ 4188 unsigned long timeout; 4189 void __iomem *bar; 4190 u32 val; 4191 4192 if (probe) 4193 return 0; 4194 4195 bar = pci_iomap(pdev, 0, 0); 4196 if (!bar) 4197 return -ENOTTY; 4198 4199 /* Get and check firmware capabilities */ 4200 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4201 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4202 pci_iounmap(pdev, bar); 4203 return -ENOTTY; 4204 } 4205 4206 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4207 val = ioread32be(bar + HINIC_VF_OP); 4208 val = val | HINIC_VF_FLR_PROC_BIT; 4209 iowrite32be(val, bar + HINIC_VF_OP); 4210 4211 pcie_flr(pdev); 4212 4213 /* 4214 * The device must recapture its Bus and Device Numbers after FLR 4215 * in order generate Completions. Issue a config write to let the 4216 * device capture this information. 4217 */ 4218 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4219 4220 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4221 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4222 do { 4223 val = ioread32be(bar + HINIC_VF_OP); 4224 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4225 goto reset_complete; 4226 msleep(20); 4227 } while (time_before(jiffies, timeout)); 4228 4229 val = ioread32be(bar + HINIC_VF_OP); 4230 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4231 goto reset_complete; 4232 4233 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4234 4235reset_complete: 4236 pci_iounmap(pdev, bar); 4237 4238 return 0; 4239} 4240 4241static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4242 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4243 reset_intel_82599_sfp_virtfn }, 4244 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4245 reset_ivb_igd }, 4246 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4247 reset_ivb_igd }, 4248 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4249 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4250 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4251 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4252 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4253 reset_chelsio_generic_dev }, 4254 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4255 reset_hinic_vf_dev }, 4256 { 0 } 4257}; 4258 4259/* 4260 * These device-specific reset methods are here rather than in a driver 4261 * because when a host assigns a device to a guest VM, the host may need 4262 * to reset the device but probably doesn't have a driver for it. 4263 */ 4264int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4265{ 4266 const struct pci_dev_reset_methods *i; 4267 4268 for (i = pci_dev_reset_methods; i->reset; i++) { 4269 if ((i->vendor == dev->vendor || 4270 i->vendor == (u16)PCI_ANY_ID) && 4271 (i->device == dev->device || 4272 i->device == (u16)PCI_ANY_ID)) 4273 return i->reset(dev, probe); 4274 } 4275 4276 return -ENOTTY; 4277} 4278 4279static void quirk_dma_func0_alias(struct pci_dev *dev) 4280{ 4281 if (PCI_FUNC(dev->devfn) != 0) 4282 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4283} 4284 4285/* 4286 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4287 * 4288 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4289 */ 4290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4291DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4292 4293/* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4294DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4295DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4296 4297static void quirk_dma_func1_alias(struct pci_dev *dev) 4298{ 4299 if (PCI_FUNC(dev->devfn) != 1) 4300 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4301} 4302 4303/* 4304 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4305 * SKUs function 1 is present and is a legacy IDE controller, in other 4306 * SKUs this function is not present, making this a ghost requester. 4307 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4308 */ 4309DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4310 quirk_dma_func1_alias); 4311DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4312 quirk_dma_func1_alias); 4313/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4314DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4315 quirk_dma_func1_alias); 4316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4317 quirk_dma_func1_alias); 4318/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4320 quirk_dma_func1_alias); 4321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4322 quirk_dma_func1_alias); 4323/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4325 quirk_dma_func1_alias); 4326/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4328 quirk_dma_func1_alias); 4329/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4331 quirk_dma_func1_alias); 4332/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4334 quirk_dma_func1_alias); 4335/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4337 quirk_dma_func1_alias); 4338/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4340 quirk_dma_func1_alias); 4341/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4343 quirk_dma_func1_alias); 4344/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4345DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4346 quirk_dma_func1_alias); 4347DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4348 quirk_dma_func1_alias); 4349DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4350 quirk_dma_func1_alias); 4351DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4352 quirk_dma_func1_alias); 4353/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4355 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4356 quirk_dma_func1_alias); 4357/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4358DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4359 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4360 quirk_dma_func1_alias); 4361 4362/* 4363 * Some devices DMA with the wrong devfn, not just the wrong function. 4364 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4365 * the alias is "fixed" and independent of the device devfn. 4366 * 4367 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4368 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4369 * single device on the secondary bus. In reality, the single exposed 4370 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4371 * that provides a bridge to the internal bus of the I/O processor. The 4372 * controller supports private devices, which can be hidden from PCI config 4373 * space. In the case of the Adaptec 3405, a private device at 01.0 4374 * appears to be the DMA engine, which therefore needs to become a DMA 4375 * alias for the device. 4376 */ 4377static const struct pci_device_id fixed_dma_alias_tbl[] = { 4378 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4379 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4380 .driver_data = PCI_DEVFN(1, 0) }, 4381 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4382 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4383 .driver_data = PCI_DEVFN(1, 0) }, 4384 { 0 } 4385}; 4386 4387static void quirk_fixed_dma_alias(struct pci_dev *dev) 4388{ 4389 const struct pci_device_id *id; 4390 4391 id = pci_match_id(fixed_dma_alias_tbl, dev); 4392 if (id) 4393 pci_add_dma_alias(dev, id->driver_data, 1); 4394} 4395DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4396 4397/* 4398 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4399 * using the wrong DMA alias for the device. Some of these devices can be 4400 * used as either forward or reverse bridges, so we need to test whether the 4401 * device is operating in the correct mode. We could probably apply this 4402 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4403 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4404 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4405 */ 4406static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4407{ 4408 if (!pci_is_root_bus(pdev->bus) && 4409 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4410 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4411 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4412 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4413} 4414/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4415DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4416 quirk_use_pcie_bridge_dma_alias); 4417/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4418DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4419/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4420DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4421/* ITE 8893 has the same problem as the 8892 */ 4422DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4423/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4424DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4425 4426/* 4427 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4428 * be added as aliases to the DMA device in order to allow buffer access 4429 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4430 * programmed in the EEPROM. 4431 */ 4432static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4433{ 4434 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4435 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4436 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4437} 4438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4440 4441/* 4442 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4443 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4444 * 4445 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4446 * when IOMMU is enabled. These aliases allow computational unit access to 4447 * host memory. These aliases mark the whole VCA device as one IOMMU 4448 * group. 4449 * 4450 * All possible slot numbers (0x20) are used, since we are unable to tell 4451 * what slot is used on other side. This quirk is intended for both host 4452 * and computational unit sides. The VCA devices have up to five functions 4453 * (four for DMA channels and one additional). 4454 */ 4455static void quirk_pex_vca_alias(struct pci_dev *pdev) 4456{ 4457 const unsigned int num_pci_slots = 0x20; 4458 unsigned int slot; 4459 4460 for (slot = 0; slot < num_pci_slots; slot++) 4461 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4462} 4463DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4465DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4467DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4468DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4469 4470/* 4471 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4472 * associated not at the root bus, but at a bridge below. This quirk avoids 4473 * generating invalid DMA aliases. 4474 */ 4475static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4476{ 4477 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4478} 4479DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4480 quirk_bridge_cavm_thrx2_pcie_root); 4481DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4482 quirk_bridge_cavm_thrx2_pcie_root); 4483 4484/* 4485 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4486 * class code. Fix it. 4487 */ 4488static void quirk_tw686x_class(struct pci_dev *pdev) 4489{ 4490 u32 class = pdev->class; 4491 4492 /* Use "Multimedia controller" class */ 4493 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4494 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4495 class, pdev->class); 4496} 4497DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4498 quirk_tw686x_class); 4499DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4500 quirk_tw686x_class); 4501DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4502 quirk_tw686x_class); 4503DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4504 quirk_tw686x_class); 4505 4506/* 4507 * Some devices have problems with Transaction Layer Packets with the Relaxed 4508 * Ordering Attribute set. Such devices should mark themselves and other 4509 * device drivers should check before sending TLPs with RO set. 4510 */ 4511static void quirk_relaxedordering_disable(struct pci_dev *dev) 4512{ 4513 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4514 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4515} 4516 4517/* 4518 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4519 * Complex have a Flow Control Credit issue which can cause performance 4520 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4521 */ 4522DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4523 quirk_relaxedordering_disable); 4524DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4525 quirk_relaxedordering_disable); 4526DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4527 quirk_relaxedordering_disable); 4528DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4529 quirk_relaxedordering_disable); 4530DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4531 quirk_relaxedordering_disable); 4532DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4533 quirk_relaxedordering_disable); 4534DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4535 quirk_relaxedordering_disable); 4536DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4537 quirk_relaxedordering_disable); 4538DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4539 quirk_relaxedordering_disable); 4540DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4541 quirk_relaxedordering_disable); 4542DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4543 quirk_relaxedordering_disable); 4544DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4545 quirk_relaxedordering_disable); 4546DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4547 quirk_relaxedordering_disable); 4548DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4549 quirk_relaxedordering_disable); 4550DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4551 quirk_relaxedordering_disable); 4552DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4553 quirk_relaxedordering_disable); 4554DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4555 quirk_relaxedordering_disable); 4556DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4557 quirk_relaxedordering_disable); 4558DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4559 quirk_relaxedordering_disable); 4560DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4561 quirk_relaxedordering_disable); 4562DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4563 quirk_relaxedordering_disable); 4564DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4565 quirk_relaxedordering_disable); 4566DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4567 quirk_relaxedordering_disable); 4568DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4569 quirk_relaxedordering_disable); 4570DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4571 quirk_relaxedordering_disable); 4572DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4573 quirk_relaxedordering_disable); 4574DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4575 quirk_relaxedordering_disable); 4576DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4577 quirk_relaxedordering_disable); 4578 4579/* 4580 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4581 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4582 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4583 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4584 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4585 * November 10, 2010). As a result, on this platform we can't use Relaxed 4586 * Ordering for Upstream TLPs. 4587 */ 4588DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4589 quirk_relaxedordering_disable); 4590DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4591 quirk_relaxedordering_disable); 4592DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4593 quirk_relaxedordering_disable); 4594 4595/* 4596 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4597 * values for the Attribute as were supplied in the header of the 4598 * corresponding Request, except as explicitly allowed when IDO is used." 4599 * 4600 * If a non-compliant device generates a completion with a different 4601 * attribute than the request, the receiver may accept it (which itself 4602 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4603 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4604 * device access timeout. 4605 * 4606 * If the non-compliant device generates completions with zero attributes 4607 * (instead of copying the attributes from the request), we can work around 4608 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4609 * upstream devices so they always generate requests with zero attributes. 4610 * 4611 * This affects other devices under the same Root Port, but since these 4612 * attributes are performance hints, there should be no functional problem. 4613 * 4614 * Note that Configuration Space accesses are never supposed to have TLP 4615 * Attributes, so we're safe waiting till after any Configuration Space 4616 * accesses to do the Root Port fixup. 4617 */ 4618static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4619{ 4620 struct pci_dev *root_port = pcie_find_root_port(pdev); 4621 4622 if (!root_port) { 4623 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4624 return; 4625 } 4626 4627 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4628 dev_name(&pdev->dev)); 4629 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4630 PCI_EXP_DEVCTL_RELAX_EN | 4631 PCI_EXP_DEVCTL_NOSNOOP_EN); 4632} 4633 4634/* 4635 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4636 * Completion it generates. 4637 */ 4638static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4639{ 4640 /* 4641 * This mask/compare operation selects for Physical Function 4 on a 4642 * T5. We only need to fix up the Root Port once for any of the 4643 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4644 * 0x54xx so we use that one. 4645 */ 4646 if ((pdev->device & 0xff00) == 0x5400) 4647 quirk_disable_root_port_attributes(pdev); 4648} 4649DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4650 quirk_chelsio_T5_disable_root_port_attributes); 4651 4652/* 4653 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4654 * by a device 4655 * @acs_ctrl_req: Bitmask of desired ACS controls 4656 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4657 * the hardware design 4658 * 4659 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4660 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4661 * caller desires. Return 0 otherwise. 4662 */ 4663static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4664{ 4665 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4666 return 1; 4667 return 0; 4668} 4669 4670/* 4671 * AMD has indicated that the devices below do not support peer-to-peer 4672 * in any system where they are found in the southbridge with an AMD 4673 * IOMMU in the system. Multifunction devices that do not support 4674 * peer-to-peer between functions can claim to support a subset of ACS. 4675 * Such devices effectively enable request redirect (RR) and completion 4676 * redirect (CR) since all transactions are redirected to the upstream 4677 * root complex. 4678 * 4679 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4680 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4681 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4682 * 4683 * 1002:4385 SBx00 SMBus Controller 4684 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4685 * 1002:4383 SBx00 Azalia (Intel HDA) 4686 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4687 * 1002:4384 SBx00 PCI to PCI Bridge 4688 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4689 * 4690 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4691 * 4692 * 1022:780f [AMD] FCH PCI Bridge 4693 * 1022:7809 [AMD] FCH USB OHCI Controller 4694 */ 4695static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4696{ 4697#ifdef CONFIG_ACPI 4698 struct acpi_table_header *header = NULL; 4699 acpi_status status; 4700 4701 /* Targeting multifunction devices on the SB (appears on root bus) */ 4702 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4703 return -ENODEV; 4704 4705 /* The IVRS table describes the AMD IOMMU */ 4706 status = acpi_get_table("IVRS", 0, &header); 4707 if (ACPI_FAILURE(status)) 4708 return -ENODEV; 4709 4710 acpi_put_table(header); 4711 4712 /* Filter out flags not applicable to multifunction */ 4713 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4714 4715 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4716#else 4717 return -ENODEV; 4718#endif 4719} 4720 4721static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4722{ 4723 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4724 return false; 4725 4726 switch (dev->device) { 4727 /* 4728 * Effectively selects all downstream ports for whole ThunderX1 4729 * (which represents 8 SoCs). 4730 */ 4731 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4732 case 0xaf84: /* ThunderX2 */ 4733 case 0xb884: /* ThunderX3 */ 4734 return true; 4735 default: 4736 return false; 4737 } 4738} 4739 4740static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4741{ 4742 if (!pci_quirk_cavium_acs_match(dev)) 4743 return -ENOTTY; 4744 4745 /* 4746 * Cavium Root Ports don't advertise an ACS capability. However, 4747 * the RTL internally implements similar protection as if ACS had 4748 * Source Validation, Request Redirection, Completion Redirection, 4749 * and Upstream Forwarding features enabled. Assert that the 4750 * hardware implements and enables equivalent ACS functionality for 4751 * these flags. 4752 */ 4753 return pci_acs_ctrl_enabled(acs_flags, 4754 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4755} 4756 4757static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4758{ 4759 /* 4760 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4761 * transactions with others, allowing masking out these bits as if they 4762 * were unimplemented in the ACS capability. 4763 */ 4764 return pci_acs_ctrl_enabled(acs_flags, 4765 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4766} 4767 4768/* 4769 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4770 * But the implementation could block peer-to-peer transactions between them 4771 * and provide ACS-like functionality. 4772 */ 4773static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4774{ 4775 if (!pci_is_pcie(dev) || 4776 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4777 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4778 return -ENOTTY; 4779 4780 /* 4781 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4782 * implement ACS capability in accordance with the PCIe Spec. 4783 */ 4784 switch (dev->device) { 4785 case 0x0710 ... 0x071e: 4786 case 0x0721: 4787 case 0x0723 ... 0x0752: 4788 return pci_acs_ctrl_enabled(acs_flags, 4789 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4790 } 4791 4792 return false; 4793} 4794 4795/* 4796 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4797 * transactions and validate bus numbers in requests, but do not provide an 4798 * actual PCIe ACS capability. This is the list of device IDs known to fall 4799 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4800 */ 4801static const u16 pci_quirk_intel_pch_acs_ids[] = { 4802 /* Ibexpeak PCH */ 4803 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4804 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4805 /* Cougarpoint PCH */ 4806 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4807 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4808 /* Pantherpoint PCH */ 4809 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4810 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4811 /* Lynxpoint-H PCH */ 4812 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4813 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4814 /* Lynxpoint-LP PCH */ 4815 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4816 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4817 /* Wildcat PCH */ 4818 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4819 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4820 /* Patsburg (X79) PCH */ 4821 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4822 /* Wellsburg (X99) PCH */ 4823 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4824 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4825 /* Lynx Point (9 series) PCH */ 4826 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4827}; 4828 4829static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4830{ 4831 int i; 4832 4833 /* Filter out a few obvious non-matches first */ 4834 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4835 return false; 4836 4837 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4838 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4839 return true; 4840 4841 return false; 4842} 4843 4844static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4845{ 4846 if (!pci_quirk_intel_pch_acs_match(dev)) 4847 return -ENOTTY; 4848 4849 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4850 return pci_acs_ctrl_enabled(acs_flags, 4851 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4852 4853 return pci_acs_ctrl_enabled(acs_flags, 0); 4854} 4855 4856/* 4857 * These QCOM Root Ports do provide ACS-like features to disable peer 4858 * transactions and validate bus numbers in requests, but do not provide an 4859 * actual PCIe ACS capability. Hardware supports source validation but it 4860 * will report the issue as Completer Abort instead of ACS Violation. 4861 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4862 * Complex with unique segment numbers. It is not possible for one Root 4863 * Port to pass traffic to another Root Port. All PCIe transactions are 4864 * terminated inside the Root Port. 4865 */ 4866static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4867{ 4868 return pci_acs_ctrl_enabled(acs_flags, 4869 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4870} 4871 4872/* 4873 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4874 * number and does provide isolation features to disable peer transactions 4875 * and validate bus numbers in requests, but does not provide an ACS 4876 * capability. 4877 */ 4878static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4879{ 4880 return pci_acs_ctrl_enabled(acs_flags, 4881 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4882} 4883 4884static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4885{ 4886 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4887 return -ENOTTY; 4888 4889 /* 4890 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4891 * but do include ACS-like functionality. The hardware doesn't support 4892 * peer-to-peer transactions via the root port and each has a unique 4893 * segment number. 4894 * 4895 * Additionally, the root ports cannot send traffic to each other. 4896 */ 4897 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4898 4899 return acs_flags ? 0 : 1; 4900} 4901 4902/* 4903 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4904 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4905 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4906 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4907 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4908 * control register is at offset 8 instead of 6 and we should probably use 4909 * dword accesses to them. This applies to the following PCI Device IDs, as 4910 * found in volume 1 of the datasheet[2]: 4911 * 4912 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4913 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4914 * 4915 * N.B. This doesn't fix what lspci shows. 4916 * 4917 * The 100 series chipset specification update includes this as errata #23[3]. 4918 * 4919 * The 200 series chipset (Union Point) has the same bug according to the 4920 * specification update (Intel 200 Series Chipset Family Platform Controller 4921 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4922 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4923 * chipset include: 4924 * 4925 * 0xa290-0xa29f PCI Express Root port #{0-16} 4926 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4927 * 4928 * Mobile chipsets are also affected, 7th & 8th Generation 4929 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4930 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4931 * Processor Family I/O for U Quad Core Platforms Specification Update, 4932 * August 2017, Revision 002, Document#: 334660-002)[6] 4933 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4934 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4935 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4936 * 4937 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4938 * 4939 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4940 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4941 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4942 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4943 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4944 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4945 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4946 */ 4947static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4948{ 4949 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4950 return false; 4951 4952 switch (dev->device) { 4953 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4954 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4955 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4956 return true; 4957 } 4958 4959 return false; 4960} 4961 4962#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4963 4964static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4965{ 4966 int pos; 4967 u32 cap, ctrl; 4968 4969 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4970 return -ENOTTY; 4971 4972 pos = dev->acs_cap; 4973 if (!pos) 4974 return -ENOTTY; 4975 4976 /* see pci_acs_flags_enabled() */ 4977 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4978 acs_flags &= (cap | PCI_ACS_EC); 4979 4980 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4981 4982 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4983} 4984 4985static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4986{ 4987 /* 4988 * SV, TB, and UF are not relevant to multifunction endpoints. 4989 * 4990 * Multifunction devices are only required to implement RR, CR, and DT 4991 * in their ACS capability if they support peer-to-peer transactions. 4992 * Devices matching this quirk have been verified by the vendor to not 4993 * perform peer-to-peer with other functions, allowing us to mask out 4994 * these bits as if they were unimplemented in the ACS capability. 4995 */ 4996 return pci_acs_ctrl_enabled(acs_flags, 4997 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4998 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4999} 5000 5001static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 5002{ 5003 /* 5004 * Intel RCiEP's are required to allow p2p only on translated 5005 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 5006 * "Root-Complex Peer to Peer Considerations". 5007 */ 5008 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 5009 return -ENOTTY; 5010 5011 return pci_acs_ctrl_enabled(acs_flags, 5012 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5013} 5014 5015static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 5016{ 5017 /* 5018 * iProc PAXB Root Ports don't advertise an ACS capability, but 5019 * they do not allow peer-to-peer transactions between Root Ports. 5020 * Allow each Root Port to be in a separate IOMMU group by masking 5021 * SV/RR/CR/UF bits. 5022 */ 5023 return pci_acs_ctrl_enabled(acs_flags, 5024 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5025} 5026 5027static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) 5028{ 5029 /* 5030 * Loongson PCIe Root Ports don't advertise an ACS capability, but 5031 * they do not allow peer-to-peer transactions between Root Ports. 5032 * Allow each Root Port to be in a separate IOMMU group by masking 5033 * SV/RR/CR/UF bits. 5034 */ 5035 return pci_acs_ctrl_enabled(acs_flags, 5036 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5037} 5038 5039/* 5040 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5041 * multi-function devices, the hardware isolates the functions by 5042 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5043 * PCI_ACS_CR were set. 5044 * SFxxx 1G NICs(em). 5045 * RP1000/RP2000 10G NICs(sp). 5046 * FF5xxx 40G/25G/10G NICs(aml). 5047 */ 5048static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5049{ 5050 switch (dev->device) { 5051 case 0x0100 ... 0x010F: /* EM */ 5052 case 0x1001: case 0x2001: /* SP */ 5053 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5054 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5055 return pci_acs_ctrl_enabled(acs_flags, 5056 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5057 } 5058 5059 return false; 5060} 5061 5062static const struct pci_dev_acs_enabled { 5063 u16 vendor; 5064 u16 device; 5065 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5066} pci_dev_acs_enabled[] = { 5067 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5068 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5069 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5070 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5071 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5072 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5073 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5074 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5075 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5076 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5077 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5078 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5079 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5080 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5081 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5082 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5083 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5084 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5085 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5086 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5087 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5088 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5089 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5090 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5091 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5092 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5093 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5094 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5095 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5096 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5097 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5098 /* 82580 */ 5099 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5100 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5101 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5102 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5103 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5104 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5105 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5106 /* 82576 */ 5107 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5109 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5110 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5111 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5112 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5113 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5114 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5115 /* 82575 */ 5116 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5117 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5118 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5119 /* I350 */ 5120 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5121 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5122 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5123 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5124 /* 82571 (Quads omitted due to non-ACS switch) */ 5125 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5126 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5127 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5128 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5129 /* I219 */ 5130 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5131 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5132 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5133 /* QCOM QDF2xxx root ports */ 5134 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5135 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5136 /* QCOM SA8775P root port */ 5137 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5138 /* QCOM Hamoa root port */ 5139 { PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs }, 5140 /* QCOM Glymur root port */ 5141 { PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs }, 5142 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5143 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5144 /* Intel PCH root ports */ 5145 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5146 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5147 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5148 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5149 /* Cavium ThunderX */ 5150 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5151 /* Cavium multi-function devices */ 5152 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5153 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5154 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5155 /* APM X-Gene */ 5156 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5157 /* Ampere Computing */ 5158 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5159 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5160 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5161 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5162 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5163 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5164 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5165 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5166 /* Broadcom multi-function device */ 5167 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5168 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5169 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5170 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5171 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5172 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5173 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5174 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5175 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5176 /* Loongson PCIe Root Ports */ 5177 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, 5178 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, 5179 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, 5180 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, 5181 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, 5182 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, 5183 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, 5184 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, 5185 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, 5186 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, 5187 /* Amazon Annapurna Labs */ 5188 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5189 /* Zhaoxin multi-function devices */ 5190 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5191 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5192 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5193 /* NXP root ports, xx=16, 12, or 08 cores */ 5194 /* LX2xx0A : without security features + CAN-FD */ 5195 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5196 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5197 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5198 /* LX2xx0C : security features + CAN-FD */ 5199 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5200 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5201 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5202 /* LX2xx0E : security features + CAN */ 5203 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5204 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5205 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5206 /* LX2xx0N : without security features + CAN */ 5207 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5208 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5209 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5210 /* LX2xx2A : without security features + CAN-FD */ 5211 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5212 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5213 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5214 /* LX2xx2C : security features + CAN-FD */ 5215 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5216 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5217 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5218 /* LX2xx2E : security features + CAN */ 5219 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5220 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5221 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5222 /* LX2xx2N : without security features + CAN */ 5223 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5224 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5225 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5226 /* Zhaoxin Root/Downstream Ports */ 5227 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5228 /* Wangxun nics */ 5229 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5230 { 0 } 5231}; 5232 5233/* 5234 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5235 * @dev: PCI device 5236 * @acs_flags: Bitmask of desired ACS controls 5237 * 5238 * Returns: 5239 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5240 * device provides the desired controls 5241 * 0: Device does not provide all the desired controls 5242 * >0: Device provides all the controls in @acs_flags 5243 */ 5244int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5245{ 5246 const struct pci_dev_acs_enabled *i; 5247 int ret; 5248 5249 /* 5250 * Allow devices that do not expose standard PCIe ACS capabilities 5251 * or control to indicate their support here. Multi-function express 5252 * devices which do not allow internal peer-to-peer between functions, 5253 * but do not implement PCIe ACS may wish to return true here. 5254 */ 5255 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5256 if ((i->vendor == dev->vendor || 5257 i->vendor == (u16)PCI_ANY_ID) && 5258 (i->device == dev->device || 5259 i->device == (u16)PCI_ANY_ID)) { 5260 ret = i->acs_enabled(dev, acs_flags); 5261 if (ret >= 0) 5262 return ret; 5263 } 5264 } 5265 5266 return -ENOTTY; 5267} 5268 5269/* Config space offset of Root Complex Base Address register */ 5270#define INTEL_LPC_RCBA_REG 0xf0 5271/* 31:14 RCBA address */ 5272#define INTEL_LPC_RCBA_MASK 0xffffc000 5273/* RCBA Enable */ 5274#define INTEL_LPC_RCBA_ENABLE (1 << 0) 5275 5276/* Backbone Scratch Pad Register */ 5277#define INTEL_BSPR_REG 0x1104 5278/* Backbone Peer Non-Posted Disable */ 5279#define INTEL_BSPR_REG_BPNPD (1 << 8) 5280/* Backbone Peer Posted Disable */ 5281#define INTEL_BSPR_REG_BPPD (1 << 9) 5282 5283/* Upstream Peer Decode Configuration Register */ 5284#define INTEL_UPDCR_REG 0x1014 5285/* 5:0 Peer Decode Enable bits */ 5286#define INTEL_UPDCR_REG_MASK 0x3f 5287 5288static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5289{ 5290 u32 rcba, bspr, updcr; 5291 void __iomem *rcba_mem; 5292 5293 /* 5294 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5295 * are D28:F* and therefore get probed before LPC, thus we can't 5296 * use pci_get_slot()/pci_read_config_dword() here. 5297 */ 5298 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5299 INTEL_LPC_RCBA_REG, &rcba); 5300 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5301 return -EINVAL; 5302 5303 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5304 PAGE_ALIGN(INTEL_UPDCR_REG)); 5305 if (!rcba_mem) 5306 return -ENOMEM; 5307 5308 /* 5309 * The BSPR can disallow peer cycles, but it's set by soft strap and 5310 * therefore read-only. If both posted and non-posted peer cycles are 5311 * disallowed, we're ok. If either are allowed, then we need to use 5312 * the UPDCR to disable peer decodes for each port. This provides the 5313 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5314 */ 5315 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5316 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5317 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5318 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5319 if (updcr & INTEL_UPDCR_REG_MASK) { 5320 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5321 updcr &= ~INTEL_UPDCR_REG_MASK; 5322 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5323 } 5324 } 5325 5326 iounmap(rcba_mem); 5327 return 0; 5328} 5329 5330/* Miscellaneous Port Configuration register */ 5331#define INTEL_MPC_REG 0xd8 5332/* MPC: Invalid Receive Bus Number Check Enable */ 5333#define INTEL_MPC_REG_IRBNCE (1 << 26) 5334 5335static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5336{ 5337 u32 mpc; 5338 5339 /* 5340 * When enabled, the IRBNCE bit of the MPC register enables the 5341 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5342 * ensures that requester IDs fall within the bus number range 5343 * of the bridge. Enable if not already. 5344 */ 5345 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5346 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5347 pci_info(dev, "Enabling MPC IRBNCE\n"); 5348 mpc |= INTEL_MPC_REG_IRBNCE; 5349 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5350 } 5351} 5352 5353/* 5354 * Currently this quirk does the equivalent of 5355 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5356 * 5357 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5358 * if dev->external_facing || dev->untrusted 5359 */ 5360static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5361{ 5362 if (!pci_quirk_intel_pch_acs_match(dev)) 5363 return -ENOTTY; 5364 5365 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5366 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5367 return 0; 5368 } 5369 5370 pci_quirk_enable_intel_rp_mpc_acs(dev); 5371 5372 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5373 5374 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5375 5376 return 0; 5377} 5378 5379static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5380{ 5381 int pos; 5382 u32 cap, ctrl; 5383 5384 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5385 return -ENOTTY; 5386 5387 pos = dev->acs_cap; 5388 if (!pos) 5389 return -ENOTTY; 5390 5391 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5392 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5393 5394 ctrl |= (cap & PCI_ACS_SV); 5395 ctrl |= (cap & PCI_ACS_RR); 5396 ctrl |= (cap & PCI_ACS_CR); 5397 ctrl |= (cap & PCI_ACS_UF); 5398 5399 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5400 ctrl |= (cap & PCI_ACS_TB); 5401 5402 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5403 5404 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5405 5406 return 0; 5407} 5408 5409static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5410{ 5411 int pos; 5412 u32 cap, ctrl; 5413 5414 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5415 return -ENOTTY; 5416 5417 pos = dev->acs_cap; 5418 if (!pos) 5419 return -ENOTTY; 5420 5421 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5422 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5423 5424 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5425 5426 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5427 5428 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5429 5430 return 0; 5431} 5432 5433static const struct pci_dev_acs_ops { 5434 u16 vendor; 5435 u16 device; 5436 int (*enable_acs)(struct pci_dev *dev); 5437 int (*disable_acs_redir)(struct pci_dev *dev); 5438} pci_dev_acs_ops[] = { 5439 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5440 .enable_acs = pci_quirk_enable_intel_pch_acs, 5441 }, 5442 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5443 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5444 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5445 }, 5446}; 5447 5448int pci_dev_specific_enable_acs(struct pci_dev *dev) 5449{ 5450 const struct pci_dev_acs_ops *p; 5451 int i, ret; 5452 5453 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5454 p = &pci_dev_acs_ops[i]; 5455 if ((p->vendor == dev->vendor || 5456 p->vendor == (u16)PCI_ANY_ID) && 5457 (p->device == dev->device || 5458 p->device == (u16)PCI_ANY_ID) && 5459 p->enable_acs) { 5460 ret = p->enable_acs(dev); 5461 if (ret >= 0) 5462 return ret; 5463 } 5464 } 5465 5466 return -ENOTTY; 5467} 5468 5469int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5470{ 5471 const struct pci_dev_acs_ops *p; 5472 int i, ret; 5473 5474 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5475 p = &pci_dev_acs_ops[i]; 5476 if ((p->vendor == dev->vendor || 5477 p->vendor == (u16)PCI_ANY_ID) && 5478 (p->device == dev->device || 5479 p->device == (u16)PCI_ANY_ID) && 5480 p->disable_acs_redir) { 5481 ret = p->disable_acs_redir(dev); 5482 if (ret >= 0) 5483 return ret; 5484 } 5485 } 5486 5487 return -ENOTTY; 5488} 5489 5490/* 5491 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5492 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5493 * Next Capability pointer in the MSI Capability Structure should point to 5494 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5495 * the list. 5496 */ 5497static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5498{ 5499 int pos, i = 0, ret; 5500 u8 next_cap; 5501 u16 reg16, *cap; 5502 struct pci_cap_saved_state *state; 5503 5504 /* Bail if the hardware bug is fixed */ 5505 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5506 return; 5507 5508 /* Bail if MSI Capability Structure is not found for some reason */ 5509 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5510 if (!pos) 5511 return; 5512 5513 /* 5514 * Bail if Next Capability pointer in the MSI Capability Structure 5515 * is not the expected incorrect 0x00. 5516 */ 5517 pci_read_config_byte(pdev, pos + 1, &next_cap); 5518 if (next_cap) 5519 return; 5520 5521 /* 5522 * PCIe Capability Structure is expected to be at 0x50 and should 5523 * terminate the list (Next Capability pointer is 0x00). Verify 5524 * Capability Id and Next Capability pointer is as expected. 5525 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5526 * to correctly set kernel data structures which have already been 5527 * set incorrectly due to the hardware bug. 5528 */ 5529 pos = 0x50; 5530 pci_read_config_word(pdev, pos, ®16); 5531 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5532 u32 status; 5533#ifndef PCI_EXP_SAVE_REGS 5534#define PCI_EXP_SAVE_REGS 7 5535#endif 5536 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5537 5538 pdev->pcie_cap = pos; 5539 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5540 pdev->pcie_flags_reg = reg16; 5541 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5542 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5543 5544 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5545 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5546 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5547 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5548 5549 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5550 return; 5551 5552 /* Save PCIe cap */ 5553 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5554 if (!state) 5555 return; 5556 5557 state->cap.cap_nr = PCI_CAP_ID_EXP; 5558 state->cap.cap_extended = 0; 5559 state->cap.size = size; 5560 cap = (u16 *)&state->cap.data[0]; 5561 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5562 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5563 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5564 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5565 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5566 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5567 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5568 hlist_add_head(&state->next, &pdev->saved_cap_space); 5569 } 5570} 5571DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5572 5573/* 5574 * FLR may cause the following to devices to hang: 5575 * 5576 * AMD Starship/Matisse HD Audio Controller 0x1487 5577 * AMD Starship USB 3.0 Host Controller 0x148c 5578 * AMD Matisse USB 3.0 Host Controller 0x149c 5579 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5580 * Intel 82579V Gigabit Ethernet Controller 0x1503 5581 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5582 */ 5583static void quirk_no_flr(struct pci_dev *dev) 5584{ 5585 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5586} 5587DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5588DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5589DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5590DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5591DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5592DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5593DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5594 5595/* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5596static void quirk_no_flr_snet(struct pci_dev *dev) 5597{ 5598 if (dev->revision == 0x1) 5599 quirk_no_flr(dev); 5600} 5601DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5602 5603static void quirk_no_ext_tags(struct pci_dev *pdev) 5604{ 5605 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5606 5607 if (!bridge) 5608 return; 5609 5610 bridge->no_ext_tags = 1; 5611 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5612 5613 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5614} 5615DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5616DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1005, quirk_no_ext_tags); 5617DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5618DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5619DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5620DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5621DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5622DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5623DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5624 5625#ifdef CONFIG_PCI_ATS 5626static void quirk_no_ats(struct pci_dev *pdev) 5627{ 5628 pci_info(pdev, "disabling ATS\n"); 5629 pdev->ats_cap = 0; 5630} 5631 5632/* 5633 * Some devices require additional driver setup to enable ATS. Don't use 5634 * ATS for those devices as ATS will be enabled before the driver has had a 5635 * chance to load and configure the device. 5636 */ 5637static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5638{ 5639 if (pdev->device == 0x15d8) { 5640 if (pdev->revision == 0xcf && 5641 pdev->subsystem_vendor == 0xea50 && 5642 (pdev->subsystem_device == 0xce19 || 5643 pdev->subsystem_device == 0xcc10 || 5644 pdev->subsystem_device == 0xcc08)) 5645 quirk_no_ats(pdev); 5646 } else { 5647 quirk_no_ats(pdev); 5648 } 5649} 5650 5651/* AMD Stoney platform GPU */ 5652DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5653/* AMD Iceland dGPU */ 5654DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5655/* AMD Navi10 dGPU */ 5656DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5657DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5659DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5660DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5662DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5663DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5664/* AMD Navi14 dGPU */ 5665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5669/* AMD Raven platform iGPU */ 5670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5671 5672/* 5673 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5674 * in ATS Invalidate Request message body. Disable ATS for those devices. 5675 */ 5676static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5677{ 5678 if (pdev->revision < 0x20) 5679 quirk_no_ats(pdev); 5680} 5681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5686DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5687DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5688DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5689DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5690#endif /* CONFIG_PCI_ATS */ 5691 5692/* Freescale PCIe doesn't support MSI in RC mode */ 5693static void quirk_fsl_no_msi(struct pci_dev *pdev) 5694{ 5695 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5696 pdev->no_msi = 1; 5697} 5698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5699 5700/* 5701 * Although not allowed by the spec, some multi-function devices have 5702 * dependencies of one function (consumer) on another (supplier). For the 5703 * consumer to work in D0, the supplier must also be in D0. Create a 5704 * device link from the consumer to the supplier to enforce this 5705 * dependency. Runtime PM is allowed by default on the consumer to prevent 5706 * it from permanently keeping the supplier awake. 5707 */ 5708static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5709 unsigned int supplier, unsigned int class, 5710 unsigned int class_shift) 5711{ 5712 struct pci_dev *supplier_pdev; 5713 5714 if (PCI_FUNC(pdev->devfn) != consumer) 5715 return; 5716 5717 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5718 pdev->bus->number, 5719 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5720 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5721 pci_dev_put(supplier_pdev); 5722 return; 5723 } 5724 5725 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5726 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5727 pci_info(pdev, "D0 power state depends on %s\n", 5728 pci_name(supplier_pdev)); 5729 else 5730 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5731 pci_name(supplier_pdev)); 5732 5733 pm_runtime_allow(&pdev->dev); 5734 pci_dev_put(supplier_pdev); 5735} 5736 5737/* 5738 * Create device link for GPUs with integrated HDA controller for streaming 5739 * audio to attached displays. 5740 */ 5741static void quirk_gpu_hda(struct pci_dev *hda) 5742{ 5743 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5744} 5745DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5746 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5747DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5748 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5749DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5750 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5751 5752/* 5753 * Create device link for GPUs with integrated USB xHCI Host 5754 * controller to VGA. 5755 */ 5756static void quirk_gpu_usb(struct pci_dev *usb) 5757{ 5758 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5759} 5760DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5761 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5762DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5763 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5764 5765/* 5766 * Create device link for GPUs with integrated Type-C UCSI controller 5767 * to VGA. Currently there is no class code defined for UCSI device over PCI 5768 * so using UNKNOWN class for now and it will be updated when UCSI 5769 * over PCI gets a class code. 5770 */ 5771#define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5772static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5773{ 5774 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5775} 5776DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5777 PCI_CLASS_SERIAL_UNKNOWN, 8, 5778 quirk_gpu_usb_typec_ucsi); 5779DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5780 PCI_CLASS_SERIAL_UNKNOWN, 8, 5781 quirk_gpu_usb_typec_ucsi); 5782 5783/* 5784 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5785 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5786 */ 5787static void quirk_nvidia_hda(struct pci_dev *gpu) 5788{ 5789 u8 hdr_type; 5790 u32 val; 5791 5792 /* There was no integrated HDA controller before MCP89 */ 5793 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5794 return; 5795 5796 /* Bit 25 at offset 0x488 enables the HDA controller */ 5797 pci_read_config_dword(gpu, 0x488, &val); 5798 if (val & BIT(25)) 5799 return; 5800 5801 pci_info(gpu, "Enabling HDA controller\n"); 5802 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5803 5804 /* The GPU becomes a multi-function device when the HDA is enabled */ 5805 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5806 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5807} 5808DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5809 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5810DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5811 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5812 5813/* 5814 * Some IDT switches incorrectly flag an ACS Source Validation error on 5815 * completions for config read requests even though PCIe r4.0, sec 5816 * 6.12.1.1, says that completions are never affected by ACS Source 5817 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5818 * 5819 * Item #36 - Downstream port applies ACS Source Validation to Completions 5820 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5821 * completions are never affected by ACS Source Validation. However, 5822 * completions received by a downstream port of the PCIe switch from a 5823 * device that has not yet captured a PCIe bus number are incorrectly 5824 * dropped by ACS Source Validation by the switch downstream port. 5825 * 5826 * The workaround suggested by IDT is to issue a config write to the 5827 * downstream device before issuing the first config read. This allows the 5828 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5829 * sec 2.2.9), thus avoiding the ACS error on the completion. 5830 * 5831 * However, we don't know when the device is ready to accept the config 5832 * write, so we do config reads until we receive a non-Config Request Retry 5833 * Status, then do the config write. 5834 * 5835 * To avoid hitting the erratum when doing the config reads, we disable ACS 5836 * SV around this process. 5837 */ 5838int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5839{ 5840 int pos; 5841 u16 ctrl = 0; 5842 bool found; 5843 struct pci_dev *bridge = bus->self; 5844 5845 pos = bridge->acs_cap; 5846 5847 /* Disable ACS SV before initial config reads */ 5848 if (pos) { 5849 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5850 if (ctrl & PCI_ACS_SV) 5851 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5852 ctrl & ~PCI_ACS_SV); 5853 } 5854 5855 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5856 5857 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5858 if (found) 5859 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5860 5861 /* Re-enable ACS_SV if it was previously enabled */ 5862 if (ctrl & PCI_ACS_SV) 5863 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5864 5865 return found; 5866} 5867 5868/* 5869 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5870 * NT endpoints via the internal switch fabric. These IDs replace the 5871 * originating Requester ID TLPs which access host memory on peer NTB 5872 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5873 * to permit access when the IOMMU is turned on. 5874 */ 5875static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5876{ 5877 void __iomem *mmio; 5878 struct ntb_info_regs __iomem *mmio_ntb; 5879 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5880 u64 partition_map; 5881 u8 partition; 5882 int pp; 5883 5884 if (pci_enable_device(pdev)) { 5885 pci_err(pdev, "Cannot enable Switchtec device\n"); 5886 return; 5887 } 5888 5889 mmio = pci_iomap(pdev, 0, 0); 5890 if (mmio == NULL) { 5891 pci_disable_device(pdev); 5892 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5893 return; 5894 } 5895 5896 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5897 5898 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5899 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5900 5901 partition = ioread8(&mmio_ntb->partition_id); 5902 5903 partition_map = ioread32(&mmio_ntb->ep_map); 5904 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5905 partition_map &= ~(1ULL << partition); 5906 5907 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5908 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5909 u32 table_sz = 0; 5910 int te; 5911 5912 if (!(partition_map & (1ULL << pp))) 5913 continue; 5914 5915 pci_dbg(pdev, "Processing partition %d\n", pp); 5916 5917 mmio_peer_ctrl = &mmio_ctrl[pp]; 5918 5919 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5920 if (!table_sz) { 5921 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5922 continue; 5923 } 5924 5925 if (table_sz > 512) { 5926 pci_warn(pdev, 5927 "Invalid Switchtec partition %d table_sz %d\n", 5928 pp, table_sz); 5929 continue; 5930 } 5931 5932 for (te = 0; te < table_sz; te++) { 5933 u32 rid_entry; 5934 u8 devfn; 5935 5936 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5937 devfn = (rid_entry >> 1) & 0xFF; 5938 pci_dbg(pdev, 5939 "Aliasing Partition %d Proxy ID %02x.%d\n", 5940 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5941 pci_add_dma_alias(pdev, devfn, 1); 5942 } 5943 } 5944 5945 pci_iounmap(pdev, mmio); 5946 pci_disable_device(pdev); 5947} 5948#define SWITCHTEC_QUIRK(vid) \ 5949 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5950 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5951 5952SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5953SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5954SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5955SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5956SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5957SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5958SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5959SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5960SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5961SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5962SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5963SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5964SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5965SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5966SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5967SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5968SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5969SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5970SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5971SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5972SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5973SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5974SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5975SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5976SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5977SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5978SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5979SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5980SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5981SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5982SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5983SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5984SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5985SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5986SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5987SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5988SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5989SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5990SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5991SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5992SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5993SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5994SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5995SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5996SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5997SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5998SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5999SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 6000SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 6001SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 6002SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 6003SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 6004SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 6005SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 6006SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 6007SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 6008SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 6009SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 6010SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 6011SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 6012SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 6013SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 6014SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 6015SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 6016SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 6017SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 6018SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 6019SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 6020SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 6021SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 6022SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 6023SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 6024SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 6025SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 6026SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 6027SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 6028SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 6029SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 6030SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 6031SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 6032SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 6033SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 6034SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 6035SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 6036SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 6037SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 6038SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 6039SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 6040SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 6041SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 6042SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 6043SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 6044SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 6045 6046#define SWITCHTEC_PCI100X_QUIRK(vid) \ 6047 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 6048 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6049SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 6050SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 6051SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 6052SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 6053SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 6054SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 6055 6056 6057/* 6058 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6059 * These IDs are used to forward responses to the originator on the other 6060 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6061 * the IOMMU is turned on. 6062 */ 6063static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6064{ 6065 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6066 /* PLX NTB may use all 256 devfns */ 6067 pci_add_dma_alias(pdev, 0, 256); 6068} 6069DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6070DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6071 6072/* 6073 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6074 * not always reset the secondary Nvidia GPU between reboots if the system 6075 * is configured to use Hybrid Graphics mode. This results in the GPU 6076 * being left in whatever state it was in during the *previous* boot, which 6077 * causes spurious interrupts from the GPU, which in turn causes us to 6078 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6079 * this also completely breaks nouveau. 6080 * 6081 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6082 * clean state and fixes all these issues. 6083 * 6084 * When the machine is configured in Dedicated display mode, the issue 6085 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6086 * mode, so we can detect that and avoid resetting it. 6087 */ 6088static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6089{ 6090 void __iomem *map; 6091 int ret; 6092 6093 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6094 pdev->subsystem_device != 0x222e || 6095 !pci_reset_supported(pdev)) 6096 return; 6097 6098 if (pci_enable_device_mem(pdev)) 6099 return; 6100 6101 /* 6102 * Based on nvkm_device_ctor() in 6103 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6104 */ 6105 map = pci_iomap(pdev, 0, 0x23000); 6106 if (!map) { 6107 pci_err(pdev, "Can't map MMIO space\n"); 6108 goto out_disable; 6109 } 6110 6111 /* 6112 * Make sure the GPU looks like it's been POSTed before resetting 6113 * it. 6114 */ 6115 if (ioread32(map + 0x2240c) & 0x2) { 6116 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6117 ret = pci_reset_bus(pdev); 6118 if (ret < 0) 6119 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6120 } 6121 6122 iounmap(map); 6123out_disable: 6124 pci_disable_device(pdev); 6125} 6126DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6127 PCI_CLASS_DISPLAY_VGA, 8, 6128 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6129 6130/* 6131 * Device [1b21:2142] 6132 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6133 */ 6134static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6135{ 6136 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6137 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6138} 6139DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6140 6141/* 6142 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6143 * 6144 * These devices advertise PME# support in all power states but don't 6145 * reliably assert it. 6146 * 6147 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6148 * says "The MSI Function is not implemented on this device" in chapters 6149 * 7.3.27, 7.3.29-7.3.31. 6150 */ 6151static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6152{ 6153#ifdef CONFIG_PCI_MSI 6154 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6155 dev->no_msi = 1; 6156#endif 6157 pci_info(dev, "PME# is unreliable, disabling it\n"); 6158 dev->pme_support = 0; 6159} 6160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6162 6163static void apex_pci_fixup_class(struct pci_dev *pdev) 6164{ 6165 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6166} 6167DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6168 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6169 6170/* 6171 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6172 * ACS P2P Request Redirect is not functional 6173 * 6174 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6175 * between upstream and downstream ports, packets are queued in an internal 6176 * buffer until CPLD packet. The workaround is to use the switch in store and 6177 * forward mode. 6178 */ 6179#define PI7C9X2Gxxx_MODE_REG 0x74 6180#define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6181static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6182{ 6183 struct pci_dev *upstream; 6184 u16 val; 6185 6186 /* Downstream ports only */ 6187 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6188 return; 6189 6190 /* Check for ACS P2P Request Redirect use */ 6191 if (!pdev->acs_cap) 6192 return; 6193 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6194 if (!(val & PCI_ACS_RR)) 6195 return; 6196 6197 upstream = pci_upstream_bridge(pdev); 6198 if (!upstream) 6199 return; 6200 6201 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6202 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6203 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6204 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6205 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6206 } 6207} 6208/* 6209 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6210 * ACS configuration changes or switch mode is reset 6211 */ 6212DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6213 pci_fixup_pericom_acs_store_forward); 6214DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6215 pci_fixup_pericom_acs_store_forward); 6216DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6217 pci_fixup_pericom_acs_store_forward); 6218DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6219 pci_fixup_pericom_acs_store_forward); 6220DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6221 pci_fixup_pericom_acs_store_forward); 6222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6223 pci_fixup_pericom_acs_store_forward); 6224DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404, 6225 pci_fixup_pericom_acs_store_forward); 6226DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404, 6227 pci_fixup_pericom_acs_store_forward); 6228 6229static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6230{ 6231 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6232} 6233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6234 6235static void rom_bar_overlap_defect(struct pci_dev *dev) 6236{ 6237 pci_info(dev, "working around ROM BAR overlap defect\n"); 6238 dev->rom_bar_overlap = 1; 6239} 6240DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6241DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6242DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6243DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6244 6245#ifdef CONFIG_PCIEASPM 6246/* 6247 * Several Intel DG2 graphics devices advertise that they can only tolerate 6248 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6249 * from being enabled. But in fact these devices can tolerate unlimited 6250 * latency. Override their Device Capabilities value to allow ASPM L1 to 6251 * be enabled. 6252 */ 6253static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6254{ 6255 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6256 6257 if (l1_lat < 7) { 6258 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6259 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6260 l1_lat); 6261 } 6262} 6263DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6264DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6265DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6266DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6267DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6268DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6269DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6270DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6271DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6273DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6274DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6275DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6276DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6277DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6278DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6279DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6280DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6281DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6282DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6283DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6284DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6285DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6286DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6287DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6289#endif 6290 6291#ifdef CONFIG_PCIE_DPC 6292/* 6293 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6294 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6295 * Ports. 6296 */ 6297static void dpc_log_size(struct pci_dev *dev) 6298{ 6299 u16 dpc, val; 6300 6301 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6302 if (!dpc) 6303 return; 6304 6305 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6306 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6307 return; 6308 6309 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6310 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6311 PCIE_STD_NUM_TLP_HEADERLOG); 6312 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6313 } 6314} 6315DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6316DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6317DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6318DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6320DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6322DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6323DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6324DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6329DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6334#endif 6335 6336/* 6337 * For a PCI device with multiple downstream devices, its driver may use 6338 * a flattened device tree to describe the downstream devices. 6339 * To overlay the flattened device tree, the PCI device and all its ancestor 6340 * devices need to have device tree nodes on system base device tree. Thus, 6341 * before driver probing, it might need to add a device tree node as the final 6342 * fixup. 6343 */ 6344DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6345DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6346DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6347DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6348 6349/* 6350 * Devices known to require a longer delay before first config space access 6351 * after reset recovery or resume from D3cold: 6352 * 6353 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6354 */ 6355static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6356{ 6357 pdev->d3cold_delay = 1000; 6358} 6359DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6360 6361#ifdef CONFIG_PCIEAER 6362static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6363{ 6364 struct pci_dev *parent = pci_upstream_bridge(pdev); 6365 u32 val; 6366 6367 if (!parent || !parent->aer_cap) 6368 return; 6369 6370 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6371 pci_name(pdev)); 6372 6373 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6374 val |= PCI_ERR_COR_REP_TIMER; 6375 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6376} 6377DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6378DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6379#endif
~/
Read-only file preview.