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probe.c
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linux-6.19.14/drivers/pci/probe.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCI detection and setup code 4 */ 5 6#include <linux/array_size.h> 7#include <linux/kernel.h> 8#include <linux/delay.h> 9#include <linux/init.h> 10#include <linux/pci.h> 11#include <linux/msi.h> 12#include <linux/of_pci.h> 13#include <linux/of_platform.h> 14#include <linux/platform_device.h> 15#include <linux/pci_hotplug.h> 16#include <linux/slab.h> 17#include <linux/module.h> 18#include <linux/cpumask.h> 19#include <linux/aer.h> 20#include <linux/acpi.h> 21#include <linux/hypervisor.h> 22#include <linux/irqdomain.h> 23#include <linux/pm_runtime.h> 24#include <linux/bitfield.h> 25#include "pci.h" 26 27#define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ 28#define CARDBUS_RESERVE_BUSNR 3 29 30static struct resource busn_resource = { 31 .name = "PCI busn", 32 .start = 0, 33 .end = 255, 34 .flags = IORESOURCE_BUS, 35}; 36 37/* Ugh. Need to stop exporting this to modules. */ 38LIST_HEAD(pci_root_buses); 39EXPORT_SYMBOL(pci_root_buses); 40 41static LIST_HEAD(pci_domain_busn_res_list); 42 43struct pci_domain_busn_res { 44 struct list_head list; 45 struct resource res; 46 int domain_nr; 47}; 48 49static struct resource *get_pci_domain_busn_res(int domain_nr) 50{ 51 struct pci_domain_busn_res *r; 52 53 list_for_each_entry(r, &pci_domain_busn_res_list, list) 54 if (r->domain_nr == domain_nr) 55 return &r->res; 56 57 r = kzalloc(sizeof(*r), GFP_KERNEL); 58 if (!r) 59 return NULL; 60 61 r->domain_nr = domain_nr; 62 r->res.start = 0; 63 r->res.end = 0xff; 64 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED; 65 66 list_add_tail(&r->list, &pci_domain_busn_res_list); 67 68 return &r->res; 69} 70 71/* 72 * Some device drivers need know if PCI is initiated. 73 * Basically, we think PCI is not initiated when there 74 * is no device to be found on the pci_bus_type. 75 */ 76int no_pci_devices(void) 77{ 78 struct device *dev; 79 int no_devices; 80 81 dev = bus_find_next_device(&pci_bus_type, NULL); 82 no_devices = (dev == NULL); 83 put_device(dev); 84 return no_devices; 85} 86EXPORT_SYMBOL(no_pci_devices); 87 88/* 89 * PCI Bus Class 90 */ 91static void release_pcibus_dev(struct device *dev) 92{ 93 struct pci_bus *pci_bus = to_pci_bus(dev); 94 95 put_device(pci_bus->bridge); 96 pci_bus_remove_resources(pci_bus); 97 pci_release_bus_of_node(pci_bus); 98 kfree(pci_bus); 99} 100 101static const struct class pcibus_class = { 102 .name = "pci_bus", 103 .dev_release = &release_pcibus_dev, 104 .dev_groups = pcibus_groups, 105}; 106 107static int __init pcibus_class_init(void) 108{ 109 return class_register(&pcibus_class); 110} 111postcore_initcall(pcibus_class_init); 112 113static u64 pci_size(u64 base, u64 maxbase, u64 mask) 114{ 115 u64 size = mask & maxbase; /* Find the significant bits */ 116 if (!size) 117 return 0; 118 119 /* 120 * Get the lowest of them to find the decode size, and from that 121 * the extent. 122 */ 123 size = size & ~(size-1); 124 125 /* 126 * base == maxbase can be valid only if the BAR has already been 127 * programmed with all 1s. 128 */ 129 if (base == maxbase && ((base | (size - 1)) & mask) != mask) 130 return 0; 131 132 return size; 133} 134 135static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar) 136{ 137 u32 mem_type; 138 unsigned long flags; 139 140 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) { 141 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK; 142 flags |= IORESOURCE_IO; 143 return flags; 144 } 145 146 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK; 147 flags |= IORESOURCE_MEM; 148 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) 149 flags |= IORESOURCE_PREFETCH; 150 151 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK; 152 switch (mem_type) { 153 case PCI_BASE_ADDRESS_MEM_TYPE_32: 154 break; 155 case PCI_BASE_ADDRESS_MEM_TYPE_1M: 156 /* 1M mem BAR treated as 32-bit BAR */ 157 break; 158 case PCI_BASE_ADDRESS_MEM_TYPE_64: 159 flags |= IORESOURCE_MEM_64; 160 break; 161 default: 162 /* mem unknown type treated as 32-bit BAR */ 163 break; 164 } 165 return flags; 166} 167 168#define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO) 169 170/** 171 * __pci_size_bars - Read the raw BAR mask for a range of PCI BARs 172 * @dev: the PCI device 173 * @count: number of BARs to size 174 * @pos: starting config space position 175 * @sizes: array to store mask values 176 * @rom: indicate whether to use ROM mask, which avoids enabling ROM BARs 177 * 178 * Provided @sizes array must be sufficiently sized to store results for 179 * @count u32 BARs. Caller is responsible for disabling decode to specified 180 * BAR range around calling this function. This function is intended to avoid 181 * disabling decode around sizing each BAR individually, which can result in 182 * non-trivial overhead in virtualized environments with very large PCI BARs. 183 */ 184static void __pci_size_bars(struct pci_dev *dev, int count, 185 unsigned int pos, u32 *sizes, bool rom) 186{ 187 u32 orig, mask = rom ? PCI_ROM_ADDRESS_MASK : ~0; 188 int i; 189 190 for (i = 0; i < count; i++, pos += 4, sizes++) { 191 pci_read_config_dword(dev, pos, &orig); 192 pci_write_config_dword(dev, pos, mask); 193 pci_read_config_dword(dev, pos, sizes); 194 pci_write_config_dword(dev, pos, orig); 195 } 196} 197 198void __pci_size_stdbars(struct pci_dev *dev, int count, 199 unsigned int pos, u32 *sizes) 200{ 201 __pci_size_bars(dev, count, pos, sizes, false); 202} 203 204static void __pci_size_rom(struct pci_dev *dev, unsigned int pos, u32 *sizes) 205{ 206 __pci_size_bars(dev, 1, pos, sizes, true); 207} 208 209/** 210 * __pci_read_base - Read a PCI BAR 211 * @dev: the PCI device 212 * @type: type of the BAR 213 * @res: resource buffer to be filled in 214 * @pos: BAR position in the config space 215 * @sizes: array of one or more pre-read BAR masks 216 * 217 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit. 218 */ 219int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 220 struct resource *res, unsigned int pos, u32 *sizes) 221{ 222 u32 l = 0, sz; 223 u64 l64, sz64, mask64; 224 struct pci_bus_region region, inverted_region; 225 const char *res_name = pci_resource_name(dev, res - dev->resource); 226 227 res->name = pci_name(dev); 228 229 pci_read_config_dword(dev, pos, &l); 230 sz = sizes[0]; 231 232 /* 233 * All bits set in sz means the device isn't working properly. 234 * If the BAR isn't implemented, all bits must be 0. If it's a 235 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit 236 * 1 must be clear. 237 */ 238 if (PCI_POSSIBLE_ERROR(sz)) 239 sz = 0; 240 241 /* 242 * I don't know how l can have all bits set. Copied from old code. 243 * Maybe it fixes a bug on some ancient platform. 244 */ 245 if (PCI_POSSIBLE_ERROR(l)) 246 l = 0; 247 248 if (type == pci_bar_unknown) { 249 res->flags = decode_bar(dev, l); 250 res->flags |= IORESOURCE_SIZEALIGN; 251 if (res->flags & IORESOURCE_IO) { 252 l64 = l & PCI_BASE_ADDRESS_IO_MASK; 253 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK; 254 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT; 255 } else { 256 l64 = l & PCI_BASE_ADDRESS_MEM_MASK; 257 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK; 258 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK; 259 } 260 } else { 261 if (l & PCI_ROM_ADDRESS_ENABLE) 262 res->flags |= IORESOURCE_ROM_ENABLE; 263 l64 = l & PCI_ROM_ADDRESS_MASK; 264 sz64 = sz & PCI_ROM_ADDRESS_MASK; 265 mask64 = PCI_ROM_ADDRESS_MASK; 266 } 267 268 if (res->flags & IORESOURCE_MEM_64) { 269 pci_read_config_dword(dev, pos + 4, &l); 270 sz = sizes[1]; 271 272 l64 |= ((u64)l << 32); 273 sz64 |= ((u64)sz << 32); 274 mask64 |= ((u64)~0 << 32); 275 } 276 277 if (!sz64) 278 goto fail; 279 280 sz64 = pci_size(l64, sz64, mask64); 281 if (!sz64) { 282 pci_info(dev, FW_BUG "%s: invalid; can't size\n", res_name); 283 goto fail; 284 } 285 286 if (res->flags & IORESOURCE_MEM_64) { 287 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8) 288 && sz64 > 0x100000000ULL) { 289 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 290 resource_set_range(res, 0, 0); 291 pci_err(dev, "%s: can't handle BAR larger than 4GB (size %#010llx)\n", 292 res_name, (unsigned long long)sz64); 293 goto out; 294 } 295 296 if ((sizeof(pci_bus_addr_t) < 8) && l) { 297 /* Above 32-bit boundary; try to reallocate */ 298 res->flags |= IORESOURCE_UNSET; 299 resource_set_range(res, 0, sz64); 300 pci_info(dev, "%s: can't handle BAR above 4GB (bus address %#010llx)\n", 301 res_name, (unsigned long long)l64); 302 goto out; 303 } 304 } 305 306 region.start = l64; 307 region.end = l64 + sz64 - 1; 308 309 pcibios_bus_to_resource(dev->bus, res, ®ion); 310 pcibios_resource_to_bus(dev->bus, &inverted_region, res); 311 312 /* 313 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is 314 * the corresponding resource address (the physical address used by 315 * the CPU. Converting that resource address back to a bus address 316 * should yield the original BAR value: 317 * 318 * resource_to_bus(bus_to_resource(A)) == A 319 * 320 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not 321 * be claimed by the device. 322 */ 323 if (inverted_region.start != region.start) { 324 res->flags |= IORESOURCE_UNSET; 325 res->start = 0; 326 res->end = region.end - region.start; 327 pci_info(dev, "%s: initial BAR value %#010llx invalid\n", 328 res_name, (unsigned long long)region.start); 329 } 330 331 goto out; 332 333 334fail: 335 res->flags = 0; 336out: 337 if (res->flags) 338 pci_info(dev, "%s %pR\n", res_name, res); 339 340 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0; 341} 342 343static __always_inline void pci_read_bases(struct pci_dev *dev, 344 unsigned int howmany, int rom) 345{ 346 u32 rombar, stdbars[PCI_STD_NUM_BARS]; 347 unsigned int pos, reg; 348 u16 orig_cmd; 349 350 BUILD_BUG_ON(statically_true(howmany > PCI_STD_NUM_BARS)); 351 352 if (dev->non_compliant_bars) 353 return; 354 355 /* Per PCIe r4.0, sec 9.3.4.1.11, the VF BARs are all RO Zero */ 356 if (dev->is_virtfn) 357 return; 358 359 /* No printks while decoding is disabled! */ 360 if (!dev->mmio_always_on) { 361 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd); 362 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) { 363 pci_write_config_word(dev, PCI_COMMAND, 364 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE); 365 } 366 } 367 368 __pci_size_stdbars(dev, howmany, PCI_BASE_ADDRESS_0, stdbars); 369 if (rom) 370 __pci_size_rom(dev, rom, &rombar); 371 372 if (!dev->mmio_always_on && 373 (orig_cmd & PCI_COMMAND_DECODE_ENABLE)) 374 pci_write_config_word(dev, PCI_COMMAND, orig_cmd); 375 376 for (pos = 0; pos < howmany; pos++) { 377 struct resource *res = &dev->resource[pos]; 378 reg = PCI_BASE_ADDRESS_0 + (pos << 2); 379 pos += __pci_read_base(dev, pci_bar_unknown, 380 res, reg, &stdbars[pos]); 381 } 382 383 if (rom) { 384 struct resource *res = &dev->resource[PCI_ROM_RESOURCE]; 385 dev->rom_base_reg = rom; 386 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH | 387 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN; 388 __pci_read_base(dev, pci_bar_mem32, res, rom, &rombar); 389 } 390} 391 392static void pci_read_bridge_io(struct pci_dev *dev, struct resource *res, 393 bool log) 394{ 395 u8 io_base_lo, io_limit_lo; 396 unsigned long io_mask, io_granularity, base, limit; 397 struct pci_bus_region region; 398 399 io_mask = PCI_IO_RANGE_MASK; 400 io_granularity = 0x1000; 401 if (dev->io_window_1k) { 402 /* Support 1K I/O space granularity */ 403 io_mask = PCI_IO_1K_RANGE_MASK; 404 io_granularity = 0x400; 405 } 406 407 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); 408 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); 409 base = (io_base_lo & io_mask) << 8; 410 limit = (io_limit_lo & io_mask) << 8; 411 412 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { 413 u16 io_base_hi, io_limit_hi; 414 415 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); 416 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); 417 base |= ((unsigned long) io_base_hi << 16); 418 limit |= ((unsigned long) io_limit_hi << 16); 419 } 420 421 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; 422 423 if (base <= limit) { 424 region.start = base; 425 region.end = limit + io_granularity - 1; 426 pcibios_bus_to_resource(dev->bus, res, ®ion); 427 if (log) 428 pci_info(dev, " bridge window %pR\n", res); 429 } else { 430 resource_set_range(res, 0, 0); 431 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 432 } 433} 434 435static void pci_read_bridge_mmio(struct pci_dev *dev, struct resource *res, 436 bool log) 437{ 438 u16 mem_base_lo, mem_limit_lo; 439 unsigned long base, limit; 440 struct pci_bus_region region; 441 442 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); 443 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); 444 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; 445 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; 446 447 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; 448 449 if (base <= limit) { 450 region.start = base; 451 region.end = limit + 0xfffff; 452 pcibios_bus_to_resource(dev->bus, res, ®ion); 453 if (log) 454 pci_info(dev, " bridge window %pR\n", res); 455 } else { 456 resource_set_range(res, 0, 0); 457 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 458 } 459} 460 461static void pci_read_bridge_mmio_pref(struct pci_dev *dev, struct resource *res, 462 bool log) 463{ 464 u16 mem_base_lo, mem_limit_lo; 465 u64 base64, limit64; 466 pci_bus_addr_t base, limit; 467 struct pci_bus_region region; 468 469 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); 470 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); 471 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; 472 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; 473 474 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 475 u32 mem_base_hi, mem_limit_hi; 476 477 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); 478 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); 479 480 /* 481 * Some bridges set the base > limit by default, and some 482 * (broken) BIOSes do not initialize them. If we find 483 * this, just assume they are not being used. 484 */ 485 if (mem_base_hi <= mem_limit_hi) { 486 base64 |= (u64) mem_base_hi << 32; 487 limit64 |= (u64) mem_limit_hi << 32; 488 } 489 } 490 491 base = (pci_bus_addr_t) base64; 492 limit = (pci_bus_addr_t) limit64; 493 494 if (base != base64) { 495 pci_err(dev, "can't handle bridge window above 4GB (bus address %#010llx)\n", 496 (unsigned long long) base64); 497 return; 498 } 499 500 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) | IORESOURCE_MEM | 501 IORESOURCE_PREFETCH; 502 if (res->flags & PCI_PREF_RANGE_TYPE_64) 503 res->flags |= IORESOURCE_MEM_64; 504 505 if (base <= limit) { 506 region.start = base; 507 region.end = limit + 0xfffff; 508 pcibios_bus_to_resource(dev->bus, res, ®ion); 509 if (log) 510 pci_info(dev, " bridge window %pR\n", res); 511 } else { 512 resource_set_range(res, 0, 0); 513 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED; 514 } 515} 516 517static void pci_read_bridge_windows(struct pci_dev *bridge) 518{ 519 u32 buses; 520 u16 io; 521 u32 pmem, tmp; 522 struct resource res; 523 524 pci_read_config_dword(bridge, PCI_PRIMARY_BUS, &buses); 525 res.flags = IORESOURCE_BUS; 526 res.start = (buses >> 8) & 0xff; 527 res.end = (buses >> 16) & 0xff; 528 pci_info(bridge, "PCI bridge to %pR%s\n", &res, 529 bridge->transparent ? " (subtractive decode)" : ""); 530 531 pci_read_config_word(bridge, PCI_IO_BASE, &io); 532 if (!io) { 533 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0); 534 pci_read_config_word(bridge, PCI_IO_BASE, &io); 535 pci_write_config_word(bridge, PCI_IO_BASE, 0x0); 536 } 537 if (io) { 538 bridge->io_window = 1; 539 pci_read_bridge_io(bridge, &res, true); 540 } 541 542 pci_read_bridge_mmio(bridge, &res, true); 543 544 /* 545 * DECchip 21050 pass 2 errata: the bridge may miss an address 546 * disconnect boundary by one PCI data phase. Workaround: do not 547 * use prefetching on this device. 548 */ 549 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) 550 return; 551 552 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 553 if (!pmem) { 554 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 555 0xffe0fff0); 556 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); 557 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); 558 } 559 if (!pmem) 560 return; 561 562 bridge->pref_window = 1; 563 564 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { 565 566 /* 567 * Bridge claims to have a 64-bit prefetchable memory 568 * window; verify that the upper bits are actually 569 * writable. 570 */ 571 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &pmem); 572 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 573 0xffffffff); 574 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp); 575 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, pmem); 576 if (tmp) 577 bridge->pref_64_window = 1; 578 } 579 580 pci_read_bridge_mmio_pref(bridge, &res, true); 581} 582 583void pci_read_bridge_bases(struct pci_bus *child) 584{ 585 struct pci_dev *dev = child->self; 586 struct resource *res; 587 int i; 588 589 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */ 590 return; 591 592 pci_info(dev, "PCI bridge to %pR%s\n", 593 &child->busn_res, 594 dev->transparent ? " (subtractive decode)" : ""); 595 596 pci_bus_remove_resources(child); 597 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) 598 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; 599 600 pci_read_bridge_io(child->self, 601 child->resource[PCI_BUS_BRIDGE_IO_WINDOW], false); 602 pci_read_bridge_mmio(child->self, 603 child->resource[PCI_BUS_BRIDGE_MEM_WINDOW], false); 604 pci_read_bridge_mmio_pref(child->self, 605 child->resource[PCI_BUS_BRIDGE_PREF_MEM_WINDOW], 606 false); 607 608 if (!dev->transparent) 609 return; 610 611 pci_bus_for_each_resource(child->parent, res) { 612 if (!res || !res->flags) 613 continue; 614 615 pci_bus_add_resource(child, res); 616 pci_info(dev, " bridge window %pR (subtractive decode)\n", res); 617 } 618} 619 620static struct pci_bus *pci_alloc_bus(struct pci_bus *parent) 621{ 622 struct pci_bus *b; 623 624 b = kzalloc(sizeof(*b), GFP_KERNEL); 625 if (!b) 626 return NULL; 627 628 INIT_LIST_HEAD(&b->node); 629 INIT_LIST_HEAD(&b->children); 630 INIT_LIST_HEAD(&b->devices); 631 INIT_LIST_HEAD(&b->slots); 632 INIT_LIST_HEAD(&b->resources); 633 b->max_bus_speed = PCI_SPEED_UNKNOWN; 634 b->cur_bus_speed = PCI_SPEED_UNKNOWN; 635#ifdef CONFIG_PCI_DOMAINS_GENERIC 636 if (parent) 637 b->domain_nr = parent->domain_nr; 638#endif 639 return b; 640} 641 642static void pci_release_host_bridge_dev(struct device *dev) 643{ 644 struct pci_host_bridge *bridge = to_pci_host_bridge(dev); 645 646 if (bridge->release_fn) 647 bridge->release_fn(bridge); 648 649 pci_free_resource_list(&bridge->windows); 650 pci_free_resource_list(&bridge->dma_ranges); 651 652 /* Host bridges only have domain_nr set in the emulation case */ 653 if (bridge->domain_nr != PCI_DOMAIN_NR_NOT_SET) 654 pci_bus_release_emul_domain_nr(bridge->domain_nr); 655 656 kfree(bridge); 657} 658 659static const struct attribute_group *pci_host_bridge_groups[] = { 660#ifdef CONFIG_PCI_IDE 661 &pci_ide_attr_group, 662#endif 663 NULL 664}; 665 666static const struct device_type pci_host_bridge_type = { 667 .groups = pci_host_bridge_groups, 668 .release = pci_release_host_bridge_dev, 669}; 670 671static void pci_init_host_bridge(struct pci_host_bridge *bridge) 672{ 673 INIT_LIST_HEAD(&bridge->windows); 674 INIT_LIST_HEAD(&bridge->dma_ranges); 675 676 /* 677 * We assume we can manage these PCIe features. Some systems may 678 * reserve these for use by the platform itself, e.g., an ACPI BIOS 679 * may implement its own AER handling and use _OSC to prevent the 680 * OS from interfering. 681 */ 682 bridge->native_aer = 1; 683 bridge->native_pcie_hotplug = 1; 684 bridge->native_shpc_hotplug = 1; 685 bridge->native_pme = 1; 686 bridge->native_ltr = 1; 687 bridge->native_dpc = 1; 688 bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET; 689 bridge->native_cxl_error = 1; 690 bridge->dev.type = &pci_host_bridge_type; 691 pci_ide_init_host_bridge(bridge); 692 693 device_initialize(&bridge->dev); 694} 695 696struct pci_host_bridge *pci_alloc_host_bridge(size_t priv) 697{ 698 struct pci_host_bridge *bridge; 699 700 bridge = kzalloc(sizeof(*bridge) + priv, GFP_KERNEL); 701 if (!bridge) 702 return NULL; 703 704 pci_init_host_bridge(bridge); 705 706 return bridge; 707} 708EXPORT_SYMBOL(pci_alloc_host_bridge); 709 710static void devm_pci_alloc_host_bridge_release(void *data) 711{ 712 pci_free_host_bridge(data); 713} 714 715struct pci_host_bridge *devm_pci_alloc_host_bridge(struct device *dev, 716 size_t priv) 717{ 718 int ret; 719 struct pci_host_bridge *bridge; 720 721 bridge = pci_alloc_host_bridge(priv); 722 if (!bridge) 723 return NULL; 724 725 bridge->dev.parent = dev; 726 727 ret = devm_add_action_or_reset(dev, devm_pci_alloc_host_bridge_release, 728 bridge); 729 if (ret) 730 return NULL; 731 732 ret = devm_of_pci_bridge_init(dev, bridge); 733 if (ret) 734 return NULL; 735 736 return bridge; 737} 738EXPORT_SYMBOL(devm_pci_alloc_host_bridge); 739 740void pci_free_host_bridge(struct pci_host_bridge *bridge) 741{ 742 put_device(&bridge->dev); 743} 744EXPORT_SYMBOL(pci_free_host_bridge); 745 746/* Indexed by PCI_X_SSTATUS_FREQ (secondary bus mode and frequency) */ 747static const unsigned char pcix_bus_speed[] = { 748 PCI_SPEED_UNKNOWN, /* 0 */ 749 PCI_SPEED_66MHz_PCIX, /* 1 */ 750 PCI_SPEED_100MHz_PCIX, /* 2 */ 751 PCI_SPEED_133MHz_PCIX, /* 3 */ 752 PCI_SPEED_UNKNOWN, /* 4 */ 753 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */ 754 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */ 755 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */ 756 PCI_SPEED_UNKNOWN, /* 8 */ 757 PCI_SPEED_66MHz_PCIX_266, /* 9 */ 758 PCI_SPEED_100MHz_PCIX_266, /* A */ 759 PCI_SPEED_133MHz_PCIX_266, /* B */ 760 PCI_SPEED_UNKNOWN, /* C */ 761 PCI_SPEED_66MHz_PCIX_533, /* D */ 762 PCI_SPEED_100MHz_PCIX_533, /* E */ 763 PCI_SPEED_133MHz_PCIX_533 /* F */ 764}; 765 766/* Indexed by PCI_EXP_LNKCAP_SLS, PCI_EXP_LNKSTA_CLS */ 767const unsigned char pcie_link_speed[] = { 768 PCI_SPEED_UNKNOWN, /* 0 */ 769 PCIE_SPEED_2_5GT, /* 1 */ 770 PCIE_SPEED_5_0GT, /* 2 */ 771 PCIE_SPEED_8_0GT, /* 3 */ 772 PCIE_SPEED_16_0GT, /* 4 */ 773 PCIE_SPEED_32_0GT, /* 5 */ 774 PCIE_SPEED_64_0GT, /* 6 */ 775 PCI_SPEED_UNKNOWN, /* 7 */ 776 PCI_SPEED_UNKNOWN, /* 8 */ 777 PCI_SPEED_UNKNOWN, /* 9 */ 778 PCI_SPEED_UNKNOWN, /* A */ 779 PCI_SPEED_UNKNOWN, /* B */ 780 PCI_SPEED_UNKNOWN, /* C */ 781 PCI_SPEED_UNKNOWN, /* D */ 782 PCI_SPEED_UNKNOWN, /* E */ 783 PCI_SPEED_UNKNOWN /* F */ 784}; 785EXPORT_SYMBOL_GPL(pcie_link_speed); 786 787const char *pci_speed_string(enum pci_bus_speed speed) 788{ 789 /* Indexed by the pci_bus_speed enum */ 790 static const char *speed_strings[] = { 791 "33 MHz PCI", /* 0x00 */ 792 "66 MHz PCI", /* 0x01 */ 793 "66 MHz PCI-X", /* 0x02 */ 794 "100 MHz PCI-X", /* 0x03 */ 795 "133 MHz PCI-X", /* 0x04 */ 796 NULL, /* 0x05 */ 797 NULL, /* 0x06 */ 798 NULL, /* 0x07 */ 799 NULL, /* 0x08 */ 800 "66 MHz PCI-X 266", /* 0x09 */ 801 "100 MHz PCI-X 266", /* 0x0a */ 802 "133 MHz PCI-X 266", /* 0x0b */ 803 "Unknown AGP", /* 0x0c */ 804 "1x AGP", /* 0x0d */ 805 "2x AGP", /* 0x0e */ 806 "4x AGP", /* 0x0f */ 807 "8x AGP", /* 0x10 */ 808 "66 MHz PCI-X 533", /* 0x11 */ 809 "100 MHz PCI-X 533", /* 0x12 */ 810 "133 MHz PCI-X 533", /* 0x13 */ 811 "2.5 GT/s PCIe", /* 0x14 */ 812 "5.0 GT/s PCIe", /* 0x15 */ 813 "8.0 GT/s PCIe", /* 0x16 */ 814 "16.0 GT/s PCIe", /* 0x17 */ 815 "32.0 GT/s PCIe", /* 0x18 */ 816 "64.0 GT/s PCIe", /* 0x19 */ 817 }; 818 819 if (speed < ARRAY_SIZE(speed_strings)) 820 return speed_strings[speed]; 821 return "Unknown"; 822} 823EXPORT_SYMBOL_GPL(pci_speed_string); 824 825void pcie_update_link_speed(struct pci_bus *bus) 826{ 827 struct pci_dev *bridge = bus->self; 828 u16 linksta, linksta2; 829 830 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta); 831 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA2, &linksta2); 832 __pcie_update_link_speed(bus, linksta, linksta2); 833} 834EXPORT_SYMBOL_GPL(pcie_update_link_speed); 835 836static unsigned char agp_speeds[] = { 837 AGP_UNKNOWN, 838 AGP_1X, 839 AGP_2X, 840 AGP_4X, 841 AGP_8X 842}; 843 844static enum pci_bus_speed agp_speed(int agp3, int agpstat) 845{ 846 int index = 0; 847 848 if (agpstat & 4) 849 index = 3; 850 else if (agpstat & 2) 851 index = 2; 852 else if (agpstat & 1) 853 index = 1; 854 else 855 goto out; 856 857 if (agp3) { 858 index += 2; 859 if (index == 5) 860 index = 0; 861 } 862 863 out: 864 return agp_speeds[index]; 865} 866 867static void pci_set_bus_speed(struct pci_bus *bus) 868{ 869 struct pci_dev *bridge = bus->self; 870 int pos; 871 872 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP); 873 if (!pos) 874 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3); 875 if (pos) { 876 u32 agpstat, agpcmd; 877 878 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat); 879 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7); 880 881 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd); 882 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7); 883 } 884 885 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 886 if (pos) { 887 u16 status; 888 enum pci_bus_speed max; 889 890 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS, 891 &status); 892 893 if (status & PCI_X_SSTATUS_533MHZ) { 894 max = PCI_SPEED_133MHz_PCIX_533; 895 } else if (status & PCI_X_SSTATUS_266MHZ) { 896 max = PCI_SPEED_133MHz_PCIX_266; 897 } else if (status & PCI_X_SSTATUS_133MHZ) { 898 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) 899 max = PCI_SPEED_133MHz_PCIX_ECC; 900 else 901 max = PCI_SPEED_133MHz_PCIX; 902 } else { 903 max = PCI_SPEED_66MHz_PCIX; 904 } 905 906 bus->max_bus_speed = max; 907 bus->cur_bus_speed = 908 pcix_bus_speed[FIELD_GET(PCI_X_SSTATUS_FREQ, status)]; 909 910 return; 911 } 912 913 if (pci_is_pcie(bridge)) { 914 u32 linkcap; 915 916 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap); 917 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS]; 918 919 pcie_update_link_speed(bus); 920 } 921} 922 923static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus) 924{ 925 struct irq_domain *d; 926 927 /* If the host bridge driver sets a MSI domain of the bridge, use it */ 928 d = dev_get_msi_domain(bus->bridge); 929 930 /* 931 * Any firmware interface that can resolve the msi_domain 932 * should be called from here. 933 */ 934 if (!d) 935 d = pci_host_bridge_of_msi_domain(bus); 936 if (!d) 937 d = pci_host_bridge_acpi_msi_domain(bus); 938 939 /* 940 * If no IRQ domain was found via the OF tree, try looking it up 941 * directly through the fwnode_handle. 942 */ 943 if (!d) { 944 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus); 945 946 if (fwnode) 947 d = irq_find_matching_fwnode(fwnode, 948 DOMAIN_BUS_PCI_MSI); 949 } 950 951 return d; 952} 953 954static void pci_set_bus_msi_domain(struct pci_bus *bus) 955{ 956 struct irq_domain *d; 957 struct pci_bus *b; 958 959 /* 960 * The bus can be a root bus, a subordinate bus, or a virtual bus 961 * created by an SR-IOV device. Walk up to the first bridge device 962 * found or derive the domain from the host bridge. 963 */ 964 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) { 965 if (b->self) 966 d = dev_get_msi_domain(&b->self->dev); 967 } 968 969 if (!d) 970 d = pci_host_bridge_msi_domain(b); 971 972 dev_set_msi_domain(&bus->dev, d); 973} 974 975static bool pci_preserve_config(struct pci_host_bridge *host_bridge) 976{ 977 if (pci_acpi_preserve_config(host_bridge)) 978 return true; 979 980 if (host_bridge->dev.parent && host_bridge->dev.parent->of_node) 981 return of_pci_preserve_config(host_bridge->dev.parent->of_node); 982 983 return false; 984} 985 986static int pci_register_host_bridge(struct pci_host_bridge *bridge) 987{ 988 struct device *parent = bridge->dev.parent; 989 struct resource_entry *window, *next, *n; 990 struct pci_bus *bus, *b; 991 resource_size_t offset, next_offset; 992 LIST_HEAD(resources); 993 struct resource *res, *next_res; 994 bool bus_registered = false; 995 char addr[64], *fmt; 996 const char *name; 997 int err; 998 999 bus = pci_alloc_bus(NULL); 1000 if (!bus) 1001 return -ENOMEM; 1002 1003 bridge->bus = bus; 1004 1005 bus->sysdata = bridge->sysdata; 1006 bus->ops = bridge->ops; 1007 bus->number = bus->busn_res.start = bridge->busnr; 1008#ifdef CONFIG_PCI_DOMAINS_GENERIC 1009 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 1010 bus->domain_nr = pci_bus_find_domain_nr(bus, parent); 1011 else 1012 bus->domain_nr = bridge->domain_nr; 1013 if (bus->domain_nr < 0) { 1014 err = bus->domain_nr; 1015 goto free; 1016 } 1017#endif 1018 1019 b = pci_find_bus(pci_domain_nr(bus), bridge->busnr); 1020 if (b) { 1021 /* Ignore it if we already got here via a different bridge */ 1022 dev_dbg(&b->dev, "bus already known\n"); 1023 err = -EEXIST; 1024 goto free; 1025 } 1026 1027 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(bus), 1028 bridge->busnr); 1029 1030 err = pcibios_root_bridge_prepare(bridge); 1031 if (err) 1032 goto free; 1033 1034 /* Temporarily move resources off the list */ 1035 list_splice_init(&bridge->windows, &resources); 1036 err = device_add(&bridge->dev); 1037 if (err) 1038 goto free; 1039 1040 bus->bridge = get_device(&bridge->dev); 1041 device_enable_async_suspend(bus->bridge); 1042 pci_set_bus_of_node(bus); 1043 pci_set_bus_msi_domain(bus); 1044 if (bridge->msi_domain && !dev_get_msi_domain(&bus->dev) && 1045 !pci_host_of_has_msi_map(parent)) 1046 bus->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 1047 1048 if (!parent) 1049 set_dev_node(bus->bridge, pcibus_to_node(bus)); 1050 1051 bus->dev.class = &pcibus_class; 1052 bus->dev.parent = bus->bridge; 1053 1054 dev_set_name(&bus->dev, "%04x:%02x", pci_domain_nr(bus), bus->number); 1055 name = dev_name(&bus->dev); 1056 1057 err = device_register(&bus->dev); 1058 bus_registered = true; 1059 if (err) 1060 goto unregister; 1061 1062 pcibios_add_bus(bus); 1063 1064 if (bus->ops->add_bus) { 1065 err = bus->ops->add_bus(bus); 1066 if (WARN_ON(err < 0)) 1067 dev_err(&bus->dev, "failed to add bus: %d\n", err); 1068 } 1069 1070 /* Create legacy_io and legacy_mem files for this bus */ 1071 pci_create_legacy_files(bus); 1072 1073 if (parent) 1074 dev_info(parent, "PCI host bridge to bus %s\n", name); 1075 else 1076 pr_info("PCI host bridge to bus %s\n", name); 1077 1078 if (nr_node_ids > 1 && pcibus_to_node(bus) == NUMA_NO_NODE) 1079 dev_warn(&bus->dev, "Unknown NUMA node; performance will be reduced\n"); 1080 1081 /* Check if the boot configuration by FW needs to be preserved */ 1082 bridge->preserve_config = pci_preserve_config(bridge); 1083 1084 /* Coalesce contiguous windows */ 1085 resource_list_for_each_entry_safe(window, n, &resources) { 1086 if (list_is_last(&window->node, &resources)) 1087 break; 1088 1089 next = list_next_entry(window, node); 1090 offset = window->offset; 1091 res = window->res; 1092 next_offset = next->offset; 1093 next_res = next->res; 1094 1095 if (res->flags != next_res->flags || offset != next_offset) 1096 continue; 1097 1098 if (res->end + 1 == next_res->start) { 1099 next_res->start = res->start; 1100 res->flags = res->start = res->end = 0; 1101 } 1102 } 1103 1104 /* Add initial resources to the bus */ 1105 resource_list_for_each_entry_safe(window, n, &resources) { 1106 offset = window->offset; 1107 res = window->res; 1108 if (!res->flags && !res->start && !res->end) { 1109 release_resource(res); 1110 resource_list_destroy_entry(window); 1111 continue; 1112 } 1113 1114 list_move_tail(&window->node, &bridge->windows); 1115 1116 if (res->flags & IORESOURCE_BUS) 1117 pci_bus_insert_busn_res(bus, bus->number, res->end); 1118 else 1119 pci_bus_add_resource(bus, res); 1120 1121 if (offset) { 1122 if (resource_type(res) == IORESOURCE_IO) 1123 fmt = " (bus address [%#06llx-%#06llx])"; 1124 else 1125 fmt = " (bus address [%#010llx-%#010llx])"; 1126 1127 snprintf(addr, sizeof(addr), fmt, 1128 (unsigned long long)(res->start - offset), 1129 (unsigned long long)(res->end - offset)); 1130 } else 1131 addr[0] = '\0'; 1132 1133 dev_info(&bus->dev, "root bus resource %pR%s\n", res, addr); 1134 } 1135 1136 of_pci_make_host_bridge_node(bridge); 1137 1138 down_write(&pci_bus_sem); 1139 list_add_tail(&bus->node, &pci_root_buses); 1140 up_write(&pci_bus_sem); 1141 1142 return 0; 1143 1144unregister: 1145 put_device(&bridge->dev); 1146 device_del(&bridge->dev); 1147free: 1148#ifdef CONFIG_PCI_DOMAINS_GENERIC 1149 if (bridge->domain_nr == PCI_DOMAIN_NR_NOT_SET) 1150 pci_bus_release_domain_nr(parent, bus->domain_nr); 1151#endif 1152 if (bus_registered) 1153 put_device(&bus->dev); 1154 else 1155 kfree(bus); 1156 1157 return err; 1158} 1159 1160static bool pci_bridge_child_ext_cfg_accessible(struct pci_dev *bridge) 1161{ 1162 int pos; 1163 u32 status; 1164 1165 /* 1166 * If extended config space isn't accessible on a bridge's primary 1167 * bus, we certainly can't access it on the secondary bus. 1168 */ 1169 if (bridge->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1170 return false; 1171 1172 /* 1173 * PCIe Root Ports and switch ports are PCIe on both sides, so if 1174 * extended config space is accessible on the primary, it's also 1175 * accessible on the secondary. 1176 */ 1177 if (pci_is_pcie(bridge) && 1178 (pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT || 1179 pci_pcie_type(bridge) == PCI_EXP_TYPE_UPSTREAM || 1180 pci_pcie_type(bridge) == PCI_EXP_TYPE_DOWNSTREAM)) 1181 return true; 1182 1183 /* 1184 * For the other bridge types: 1185 * - PCI-to-PCI bridges 1186 * - PCIe-to-PCI/PCI-X forward bridges 1187 * - PCI/PCI-X-to-PCIe reverse bridges 1188 * extended config space on the secondary side is only accessible 1189 * if the bridge supports PCI-X Mode 2. 1190 */ 1191 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX); 1192 if (!pos) 1193 return false; 1194 1195 pci_read_config_dword(bridge, pos + PCI_X_STATUS, &status); 1196 return status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ); 1197} 1198 1199static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent, 1200 struct pci_dev *bridge, int busnr) 1201{ 1202 struct pci_bus *child; 1203 struct pci_host_bridge *host; 1204 int i; 1205 int ret; 1206 1207 /* Allocate a new bus and inherit stuff from the parent */ 1208 child = pci_alloc_bus(parent); 1209 if (!child) 1210 return NULL; 1211 1212 child->parent = parent; 1213 child->sysdata = parent->sysdata; 1214 child->bus_flags = parent->bus_flags; 1215 1216 host = pci_find_host_bridge(parent); 1217 if (host->child_ops) 1218 child->ops = host->child_ops; 1219 else 1220 child->ops = parent->ops; 1221 1222 /* 1223 * Initialize some portions of the bus device, but don't register 1224 * it now as the parent is not properly set up yet. 1225 */ 1226 child->dev.class = &pcibus_class; 1227 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr); 1228 1229 /* Set up the primary, secondary and subordinate bus numbers */ 1230 child->number = child->busn_res.start = busnr; 1231 child->primary = parent->busn_res.start; 1232 child->busn_res.end = 0xff; 1233 1234 if (!bridge) { 1235 child->dev.parent = parent->bridge; 1236 goto add_dev; 1237 } 1238 1239 child->self = bridge; 1240 child->bridge = get_device(&bridge->dev); 1241 child->dev.parent = child->bridge; 1242 pci_set_bus_of_node(child); 1243 pci_set_bus_speed(child); 1244 1245 /* 1246 * Check whether extended config space is accessible on the child 1247 * bus. Note that we currently assume it is always accessible on 1248 * the root bus. 1249 */ 1250 if (!pci_bridge_child_ext_cfg_accessible(bridge)) { 1251 child->bus_flags |= PCI_BUS_FLAGS_NO_EXTCFG; 1252 pci_info(child, "extended config space not accessible\n"); 1253 } 1254 1255 /* Set up default resource pointers and names */ 1256 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) { 1257 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; 1258 child->resource[i]->name = child->name; 1259 } 1260 bridge->subordinate = child; 1261 1262add_dev: 1263 pci_set_bus_msi_domain(child); 1264 ret = device_register(&child->dev); 1265 if (WARN_ON(ret < 0)) { 1266 put_device(&child->dev); 1267 return NULL; 1268 } 1269 1270 pcibios_add_bus(child); 1271 1272 if (child->ops->add_bus) { 1273 ret = child->ops->add_bus(child); 1274 if (WARN_ON(ret < 0)) 1275 dev_err(&child->dev, "failed to add bus: %d\n", ret); 1276 } 1277 1278 /* Create legacy_io and legacy_mem files for this bus */ 1279 pci_create_legacy_files(child); 1280 1281 return child; 1282} 1283 1284struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, 1285 int busnr) 1286{ 1287 struct pci_bus *child; 1288 1289 child = pci_alloc_child_bus(parent, dev, busnr); 1290 if (child) { 1291 down_write(&pci_bus_sem); 1292 list_add_tail(&child->node, &parent->children); 1293 up_write(&pci_bus_sem); 1294 } 1295 return child; 1296} 1297EXPORT_SYMBOL(pci_add_new_bus); 1298 1299static void pci_enable_rrs_sv(struct pci_dev *pdev) 1300{ 1301 u16 root_cap = 0; 1302 1303 /* Enable Configuration RRS Software Visibility if supported */ 1304 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap); 1305 if (root_cap & PCI_EXP_RTCAP_RRS_SV) { 1306 pcie_capability_set_word(pdev, PCI_EXP_RTCTL, 1307 PCI_EXP_RTCTL_RRS_SVE); 1308 pdev->config_rrs_sv = 1; 1309 } 1310} 1311 1312static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 1313 unsigned int available_buses); 1314/** 1315 * pci_ea_fixed_busnrs() - Read fixed Secondary and Subordinate bus 1316 * numbers from EA capability. 1317 * @dev: Bridge 1318 * @sec: updated with secondary bus number from EA 1319 * @sub: updated with subordinate bus number from EA 1320 * 1321 * If @dev is a bridge with EA capability that specifies valid secondary 1322 * and subordinate bus numbers, return true with the bus numbers in @sec 1323 * and @sub. Otherwise return false. 1324 */ 1325static bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub) 1326{ 1327 int ea, offset; 1328 u32 dw; 1329 u8 ea_sec, ea_sub; 1330 1331 if (dev->hdr_type != PCI_HEADER_TYPE_BRIDGE) 1332 return false; 1333 1334 /* find PCI EA capability in list */ 1335 ea = pci_find_capability(dev, PCI_CAP_ID_EA); 1336 if (!ea) 1337 return false; 1338 1339 offset = ea + PCI_EA_FIRST_ENT; 1340 pci_read_config_dword(dev, offset, &dw); 1341 ea_sec = FIELD_GET(PCI_EA_SEC_BUS_MASK, dw); 1342 ea_sub = FIELD_GET(PCI_EA_SUB_BUS_MASK, dw); 1343 if (ea_sec == 0 || ea_sub < ea_sec) 1344 return false; 1345 1346 *sec = ea_sec; 1347 *sub = ea_sub; 1348 return true; 1349} 1350 1351/* 1352 * pci_scan_bridge_extend() - Scan buses behind a bridge 1353 * @bus: Parent bus the bridge is on 1354 * @dev: Bridge itself 1355 * @max: Starting subordinate number of buses behind this bridge 1356 * @available_buses: Total number of buses available for this bridge and 1357 * the devices below. After the minimal bus space has 1358 * been allocated the remaining buses will be 1359 * distributed equally between hotplug-capable bridges. 1360 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1361 * that need to be reconfigured. 1362 * 1363 * If it's a bridge, configure it and scan the bus behind it. 1364 * For CardBus bridges, we don't scan behind as the devices will 1365 * be handled by the bridge driver itself. 1366 * 1367 * We need to process bridges in two passes -- first we scan those 1368 * already configured by the BIOS and after we are done with all of 1369 * them, we proceed to assigning numbers to the remaining buses in 1370 * order to avoid overlaps between old and new bus numbers. 1371 * 1372 * Return: New subordinate number covering all buses behind this bridge. 1373 */ 1374static int pci_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 1375 int max, unsigned int available_buses, 1376 int pass) 1377{ 1378 struct pci_bus *child; 1379 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); 1380 u32 buses, i, j = 0; 1381 u16 bctl; 1382 u8 primary, secondary, subordinate; 1383 int broken = 0; 1384 bool fixed_buses; 1385 u8 fixed_sec, fixed_sub; 1386 int next_busnr; 1387 1388 /* 1389 * Make sure the bridge is powered on to be able to access config 1390 * space of devices below it. 1391 */ 1392 pm_runtime_get_sync(&dev->dev); 1393 1394 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); 1395 primary = buses & 0xFF; 1396 secondary = (buses >> 8) & 0xFF; 1397 subordinate = (buses >> 16) & 0xFF; 1398 1399 pci_dbg(dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n", 1400 secondary, subordinate, pass); 1401 1402 if (!primary && (primary != bus->number) && secondary && subordinate) { 1403 pci_warn(dev, "Primary bus is hard wired to 0\n"); 1404 primary = bus->number; 1405 } 1406 1407 /* Check if setup is sensible at all */ 1408 if (!pass && 1409 (primary != bus->number || secondary <= bus->number || 1410 secondary > subordinate)) { 1411 pci_info(dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n", 1412 secondary, subordinate); 1413 broken = 1; 1414 } 1415 1416 /* 1417 * Disable Master-Abort Mode during probing to avoid reporting of 1418 * bus errors in some architectures. 1419 */ 1420 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl); 1421 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, 1422 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT); 1423 1424 if ((secondary || subordinate) && !pcibios_assign_all_busses() && 1425 !is_cardbus && !broken) { 1426 unsigned int cmax, buses; 1427 1428 /* 1429 * Bus already configured by firmware, process it in the 1430 * first pass and just note the configuration. 1431 */ 1432 if (pass) 1433 goto out; 1434 1435 /* 1436 * The bus might already exist for two reasons: Either we 1437 * are rescanning the bus or the bus is reachable through 1438 * more than one bridge. The second case can happen with 1439 * the i450NX chipset. 1440 */ 1441 child = pci_find_bus(pci_domain_nr(bus), secondary); 1442 if (!child) { 1443 child = pci_add_new_bus(bus, dev, secondary); 1444 if (!child) 1445 goto out; 1446 child->primary = primary; 1447 pci_bus_insert_busn_res(child, secondary, subordinate); 1448 child->bridge_ctl = bctl; 1449 } 1450 1451 buses = subordinate - secondary; 1452 cmax = pci_scan_child_bus_extend(child, buses); 1453 if (cmax > subordinate) 1454 pci_warn(dev, "bridge has subordinate %02x but max busn %02x\n", 1455 subordinate, cmax); 1456 1457 /* Subordinate should equal child->busn_res.end */ 1458 if (subordinate > max) 1459 max = subordinate; 1460 } else { 1461 1462 /* 1463 * We need to assign a number to this bus which we always 1464 * do in the second pass. 1465 */ 1466 if (!pass) { 1467 if (pcibios_assign_all_busses() || broken || is_cardbus) 1468 1469 /* 1470 * Temporarily disable forwarding of the 1471 * configuration cycles on all bridges in 1472 * this bus segment to avoid possible 1473 * conflicts in the second pass between two 1474 * bridges programmed with overlapping bus 1475 * ranges. 1476 */ 1477 pci_write_config_dword(dev, PCI_PRIMARY_BUS, 1478 buses & ~0xffffff); 1479 goto out; 1480 } 1481 1482 /* Clear errors */ 1483 pci_write_config_word(dev, PCI_STATUS, 0xffff); 1484 1485 /* Read bus numbers from EA Capability (if present) */ 1486 fixed_buses = pci_ea_fixed_busnrs(dev, &fixed_sec, &fixed_sub); 1487 if (fixed_buses) 1488 next_busnr = fixed_sec; 1489 else 1490 next_busnr = max + 1; 1491 1492 /* 1493 * Prevent assigning a bus number that already exists. 1494 * This can happen when a bridge is hot-plugged, so in this 1495 * case we only re-scan this bus. 1496 */ 1497 child = pci_find_bus(pci_domain_nr(bus), next_busnr); 1498 if (!child) { 1499 child = pci_add_new_bus(bus, dev, next_busnr); 1500 if (!child) 1501 goto out; 1502 pci_bus_insert_busn_res(child, next_busnr, 1503 bus->busn_res.end); 1504 } 1505 max++; 1506 if (available_buses) 1507 available_buses--; 1508 1509 buses = (buses & 0xff000000) 1510 | ((unsigned int)(child->primary) << 0) 1511 | ((unsigned int)(child->busn_res.start) << 8) 1512 | ((unsigned int)(child->busn_res.end) << 16); 1513 1514 /* 1515 * yenta.c forces a secondary latency timer of 176. 1516 * Copy that behaviour here. 1517 */ 1518 if (is_cardbus) { 1519 buses &= ~0xff000000; 1520 buses |= CARDBUS_LATENCY_TIMER << 24; 1521 } 1522 1523 /* We need to blast all three values with a single write */ 1524 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); 1525 1526 if (!is_cardbus) { 1527 child->bridge_ctl = bctl; 1528 max = pci_scan_child_bus_extend(child, available_buses); 1529 } else { 1530 1531 /* 1532 * For CardBus bridges, we leave 4 bus numbers as 1533 * cards with a PCI-to-PCI bridge can be inserted 1534 * later. 1535 */ 1536 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) { 1537 struct pci_bus *parent = bus; 1538 if (pci_find_bus(pci_domain_nr(bus), 1539 max+i+1)) 1540 break; 1541 while (parent->parent) { 1542 if ((!pcibios_assign_all_busses()) && 1543 (parent->busn_res.end > max) && 1544 (parent->busn_res.end <= max+i)) { 1545 j = 1; 1546 } 1547 parent = parent->parent; 1548 } 1549 if (j) { 1550 1551 /* 1552 * Often, there are two CardBus 1553 * bridges -- try to leave one 1554 * valid bus number for each one. 1555 */ 1556 i /= 2; 1557 break; 1558 } 1559 } 1560 max += i; 1561 } 1562 1563 /* 1564 * Set subordinate bus number to its real value. 1565 * If fixed subordinate bus number exists from EA 1566 * capability then use it. 1567 */ 1568 if (fixed_buses) 1569 max = fixed_sub; 1570 pci_bus_update_busn_res_end(child, max); 1571 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); 1572 } 1573 1574 sprintf(child->name, 1575 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"), 1576 pci_domain_nr(bus), child->number); 1577 1578 /* Check that all devices are accessible */ 1579 while (bus->parent) { 1580 if ((child->busn_res.end > bus->busn_res.end) || 1581 (child->number > bus->busn_res.end) || 1582 (child->number < bus->number) || 1583 (child->busn_res.end < bus->number)) { 1584 dev_info(&dev->dev, "devices behind bridge are unusable because %pR cannot be assigned for them\n", 1585 &child->busn_res); 1586 break; 1587 } 1588 bus = bus->parent; 1589 } 1590 1591out: 1592 /* Clear errors in the Secondary Status Register */ 1593 pci_write_config_word(dev, PCI_SEC_STATUS, 0xffff); 1594 1595 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl); 1596 1597 pm_runtime_put(&dev->dev); 1598 1599 return max; 1600} 1601 1602/* 1603 * pci_scan_bridge() - Scan buses behind a bridge 1604 * @bus: Parent bus the bridge is on 1605 * @dev: Bridge itself 1606 * @max: Starting subordinate number of buses behind this bridge 1607 * @pass: Either %0 (scan already configured bridges) or %1 (scan bridges 1608 * that need to be reconfigured. 1609 * 1610 * If it's a bridge, configure it and scan the bus behind it. 1611 * For CardBus bridges, we don't scan behind as the devices will 1612 * be handled by the bridge driver itself. 1613 * 1614 * We need to process bridges in two passes -- first we scan those 1615 * already configured by the BIOS and after we are done with all of 1616 * them, we proceed to assigning numbers to the remaining buses in 1617 * order to avoid overlaps between old and new bus numbers. 1618 * 1619 * Return: New subordinate number covering all buses behind this bridge. 1620 */ 1621int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass) 1622{ 1623 return pci_scan_bridge_extend(bus, dev, max, 0, pass); 1624} 1625EXPORT_SYMBOL(pci_scan_bridge); 1626 1627/* 1628 * Read interrupt line and base address registers. 1629 * The architecture-dependent code can tweak these, of course. 1630 */ 1631static void pci_read_irq(struct pci_dev *dev) 1632{ 1633 unsigned char irq; 1634 1635 /* VFs are not allowed to use INTx, so skip the config reads */ 1636 if (dev->is_virtfn) { 1637 dev->pin = 0; 1638 dev->irq = 0; 1639 return; 1640 } 1641 1642 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); 1643 dev->pin = irq; 1644 if (irq) 1645 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1646 dev->irq = irq; 1647} 1648 1649void set_pcie_port_type(struct pci_dev *pdev) 1650{ 1651 int pos; 1652 u16 reg16; 1653 u32 reg32; 1654 int type; 1655 struct pci_dev *parent; 1656 1657 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP); 1658 if (!pos) 1659 return; 1660 1661 pdev->pcie_cap = pos; 1662 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 1663 pdev->pcie_flags_reg = reg16; 1664 1665 type = pci_pcie_type(pdev); 1666 if (type == PCI_EXP_TYPE_ROOT_PORT) 1667 pci_enable_rrs_sv(pdev); 1668 1669 pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->devcap); 1670 pdev->pcie_mpss = FIELD_GET(PCI_EXP_DEVCAP_PAYLOAD, pdev->devcap); 1671 1672 pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, ®32); 1673 if (reg32 & PCI_EXP_LNKCAP_DLLLARC) 1674 pdev->link_active_reporting = 1; 1675 1676#ifdef CONFIG_PCIEASPM 1677 if (reg32 & PCI_EXP_LNKCAP_ASPM_L0S) 1678 pdev->aspm_l0s_support = 1; 1679 if (reg32 & PCI_EXP_LNKCAP_ASPM_L1) 1680 pdev->aspm_l1_support = 1; 1681#endif 1682 1683 parent = pci_upstream_bridge(pdev); 1684 if (!parent) 1685 return; 1686 1687 /* 1688 * Some systems do not identify their upstream/downstream ports 1689 * correctly so detect impossible configurations here and correct 1690 * the port type accordingly. 1691 */ 1692 if (type == PCI_EXP_TYPE_DOWNSTREAM) { 1693 /* 1694 * If pdev claims to be downstream port but the parent 1695 * device is also downstream port assume pdev is actually 1696 * upstream port. 1697 */ 1698 if (pcie_downstream_port(parent)) { 1699 pci_info(pdev, "claims to be downstream port but is acting as upstream port, correcting type\n"); 1700 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1701 pdev->pcie_flags_reg |= PCI_EXP_TYPE_UPSTREAM; 1702 } 1703 } else if (type == PCI_EXP_TYPE_UPSTREAM) { 1704 /* 1705 * If pdev claims to be upstream port but the parent 1706 * device is also upstream port assume pdev is actually 1707 * downstream port. 1708 */ 1709 if (pci_pcie_type(parent) == PCI_EXP_TYPE_UPSTREAM) { 1710 pci_info(pdev, "claims to be upstream port but is acting as downstream port, correcting type\n"); 1711 pdev->pcie_flags_reg &= ~PCI_EXP_FLAGS_TYPE; 1712 pdev->pcie_flags_reg |= PCI_EXP_TYPE_DOWNSTREAM; 1713 } 1714 } 1715} 1716 1717void set_pcie_hotplug_bridge(struct pci_dev *pdev) 1718{ 1719 u32 reg32; 1720 1721 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32); 1722 if (reg32 & PCI_EXP_SLTCAP_HPC) 1723 pdev->is_hotplug_bridge = pdev->is_pciehp = 1; 1724} 1725 1726static void set_pcie_thunderbolt(struct pci_dev *dev) 1727{ 1728 u16 vsec; 1729 1730 /* Is the device part of a Thunderbolt controller? */ 1731 vsec = pci_find_vsec_capability(dev, PCI_VENDOR_ID_INTEL, PCI_VSEC_ID_INTEL_TBT); 1732 if (vsec) 1733 dev->is_thunderbolt = 1; 1734} 1735 1736static void set_pcie_untrusted(struct pci_dev *dev) 1737{ 1738 struct pci_dev *parent = pci_upstream_bridge(dev); 1739 1740 if (!parent) 1741 return; 1742 /* 1743 * If the upstream bridge is untrusted we treat this device as 1744 * untrusted as well. 1745 */ 1746 if (parent->untrusted) { 1747 dev->untrusted = true; 1748 return; 1749 } 1750 1751 if (arch_pci_dev_is_removable(dev)) { 1752 pci_dbg(dev, "marking as untrusted\n"); 1753 dev->untrusted = true; 1754 } 1755} 1756 1757static void pci_set_removable(struct pci_dev *dev) 1758{ 1759 struct pci_dev *parent = pci_upstream_bridge(dev); 1760 1761 if (!parent) 1762 return; 1763 /* 1764 * We (only) consider everything tunneled below an external_facing 1765 * device to be removable by the user. We're mainly concerned with 1766 * consumer platforms with user accessible thunderbolt ports that are 1767 * vulnerable to DMA attacks, and we expect those ports to be marked by 1768 * the firmware as external_facing. Devices in traditional hotplug 1769 * slots can technically be removed, but the expectation is that unless 1770 * the port is marked with external_facing, such devices are less 1771 * accessible to user / may not be removed by end user, and thus not 1772 * exposed as "removable" to userspace. 1773 */ 1774 if (dev_is_removable(&parent->dev)) { 1775 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1776 return; 1777 } 1778 1779 if (arch_pci_dev_is_removable(dev)) { 1780 pci_dbg(dev, "marking as removable\n"); 1781 dev_set_removable(&dev->dev, DEVICE_REMOVABLE); 1782 } 1783} 1784 1785/** 1786 * pci_ext_cfg_is_aliased - Is ext config space just an alias of std config? 1787 * @dev: PCI device 1788 * 1789 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that 1790 * when forwarding a type1 configuration request the bridge must check that 1791 * the extended register address field is zero. The bridge is not permitted 1792 * to forward the transactions and must handle it as an Unsupported Request. 1793 * Some bridges do not follow this rule and simply drop the extended register 1794 * bits, resulting in the standard config space being aliased, every 256 1795 * bytes across the entire configuration space. Test for this condition by 1796 * comparing the first dword of each potential alias to the vendor/device ID. 1797 * Known offenders: 1798 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03) 1799 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40) 1800 */ 1801static bool pci_ext_cfg_is_aliased(struct pci_dev *dev) 1802{ 1803#ifdef CONFIG_PCI_QUIRKS 1804 int pos, ret; 1805 u32 header, tmp; 1806 1807 pci_read_config_dword(dev, PCI_VENDOR_ID, &header); 1808 1809 for (pos = PCI_CFG_SPACE_SIZE; 1810 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) { 1811 ret = pci_read_config_dword(dev, pos, &tmp); 1812 if ((ret != PCIBIOS_SUCCESSFUL) || (header != tmp)) 1813 return false; 1814 } 1815 1816 return true; 1817#else 1818 return false; 1819#endif 1820} 1821 1822/** 1823 * pci_cfg_space_size_ext - Get the configuration space size of the PCI device 1824 * @dev: PCI device 1825 * 1826 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices 1827 * have 4096 bytes. Even if the device is capable, that doesn't mean we can 1828 * access it. Maybe we don't have a way to generate extended config space 1829 * accesses, or the device is behind a reverse Express bridge. So we try 1830 * reading the dword at 0x100 which must either be 0 or a valid extended 1831 * capability header. 1832 */ 1833static int pci_cfg_space_size_ext(struct pci_dev *dev) 1834{ 1835 u32 status; 1836 int pos = PCI_CFG_SPACE_SIZE; 1837 1838 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL) 1839 return PCI_CFG_SPACE_SIZE; 1840 if (PCI_POSSIBLE_ERROR(status) || pci_ext_cfg_is_aliased(dev)) 1841 return PCI_CFG_SPACE_SIZE; 1842 1843 return PCI_CFG_SPACE_EXP_SIZE; 1844} 1845 1846int pci_cfg_space_size(struct pci_dev *dev) 1847{ 1848 int pos; 1849 u32 status; 1850 u16 class; 1851 1852#ifdef CONFIG_PCI_IOV 1853 /* 1854 * Per the SR-IOV specification (rev 1.1, sec 3.5), VFs are required to 1855 * implement a PCIe capability and therefore must implement extended 1856 * config space. We can skip the NO_EXTCFG test below and the 1857 * reachability/aliasing test in pci_cfg_space_size_ext() by virtue of 1858 * the fact that the SR-IOV capability on the PF resides in extended 1859 * config space and must be accessible and non-aliased to have enabled 1860 * support for this VF. This is a micro performance optimization for 1861 * systems supporting many VFs. 1862 */ 1863 if (dev->is_virtfn) 1864 return PCI_CFG_SPACE_EXP_SIZE; 1865#endif 1866 1867 if (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_EXTCFG) 1868 return PCI_CFG_SPACE_SIZE; 1869 1870 class = dev->class >> 8; 1871 if (class == PCI_CLASS_BRIDGE_HOST) 1872 return pci_cfg_space_size_ext(dev); 1873 1874 if (pci_is_pcie(dev)) 1875 return pci_cfg_space_size_ext(dev); 1876 1877 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX); 1878 if (!pos) 1879 return PCI_CFG_SPACE_SIZE; 1880 1881 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status); 1882 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)) 1883 return pci_cfg_space_size_ext(dev); 1884 1885 return PCI_CFG_SPACE_SIZE; 1886} 1887 1888static u32 pci_class(struct pci_dev *dev) 1889{ 1890 u32 class; 1891 1892#ifdef CONFIG_PCI_IOV 1893 if (dev->is_virtfn) 1894 return dev->physfn->sriov->class; 1895#endif 1896 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); 1897 return class; 1898} 1899 1900static void pci_subsystem_ids(struct pci_dev *dev, u16 *vendor, u16 *device) 1901{ 1902#ifdef CONFIG_PCI_IOV 1903 if (dev->is_virtfn) { 1904 *vendor = dev->physfn->sriov->subsystem_vendor; 1905 *device = dev->physfn->sriov->subsystem_device; 1906 return; 1907 } 1908#endif 1909 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, vendor); 1910 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, device); 1911} 1912 1913static u8 pci_hdr_type(struct pci_dev *dev) 1914{ 1915 u8 hdr_type; 1916 1917#ifdef CONFIG_PCI_IOV 1918 if (dev->is_virtfn) 1919 return dev->physfn->sriov->hdr_type; 1920#endif 1921 pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type); 1922 return hdr_type; 1923} 1924 1925#define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED) 1926 1927/** 1928 * pci_intx_mask_broken - Test PCI_COMMAND_INTX_DISABLE writability 1929 * @dev: PCI device 1930 * 1931 * Test whether PCI_COMMAND_INTX_DISABLE is writable for @dev. Check this 1932 * at enumeration-time to avoid modifying PCI_COMMAND at run-time. 1933 */ 1934static int pci_intx_mask_broken(struct pci_dev *dev) 1935{ 1936 u16 orig, toggle, new; 1937 1938 pci_read_config_word(dev, PCI_COMMAND, &orig); 1939 toggle = orig ^ PCI_COMMAND_INTX_DISABLE; 1940 pci_write_config_word(dev, PCI_COMMAND, toggle); 1941 pci_read_config_word(dev, PCI_COMMAND, &new); 1942 1943 pci_write_config_word(dev, PCI_COMMAND, orig); 1944 1945 /* 1946 * PCI_COMMAND_INTX_DISABLE was reserved and read-only prior to PCI 1947 * r2.3, so strictly speaking, a device is not *broken* if it's not 1948 * writable. But we'll live with the misnomer for now. 1949 */ 1950 if (new != toggle) 1951 return 1; 1952 return 0; 1953} 1954 1955static void early_dump_pci_device(struct pci_dev *pdev) 1956{ 1957 u32 value[PCI_CFG_SPACE_SIZE / sizeof(u32)]; 1958 int i; 1959 1960 pci_info(pdev, "config space:\n"); 1961 1962 for (i = 0; i < ARRAY_SIZE(value); i++) 1963 pci_read_config_dword(pdev, i * sizeof(u32), &value[i]); 1964 1965 print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 16, 1, 1966 value, ARRAY_SIZE(value) * sizeof(u32), false); 1967} 1968 1969static const char *pci_type_str(struct pci_dev *dev) 1970{ 1971 static const char * const str[] = { 1972 "PCIe Endpoint", 1973 "PCIe Legacy Endpoint", 1974 "PCIe unknown", 1975 "PCIe unknown", 1976 "PCIe Root Port", 1977 "PCIe Switch Upstream Port", 1978 "PCIe Switch Downstream Port", 1979 "PCIe to PCI/PCI-X bridge", 1980 "PCI/PCI-X to PCIe bridge", 1981 "PCIe Root Complex Integrated Endpoint", 1982 "PCIe Root Complex Event Collector", 1983 }; 1984 int type; 1985 1986 if (pci_is_pcie(dev)) { 1987 type = pci_pcie_type(dev); 1988 if (type < ARRAY_SIZE(str)) 1989 return str[type]; 1990 1991 return "PCIe unknown"; 1992 } 1993 1994 switch (dev->hdr_type) { 1995 case PCI_HEADER_TYPE_NORMAL: 1996 return "conventional PCI endpoint"; 1997 case PCI_HEADER_TYPE_BRIDGE: 1998 return "conventional PCI bridge"; 1999 case PCI_HEADER_TYPE_CARDBUS: 2000 return "CardBus bridge"; 2001 default: 2002 return "conventional PCI"; 2003 } 2004} 2005 2006/** 2007 * pci_setup_device - Fill in class and map information of a device 2008 * @dev: the device structure to fill 2009 * 2010 * Initialize the device structure with information about the device's 2011 * vendor,class,memory and IO-space addresses, IRQ lines etc. 2012 * Called at initialisation of the PCI subsystem and by CardBus services. 2013 * Returns 0 on success and negative if unknown type of device (not normal, 2014 * bridge or CardBus). 2015 */ 2016int pci_setup_device(struct pci_dev *dev) 2017{ 2018 u32 class; 2019 u16 cmd; 2020 u8 hdr_type; 2021 int err, pos = 0; 2022 struct pci_bus_region region; 2023 struct resource *res; 2024 2025 hdr_type = pci_hdr_type(dev); 2026 2027 dev->sysdata = dev->bus->sysdata; 2028 dev->dev.parent = dev->bus->bridge; 2029 dev->dev.bus = &pci_bus_type; 2030 dev->hdr_type = FIELD_GET(PCI_HEADER_TYPE_MASK, hdr_type); 2031 dev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 2032 dev->error_state = pci_channel_io_normal; 2033 set_pcie_port_type(dev); 2034 2035 err = pci_set_of_node(dev); 2036 if (err) 2037 return err; 2038 pci_set_acpi_fwnode(dev); 2039 2040 pci_dev_assign_slot(dev); 2041 2042 /* 2043 * Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) 2044 * set this higher, assuming the system even supports it. 2045 */ 2046 dev->dma_mask = 0xffffffff; 2047 2048 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), 2049 dev->bus->number, PCI_SLOT(dev->devfn), 2050 PCI_FUNC(dev->devfn)); 2051 2052 class = pci_class(dev); 2053 2054 dev->revision = class & 0xff; 2055 dev->class = class >> 8; /* upper 3 bytes */ 2056 2057 if (pci_early_dump) 2058 early_dump_pci_device(dev); 2059 2060 /* Need to have dev->class ready */ 2061 dev->cfg_size = pci_cfg_space_size(dev); 2062 2063 /* Need to have dev->cfg_size ready */ 2064 set_pcie_thunderbolt(dev); 2065 2066 set_pcie_untrusted(dev); 2067 2068 if (pci_is_pcie(dev)) 2069 dev->supported_speeds = pcie_get_supported_speeds(dev); 2070 2071 /* "Unknown power state" */ 2072 dev->current_state = PCI_UNKNOWN; 2073 2074 /* Early fixups, before probing the BARs */ 2075 pci_fixup_device(pci_fixup_early, dev); 2076 2077 pci_set_removable(dev); 2078 2079 pci_info(dev, "[%04x:%04x] type %02x class %#08x %s\n", 2080 dev->vendor, dev->device, dev->hdr_type, dev->class, 2081 pci_type_str(dev)); 2082 2083 /* Device class may be changed after fixup */ 2084 class = dev->class >> 8; 2085 2086 if (dev->non_compliant_bars && !dev->mmio_always_on) { 2087 pci_read_config_word(dev, PCI_COMMAND, &cmd); 2088 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) { 2089 pci_info(dev, "device has non-compliant BARs; disabling IO/MEM decoding\n"); 2090 cmd &= ~PCI_COMMAND_IO; 2091 cmd &= ~PCI_COMMAND_MEMORY; 2092 pci_write_config_word(dev, PCI_COMMAND, cmd); 2093 } 2094 } 2095 2096 dev->broken_intx_masking = pci_intx_mask_broken(dev); 2097 2098 switch (dev->hdr_type) { /* header type */ 2099 case PCI_HEADER_TYPE_NORMAL: /* standard header */ 2100 if (class == PCI_CLASS_BRIDGE_PCI) 2101 goto bad; 2102 pci_read_irq(dev); 2103 pci_read_bases(dev, PCI_STD_NUM_BARS, PCI_ROM_ADDRESS); 2104 2105 pci_subsystem_ids(dev, &dev->subsystem_vendor, &dev->subsystem_device); 2106 2107 /* 2108 * Do the ugly legacy mode stuff here rather than broken chip 2109 * quirk code. Legacy mode ATA controllers have fixed 2110 * addresses. These are not always echoed in BAR0-3, and 2111 * BAR0-3 in a few cases contain junk! 2112 */ 2113 if (class == PCI_CLASS_STORAGE_IDE) { 2114 u8 progif; 2115 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif); 2116 if ((progif & 1) == 0) { 2117 region.start = 0x1F0; 2118 region.end = 0x1F7; 2119 res = &dev->resource[0]; 2120 res->flags = LEGACY_IO_RESOURCE; 2121 pcibios_bus_to_resource(dev->bus, res, ®ion); 2122 pci_info(dev, "BAR 0 %pR: legacy IDE quirk\n", 2123 res); 2124 region.start = 0x3F6; 2125 region.end = 0x3F6; 2126 res = &dev->resource[1]; 2127 res->flags = LEGACY_IO_RESOURCE; 2128 pcibios_bus_to_resource(dev->bus, res, ®ion); 2129 pci_info(dev, "BAR 1 %pR: legacy IDE quirk\n", 2130 res); 2131 } 2132 if ((progif & 4) == 0) { 2133 region.start = 0x170; 2134 region.end = 0x177; 2135 res = &dev->resource[2]; 2136 res->flags = LEGACY_IO_RESOURCE; 2137 pcibios_bus_to_resource(dev->bus, res, ®ion); 2138 pci_info(dev, "BAR 2 %pR: legacy IDE quirk\n", 2139 res); 2140 region.start = 0x376; 2141 region.end = 0x376; 2142 res = &dev->resource[3]; 2143 res->flags = LEGACY_IO_RESOURCE; 2144 pcibios_bus_to_resource(dev->bus, res, ®ion); 2145 pci_info(dev, "BAR 3 %pR: legacy IDE quirk\n", 2146 res); 2147 } 2148 } 2149 break; 2150 2151 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ 2152 /* 2153 * The PCI-to-PCI bridge spec requires that subtractive 2154 * decoding (i.e. transparent) bridge must have programming 2155 * interface code of 0x01. 2156 */ 2157 pci_read_irq(dev); 2158 dev->transparent = ((dev->class & 0xff) == 1); 2159 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); 2160 pci_read_bridge_windows(dev); 2161 set_pcie_hotplug_bridge(dev); 2162 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID); 2163 if (pos) { 2164 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor); 2165 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device); 2166 } 2167 break; 2168 2169 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ 2170 if (class != PCI_CLASS_BRIDGE_CARDBUS) 2171 goto bad; 2172 pci_read_irq(dev); 2173 pci_read_bases(dev, 1, 0); 2174 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); 2175 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); 2176 break; 2177 2178 default: /* unknown header */ 2179 pci_err(dev, "unknown header type %02x, ignoring device\n", 2180 dev->hdr_type); 2181 pci_release_of_node(dev); 2182 return -EIO; 2183 2184 bad: 2185 pci_err(dev, "ignoring class %#08x (doesn't match header type %02x)\n", 2186 dev->class, dev->hdr_type); 2187 dev->class = PCI_CLASS_NOT_DEFINED << 8; 2188 } 2189 2190 /* We found a fine healthy device, go go go... */ 2191 return 0; 2192} 2193 2194static void pci_configure_mps(struct pci_dev *dev) 2195{ 2196 struct pci_dev *bridge = pci_upstream_bridge(dev); 2197 int mps, mpss, p_mps, rc; 2198 2199 if (!pci_is_pcie(dev)) 2200 return; 2201 2202 /* MPS and MRRS fields are of type 'RsvdP' for VFs, short-circuit out */ 2203 if (dev->is_virtfn) 2204 return; 2205 2206 /* 2207 * For Root Complex Integrated Endpoints, program the maximum 2208 * supported value unless limited by the PCIE_BUS_PEER2PEER case. 2209 */ 2210 if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_END) { 2211 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 2212 mps = 128; 2213 else 2214 mps = 128 << dev->pcie_mpss; 2215 rc = pcie_set_mps(dev, mps); 2216 if (rc) { 2217 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2218 mps); 2219 } 2220 return; 2221 } 2222 2223 if (!bridge || !pci_is_pcie(bridge)) 2224 return; 2225 2226 mps = pcie_get_mps(dev); 2227 p_mps = pcie_get_mps(bridge); 2228 2229 if (mps == p_mps) 2230 return; 2231 2232 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) { 2233 pci_warn(dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2234 mps, pci_name(bridge), p_mps); 2235 return; 2236 } 2237 2238 /* 2239 * Fancier MPS configuration is done later by 2240 * pcie_bus_configure_settings() 2241 */ 2242 if (pcie_bus_config != PCIE_BUS_DEFAULT) 2243 return; 2244 2245 mpss = 128 << dev->pcie_mpss; 2246 if (mpss < p_mps && pci_pcie_type(bridge) == PCI_EXP_TYPE_ROOT_PORT) { 2247 pcie_set_mps(bridge, mpss); 2248 pci_info(dev, "Upstream bridge's Max Payload Size set to %d (was %d, max %d)\n", 2249 mpss, p_mps, 128 << bridge->pcie_mpss); 2250 p_mps = pcie_get_mps(bridge); 2251 } 2252 2253 rc = pcie_set_mps(dev, p_mps); 2254 if (rc) { 2255 pci_warn(dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n", 2256 p_mps); 2257 return; 2258 } 2259 2260 pci_info(dev, "Max Payload Size set to %d (was %d, max %d)\n", 2261 p_mps, mps, mpss); 2262} 2263 2264int pci_configure_extended_tags(struct pci_dev *dev, void *ign) 2265{ 2266 struct pci_host_bridge *host; 2267 u32 cap; 2268 u16 ctl; 2269 int ret; 2270 2271 /* PCI_EXP_DEVCTL_EXT_TAG is RsvdP in VFs */ 2272 if (!pci_is_pcie(dev) || dev->is_virtfn) 2273 return 0; 2274 2275 ret = pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap); 2276 if (ret) 2277 return 0; 2278 2279 if (!(cap & PCI_EXP_DEVCAP_EXT_TAG)) 2280 return 0; 2281 2282 ret = pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl); 2283 if (ret) 2284 return 0; 2285 2286 host = pci_find_host_bridge(dev->bus); 2287 if (!host) 2288 return 0; 2289 2290 /* 2291 * If some device in the hierarchy doesn't handle Extended Tags 2292 * correctly, make sure they're disabled. 2293 */ 2294 if (host->no_ext_tags) { 2295 if (ctl & PCI_EXP_DEVCTL_EXT_TAG) { 2296 pci_info(dev, "disabling Extended Tags\n"); 2297 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2298 PCI_EXP_DEVCTL_EXT_TAG); 2299 } 2300 return 0; 2301 } 2302 2303 if (!(ctl & PCI_EXP_DEVCTL_EXT_TAG)) { 2304 pci_info(dev, "enabling Extended Tags\n"); 2305 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, 2306 PCI_EXP_DEVCTL_EXT_TAG); 2307 } 2308 return 0; 2309} 2310 2311static void pci_dev3_init(struct pci_dev *pdev) 2312{ 2313 u16 cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_DEV3); 2314 u32 val = 0; 2315 2316 if (!cap) 2317 return; 2318 pci_read_config_dword(pdev, cap + PCI_DEV3_STA, &val); 2319 pdev->fm_enabled = !!(val & PCI_DEV3_STA_SEGMENT); 2320} 2321 2322/** 2323 * pcie_relaxed_ordering_enabled - Probe for PCIe relaxed ordering enable 2324 * @dev: PCI device to query 2325 * 2326 * Returns true if the device has enabled relaxed ordering attribute. 2327 */ 2328bool pcie_relaxed_ordering_enabled(struct pci_dev *dev) 2329{ 2330 u16 v; 2331 2332 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &v); 2333 2334 return !!(v & PCI_EXP_DEVCTL_RELAX_EN); 2335} 2336EXPORT_SYMBOL(pcie_relaxed_ordering_enabled); 2337 2338static void pci_configure_relaxed_ordering(struct pci_dev *dev) 2339{ 2340 struct pci_dev *root; 2341 2342 /* PCI_EXP_DEVCTL_RELAX_EN is RsvdP in VFs */ 2343 if (dev->is_virtfn) 2344 return; 2345 2346 if (!pcie_relaxed_ordering_enabled(dev)) 2347 return; 2348 2349 /* 2350 * For now, we only deal with Relaxed Ordering issues with Root 2351 * Ports. Peer-to-Peer DMA is another can of worms. 2352 */ 2353 root = pcie_find_root_port(dev); 2354 if (!root) 2355 return; 2356 2357 if (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING) { 2358 pcie_capability_clear_word(dev, PCI_EXP_DEVCTL, 2359 PCI_EXP_DEVCTL_RELAX_EN); 2360 pci_info(dev, "Relaxed Ordering disabled because the Root Port didn't support it\n"); 2361 } 2362} 2363 2364static void pci_configure_eetlp_prefix(struct pci_dev *dev) 2365{ 2366 struct pci_dev *bridge; 2367 unsigned int eetlp_max; 2368 int pcie_type; 2369 u32 cap; 2370 2371 if (!pci_is_pcie(dev)) 2372 return; 2373 2374 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap); 2375 if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX)) 2376 return; 2377 2378 pcie_type = pci_pcie_type(dev); 2379 2380 eetlp_max = FIELD_GET(PCI_EXP_DEVCAP2_EE_PREFIX_MAX, cap); 2381 /* 00b means 4 */ 2382 eetlp_max = eetlp_max ?: 4; 2383 2384 if (pcie_type == PCI_EXP_TYPE_ROOT_PORT || 2385 pcie_type == PCI_EXP_TYPE_RC_END) 2386 dev->eetlp_prefix_max = eetlp_max; 2387 else { 2388 bridge = pci_upstream_bridge(dev); 2389 if (bridge && bridge->eetlp_prefix_max) 2390 dev->eetlp_prefix_max = eetlp_max; 2391 } 2392} 2393 2394static void pci_configure_serr(struct pci_dev *dev) 2395{ 2396 u16 control; 2397 2398 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { 2399 2400 /* 2401 * A bridge will not forward ERR_ messages coming from an 2402 * endpoint unless SERR# forwarding is enabled. 2403 */ 2404 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &control); 2405 if (!(control & PCI_BRIDGE_CTL_SERR)) { 2406 control |= PCI_BRIDGE_CTL_SERR; 2407 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, control); 2408 } 2409 } 2410} 2411 2412static void pci_configure_rcb(struct pci_dev *dev) 2413{ 2414 struct pci_dev *rp; 2415 u16 rp_lnkctl; 2416 2417 /* 2418 * Per PCIe r7.0, sec 7.5.3.7, RCB is only meaningful in Root Ports 2419 * (where it is read-only), Endpoints, and Bridges. It may only be 2420 * set for Endpoints and Bridges if it is set in the Root Port. For 2421 * Endpoints, it is 'RsvdP' for Virtual Functions. 2422 */ 2423 if (!pci_is_pcie(dev) || 2424 pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT || 2425 pci_pcie_type(dev) == PCI_EXP_TYPE_UPSTREAM || 2426 pci_pcie_type(dev) == PCI_EXP_TYPE_DOWNSTREAM || 2427 pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC || 2428 dev->is_virtfn) 2429 return; 2430 2431 /* Root Port often not visible to virtualized guests */ 2432 rp = pcie_find_root_port(dev); 2433 if (!rp) 2434 return; 2435 2436 pcie_capability_read_word(rp, PCI_EXP_LNKCTL, &rp_lnkctl); 2437 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL, 2438 PCI_EXP_LNKCTL_RCB, 2439 (rp_lnkctl & PCI_EXP_LNKCTL_RCB) ? 2440 PCI_EXP_LNKCTL_RCB : 0); 2441} 2442 2443static void pci_configure_device(struct pci_dev *dev) 2444{ 2445 pci_configure_mps(dev); 2446 pci_configure_extended_tags(dev, NULL); 2447 pci_configure_relaxed_ordering(dev); 2448 pci_configure_ltr(dev); 2449 pci_configure_aspm_l1ss(dev); 2450 pci_configure_eetlp_prefix(dev); 2451 pci_configure_serr(dev); 2452 pci_configure_rcb(dev); 2453 2454 pci_acpi_program_hp_params(dev); 2455} 2456 2457static void pci_release_capabilities(struct pci_dev *dev) 2458{ 2459 pci_aer_exit(dev); 2460 pci_rcec_exit(dev); 2461 pci_iov_release(dev); 2462 pci_free_cap_save_buffers(dev); 2463} 2464 2465/** 2466 * pci_release_dev - Free a PCI device structure when all users of it are 2467 * finished 2468 * @dev: device that's been disconnected 2469 * 2470 * Will be called only by the device core when all users of this PCI device are 2471 * done. 2472 */ 2473static void pci_release_dev(struct device *dev) 2474{ 2475 struct pci_dev *pci_dev; 2476 2477 pci_dev = to_pci_dev(dev); 2478 pci_release_capabilities(pci_dev); 2479 pci_release_of_node(pci_dev); 2480 pcibios_release_device(pci_dev); 2481 pci_bus_put(pci_dev->bus); 2482 kfree(pci_dev->driver_override); 2483 bitmap_free(pci_dev->dma_alias_mask); 2484 dev_dbg(dev, "device released\n"); 2485 kfree(pci_dev); 2486} 2487 2488static const struct device_type pci_dev_type = { 2489 .groups = pci_dev_attr_groups, 2490}; 2491 2492struct pci_dev *pci_alloc_dev(struct pci_bus *bus) 2493{ 2494 struct pci_dev *dev; 2495 2496 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL); 2497 if (!dev) 2498 return NULL; 2499 2500 INIT_LIST_HEAD(&dev->bus_list); 2501 dev->dev.type = &pci_dev_type; 2502 dev->bus = pci_bus_get(bus); 2503 dev->driver_exclusive_resource = (struct resource) { 2504 .name = "PCI Exclusive", 2505 .start = 0, 2506 .end = -1, 2507 }; 2508 2509 spin_lock_init(&dev->pcie_cap_lock); 2510#ifdef CONFIG_PCI_MSI 2511 raw_spin_lock_init(&dev->msi_lock); 2512#endif 2513 return dev; 2514} 2515EXPORT_SYMBOL(pci_alloc_dev); 2516 2517static bool pci_bus_wait_rrs(struct pci_bus *bus, int devfn, u32 *l, 2518 int timeout) 2519{ 2520 int delay = 1; 2521 2522 if (!pci_bus_rrs_vendor_id(*l)) 2523 return true; /* not a Configuration RRS completion */ 2524 2525 if (!timeout) 2526 return false; /* RRS, but caller doesn't want to wait */ 2527 2528 /* 2529 * We got the reserved Vendor ID that indicates a completion with 2530 * Configuration Request Retry Status (RRS). Retry until we get a 2531 * valid Vendor ID or we time out. 2532 */ 2533 while (pci_bus_rrs_vendor_id(*l)) { 2534 if (delay > timeout) { 2535 pr_warn("pci %04x:%02x:%02x.%d: not ready after %dms; giving up\n", 2536 pci_domain_nr(bus), bus->number, 2537 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2538 2539 return false; 2540 } 2541 if (delay >= 1000) 2542 pr_info("pci %04x:%02x:%02x.%d: not ready after %dms; waiting\n", 2543 pci_domain_nr(bus), bus->number, 2544 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2545 2546 msleep(delay); 2547 delay *= 2; 2548 2549 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2550 return false; 2551 } 2552 2553 if (delay >= 1000) 2554 pr_info("pci %04x:%02x:%02x.%d: ready after %dms\n", 2555 pci_domain_nr(bus), bus->number, 2556 PCI_SLOT(devfn), PCI_FUNC(devfn), delay - 1); 2557 2558 return true; 2559} 2560 2561bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2562 int timeout) 2563{ 2564 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l)) 2565 return false; 2566 2567 /* Some broken boards return 0 or ~0 (PCI_ERROR_RESPONSE) if a slot is empty: */ 2568 if (PCI_POSSIBLE_ERROR(*l) || *l == 0x00000000 || 2569 *l == 0x0000ffff || *l == 0xffff0000) 2570 return false; 2571 2572 if (pci_bus_rrs_vendor_id(*l)) 2573 return pci_bus_wait_rrs(bus, devfn, l, timeout); 2574 2575 return true; 2576} 2577 2578bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l, 2579 int timeout) 2580{ 2581#ifdef CONFIG_PCI_QUIRKS 2582 struct pci_dev *bridge = bus->self; 2583 2584 /* 2585 * Certain IDT switches have an issue where they improperly trigger 2586 * ACS Source Validation errors on completions for config reads. 2587 */ 2588 if (bridge && bridge->vendor == PCI_VENDOR_ID_IDT && 2589 bridge->device == 0x80b5) 2590 return pci_idt_bus_quirk(bus, devfn, l, timeout); 2591#endif 2592 2593 return pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 2594} 2595EXPORT_SYMBOL(pci_bus_read_dev_vendor_id); 2596 2597#if IS_ENABLED(CONFIG_PCI_PWRCTRL) 2598static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *bus, int devfn) 2599{ 2600 struct pci_host_bridge *host = pci_find_host_bridge(bus); 2601 struct platform_device *pdev; 2602 struct device_node *np; 2603 2604 np = of_pci_find_child_device(dev_of_node(&bus->dev), devfn); 2605 if (!np) 2606 return NULL; 2607 2608 pdev = of_find_device_by_node(np); 2609 if (pdev) { 2610 put_device(&pdev->dev); 2611 goto err_put_of_node; 2612 } 2613 2614 /* 2615 * First check whether the pwrctrl device really needs to be created or 2616 * not. This is decided based on at least one of the power supplies 2617 * being defined in the devicetree node of the device. 2618 */ 2619 if (!of_pci_supply_present(np)) { 2620 pr_debug("PCI/pwrctrl: Skipping OF node: %s\n", np->name); 2621 goto err_put_of_node; 2622 } 2623 2624 /* Now create the pwrctrl device */ 2625 pdev = of_platform_device_create(np, NULL, &host->dev); 2626 if (!pdev) { 2627 pr_err("PCI/pwrctrl: Failed to create pwrctrl device for node: %s\n", np->name); 2628 goto err_put_of_node; 2629 } 2630 2631 of_node_put(np); 2632 2633 return pdev; 2634 2635err_put_of_node: 2636 of_node_put(np); 2637 2638 return NULL; 2639} 2640#else 2641static struct platform_device *pci_pwrctrl_create_device(struct pci_bus *bus, int devfn) 2642{ 2643 return NULL; 2644} 2645#endif 2646 2647/* 2648 * Read the config data for a PCI device, sanity-check it, 2649 * and fill in the dev structure. 2650 */ 2651static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn) 2652{ 2653 struct pci_dev *dev; 2654 u32 l; 2655 2656 /* 2657 * Create pwrctrl device (if required) for the PCI device to handle the 2658 * power state. If the pwrctrl device is created, then skip scanning 2659 * further as the pwrctrl core will rescan the bus after powering on 2660 * the device. 2661 */ 2662 if (pci_pwrctrl_create_device(bus, devfn)) 2663 return NULL; 2664 2665 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000)) 2666 return NULL; 2667 2668 dev = pci_alloc_dev(bus); 2669 if (!dev) 2670 return NULL; 2671 2672 dev->devfn = devfn; 2673 dev->vendor = l & 0xffff; 2674 dev->device = (l >> 16) & 0xffff; 2675 2676 if (pci_setup_device(dev)) { 2677 pci_bus_put(dev->bus); 2678 kfree(dev); 2679 return NULL; 2680 } 2681 2682 return dev; 2683} 2684 2685void pcie_report_downtraining(struct pci_dev *dev) 2686{ 2687 if (!pci_is_pcie(dev)) 2688 return; 2689 2690 /* Look from the device up to avoid downstream ports with no devices */ 2691 if ((pci_pcie_type(dev) != PCI_EXP_TYPE_ENDPOINT) && 2692 (pci_pcie_type(dev) != PCI_EXP_TYPE_LEG_END) && 2693 (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)) 2694 return; 2695 2696 /* Multi-function PCIe devices share the same link/status */ 2697 if (PCI_FUNC(dev->devfn) != 0 || dev->is_virtfn) 2698 return; 2699 2700 /* Print link status only if the device is constrained by the fabric */ 2701 __pcie_print_link_status(dev, false); 2702} 2703 2704static void pci_imm_ready_init(struct pci_dev *dev) 2705{ 2706 u16 status; 2707 2708 pci_read_config_word(dev, PCI_STATUS, &status); 2709 if (status & PCI_STATUS_IMM_READY) 2710 dev->imm_ready = 1; 2711} 2712 2713static void pci_init_capabilities(struct pci_dev *dev) 2714{ 2715 pci_ea_init(dev); /* Enhanced Allocation */ 2716 pci_msi_init(dev); /* Disable MSI */ 2717 pci_msix_init(dev); /* Disable MSI-X */ 2718 2719 /* Buffers for saving PCIe and PCI-X capabilities */ 2720 pci_allocate_cap_save_buffers(dev); 2721 2722 pci_imm_ready_init(dev); /* Immediate Readiness */ 2723 pci_pm_init(dev); /* Power Management */ 2724 pci_vpd_init(dev); /* Vital Product Data */ 2725 pci_configure_ari(dev); /* Alternative Routing-ID Forwarding */ 2726 pci_iov_init(dev); /* Single Root I/O Virtualization */ 2727 pci_ats_init(dev); /* Address Translation Services */ 2728 pci_pri_init(dev); /* Page Request Interface */ 2729 pci_pasid_init(dev); /* Process Address Space ID */ 2730 pci_acs_init(dev); /* Access Control Services */ 2731 pci_ptm_init(dev); /* Precision Time Measurement */ 2732 pci_aer_init(dev); /* Advanced Error Reporting */ 2733 pci_dpc_init(dev); /* Downstream Port Containment */ 2734 pci_rcec_init(dev); /* Root Complex Event Collector */ 2735 pci_doe_init(dev); /* Data Object Exchange */ 2736 pci_tph_init(dev); /* TLP Processing Hints */ 2737 pci_rebar_init(dev); /* Resizable BAR */ 2738 pci_dev3_init(dev); /* Device 3 capabilities */ 2739 pci_ide_init(dev); /* Link Integrity and Data Encryption */ 2740 2741 pcie_report_downtraining(dev); 2742 pci_init_reset_methods(dev); 2743} 2744 2745/* 2746 * This is the equivalent of pci_host_bridge_msi_domain() that acts on 2747 * devices. Firmware interfaces that can select the MSI domain on a 2748 * per-device basis should be called from here. 2749 */ 2750static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev) 2751{ 2752 struct irq_domain *d; 2753 2754 /* 2755 * If a domain has been set through the pcibios_device_add() 2756 * callback, then this is the one (platform code knows best). 2757 */ 2758 d = dev_get_msi_domain(&dev->dev); 2759 if (d) 2760 return d; 2761 2762 /* 2763 * Let's see if we have a firmware interface able to provide 2764 * the domain. 2765 */ 2766 d = pci_msi_get_device_domain(dev); 2767 if (d) 2768 return d; 2769 2770 return NULL; 2771} 2772 2773static void pci_set_msi_domain(struct pci_dev *dev) 2774{ 2775 struct irq_domain *d; 2776 2777 /* 2778 * If the platform or firmware interfaces cannot supply a 2779 * device-specific MSI domain, then inherit the default domain 2780 * from the host bridge itself. 2781 */ 2782 d = pci_dev_msi_domain(dev); 2783 if (!d) 2784 d = dev_get_msi_domain(&dev->bus->dev); 2785 2786 dev_set_msi_domain(&dev->dev, d); 2787} 2788 2789void pci_device_add(struct pci_dev *dev, struct pci_bus *bus) 2790{ 2791 int ret; 2792 2793 pci_configure_device(dev); 2794 2795 device_initialize(&dev->dev); 2796 dev->dev.release = pci_release_dev; 2797 2798 set_dev_node(&dev->dev, pcibus_to_node(bus)); 2799 dev->dev.dma_mask = &dev->dma_mask; 2800 dev->dev.dma_parms = &dev->dma_parms; 2801 dev->dev.coherent_dma_mask = 0xffffffffull; 2802 2803 dma_set_max_seg_size(&dev->dev, 65536); 2804 dma_set_seg_boundary(&dev->dev, 0xffffffff); 2805 2806 pcie_failed_link_retrain(dev); 2807 2808 /* Fix up broken headers */ 2809 pci_fixup_device(pci_fixup_header, dev); 2810 2811 pci_reassigndev_resource_alignment(dev); 2812 2813 pci_init_capabilities(dev); 2814 2815 /* 2816 * Add the device to our list of discovered devices 2817 * and the bus list for fixup functions, etc. 2818 */ 2819 down_write(&pci_bus_sem); 2820 list_add_tail(&dev->bus_list, &bus->devices); 2821 up_write(&pci_bus_sem); 2822 2823 ret = pcibios_device_add(dev); 2824 WARN_ON(ret < 0); 2825 2826 /* Set up MSI IRQ domain */ 2827 pci_set_msi_domain(dev); 2828 2829 /* Notifier could use PCI capabilities */ 2830 ret = device_add(&dev->dev); 2831 WARN_ON(ret < 0); 2832 2833 /* Establish pdev->tsm for newly added (e.g. new SR-IOV VFs) */ 2834 pci_tsm_init(dev); 2835 2836 pci_npem_create(dev); 2837 2838 pci_doe_sysfs_init(dev); 2839} 2840 2841struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn) 2842{ 2843 struct pci_dev *dev; 2844 2845 dev = pci_get_slot(bus, devfn); 2846 if (dev) { 2847 pci_dev_put(dev); 2848 return dev; 2849 } 2850 2851 dev = pci_scan_device(bus, devfn); 2852 if (!dev) 2853 return NULL; 2854 2855 pci_device_add(dev, bus); 2856 2857 return dev; 2858} 2859EXPORT_SYMBOL(pci_scan_single_device); 2860 2861static int next_ari_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2862{ 2863 int pos; 2864 u16 cap = 0; 2865 unsigned int next_fn; 2866 2867 if (!dev) 2868 return -ENODEV; 2869 2870 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI); 2871 if (!pos) 2872 return -ENODEV; 2873 2874 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap); 2875 next_fn = PCI_ARI_CAP_NFN(cap); 2876 if (next_fn <= fn) 2877 return -ENODEV; /* protect against malformed list */ 2878 2879 return next_fn; 2880} 2881 2882static int next_fn(struct pci_bus *bus, struct pci_dev *dev, int fn) 2883{ 2884 if (pci_ari_enabled(bus)) 2885 return next_ari_fn(bus, dev, fn); 2886 2887 if (fn >= 7) 2888 return -ENODEV; 2889 /* only multifunction devices may have more functions */ 2890 if (dev && !dev->multifunction) 2891 return -ENODEV; 2892 2893 return fn + 1; 2894} 2895 2896static int only_one_child(struct pci_bus *bus) 2897{ 2898 struct pci_dev *bridge = bus->self; 2899 2900 /* 2901 * Systems with unusual topologies set PCI_SCAN_ALL_PCIE_DEVS so 2902 * we scan for all possible devices, not just Device 0. 2903 */ 2904 if (pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS)) 2905 return 0; 2906 2907 /* 2908 * A PCIe Downstream Port normally leads to a Link with only Device 2909 * 0 on it (PCIe spec r3.1, sec 7.3.1). As an optimization, scan 2910 * only for Device 0 in that situation. 2911 */ 2912 if (bridge && pci_is_pcie(bridge) && pcie_downstream_port(bridge)) 2913 return 1; 2914 2915 return 0; 2916} 2917 2918/** 2919 * pci_scan_slot - Scan a PCI slot on a bus for devices 2920 * @bus: PCI bus to scan 2921 * @devfn: slot number to scan (must have zero function) 2922 * 2923 * Scan a PCI slot on the specified PCI bus for devices, adding 2924 * discovered devices to the @bus->devices list. New devices 2925 * will not have is_added set. 2926 * 2927 * Returns the number of new devices found. 2928 */ 2929int pci_scan_slot(struct pci_bus *bus, int devfn) 2930{ 2931 struct pci_dev *dev; 2932 int fn = 0, nr = 0; 2933 2934 if (only_one_child(bus) && (devfn > 0)) 2935 return 0; /* Already scanned the entire slot */ 2936 2937 do { 2938 dev = pci_scan_single_device(bus, devfn + fn); 2939 if (dev) { 2940 if (!pci_dev_is_added(dev)) 2941 nr++; 2942 if (fn > 0) 2943 dev->multifunction = 1; 2944 } else if (fn == 0) { 2945 /* 2946 * Function 0 is required unless we are running on 2947 * a hypervisor that passes through individual PCI 2948 * functions. 2949 */ 2950 if (!hypervisor_isolated_pci_functions()) 2951 break; 2952 } 2953 fn = next_fn(bus, dev, fn); 2954 } while (fn >= 0); 2955 2956 /* Only one slot has PCIe device */ 2957 if (bus->self && nr) 2958 pcie_aspm_init_link_state(bus->self); 2959 2960 return nr; 2961} 2962EXPORT_SYMBOL(pci_scan_slot); 2963 2964static int pcie_find_smpss(struct pci_dev *dev, void *data) 2965{ 2966 u8 *smpss = data; 2967 2968 if (!pci_is_pcie(dev)) 2969 return 0; 2970 2971 /* 2972 * We don't have a way to change MPS settings on devices that have 2973 * drivers attached. A hot-added device might support only the minimum 2974 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge 2975 * where devices may be hot-added, we limit the fabric MPS to 128 so 2976 * hot-added devices will work correctly. 2977 * 2978 * However, if we hot-add a device to a slot directly below a Root 2979 * Port, it's impossible for there to be other existing devices below 2980 * the port. We don't limit the MPS in this case because we can 2981 * reconfigure MPS on both the Root Port and the hot-added device, 2982 * and there are no other devices involved. 2983 * 2984 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA. 2985 */ 2986 if (dev->is_hotplug_bridge && 2987 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 2988 *smpss = 0; 2989 2990 if (*smpss > dev->pcie_mpss) 2991 *smpss = dev->pcie_mpss; 2992 2993 return 0; 2994} 2995 2996static void pcie_write_mps(struct pci_dev *dev, int mps) 2997{ 2998 int rc; 2999 3000 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) { 3001 mps = 128 << dev->pcie_mpss; 3002 3003 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT && 3004 dev->bus->self) 3005 3006 /* 3007 * For "Performance", the assumption is made that 3008 * downstream communication will never be larger than 3009 * the MRRS. So, the MPS only needs to be configured 3010 * for the upstream communication. This being the case, 3011 * walk from the top down and set the MPS of the child 3012 * to that of the parent bus. 3013 * 3014 * Configure the device MPS with the smaller of the 3015 * device MPSS or the bridge MPS (which is assumed to be 3016 * properly configured at this point to the largest 3017 * allowable MPS based on its parent bus). 3018 */ 3019 mps = min(mps, pcie_get_mps(dev->bus->self)); 3020 } 3021 3022 rc = pcie_set_mps(dev, mps); 3023 if (rc) 3024 pci_err(dev, "Failed attempting to set the MPS\n"); 3025} 3026 3027static void pcie_write_mrrs(struct pci_dev *dev) 3028{ 3029 int rc, mrrs; 3030 3031 /* 3032 * In the "safe" case, do not configure the MRRS. There appear to be 3033 * issues with setting MRRS to 0 on a number of devices. 3034 */ 3035 if (pcie_bus_config != PCIE_BUS_PERFORMANCE) 3036 return; 3037 3038 /* 3039 * For max performance, the MRRS must be set to the largest supported 3040 * value. However, it cannot be configured larger than the MPS the 3041 * device or the bus can support. This should already be properly 3042 * configured by a prior call to pcie_write_mps(). 3043 */ 3044 mrrs = pcie_get_mps(dev); 3045 3046 /* 3047 * MRRS is a R/W register. Invalid values can be written, but a 3048 * subsequent read will verify if the value is acceptable or not. 3049 * If the MRRS value provided is not acceptable (e.g., too large), 3050 * shrink the value until it is acceptable to the HW. 3051 */ 3052 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) { 3053 rc = pcie_set_readrq(dev, mrrs); 3054 if (!rc) 3055 break; 3056 3057 pci_warn(dev, "Failed attempting to set the MRRS\n"); 3058 mrrs /= 2; 3059 } 3060 3061 if (mrrs < 128) 3062 pci_err(dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n"); 3063} 3064 3065static int pcie_bus_configure_set(struct pci_dev *dev, void *data) 3066{ 3067 int mps, orig_mps; 3068 3069 if (!pci_is_pcie(dev)) 3070 return 0; 3071 3072 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3073 pcie_bus_config == PCIE_BUS_DEFAULT) 3074 return 0; 3075 3076 mps = 128 << *(u8 *)data; 3077 orig_mps = pcie_get_mps(dev); 3078 3079 pcie_write_mps(dev, mps); 3080 pcie_write_mrrs(dev); 3081 3082 pci_info(dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n", 3083 pcie_get_mps(dev), 128 << dev->pcie_mpss, 3084 orig_mps, pcie_get_readrq(dev)); 3085 3086 return 0; 3087} 3088 3089/* 3090 * pcie_bus_configure_settings() requires that pci_walk_bus work in a top-down, 3091 * parents then children fashion. If this changes, then this code will not 3092 * work as designed. 3093 */ 3094void pcie_bus_configure_settings(struct pci_bus *bus) 3095{ 3096 u8 smpss = 0; 3097 3098 if (!bus->self) 3099 return; 3100 3101 if (!pci_is_pcie(bus->self)) 3102 return; 3103 3104 /* 3105 * FIXME - Peer to peer DMA is possible, though the endpoint would need 3106 * to be aware of the MPS of the destination. To work around this, 3107 * simply force the MPS of the entire system to the smallest possible. 3108 */ 3109 if (pcie_bus_config == PCIE_BUS_PEER2PEER) 3110 smpss = 0; 3111 3112 if (pcie_bus_config == PCIE_BUS_SAFE) { 3113 smpss = bus->self->pcie_mpss; 3114 3115 pcie_find_smpss(bus->self, &smpss); 3116 pci_walk_bus(bus, pcie_find_smpss, &smpss); 3117 } 3118 3119 pcie_bus_configure_set(bus->self, &smpss); 3120 pci_walk_bus(bus, pcie_bus_configure_set, &smpss); 3121} 3122EXPORT_SYMBOL_GPL(pcie_bus_configure_settings); 3123 3124/* 3125 * Called after each bus is probed, but before its children are examined. This 3126 * is marked as __weak because multiple architectures define it. 3127 */ 3128void __weak pcibios_fixup_bus(struct pci_bus *bus) 3129{ 3130 /* nothing to do, expected to be removed in the future */ 3131} 3132 3133/** 3134 * pci_scan_child_bus_extend() - Scan devices below a bus 3135 * @bus: Bus to scan for devices 3136 * @available_buses: Total number of buses available (%0 does not try to 3137 * extend beyond the minimal) 3138 * 3139 * Scans devices below @bus including subordinate buses. Returns new 3140 * subordinate number including all the found devices. Passing 3141 * @available_buses causes the remaining bus space to be distributed 3142 * equally between hotplug-capable bridges to allow future extension of the 3143 * hierarchy. 3144 */ 3145static unsigned int pci_scan_child_bus_extend(struct pci_bus *bus, 3146 unsigned int available_buses) 3147{ 3148 unsigned int used_buses, normal_bridges = 0, hotplug_bridges = 0; 3149 unsigned int start = bus->busn_res.start; 3150 unsigned int devnr, cmax, max = start; 3151 struct pci_dev *dev; 3152 3153 dev_dbg(&bus->dev, "scanning bus\n"); 3154 3155 /* Go find them, Rover! */ 3156 for (devnr = 0; devnr < PCI_MAX_NR_DEVS; devnr++) 3157 pci_scan_slot(bus, PCI_DEVFN(devnr, 0)); 3158 3159 /* Reserve buses for SR-IOV capability */ 3160 used_buses = pci_iov_bus_range(bus); 3161 max += used_buses; 3162 3163 /* 3164 * After performing arch-dependent fixup of the bus, look behind 3165 * all PCI-to-PCI bridges on this bus. 3166 */ 3167 if (!bus->is_added) { 3168 dev_dbg(&bus->dev, "fixups for bus\n"); 3169 pcibios_fixup_bus(bus); 3170 bus->is_added = 1; 3171 } 3172 3173 /* 3174 * Calculate how many hotplug bridges and normal bridges there 3175 * are on this bus. We will distribute the additional available 3176 * buses between hotplug bridges. 3177 */ 3178 for_each_pci_bridge(dev, bus) { 3179 if (dev->is_hotplug_bridge) 3180 hotplug_bridges++; 3181 else 3182 normal_bridges++; 3183 } 3184 3185 /* 3186 * Scan bridges that are already configured. We don't touch them 3187 * unless they are misconfigured (which will be done in the second 3188 * scan below). 3189 */ 3190 for_each_pci_bridge(dev, bus) { 3191 cmax = max; 3192 max = pci_scan_bridge_extend(bus, dev, max, 0, 0); 3193 3194 /* 3195 * Reserve one bus for each bridge now to avoid extending 3196 * hotplug bridges too much during the second scan below. 3197 */ 3198 used_buses++; 3199 if (max - cmax > 1) 3200 used_buses += max - cmax - 1; 3201 } 3202 3203 /* Scan bridges that need to be reconfigured */ 3204 for_each_pci_bridge(dev, bus) { 3205 unsigned int buses = 0; 3206 3207 if (!hotplug_bridges && normal_bridges == 1) { 3208 /* 3209 * There is only one bridge on the bus (upstream 3210 * port) so it gets all available buses which it 3211 * can then distribute to the possible hotplug 3212 * bridges below. 3213 */ 3214 buses = available_buses; 3215 } else if (dev->is_hotplug_bridge) { 3216 /* 3217 * Distribute the extra buses between hotplug 3218 * bridges if any. 3219 */ 3220 buses = available_buses / hotplug_bridges; 3221 buses = min(buses, available_buses - used_buses + 1); 3222 } 3223 3224 cmax = max; 3225 max = pci_scan_bridge_extend(bus, dev, cmax, buses, 1); 3226 /* One bus is already accounted so don't add it again */ 3227 if (max - cmax > 1) 3228 used_buses += max - cmax - 1; 3229 } 3230 3231 /* 3232 * Make sure a hotplug bridge has at least the minimum requested 3233 * number of buses but allow it to grow up to the maximum available 3234 * bus number if there is room. 3235 */ 3236 if (bus->self && bus->self->is_hotplug_bridge) { 3237 used_buses = max(available_buses, pci_hotplug_bus_size - 1); 3238 if (max - start < used_buses) { 3239 max = start + used_buses; 3240 3241 /* Do not allocate more buses than we have room left */ 3242 if (max > bus->busn_res.end) 3243 max = bus->busn_res.end; 3244 3245 dev_dbg(&bus->dev, "%pR extended by %#02x\n", 3246 &bus->busn_res, max - start); 3247 } 3248 } 3249 3250 /* 3251 * We've scanned the bus and so we know all about what's on 3252 * the other side of any bridges that may be on this bus plus 3253 * any devices. 3254 * 3255 * Return how far we've got finding sub-buses. 3256 */ 3257 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max); 3258 return max; 3259} 3260 3261/** 3262 * pci_scan_child_bus() - Scan devices below a bus 3263 * @bus: Bus to scan for devices 3264 * 3265 * Scans devices below @bus including subordinate buses. Returns new 3266 * subordinate number including all the found devices. 3267 */ 3268unsigned int pci_scan_child_bus(struct pci_bus *bus) 3269{ 3270 return pci_scan_child_bus_extend(bus, 0); 3271} 3272EXPORT_SYMBOL_GPL(pci_scan_child_bus); 3273 3274/** 3275 * pcibios_root_bridge_prepare - Platform-specific host bridge setup 3276 * @bridge: Host bridge to set up 3277 * 3278 * Default empty implementation. Replace with an architecture-specific setup 3279 * routine, if necessary. 3280 */ 3281int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) 3282{ 3283 return 0; 3284} 3285 3286void __weak pcibios_add_bus(struct pci_bus *bus) 3287{ 3288} 3289 3290void __weak pcibios_remove_bus(struct pci_bus *bus) 3291{ 3292} 3293 3294struct pci_bus *pci_create_root_bus(struct device *parent, int bus, 3295 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3296{ 3297 int error; 3298 struct pci_host_bridge *bridge; 3299 3300 bridge = pci_alloc_host_bridge(0); 3301 if (!bridge) 3302 return NULL; 3303 3304 bridge->dev.parent = parent; 3305 3306 list_splice_init(resources, &bridge->windows); 3307 bridge->sysdata = sysdata; 3308 bridge->busnr = bus; 3309 bridge->ops = ops; 3310 3311 error = pci_register_host_bridge(bridge); 3312 if (error < 0) 3313 goto err_out; 3314 3315 return bridge->bus; 3316 3317err_out: 3318 put_device(&bridge->dev); 3319 return NULL; 3320} 3321EXPORT_SYMBOL_GPL(pci_create_root_bus); 3322 3323int pci_host_probe(struct pci_host_bridge *bridge) 3324{ 3325 struct pci_bus *bus, *child; 3326 int ret; 3327 3328 pci_lock_rescan_remove(); 3329 ret = pci_scan_root_bus_bridge(bridge); 3330 pci_unlock_rescan_remove(); 3331 if (ret < 0) { 3332 dev_err(bridge->dev.parent, "Scanning root bridge failed"); 3333 return ret; 3334 } 3335 3336 bus = bridge->bus; 3337 3338 /* If we must preserve the resource configuration, claim now */ 3339 if (bridge->preserve_config) 3340 pci_bus_claim_resources(bus); 3341 3342 /* 3343 * Assign whatever was left unassigned. If we didn't claim above, 3344 * this will reassign everything. 3345 */ 3346 pci_assign_unassigned_root_bus_resources(bus); 3347 3348 list_for_each_entry(child, &bus->children, node) 3349 pcie_bus_configure_settings(child); 3350 3351 pci_lock_rescan_remove(); 3352 pci_bus_add_devices(bus); 3353 pci_unlock_rescan_remove(); 3354 3355 /* 3356 * Ensure pm_runtime_enable() is called for the controller drivers 3357 * before calling pci_host_probe(). The PM framework expects that 3358 * if the parent device supports runtime PM, it will be enabled 3359 * before child runtime PM is enabled. 3360 */ 3361 pm_runtime_set_active(&bridge->dev); 3362 pm_runtime_no_callbacks(&bridge->dev); 3363 devm_pm_runtime_enable(&bridge->dev); 3364 3365 return 0; 3366} 3367EXPORT_SYMBOL_GPL(pci_host_probe); 3368 3369int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max) 3370{ 3371 struct resource *res = &b->busn_res; 3372 struct resource *parent_res, *conflict; 3373 3374 res->start = bus; 3375 res->end = bus_max; 3376 res->flags = IORESOURCE_BUS; 3377 3378 if (!pci_is_root_bus(b)) 3379 parent_res = &b->parent->busn_res; 3380 else { 3381 parent_res = get_pci_domain_busn_res(pci_domain_nr(b)); 3382 res->flags |= IORESOURCE_PCI_FIXED; 3383 } 3384 3385 conflict = request_resource_conflict(parent_res, res); 3386 3387 if (conflict) 3388 dev_info(&b->dev, 3389 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n", 3390 res, pci_is_root_bus(b) ? "domain " : "", 3391 parent_res, conflict->name, conflict); 3392 3393 return conflict == NULL; 3394} 3395 3396int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max) 3397{ 3398 struct resource *res = &b->busn_res; 3399 struct resource old_res = *res; 3400 resource_size_t size; 3401 int ret; 3402 3403 if (res->start > bus_max) 3404 return -EINVAL; 3405 3406 size = bus_max - res->start + 1; 3407 ret = adjust_resource(res, res->start, size); 3408 dev_info(&b->dev, "busn_res: %pR end %s updated to %02x\n", 3409 &old_res, ret ? "can not be" : "is", bus_max); 3410 3411 if (!ret && !res->parent) 3412 pci_bus_insert_busn_res(b, res->start, res->end); 3413 3414 return ret; 3415} 3416 3417void pci_bus_release_busn_res(struct pci_bus *b) 3418{ 3419 struct resource *res = &b->busn_res; 3420 int ret; 3421 3422 if (!res->flags || !res->parent) 3423 return; 3424 3425 ret = release_resource(res); 3426 dev_info(&b->dev, "busn_res: %pR %s released\n", 3427 res, ret ? "can not be" : "is"); 3428} 3429 3430int pci_scan_root_bus_bridge(struct pci_host_bridge *bridge) 3431{ 3432 struct resource_entry *window; 3433 bool found = false; 3434 struct pci_bus *b; 3435 int max, bus, ret; 3436 3437 if (!bridge) 3438 return -EINVAL; 3439 3440 resource_list_for_each_entry(window, &bridge->windows) 3441 if (window->res->flags & IORESOURCE_BUS) { 3442 bridge->busnr = window->res->start; 3443 found = true; 3444 break; 3445 } 3446 3447 ret = pci_register_host_bridge(bridge); 3448 if (ret < 0) 3449 return ret; 3450 3451 b = bridge->bus; 3452 bus = bridge->busnr; 3453 3454 if (!found) { 3455 dev_info(&b->dev, 3456 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3457 bus); 3458 pci_bus_insert_busn_res(b, bus, 255); 3459 } 3460 3461 max = pci_scan_child_bus(b); 3462 3463 if (!found) 3464 pci_bus_update_busn_res_end(b, max); 3465 3466 return 0; 3467} 3468EXPORT_SYMBOL(pci_scan_root_bus_bridge); 3469 3470struct pci_bus *pci_scan_root_bus(struct device *parent, int bus, 3471 struct pci_ops *ops, void *sysdata, struct list_head *resources) 3472{ 3473 struct resource_entry *window; 3474 bool found = false; 3475 struct pci_bus *b; 3476 int max; 3477 3478 resource_list_for_each_entry(window, resources) 3479 if (window->res->flags & IORESOURCE_BUS) { 3480 found = true; 3481 break; 3482 } 3483 3484 b = pci_create_root_bus(parent, bus, ops, sysdata, resources); 3485 if (!b) 3486 return NULL; 3487 3488 if (!found) { 3489 dev_info(&b->dev, 3490 "No busn resource found for root bus, will use [bus %02x-ff]\n", 3491 bus); 3492 pci_bus_insert_busn_res(b, bus, 255); 3493 } 3494 3495 max = pci_scan_child_bus(b); 3496 3497 if (!found) 3498 pci_bus_update_busn_res_end(b, max); 3499 3500 return b; 3501} 3502EXPORT_SYMBOL(pci_scan_root_bus); 3503 3504struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops, 3505 void *sysdata) 3506{ 3507 LIST_HEAD(resources); 3508 struct pci_bus *b; 3509 3510 pci_add_resource(&resources, &ioport_resource); 3511 pci_add_resource(&resources, &iomem_resource); 3512 pci_add_resource(&resources, &busn_resource); 3513 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources); 3514 if (b) { 3515 pci_scan_child_bus(b); 3516 } else { 3517 pci_free_resource_list(&resources); 3518 } 3519 return b; 3520} 3521EXPORT_SYMBOL(pci_scan_bus); 3522 3523/** 3524 * pci_rescan_bus_bridge_resize - Scan a PCI bus for devices 3525 * @bridge: PCI bridge for the bus to scan 3526 * 3527 * Scan a PCI bus and child buses for new devices, add them, 3528 * and enable them, resizing bridge mmio/io resource if necessary 3529 * and possible. The caller must ensure the child devices are already 3530 * removed for resizing to occur. 3531 * 3532 * Returns the max number of subordinate bus discovered. 3533 */ 3534unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge) 3535{ 3536 unsigned int max; 3537 struct pci_bus *bus = bridge->subordinate; 3538 3539 max = pci_scan_child_bus(bus); 3540 3541 pci_assign_unassigned_bridge_resources(bridge); 3542 3543 pci_bus_add_devices(bus); 3544 3545 return max; 3546} 3547 3548/** 3549 * pci_rescan_bus - Scan a PCI bus for devices 3550 * @bus: PCI bus to scan 3551 * 3552 * Scan a PCI bus and child buses for new devices, add them, 3553 * and enable them. 3554 * 3555 * Returns the max number of subordinate bus discovered. 3556 */ 3557unsigned int pci_rescan_bus(struct pci_bus *bus) 3558{ 3559 unsigned int max; 3560 3561 max = pci_scan_child_bus(bus); 3562 pci_assign_unassigned_bus_resources(bus); 3563 pci_bus_add_devices(bus); 3564 3565 return max; 3566} 3567EXPORT_SYMBOL_GPL(pci_rescan_bus); 3568 3569/* 3570 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal 3571 * routines should always be executed under this mutex. 3572 */ 3573DEFINE_MUTEX(pci_rescan_remove_lock); 3574 3575void pci_lock_rescan_remove(void) 3576{ 3577 mutex_lock(&pci_rescan_remove_lock); 3578} 3579EXPORT_SYMBOL_GPL(pci_lock_rescan_remove); 3580 3581void pci_unlock_rescan_remove(void) 3582{ 3583 mutex_unlock(&pci_rescan_remove_lock); 3584} 3585EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove); 3586 3587static int __init pci_sort_bf_cmp(const struct device *d_a, 3588 const struct device *d_b) 3589{ 3590 const struct pci_dev *a = to_pci_dev(d_a); 3591 const struct pci_dev *b = to_pci_dev(d_b); 3592 3593 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1; 3594 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1; 3595 3596 if (a->bus->number < b->bus->number) return -1; 3597 else if (a->bus->number > b->bus->number) return 1; 3598 3599 if (a->devfn < b->devfn) return -1; 3600 else if (a->devfn > b->devfn) return 1; 3601 3602 return 0; 3603} 3604 3605void __init pci_sort_breadthfirst(void) 3606{ 3607 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp); 3608} 3609 3610int pci_hp_add_bridge(struct pci_dev *dev) 3611{ 3612 struct pci_bus *parent = dev->bus; 3613 int busnr, start = parent->busn_res.start; 3614 unsigned int available_buses = 0; 3615 int end = parent->busn_res.end; 3616 3617 for (busnr = start; busnr <= end; busnr++) { 3618 if (!pci_find_bus(pci_domain_nr(parent), busnr)) 3619 break; 3620 } 3621 if (busnr-- > end) { 3622 pci_err(dev, "No bus number available for hot-added bridge\n"); 3623 return -1; 3624 } 3625 3626 /* Scan bridges that are already configured */ 3627 busnr = pci_scan_bridge(parent, dev, busnr, 0); 3628 3629 /* 3630 * Distribute the available bus numbers between hotplug-capable 3631 * bridges to make extending the chain later possible. 3632 */ 3633 available_buses = end - busnr; 3634 3635 /* Scan bridges that need to be reconfigured */ 3636 pci_scan_bridge_extend(parent, dev, busnr, available_buses, 1); 3637 3638 if (!dev->subordinate) 3639 return -1; 3640 3641 return 0; 3642} 3643EXPORT_SYMBOL_GPL(pci_hp_add_bridge);
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