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pci.h
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linux-6.19.14/drivers/pci/pci.h
1/* SPDX-License-Identifier: GPL-2.0 */ 2#ifndef DRIVERS_PCI_H 3#define DRIVERS_PCI_H 4 5#include <linux/align.h> 6#include <linux/bitfield.h> 7#include <linux/pci.h> 8 9struct pcie_tlp_log; 10 11/* Number of possible devfns: 0.0 to 1f.7 inclusive */ 12#define MAX_NR_DEVFNS 256 13#define PCI_MAX_NR_DEVS 32 14 15#define MAX_NR_LANES 16 16 17#define PCI_FIND_CAP_TTL 48 18 19#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 20 21#define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 22 23/* 24 * Power stable to PERST# inactive. 25 * 26 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 27 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 28 * "T_PVPERL". 29 */ 30#define PCIE_T_PVPERL_MS 100 31 32/* 33 * REFCLK stable before PERST# inactive. 34 * 35 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 36 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 37 * "T_PERST-CLK". 38 */ 39#define PCIE_T_PERST_CLK_US 100 40 41/* 42 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 43 * Recommends 1ms to 10ms timeout to check L2 ready. 44 */ 45#define PCIE_PME_TO_L2_TIMEOUT_US 10000 46 47/* 48 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 49 * 50 * - "With a Downstream Port that does not support Link speeds greater 51 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 52 * from a Conventional Reset before sending a Configuration Request to 53 * the device immediately below that Port." 54 * 55 * - "With a Downstream Port that supports Link speeds greater than 56 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 57 * completes before sending a Configuration Request to the device 58 * immediately below that Port." 59 */ 60#define PCIE_RESET_CONFIG_WAIT_MS 100 61 62/* Parameters for the waiting for link up routine */ 63#define PCIE_LINK_WAIT_MAX_RETRIES 10 64#define PCIE_LINK_WAIT_SLEEP_MS 90 65 66/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 67#define PCIE_MSG_TYPE_R_RC 0 68#define PCIE_MSG_TYPE_R_ADDR 1 69#define PCIE_MSG_TYPE_R_ID 2 70#define PCIE_MSG_TYPE_R_BC 3 71#define PCIE_MSG_TYPE_R_LOCAL 4 72#define PCIE_MSG_TYPE_R_GATHER 5 73 74/* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 75#define PCIE_MSG_CODE_PME_TURN_OFF 0x19 76 77/* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 78#define PCIE_MSG_CODE_ASSERT_INTA 0x20 79#define PCIE_MSG_CODE_ASSERT_INTB 0x21 80#define PCIE_MSG_CODE_ASSERT_INTC 0x22 81#define PCIE_MSG_CODE_ASSERT_INTD 0x23 82#define PCIE_MSG_CODE_DEASSERT_INTA 0x24 83#define PCIE_MSG_CODE_DEASSERT_INTB 0x25 84#define PCIE_MSG_CODE_DEASSERT_INTC 0x26 85#define PCIE_MSG_CODE_DEASSERT_INTD 0x27 86 87#define PCI_BUS_BRIDGE_IO_WINDOW 0 88#define PCI_BUS_BRIDGE_MEM_WINDOW 1 89#define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 90 91#define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 92 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 93 94extern const unsigned char pcie_link_speed[]; 95extern bool pci_early_dump; 96 97extern struct mutex pci_rescan_remove_lock; 98 99bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 100bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 101bool pcie_cap_has_rtctl(const struct pci_dev *dev); 102 103/* Standard Capability finder */ 104/** 105 * PCI_FIND_NEXT_CAP - Find a PCI standard capability 106 * @read_cfg: Function pointer for reading PCI config space 107 * @start: Starting position to begin search 108 * @cap: Capability ID to find 109 * @prev_ptr: Pointer to store position of preceding capability (optional) 110 * @args: Arguments to pass to read_cfg function 111 * 112 * Search the capability list in PCI config space to find @cap. If 113 * found, update *prev_ptr with the position of the preceding capability 114 * (if prev_ptr != NULL) 115 * Implements TTL (time-to-live) protection against infinite loops. 116 * 117 * Return: Position of the capability if found, 0 otherwise. 118 */ 119#define PCI_FIND_NEXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 120({ \ 121 int __ttl = PCI_FIND_CAP_TTL; \ 122 u8 __id, __found_pos = 0; \ 123 u8 __prev_pos = (start); \ 124 u8 __pos = (start); \ 125 u16 __ent; \ 126 \ 127 read_cfg##_byte(args, __pos, &__pos); \ 128 \ 129 while (__ttl--) { \ 130 if (__pos < PCI_STD_HEADER_SIZEOF) \ 131 break; \ 132 \ 133 __pos = ALIGN_DOWN(__pos, 4); \ 134 read_cfg##_word(args, __pos, &__ent); \ 135 \ 136 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ 137 if (__id == 0xff) \ 138 break; \ 139 \ 140 if (__id == (cap)) { \ 141 __found_pos = __pos; \ 142 if (prev_ptr != NULL) \ 143 *(u8 *)prev_ptr = __prev_pos; \ 144 break; \ 145 } \ 146 \ 147 __prev_pos = __pos; \ 148 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ 149 } \ 150 __found_pos; \ 151}) 152 153/* Extended Capability finder */ 154/** 155 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability 156 * @read_cfg: Function pointer for reading PCI config space 157 * @start: Starting position to begin search (0 for initial search) 158 * @cap: Extended capability ID to find 159 * @prev_ptr: Pointer to store position of preceding capability (optional) 160 * @args: Arguments to pass to read_cfg function 161 * 162 * Search the extended capability list in PCI config space to find @cap. 163 * If found, update *prev_ptr with the position of the preceding capability 164 * (if prev_ptr != NULL) 165 * Implements TTL protection against infinite loops using a calculated 166 * maximum search count. 167 * 168 * Return: Position of the capability if found, 0 otherwise. 169 */ 170#define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 171({ \ 172 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ 173 u16 __found_pos = 0; \ 174 u16 __prev_pos; \ 175 int __ttl, __ret; \ 176 u32 __header; \ 177 \ 178 __prev_pos = __pos; \ 179 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ 180 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ 181 __ret = read_cfg##_dword(args, __pos, &__header); \ 182 if (__ret != PCIBIOS_SUCCESSFUL) \ 183 break; \ 184 \ 185 if (__header == 0) \ 186 break; \ 187 \ 188 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\ 189 __found_pos = __pos; \ 190 if (prev_ptr != NULL) \ 191 *(u16 *)prev_ptr = __prev_pos; \ 192 break; \ 193 } \ 194 \ 195 __prev_pos = __pos; \ 196 __pos = PCI_EXT_CAP_NEXT(__header); \ 197 } \ 198 __found_pos; \ 199}) 200 201/* Functions internal to the PCI core code */ 202 203#ifdef CONFIG_DMI 204extern const struct attribute_group pci_dev_smbios_attr_group; 205#endif 206 207enum pci_mmap_api { 208 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 209 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 210}; 211int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 212 enum pci_mmap_api mmap_api); 213 214bool pci_reset_supported(struct pci_dev *dev); 215void pci_init_reset_methods(struct pci_dev *dev); 216int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 217int pci_bus_error_reset(struct pci_dev *dev); 218int __pci_reset_bus(struct pci_bus *bus); 219 220struct pci_cap_saved_data { 221 u16 cap_nr; 222 bool cap_extended; 223 unsigned int size; 224 u32 data[]; 225}; 226 227struct pci_cap_saved_state { 228 struct hlist_node next; 229 struct pci_cap_saved_data cap; 230}; 231 232void pci_allocate_cap_save_buffers(struct pci_dev *dev); 233void pci_free_cap_save_buffers(struct pci_dev *dev); 234int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 235int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 236 u16 cap, unsigned int size); 237struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 238struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 239 u16 cap); 240 241#define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 242#define PCI_PM_D3HOT_WAIT 10 /* msec */ 243#define PCI_PM_D3COLD_WAIT 100 /* msec */ 244 245void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 246void pci_refresh_power_state(struct pci_dev *dev); 247int pci_power_up(struct pci_dev *dev); 248void pci_disable_enabled_device(struct pci_dev *dev); 249int pci_finish_runtime_suspend(struct pci_dev *dev); 250void pcie_clear_device_status(struct pci_dev *dev); 251void pcie_clear_root_pme_status(struct pci_dev *dev); 252bool pci_check_pme_status(struct pci_dev *dev); 253void pci_pme_wakeup_bus(struct pci_bus *bus); 254void pci_pme_restore(struct pci_dev *dev); 255bool pci_dev_need_resume(struct pci_dev *dev); 256void pci_dev_adjust_pme(struct pci_dev *dev); 257void pci_dev_complete_resume(struct pci_dev *pci_dev); 258void pci_config_pm_runtime_get(struct pci_dev *dev); 259void pci_config_pm_runtime_put(struct pci_dev *dev); 260void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 261void pci_pm_init(struct pci_dev *dev); 262void pci_ea_init(struct pci_dev *dev); 263void pci_msi_init(struct pci_dev *dev); 264void pci_msix_init(struct pci_dev *dev); 265bool pci_bridge_d3_possible(struct pci_dev *dev); 266void pci_bridge_d3_update(struct pci_dev *dev); 267int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 268 269static inline bool pci_bus_rrs_vendor_id(u32 l) 270{ 271 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 272} 273 274static inline void pci_wakeup_event(struct pci_dev *dev) 275{ 276 /* Wait 100 ms before the system can be put into a sleep state. */ 277 pm_wakeup_event(&dev->dev, 100); 278} 279 280/** 281 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 282 * @bar: BAR index 283 * 284 * Protects against overflowing &struct pci_dev.resource array. 285 * 286 * Return: true for valid index, false otherwise. 287 */ 288static inline bool pci_bar_index_is_valid(int bar) 289{ 290 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 291 return true; 292 293 return false; 294} 295 296static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 297{ 298 return !!(pci_dev->subordinate); 299} 300 301static inline bool pci_power_manageable(struct pci_dev *pci_dev) 302{ 303 /* 304 * Currently we allow normal PCI devices and PCI bridges transition 305 * into D3 if their bridge_d3 is set. 306 */ 307 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 308} 309 310static inline bool pcie_downstream_port(const struct pci_dev *dev) 311{ 312 int type = pci_pcie_type(dev); 313 314 return type == PCI_EXP_TYPE_ROOT_PORT || 315 type == PCI_EXP_TYPE_DOWNSTREAM || 316 type == PCI_EXP_TYPE_PCIE_BRIDGE; 317} 318 319void pci_vpd_init(struct pci_dev *dev); 320extern const struct attribute_group pci_dev_vpd_attr_group; 321 322/* PCI Virtual Channel */ 323int pci_save_vc_state(struct pci_dev *dev); 324void pci_restore_vc_state(struct pci_dev *dev); 325void pci_allocate_vc_save_buffers(struct pci_dev *dev); 326 327/* PCI /proc functions */ 328#ifdef CONFIG_PROC_FS 329int pci_proc_attach_device(struct pci_dev *dev); 330int pci_proc_detach_device(struct pci_dev *dev); 331int pci_proc_detach_bus(struct pci_bus *bus); 332#else 333static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 334static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 335static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 336#endif 337 338/* Functions for PCI Hotplug drivers to use */ 339int pci_hp_add_bridge(struct pci_dev *dev); 340bool pci_hp_spurious_link_change(struct pci_dev *pdev); 341 342#if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 343void pci_create_legacy_files(struct pci_bus *bus); 344void pci_remove_legacy_files(struct pci_bus *bus); 345#else 346static inline void pci_create_legacy_files(struct pci_bus *bus) { } 347static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 348#endif 349 350/* Lock for read/write access to pci device and bus lists */ 351extern struct rw_semaphore pci_bus_sem; 352extern struct mutex pci_slot_mutex; 353 354extern raw_spinlock_t pci_lock; 355 356extern unsigned int pci_pm_d3hot_delay; 357 358#ifdef CONFIG_PCI_MSI 359void pci_no_msi(void); 360#else 361static inline void pci_no_msi(void) { } 362#endif 363 364void pci_realloc_get_opt(char *); 365 366static inline int pci_no_d1d2(struct pci_dev *dev) 367{ 368 unsigned int parent_dstates = 0; 369 370 if (dev->bus->self) 371 parent_dstates = dev->bus->self->no_d1d2; 372 return (dev->no_d1d2 || parent_dstates); 373 374} 375 376#ifdef CONFIG_SYSFS 377int pci_create_sysfs_dev_files(struct pci_dev *pdev); 378void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 379extern const struct attribute_group *pci_dev_groups[]; 380extern const struct attribute_group *pci_dev_attr_groups[]; 381extern const struct attribute_group *pcibus_groups[]; 382extern const struct attribute_group *pci_bus_groups[]; 383extern const struct attribute_group pci_doe_sysfs_group; 384#else 385static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 386static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 387#define pci_dev_groups NULL 388#define pci_dev_attr_groups NULL 389#define pcibus_groups NULL 390#define pci_bus_groups NULL 391#endif 392 393extern unsigned long pci_hotplug_io_size; 394extern unsigned long pci_hotplug_mmio_size; 395extern unsigned long pci_hotplug_mmio_pref_size; 396extern unsigned long pci_hotplug_bus_size; 397extern unsigned long pci_cardbus_io_size; 398extern unsigned long pci_cardbus_mem_size; 399 400/** 401 * pci_match_one_device - Tell if a PCI device structure has a matching 402 * PCI device id structure 403 * @id: single PCI device id structure to match 404 * @dev: the PCI device structure to match against 405 * 406 * Returns the matching pci_device_id structure or %NULL if there is no match. 407 */ 408static inline const struct pci_device_id * 409pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 410{ 411 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 412 (id->device == PCI_ANY_ID || id->device == dev->device) && 413 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 414 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 415 !((id->class ^ dev->class) & id->class_mask)) 416 return id; 417 return NULL; 418} 419 420/* PCI slot sysfs helper code */ 421#define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 422 423extern struct kset *pci_slots_kset; 424 425struct pci_slot_attribute { 426 struct attribute attr; 427 ssize_t (*show)(struct pci_slot *, char *); 428 ssize_t (*store)(struct pci_slot *, const char *, size_t); 429}; 430#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 431 432enum pci_bar_type { 433 pci_bar_unknown, /* Standard PCI BAR probe */ 434 pci_bar_io, /* An I/O port BAR */ 435 pci_bar_mem32, /* A 32-bit memory BAR */ 436 pci_bar_mem64, /* A 64-bit memory BAR */ 437}; 438 439struct device *pci_get_host_bridge_device(struct pci_dev *dev); 440void pci_put_host_bridge_device(struct device *dev); 441 442void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size); 443int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size, 444 int exclude_bars); 445unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 446int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 447 448int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 449bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 450 int rrs_timeout); 451bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 452 int rrs_timeout); 453int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int rrs_timeout); 454 455int pci_setup_device(struct pci_dev *dev); 456void __pci_size_stdbars(struct pci_dev *dev, int count, 457 unsigned int pos, u32 *sizes); 458int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 459 struct resource *res, unsigned int reg, u32 *sizes); 460void pci_configure_ari(struct pci_dev *dev); 461void __pci_bus_size_bridges(struct pci_bus *bus, 462 struct list_head *realloc_head); 463void __pci_bus_assign_resources(const struct pci_bus *bus, 464 struct list_head *realloc_head, 465 struct list_head *fail_head); 466bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 467void pci_walk_bus_locked(struct pci_bus *top, 468 int (*cb)(struct pci_dev *, void *), 469 void *userdata); 470 471const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 472bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 473 474/** 475 * pci_resource_num - Reverse lookup resource number from device resources 476 * @dev: PCI device 477 * @res: Resource to lookup index for (MUST be a @dev's resource) 478 * 479 * Perform reverse lookup to determine the resource number for @res within 480 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 481 * among @dev's resources! 482 * 483 * Returns: resource number. 484 */ 485static inline int pci_resource_num(const struct pci_dev *dev, 486 const struct resource *res) 487{ 488 int resno = res - &dev->resource[0]; 489 490 /* Passing a resource that is not among dev's resources? */ 491 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 492 493 return resno; 494} 495 496struct resource *pbus_select_window(struct pci_bus *bus, 497 const struct resource *res); 498void pci_reassigndev_resource_alignment(struct pci_dev *dev); 499void pci_disable_bridge_window(struct pci_dev *dev); 500struct pci_bus *pci_bus_get(struct pci_bus *bus); 501void pci_bus_put(struct pci_bus *bus); 502 503#define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 504({ \ 505 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 506 \ 507 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 508 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 509 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 510 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 511 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 512 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 513 PCI_SPEED_UNKNOWN); \ 514}) 515 516/* PCIe link information from Link Capabilities 2 */ 517#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 518 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 519 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 520 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 521 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 522 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 523 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 524 PCI_SPEED_UNKNOWN) 525 526#define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 527({ \ 528 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 529 \ 530 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 531 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 532 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 533 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 534 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 535 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 536 PCI_SPEED_UNKNOWN); \ 537}) 538 539/* PCIe speed to Mb/s reduced by encoding overhead */ 540#define PCIE_SPEED2MBS_ENC(speed) \ 541 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 542 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 543 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 544 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 545 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 546 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 547 0) 548 549static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 550{ 551 switch (speed) { 552 case PCIE_SPEED_2_5GT: 553 return 2500; 554 case PCIE_SPEED_5_0GT: 555 return 5000; 556 case PCIE_SPEED_8_0GT: 557 return 8000; 558 case PCIE_SPEED_16_0GT: 559 return 16000; 560 case PCIE_SPEED_32_0GT: 561 return 32000; 562 case PCIE_SPEED_64_0GT: 563 return 64000; 564 default: 565 break; 566 } 567 568 return -EINVAL; 569} 570 571u8 pcie_get_supported_speeds(struct pci_dev *dev); 572const char *pci_speed_string(enum pci_bus_speed speed); 573void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 574void pcie_report_downtraining(struct pci_dev *dev); 575 576static inline void __pcie_update_link_speed(struct pci_bus *bus, u16 linksta, u16 linksta2) 577{ 578 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 579 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 580} 581void pcie_update_link_speed(struct pci_bus *bus); 582 583/* Single Root I/O Virtualization */ 584struct pci_sriov { 585 int pos; /* Capability position */ 586 int nres; /* Number of resources */ 587 u32 cap; /* SR-IOV Capabilities */ 588 u16 ctrl; /* SR-IOV Control */ 589 u16 total_VFs; /* Total VFs associated with the PF */ 590 u16 initial_VFs; /* Initial VFs associated with the PF */ 591 u16 num_VFs; /* Number of VFs available */ 592 u16 offset; /* First VF Routing ID offset */ 593 u16 stride; /* Following VF stride */ 594 u16 vf_device; /* VF device ID */ 595 u32 pgsz; /* Page size for BAR alignment */ 596 u8 link; /* Function Dependency Link */ 597 u8 max_VF_buses; /* Max buses consumed by VFs */ 598 u16 driver_max_VFs; /* Max num VFs driver supports */ 599 struct pci_dev *dev; /* Lowest numbered PF */ 600 struct pci_dev *self; /* This PF */ 601 u32 class; /* VF device */ 602 u8 hdr_type; /* VF header type */ 603 u16 subsystem_vendor; /* VF subsystem vendor */ 604 u16 subsystem_device; /* VF subsystem device */ 605 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 606 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 607 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 608}; 609 610#ifdef CONFIG_PCI_DOE 611void pci_doe_init(struct pci_dev *pdev); 612void pci_doe_destroy(struct pci_dev *pdev); 613void pci_doe_disconnected(struct pci_dev *pdev); 614#else 615static inline void pci_doe_init(struct pci_dev *pdev) { } 616static inline void pci_doe_destroy(struct pci_dev *pdev) { } 617static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 618#endif 619 620#ifdef CONFIG_PCI_NPEM 621void pci_npem_create(struct pci_dev *dev); 622void pci_npem_remove(struct pci_dev *dev); 623#else 624static inline void pci_npem_create(struct pci_dev *dev) { } 625static inline void pci_npem_remove(struct pci_dev *dev) { } 626#endif 627 628#if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 629void pci_doe_sysfs_init(struct pci_dev *pci_dev); 630void pci_doe_sysfs_teardown(struct pci_dev *pdev); 631#else 632static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 633static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 634#endif 635 636#ifdef CONFIG_PCI_IDE 637void pci_ide_init(struct pci_dev *dev); 638void pci_ide_init_host_bridge(struct pci_host_bridge *hb); 639void pci_ide_destroy(struct pci_dev *dev); 640extern const struct attribute_group pci_ide_attr_group; 641#else 642static inline void pci_ide_init(struct pci_dev *dev) { } 643static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { } 644static inline void pci_ide_destroy(struct pci_dev *dev) { } 645#endif 646 647#ifdef CONFIG_PCI_TSM 648void pci_tsm_init(struct pci_dev *pdev); 649void pci_tsm_destroy(struct pci_dev *pdev); 650extern const struct attribute_group pci_tsm_attr_group; 651extern const struct attribute_group pci_tsm_auth_attr_group; 652#else 653static inline void pci_tsm_init(struct pci_dev *pdev) { } 654static inline void pci_tsm_destroy(struct pci_dev *pdev) { } 655#endif 656 657/** 658 * pci_dev_set_io_state - Set the new error state if possible. 659 * 660 * @dev: PCI device to set new error_state 661 * @new: the state we want dev to be in 662 * 663 * If the device is experiencing perm_failure, it has to remain in that state. 664 * Any other transition is allowed. 665 * 666 * Returns true if state has been changed to the requested state. 667 */ 668static inline bool pci_dev_set_io_state(struct pci_dev *dev, 669 pci_channel_state_t new) 670{ 671 pci_channel_state_t old; 672 673 switch (new) { 674 case pci_channel_io_perm_failure: 675 xchg(&dev->error_state, pci_channel_io_perm_failure); 676 return true; 677 case pci_channel_io_frozen: 678 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 679 pci_channel_io_frozen); 680 return old != pci_channel_io_perm_failure; 681 case pci_channel_io_normal: 682 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 683 pci_channel_io_normal); 684 return old != pci_channel_io_perm_failure; 685 default: 686 return false; 687 } 688} 689 690static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 691{ 692 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 693 pci_doe_disconnected(dev); 694 695 return 0; 696} 697 698/* pci_dev priv_flags */ 699#define PCI_DEV_ADDED 0 700#define PCI_DPC_RECOVERED 1 701#define PCI_DPC_RECOVERING 2 702#define PCI_DEV_REMOVED 3 703#define PCI_LINK_CHANGED 4 704#define PCI_LINK_CHANGING 5 705#define PCI_LINK_LBMS_SEEN 6 706#define PCI_DEV_ALLOW_BINDING 7 707 708static inline void pci_dev_assign_added(struct pci_dev *dev) 709{ 710 smp_mb__before_atomic(); 711 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 712 smp_mb__after_atomic(); 713} 714 715static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 716{ 717 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 718} 719 720static inline bool pci_dev_is_added(const struct pci_dev *dev) 721{ 722 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 723} 724 725static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 726{ 727 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 728} 729 730static inline void pci_dev_allow_binding(struct pci_dev *dev) 731{ 732 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 733} 734 735static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 736{ 737 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 738} 739 740#ifdef CONFIG_PCIEAER 741#include <linux/aer.h> 742 743#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 744 745struct aer_err_info { 746 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 747 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 748 int error_dev_num; 749 const char *level; /* printk level */ 750 751 unsigned int id:16; 752 753 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */ 754 unsigned int root_ratelimit_print:1; /* 0=skip, 1=print */ 755 unsigned int __pad1:4; 756 unsigned int multi_error_valid:1; 757 758 unsigned int first_error:5; 759 unsigned int __pad2:2; 760 unsigned int tlp_header_valid:1; 761 762 unsigned int status; /* COR/UNCOR Error Status */ 763 unsigned int mask; /* COR/UNCOR Error Mask */ 764 struct pcie_tlp_log tlp; /* TLP Header */ 765}; 766 767int aer_get_device_error_info(struct aer_err_info *info, int i); 768void aer_print_error(struct aer_err_info *info, int i); 769 770int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 771 unsigned int tlp_len, bool flit, 772 struct pcie_tlp_log *log); 773unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 774void pcie_print_tlp_log(const struct pci_dev *dev, 775 const struct pcie_tlp_log *log, const char *level, 776 const char *pfx); 777#endif /* CONFIG_PCIEAER */ 778 779#ifdef CONFIG_PCIEPORTBUS 780/* Cached RCEC Endpoint Association */ 781struct rcec_ea { 782 u8 nextbusn; 783 u8 lastbusn; 784 u32 bitmap; 785}; 786#endif 787 788#ifdef CONFIG_PCIE_DPC 789void pci_save_dpc_state(struct pci_dev *dev); 790void pci_restore_dpc_state(struct pci_dev *dev); 791void pci_dpc_init(struct pci_dev *pdev); 792void dpc_process_error(struct pci_dev *pdev); 793pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 794bool pci_dpc_recovered(struct pci_dev *pdev); 795unsigned int dpc_tlp_log_len(struct pci_dev *dev); 796#else 797static inline void pci_save_dpc_state(struct pci_dev *dev) { } 798static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 799static inline void pci_dpc_init(struct pci_dev *pdev) { } 800static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 801#endif 802 803#ifdef CONFIG_PCIEPORTBUS 804void pci_rcec_init(struct pci_dev *dev); 805void pci_rcec_exit(struct pci_dev *dev); 806void pcie_link_rcec(struct pci_dev *rcec); 807void pcie_walk_rcec(struct pci_dev *rcec, 808 int (*cb)(struct pci_dev *, void *), 809 void *userdata); 810#else 811static inline void pci_rcec_init(struct pci_dev *dev) { } 812static inline void pci_rcec_exit(struct pci_dev *dev) { } 813static inline void pcie_link_rcec(struct pci_dev *rcec) { } 814static inline void pcie_walk_rcec(struct pci_dev *rcec, 815 int (*cb)(struct pci_dev *, void *), 816 void *userdata) { } 817#endif 818 819#ifdef CONFIG_PCI_ATS 820/* Address Translation Service */ 821void pci_ats_init(struct pci_dev *dev); 822void pci_restore_ats_state(struct pci_dev *dev); 823#else 824static inline void pci_ats_init(struct pci_dev *d) { } 825static inline void pci_restore_ats_state(struct pci_dev *dev) { } 826#endif /* CONFIG_PCI_ATS */ 827 828#ifdef CONFIG_PCI_PRI 829void pci_pri_init(struct pci_dev *dev); 830void pci_restore_pri_state(struct pci_dev *pdev); 831#else 832static inline void pci_pri_init(struct pci_dev *dev) { } 833static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 834#endif 835 836#ifdef CONFIG_PCI_PASID 837void pci_pasid_init(struct pci_dev *dev); 838void pci_restore_pasid_state(struct pci_dev *pdev); 839#else 840static inline void pci_pasid_init(struct pci_dev *dev) { } 841static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 842#endif 843 844#ifdef CONFIG_PCI_IOV 845int pci_iov_init(struct pci_dev *dev); 846void pci_iov_release(struct pci_dev *dev); 847void pci_iov_remove(struct pci_dev *dev); 848void pci_iov_update_resource(struct pci_dev *dev, int resno); 849resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 850void pci_restore_iov_state(struct pci_dev *dev); 851int pci_iov_bus_range(struct pci_bus *bus); 852void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); 853bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 854static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 855{ 856 if (!dev->is_physfn) 857 return 0; 858 859 return dev->sriov->vf_rebar_cap; 860} 861static inline bool pci_resource_is_iov(int resno) 862{ 863 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 864} 865static inline int pci_resource_num_from_vf_bar(int resno) 866{ 867 return resno + PCI_IOV_RESOURCES; 868} 869static inline int pci_resource_num_to_vf_bar(int resno) 870{ 871 return resno - PCI_IOV_RESOURCES; 872} 873extern const struct attribute_group sriov_pf_dev_attr_group; 874extern const struct attribute_group sriov_vf_dev_attr_group; 875#else 876static inline int pci_iov_init(struct pci_dev *dev) 877{ 878 return -ENODEV; 879} 880static inline void pci_iov_release(struct pci_dev *dev) { } 881static inline void pci_iov_remove(struct pci_dev *dev) { } 882static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 883static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 884 int resno) 885{ 886 return 0; 887} 888static inline void pci_restore_iov_state(struct pci_dev *dev) { } 889static inline int pci_iov_bus_range(struct pci_bus *bus) 890{ 891 return 0; 892} 893static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 894 int size) { } 895static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 896{ 897 return false; 898} 899static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 900{ 901 return 0; 902} 903static inline bool pci_resource_is_iov(int resno) 904{ 905 return false; 906} 907static inline int pci_resource_num_from_vf_bar(int resno) 908{ 909 WARN_ON_ONCE(1); 910 return -ENODEV; 911} 912static inline int pci_resource_num_to_vf_bar(int resno) 913{ 914 WARN_ON_ONCE(1); 915 return -ENODEV; 916} 917#endif /* CONFIG_PCI_IOV */ 918 919#ifdef CONFIG_PCIE_TPH 920void pci_restore_tph_state(struct pci_dev *dev); 921void pci_save_tph_state(struct pci_dev *dev); 922void pci_no_tph(void); 923void pci_tph_init(struct pci_dev *dev); 924#else 925static inline void pci_restore_tph_state(struct pci_dev *dev) { } 926static inline void pci_save_tph_state(struct pci_dev *dev) { } 927static inline void pci_no_tph(void) { } 928static inline void pci_tph_init(struct pci_dev *dev) { } 929#endif 930 931#ifdef CONFIG_PCIE_PTM 932void pci_ptm_init(struct pci_dev *dev); 933void pci_save_ptm_state(struct pci_dev *dev); 934void pci_restore_ptm_state(struct pci_dev *dev); 935void pci_suspend_ptm(struct pci_dev *dev); 936void pci_resume_ptm(struct pci_dev *dev); 937#else 938static inline void pci_ptm_init(struct pci_dev *dev) { } 939static inline void pci_save_ptm_state(struct pci_dev *dev) { } 940static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 941static inline void pci_suspend_ptm(struct pci_dev *dev) { } 942static inline void pci_resume_ptm(struct pci_dev *dev) { } 943#endif 944 945unsigned long pci_cardbus_resource_alignment(struct resource *); 946 947static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 948 struct resource *res) 949{ 950 int resno = pci_resource_num(dev, res); 951 952 if (pci_resource_is_iov(resno)) 953 return pci_sriov_resource_alignment(dev, resno); 954 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 955 return pci_cardbus_resource_alignment(res); 956 return resource_alignment(res); 957} 958 959void pci_acs_init(struct pci_dev *dev); 960void pci_enable_acs(struct pci_dev *dev); 961#ifdef CONFIG_PCI_QUIRKS 962int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 963int pci_dev_specific_enable_acs(struct pci_dev *dev); 964int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 965int pcie_failed_link_retrain(struct pci_dev *dev); 966#else 967static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 968 u16 acs_flags) 969{ 970 return -ENOTTY; 971} 972static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 973{ 974 return -ENOTTY; 975} 976static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 977{ 978 return -ENOTTY; 979} 980static inline int pcie_failed_link_retrain(struct pci_dev *dev) 981{ 982 return -ENOTTY; 983} 984#endif 985 986/* PCI error reporting and recovery */ 987pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 988 pci_channel_state_t state, 989 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 990 991bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 992int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 993 994/* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 995void pci_save_ltr_state(struct pci_dev *dev); 996void pci_restore_ltr_state(struct pci_dev *dev); 997void pci_configure_aspm_l1ss(struct pci_dev *dev); 998void pci_save_aspm_l1ss_state(struct pci_dev *dev); 999void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 1000 1001#ifdef CONFIG_PCIEASPM 1002void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap); 1003void pcie_aspm_init_link_state(struct pci_dev *pdev); 1004void pcie_aspm_exit_link_state(struct pci_dev *pdev); 1005void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 1006void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 1007void pci_configure_ltr(struct pci_dev *pdev); 1008void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 1009#else 1010static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } 1011static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 1012static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 1013static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 1014static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 1015static inline void pci_configure_ltr(struct pci_dev *pdev) { } 1016static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 1017#endif 1018 1019#ifdef CONFIG_PCIE_ECRC 1020void pcie_set_ecrc_checking(struct pci_dev *dev); 1021void pcie_ecrc_get_policy(char *str); 1022#else 1023static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1024static inline void pcie_ecrc_get_policy(char *str) { } 1025#endif 1026 1027#ifdef CONFIG_PCIEPORTBUS 1028void pcie_reset_lbms(struct pci_dev *port); 1029#else 1030static inline void pcie_reset_lbms(struct pci_dev *port) {} 1031#endif 1032 1033struct pci_dev_reset_methods { 1034 u16 vendor; 1035 u16 device; 1036 int (*reset)(struct pci_dev *dev, bool probe); 1037}; 1038 1039struct pci_reset_fn_method { 1040 int (*reset_fn)(struct pci_dev *pdev, bool probe); 1041 char *name; 1042}; 1043extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 1044 1045#ifdef CONFIG_PCI_QUIRKS 1046int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 1047#else 1048static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 1049{ 1050 return -ENOTTY; 1051} 1052#endif 1053 1054#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 1055int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 1056 struct resource *res); 1057#else 1058static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 1059 u16 segment, struct resource *res) 1060{ 1061 return -ENODEV; 1062} 1063#endif 1064 1065void pci_rebar_init(struct pci_dev *pdev); 1066void pci_restore_rebar_state(struct pci_dev *pdev); 1067int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 1068int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 1069 1070struct device_node; 1071 1072#define PCI_EQ_RESV 0xff 1073 1074enum equalization_preset_type { 1075 EQ_PRESET_TYPE_8GTS, 1076 EQ_PRESET_TYPE_16GTS, 1077 EQ_PRESET_TYPE_32GTS, 1078 EQ_PRESET_TYPE_64GTS, 1079 EQ_PRESET_TYPE_MAX 1080}; 1081 1082struct pci_eq_presets { 1083 u16 eq_presets_8gts[MAX_NR_LANES]; 1084 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 1085}; 1086 1087#ifdef CONFIG_OF 1088int of_get_pci_domain_nr(struct device_node *node); 1089int of_pci_get_max_link_speed(struct device_node *node); 1090u32 of_pci_get_slot_power_limit(struct device_node *node, 1091 u8 *slot_power_limit_value, 1092 u8 *slot_power_limit_scale); 1093bool of_pci_preserve_config(struct device_node *node); 1094int pci_set_of_node(struct pci_dev *dev); 1095void pci_release_of_node(struct pci_dev *dev); 1096void pci_set_bus_of_node(struct pci_bus *bus); 1097void pci_release_bus_of_node(struct pci_bus *bus); 1098 1099int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 1100bool of_pci_supply_present(struct device_node *np); 1101int of_pci_get_equalization_presets(struct device *dev, 1102 struct pci_eq_presets *presets, 1103 int num_lanes); 1104#else 1105static inline int 1106of_get_pci_domain_nr(struct device_node *node) 1107{ 1108 return -1; 1109} 1110 1111static inline int 1112of_pci_get_max_link_speed(struct device_node *node) 1113{ 1114 return -EINVAL; 1115} 1116 1117static inline u32 1118of_pci_get_slot_power_limit(struct device_node *node, 1119 u8 *slot_power_limit_value, 1120 u8 *slot_power_limit_scale) 1121{ 1122 if (slot_power_limit_value) 1123 *slot_power_limit_value = 0; 1124 if (slot_power_limit_scale) 1125 *slot_power_limit_scale = 0; 1126 return 0; 1127} 1128 1129static inline bool of_pci_preserve_config(struct device_node *node) 1130{ 1131 return false; 1132} 1133 1134static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1135static inline void pci_release_of_node(struct pci_dev *dev) { } 1136static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1137static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1138 1139static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1140{ 1141 return 0; 1142} 1143 1144static inline bool of_pci_supply_present(struct device_node *np) 1145{ 1146 return false; 1147} 1148 1149static inline int of_pci_get_equalization_presets(struct device *dev, 1150 struct pci_eq_presets *presets, 1151 int num_lanes) 1152{ 1153 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1154 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1155 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1156 1157 return 0; 1158} 1159#endif /* CONFIG_OF */ 1160 1161struct of_changeset; 1162 1163#ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1164void of_pci_make_dev_node(struct pci_dev *pdev); 1165void of_pci_remove_node(struct pci_dev *pdev); 1166int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1167 struct device_node *np); 1168void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1169void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1170int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1171 struct of_changeset *ocs, 1172 struct device_node *np); 1173#else 1174static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1175static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1176static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1177static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1178#endif 1179 1180#ifdef CONFIG_PCIEAER 1181void pci_no_aer(void); 1182void pci_aer_init(struct pci_dev *dev); 1183void pci_aer_exit(struct pci_dev *dev); 1184extern const struct attribute_group aer_stats_attr_group; 1185extern const struct attribute_group aer_attr_group; 1186void pci_aer_clear_fatal_status(struct pci_dev *dev); 1187int pci_aer_clear_status(struct pci_dev *dev); 1188int pci_aer_raw_clear_status(struct pci_dev *dev); 1189void pci_save_aer_state(struct pci_dev *dev); 1190void pci_restore_aer_state(struct pci_dev *dev); 1191#else 1192static inline void pci_no_aer(void) { } 1193static inline void pci_aer_init(struct pci_dev *d) { } 1194static inline void pci_aer_exit(struct pci_dev *d) { } 1195static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1196static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1197static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1198static inline void pci_save_aer_state(struct pci_dev *dev) { } 1199static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1200#endif 1201 1202#ifdef CONFIG_ACPI 1203bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1204int pci_acpi_program_hp_params(struct pci_dev *dev); 1205extern const struct attribute_group pci_dev_acpi_attr_group; 1206void pci_set_acpi_fwnode(struct pci_dev *dev); 1207int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1208bool acpi_pci_power_manageable(struct pci_dev *dev); 1209bool acpi_pci_bridge_d3(struct pci_dev *dev); 1210int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1211pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1212void acpi_pci_refresh_power_state(struct pci_dev *dev); 1213int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1214bool acpi_pci_need_resume(struct pci_dev *dev); 1215pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1216#else 1217static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1218{ 1219 return false; 1220} 1221static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1222{ 1223 return -ENOTTY; 1224} 1225static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1226static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1227{ 1228 return -ENODEV; 1229} 1230static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1231{ 1232 return false; 1233} 1234static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1235{ 1236 return false; 1237} 1238static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1239{ 1240 return -ENODEV; 1241} 1242static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1243{ 1244 return PCI_UNKNOWN; 1245} 1246static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1247static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1248{ 1249 return -ENODEV; 1250} 1251static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1252{ 1253 return false; 1254} 1255static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1256{ 1257 return PCI_POWER_ERROR; 1258} 1259#endif 1260 1261#ifdef CONFIG_PCIEASPM 1262extern const struct attribute_group aspm_ctrl_attr_group; 1263#endif 1264 1265#ifdef CONFIG_X86_INTEL_MID 1266bool pci_use_mid_pm(void); 1267int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1268pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1269#else 1270static inline bool pci_use_mid_pm(void) 1271{ 1272 return false; 1273} 1274static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1275{ 1276 return -ENODEV; 1277} 1278static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1279{ 1280 return PCI_UNKNOWN; 1281} 1282#endif 1283 1284#ifdef CONFIG_PCI_MSI 1285int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1286#else 1287static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1288{ 1289 return -ENODEV; 1290} 1291#endif 1292 1293/* 1294 * Config Address for PCI Configuration Mechanism #1 1295 * 1296 * See PCI Local Bus Specification, Revision 3.0, 1297 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1298 */ 1299 1300#define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1301#define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1302#define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1303 1304#define PCI_CONF1_BUS_MASK 0xff 1305#define PCI_CONF1_DEV_MASK 0x1f 1306#define PCI_CONF1_FUNC_MASK 0x7 1307#define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1308 1309#define PCI_CONF1_ENABLE BIT(31) 1310#define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1311#define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1312#define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1313#define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1314 1315#define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1316 (PCI_CONF1_ENABLE | \ 1317 PCI_CONF1_BUS(bus) | \ 1318 PCI_CONF1_DEV(dev) | \ 1319 PCI_CONF1_FUNC(func) | \ 1320 PCI_CONF1_REG(reg)) 1321 1322/* 1323 * Extension of PCI Config Address for accessing extended PCIe registers 1324 * 1325 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1326 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1327 * are used for specifying additional 4 high bits of PCI Express register. 1328 */ 1329 1330#define PCI_CONF1_EXT_REG_SHIFT 16 1331#define PCI_CONF1_EXT_REG_MASK 0xf00 1332#define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1333 1334#define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1335 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1336 PCI_CONF1_EXT_REG(reg)) 1337 1338#endif /* DRIVERS_PCI_H */
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