pci-acpi.c

   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * PCI support in ACPI
   4 *
   5 * Copyright (C) 2005 David Shaohua Li <shaohua.li@intel.com>
   6 * Copyright (C) 2004 Tom Long Nguyen <tom.l.nguyen@intel.com>
   7 * Copyright (C) 2004 Intel Corp.
   8 */
   9
  10#include <linux/delay.h>
  11#include <linux/init.h>
  12#include <linux/irqdomain.h>
  13#include <linux/pci.h>
  14#include <linux/msi.h>
  15#include <linux/pci_hotplug.h>
  16#include <linux/module.h>
  17#include <linux/pci-acpi.h>
  18#include <linux/pci-ecam.h>
  19#include <linux/pm_runtime.h>
  20#include <linux/pm_qos.h>
  21#include <linux/rwsem.h>
  22#include "pci.h"
  23
  24/*
  25 * The GUID is defined in the PCI Firmware Specification available
  26 * here to PCI-SIG members:
  27 * https://members.pcisig.com/wg/PCI-SIG/document/15350
  28 */
  29const guid_t pci_acpi_dsm_guid =
  30	GUID_INIT(0xe5c937d0, 0x3553, 0x4d7a,
  31		  0x91, 0x17, 0xea, 0x4d, 0x19, 0xc3, 0x43, 0x4d);
  32
  33#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
  34static int acpi_get_rc_addr(struct acpi_device *adev, struct resource *res)
  35{
  36	struct device *dev = &adev->dev;
  37	struct resource_entry *entry;
  38	struct list_head list;
  39	unsigned long flags;
  40	int ret;
  41
  42	INIT_LIST_HEAD(&list);
  43	flags = IORESOURCE_MEM;
  44	ret = acpi_dev_get_resources(adev, &list,
  45				     acpi_dev_filter_resource_type_cb,
  46				     (void *) flags);
  47	if (ret < 0) {
  48		dev_err(dev, "failed to parse _CRS method, error code %d\n",
  49			ret);
  50		return ret;
  51	}
  52
  53	if (ret == 0) {
  54		dev_err(dev, "no IO and memory resources present in _CRS\n");
  55		return -EINVAL;
  56	}
  57
  58	entry = list_first_entry(&list, struct resource_entry, node);
  59	*res = *entry->res;
  60	acpi_dev_free_resource_list(&list);
  61	return 0;
  62}
  63
  64static acpi_status acpi_match_rc(acpi_handle handle, u32 lvl, void *context,
  65				 void **retval)
  66{
  67	u16 *segment = context;
  68	unsigned long long uid;
  69	acpi_status status;
  70
  71	status = acpi_evaluate_integer(handle, METHOD_NAME__UID, NULL, &uid);
  72	if (ACPI_FAILURE(status) || uid != *segment)
  73		return AE_CTRL_DEPTH;
  74
  75	*(acpi_handle *)retval = handle;
  76	return AE_CTRL_TERMINATE;
  77}
  78
  79int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
  80			  struct resource *res)
  81{
  82	struct acpi_device *adev;
  83	acpi_status status;
  84	acpi_handle handle;
  85	int ret;
  86
  87	status = acpi_get_devices(hid, acpi_match_rc, &segment, &handle);
  88	if (ACPI_FAILURE(status)) {
  89		dev_err(dev, "can't find _HID %s device to locate resources\n",
  90			hid);
  91		return -ENODEV;
  92	}
  93
  94	adev = acpi_fetch_acpi_dev(handle);
  95	if (!adev)
  96		return -ENODEV;
  97
  98	ret = acpi_get_rc_addr(adev, res);
  99	if (ret) {
 100		dev_err(dev, "can't get resource from %s\n",
 101			dev_name(&adev->dev));
 102		return ret;
 103	}
 104
 105	return 0;
 106}
 107#endif
 108
 109phys_addr_t acpi_pci_root_get_mcfg_addr(acpi_handle handle)
 110{
 111	acpi_status status = AE_NOT_EXIST;
 112	unsigned long long mcfg_addr;
 113
 114	if (handle)
 115		status = acpi_evaluate_integer(handle, METHOD_NAME__CBA,
 116					       NULL, &mcfg_addr);
 117	if (ACPI_FAILURE(status))
 118		return 0;
 119
 120	return (phys_addr_t)mcfg_addr;
 121}
 122
 123bool pci_acpi_preserve_config(struct pci_host_bridge *host_bridge)
 124{
 125	bool ret = false;
 126
 127	if (ACPI_HANDLE(&host_bridge->dev)) {
 128		union acpi_object *obj;
 129
 130		/*
 131		 * Evaluate the "PCI Boot Configuration" _DSM Function.  If it
 132		 * exists and returns 0, we must preserve any PCI resource
 133		 * assignments made by firmware for this host bridge.
 134		 */
 135		obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(&host_bridge->dev),
 136					      &pci_acpi_dsm_guid,
 137					      1, DSM_PCI_PRESERVE_BOOT_CONFIG,
 138					      NULL, ACPI_TYPE_INTEGER);
 139		if (obj && obj->integer.value == 0)
 140			ret = true;
 141		ACPI_FREE(obj);
 142	}
 143
 144	return ret;
 145}
 146
 147/* _HPX PCI Setting Record (Type 0); same as _HPP */
 148struct hpx_type0 {
 149	u32 revision;		/* Not present in _HPP */
 150	u8  cache_line_size;	/* Not applicable to PCIe */
 151	u8  latency_timer;	/* Not applicable to PCIe */
 152	u8  enable_serr;
 153	u8  enable_perr;
 154};
 155
 156static struct hpx_type0 pci_default_type0 = {
 157	.revision = 1,
 158	.cache_line_size = 8,
 159	.latency_timer = 0x40,
 160	.enable_serr = 0,
 161	.enable_perr = 0,
 162};
 163
 164static void program_hpx_type0(struct pci_dev *dev, struct hpx_type0 *hpx)
 165{
 166	u16 pci_cmd, pci_bctl;
 167
 168	if (!hpx)
 169		hpx = &pci_default_type0;
 170
 171	if (hpx->revision > 1) {
 172		pci_warn(dev, "PCI settings rev %d not supported; using defaults\n",
 173			 hpx->revision);
 174		hpx = &pci_default_type0;
 175	}
 176
 177	pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpx->cache_line_size);
 178	pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpx->latency_timer);
 179	pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
 180	if (hpx->enable_serr)
 181		pci_cmd |= PCI_COMMAND_SERR;
 182	if (hpx->enable_perr)
 183		pci_cmd |= PCI_COMMAND_PARITY;
 184	pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
 185
 186	/* Program bridge control value */
 187	if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
 188		pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
 189				      hpx->latency_timer);
 190		pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
 191		if (hpx->enable_perr)
 192			pci_bctl |= PCI_BRIDGE_CTL_PARITY;
 193		pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
 194	}
 195}
 196
 197static acpi_status decode_type0_hpx_record(union acpi_object *record,
 198					   struct hpx_type0 *hpx0)
 199{
 200	int i;
 201	union acpi_object *fields = record->package.elements;
 202	u32 revision = fields[1].integer.value;
 203
 204	switch (revision) {
 205	case 1:
 206		if (record->package.count != 6)
 207			return AE_ERROR;
 208		for (i = 2; i < 6; i++)
 209			if (fields[i].type != ACPI_TYPE_INTEGER)
 210				return AE_ERROR;
 211		hpx0->revision        = revision;
 212		hpx0->cache_line_size = fields[2].integer.value;
 213		hpx0->latency_timer   = fields[3].integer.value;
 214		hpx0->enable_serr     = fields[4].integer.value;
 215		hpx0->enable_perr     = fields[5].integer.value;
 216		break;
 217	default:
 218		pr_warn("%s: Type 0 Revision %d record not supported\n",
 219		       __func__, revision);
 220		return AE_ERROR;
 221	}
 222	return AE_OK;
 223}
 224
 225/* _HPX PCI-X Setting Record (Type 1) */
 226struct hpx_type1 {
 227	u32 revision;
 228	u8  max_mem_read;
 229	u8  avg_max_split;
 230	u16 tot_max_split;
 231};
 232
 233static void program_hpx_type1(struct pci_dev *dev, struct hpx_type1 *hpx)
 234{
 235	int pos;
 236
 237	if (!hpx)
 238		return;
 239
 240	pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
 241	if (!pos)
 242		return;
 243
 244	pci_warn(dev, "PCI-X settings not supported\n");
 245}
 246
 247static acpi_status decode_type1_hpx_record(union acpi_object *record,
 248					   struct hpx_type1 *hpx1)
 249{
 250	int i;
 251	union acpi_object *fields = record->package.elements;
 252	u32 revision = fields[1].integer.value;
 253
 254	switch (revision) {
 255	case 1:
 256		if (record->package.count != 5)
 257			return AE_ERROR;
 258		for (i = 2; i < 5; i++)
 259			if (fields[i].type != ACPI_TYPE_INTEGER)
 260				return AE_ERROR;
 261		hpx1->revision      = revision;
 262		hpx1->max_mem_read  = fields[2].integer.value;
 263		hpx1->avg_max_split = fields[3].integer.value;
 264		hpx1->tot_max_split = fields[4].integer.value;
 265		break;
 266	default:
 267		pr_warn("%s: Type 1 Revision %d record not supported\n",
 268		       __func__, revision);
 269		return AE_ERROR;
 270	}
 271	return AE_OK;
 272}
 273
 274/* _HPX PCI Express Setting Record (Type 2) */
 275struct hpx_type2 {
 276	u32 revision;
 277	u32 unc_err_mask_and;
 278	u32 unc_err_mask_or;
 279	u32 unc_err_sever_and;
 280	u32 unc_err_sever_or;
 281	u32 cor_err_mask_and;
 282	u32 cor_err_mask_or;
 283	u32 adv_err_cap_and;
 284	u32 adv_err_cap_or;
 285	u16 pci_exp_devctl_and;
 286	u16 pci_exp_devctl_or;
 287	u16 pci_exp_lnkctl_and;
 288	u16 pci_exp_lnkctl_or;
 289	u32 sec_unc_err_sever_and;
 290	u32 sec_unc_err_sever_or;
 291	u32 sec_unc_err_mask_and;
 292	u32 sec_unc_err_mask_or;
 293};
 294
 295static void program_hpx_type2(struct pci_dev *dev, struct hpx_type2 *hpx)
 296{
 297	int pos;
 298	u32 reg32;
 299	const struct pci_host_bridge *host;
 300
 301	if (!hpx)
 302		return;
 303
 304	if (!pci_is_pcie(dev))
 305		return;
 306
 307	host = pci_find_host_bridge(dev->bus);
 308
 309	/*
 310	 * Only do the _HPX Type 2 programming if OS owns PCIe native
 311	 * hotplug but not AER.
 312	 */
 313	if (!host->native_pcie_hotplug || host->native_aer)
 314		return;
 315
 316	if (hpx->revision > 1) {
 317		pci_warn(dev, "PCIe settings rev %d not supported\n",
 318			 hpx->revision);
 319		return;
 320	}
 321
 322	/*
 323	 * We only allow _HPX to program DEVCTL bits related to AER, namely
 324	 * PCI_EXP_DEVCTL_CERE, PCI_EXP_DEVCTL_NFERE, PCI_EXP_DEVCTL_FERE,
 325	 * and PCI_EXP_DEVCTL_URRE.
 326	 *
 327	 * The rest of DEVCTL is managed by the OS to make sure it's
 328	 * consistent with the rest of the platform.
 329	 */
 330	hpx->pci_exp_devctl_and |= ~PCI_EXP_AER_FLAGS;
 331	hpx->pci_exp_devctl_or &= PCI_EXP_AER_FLAGS;
 332
 333	/* Initialize Device Control Register */
 334	pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
 335			~hpx->pci_exp_devctl_and, hpx->pci_exp_devctl_or);
 336
 337	/* Log if _HPX attempts to modify Link Control Register */
 338	if (pcie_cap_has_lnkctl(dev)) {
 339		if (hpx->pci_exp_lnkctl_and != 0xffff ||
 340		    hpx->pci_exp_lnkctl_or != 0)
 341			pci_info(dev, "_HPX attempts Link Control setting (AND %#06x OR %#06x)\n",
 342				 hpx->pci_exp_lnkctl_and,
 343				 hpx->pci_exp_lnkctl_or);
 344	}
 345
 346	/* Find Advanced Error Reporting Enhanced Capability */
 347	pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
 348	if (!pos)
 349		return;
 350
 351	/* Initialize Uncorrectable Error Mask Register */
 352	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
 353	reg32 = (reg32 & hpx->unc_err_mask_and) | hpx->unc_err_mask_or;
 354	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
 355
 356	/* Initialize Uncorrectable Error Severity Register */
 357	pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
 358	reg32 = (reg32 & hpx->unc_err_sever_and) | hpx->unc_err_sever_or;
 359	pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
 360
 361	/* Initialize Correctable Error Mask Register */
 362	pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
 363	reg32 = (reg32 & hpx->cor_err_mask_and) | hpx->cor_err_mask_or;
 364	pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
 365
 366	/* Initialize Advanced Error Capabilities and Control Register */
 367	pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
 368	reg32 = (reg32 & hpx->adv_err_cap_and) | hpx->adv_err_cap_or;
 369
 370	/* Don't enable ECRC generation or checking if unsupported */
 371	if (!(reg32 & PCI_ERR_CAP_ECRC_GENC))
 372		reg32 &= ~PCI_ERR_CAP_ECRC_GENE;
 373	if (!(reg32 & PCI_ERR_CAP_ECRC_CHKC))
 374		reg32 &= ~PCI_ERR_CAP_ECRC_CHKE;
 375	pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
 376
 377	/*
 378	 * FIXME: The following two registers are not supported yet.
 379	 *
 380	 *   o Secondary Uncorrectable Error Severity Register
 381	 *   o Secondary Uncorrectable Error Mask Register
 382	 */
 383}
 384
 385static acpi_status decode_type2_hpx_record(union acpi_object *record,
 386					   struct hpx_type2 *hpx2)
 387{
 388	int i;
 389	union acpi_object *fields = record->package.elements;
 390	u32 revision = fields[1].integer.value;
 391
 392	switch (revision) {
 393	case 1:
 394		if (record->package.count != 18)
 395			return AE_ERROR;
 396		for (i = 2; i < 18; i++)
 397			if (fields[i].type != ACPI_TYPE_INTEGER)
 398				return AE_ERROR;
 399		hpx2->revision      = revision;
 400		hpx2->unc_err_mask_and      = fields[2].integer.value;
 401		hpx2->unc_err_mask_or       = fields[3].integer.value;
 402		hpx2->unc_err_sever_and     = fields[4].integer.value;
 403		hpx2->unc_err_sever_or      = fields[5].integer.value;
 404		hpx2->cor_err_mask_and      = fields[6].integer.value;
 405		hpx2->cor_err_mask_or       = fields[7].integer.value;
 406		hpx2->adv_err_cap_and       = fields[8].integer.value;
 407		hpx2->adv_err_cap_or        = fields[9].integer.value;
 408		hpx2->pci_exp_devctl_and    = fields[10].integer.value;
 409		hpx2->pci_exp_devctl_or     = fields[11].integer.value;
 410		hpx2->pci_exp_lnkctl_and    = fields[12].integer.value;
 411		hpx2->pci_exp_lnkctl_or     = fields[13].integer.value;
 412		hpx2->sec_unc_err_sever_and = fields[14].integer.value;
 413		hpx2->sec_unc_err_sever_or  = fields[15].integer.value;
 414		hpx2->sec_unc_err_mask_and  = fields[16].integer.value;
 415		hpx2->sec_unc_err_mask_or   = fields[17].integer.value;
 416		break;
 417	default:
 418		pr_warn("%s: Type 2 Revision %d record not supported\n",
 419		       __func__, revision);
 420		return AE_ERROR;
 421	}
 422	return AE_OK;
 423}
 424
 425/* _HPX PCI Express Setting Record (Type 3) */
 426struct hpx_type3 {
 427	u16 device_type;
 428	u16 function_type;
 429	u16 config_space_location;
 430	u16 pci_exp_cap_id;
 431	u16 pci_exp_cap_ver;
 432	u16 pci_exp_vendor_id;
 433	u16 dvsec_id;
 434	u16 dvsec_rev;
 435	u16 match_offset;
 436	u32 match_mask_and;
 437	u32 match_value;
 438	u16 reg_offset;
 439	u32 reg_mask_and;
 440	u32 reg_mask_or;
 441};
 442
 443enum hpx_type3_dev_type {
 444	HPX_TYPE_ENDPOINT	= BIT(0),
 445	HPX_TYPE_LEG_END	= BIT(1),
 446	HPX_TYPE_RC_END		= BIT(2),
 447	HPX_TYPE_RC_EC		= BIT(3),
 448	HPX_TYPE_ROOT_PORT	= BIT(4),
 449	HPX_TYPE_UPSTREAM	= BIT(5),
 450	HPX_TYPE_DOWNSTREAM	= BIT(6),
 451	HPX_TYPE_PCI_BRIDGE	= BIT(7),
 452	HPX_TYPE_PCIE_BRIDGE	= BIT(8),
 453};
 454
 455static u16 hpx3_device_type(struct pci_dev *dev)
 456{
 457	u16 pcie_type = pci_pcie_type(dev);
 458	static const int pcie_to_hpx3_type[] = {
 459		[PCI_EXP_TYPE_ENDPOINT]    = HPX_TYPE_ENDPOINT,
 460		[PCI_EXP_TYPE_LEG_END]     = HPX_TYPE_LEG_END,
 461		[PCI_EXP_TYPE_RC_END]      = HPX_TYPE_RC_END,
 462		[PCI_EXP_TYPE_RC_EC]       = HPX_TYPE_RC_EC,
 463		[PCI_EXP_TYPE_ROOT_PORT]   = HPX_TYPE_ROOT_PORT,
 464		[PCI_EXP_TYPE_UPSTREAM]    = HPX_TYPE_UPSTREAM,
 465		[PCI_EXP_TYPE_DOWNSTREAM]  = HPX_TYPE_DOWNSTREAM,
 466		[PCI_EXP_TYPE_PCI_BRIDGE]  = HPX_TYPE_PCI_BRIDGE,
 467		[PCI_EXP_TYPE_PCIE_BRIDGE] = HPX_TYPE_PCIE_BRIDGE,
 468	};
 469
 470	if (pcie_type >= ARRAY_SIZE(pcie_to_hpx3_type))
 471		return 0;
 472
 473	return pcie_to_hpx3_type[pcie_type];
 474}
 475
 476enum hpx_type3_fn_type {
 477	HPX_FN_NORMAL		= BIT(0),
 478	HPX_FN_SRIOV_PHYS	= BIT(1),
 479	HPX_FN_SRIOV_VIRT	= BIT(2),
 480};
 481
 482static u8 hpx3_function_type(struct pci_dev *dev)
 483{
 484	if (dev->is_virtfn)
 485		return HPX_FN_SRIOV_VIRT;
 486	else if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_SRIOV) > 0)
 487		return HPX_FN_SRIOV_PHYS;
 488	else
 489		return HPX_FN_NORMAL;
 490}
 491
 492static bool hpx3_cap_ver_matches(u8 pcie_cap_id, u8 hpx3_cap_id)
 493{
 494	u8 cap_ver = hpx3_cap_id & 0xf;
 495
 496	if ((hpx3_cap_id & BIT(4)) && cap_ver >= pcie_cap_id)
 497		return true;
 498	else if (cap_ver == pcie_cap_id)
 499		return true;
 500
 501	return false;
 502}
 503
 504enum hpx_type3_cfg_loc {
 505	HPX_CFG_PCICFG		= 0,
 506	HPX_CFG_PCIE_CAP	= 1,
 507	HPX_CFG_PCIE_CAP_EXT	= 2,
 508	HPX_CFG_VEND_CAP	= 3,
 509	HPX_CFG_DVSEC		= 4,
 510	HPX_CFG_MAX,
 511};
 512
 513static void program_hpx_type3_register(struct pci_dev *dev,
 514				       const struct hpx_type3 *reg)
 515{
 516	u32 match_reg, write_reg, header, orig_value;
 517	u16 pos;
 518
 519	if (!(hpx3_device_type(dev) & reg->device_type))
 520		return;
 521
 522	if (!(hpx3_function_type(dev) & reg->function_type))
 523		return;
 524
 525	switch (reg->config_space_location) {
 526	case HPX_CFG_PCICFG:
 527		pos = 0;
 528		break;
 529	case HPX_CFG_PCIE_CAP:
 530		pos = pci_find_capability(dev, reg->pci_exp_cap_id);
 531		if (pos == 0)
 532			return;
 533
 534		break;
 535	case HPX_CFG_PCIE_CAP_EXT:
 536		pos = pci_find_ext_capability(dev, reg->pci_exp_cap_id);
 537		if (pos == 0)
 538			return;
 539
 540		pci_read_config_dword(dev, pos, &header);
 541		if (!hpx3_cap_ver_matches(PCI_EXT_CAP_VER(header),
 542					  reg->pci_exp_cap_ver))
 543			return;
 544
 545		break;
 546	case HPX_CFG_VEND_CAP:
 547	case HPX_CFG_DVSEC:
 548	default:
 549		pci_warn(dev, "Encountered _HPX type 3 with unsupported config space location");
 550		return;
 551	}
 552
 553	pci_read_config_dword(dev, pos + reg->match_offset, &match_reg);
 554
 555	if ((match_reg & reg->match_mask_and) != reg->match_value)
 556		return;
 557
 558	pci_read_config_dword(dev, pos + reg->reg_offset, &write_reg);
 559	orig_value = write_reg;
 560	write_reg &= reg->reg_mask_and;
 561	write_reg |= reg->reg_mask_or;
 562
 563	if (orig_value == write_reg)
 564		return;
 565
 566	pci_write_config_dword(dev, pos + reg->reg_offset, write_reg);
 567
 568	pci_dbg(dev, "Applied _HPX3 at [0x%x]: 0x%08x -> 0x%08x",
 569		pos, orig_value, write_reg);
 570}
 571
 572static void program_hpx_type3(struct pci_dev *dev, struct hpx_type3 *hpx)
 573{
 574	if (!hpx)
 575		return;
 576
 577	if (!pci_is_pcie(dev))
 578		return;
 579
 580	program_hpx_type3_register(dev, hpx);
 581}
 582
 583static void parse_hpx3_register(struct hpx_type3 *hpx3_reg,
 584				union acpi_object *reg_fields)
 585{
 586	hpx3_reg->device_type            = reg_fields[0].integer.value;
 587	hpx3_reg->function_type          = reg_fields[1].integer.value;
 588	hpx3_reg->config_space_location  = reg_fields[2].integer.value;
 589	hpx3_reg->pci_exp_cap_id         = reg_fields[3].integer.value;
 590	hpx3_reg->pci_exp_cap_ver        = reg_fields[4].integer.value;
 591	hpx3_reg->pci_exp_vendor_id      = reg_fields[5].integer.value;
 592	hpx3_reg->dvsec_id               = reg_fields[6].integer.value;
 593	hpx3_reg->dvsec_rev              = reg_fields[7].integer.value;
 594	hpx3_reg->match_offset           = reg_fields[8].integer.value;
 595	hpx3_reg->match_mask_and         = reg_fields[9].integer.value;
 596	hpx3_reg->match_value            = reg_fields[10].integer.value;
 597	hpx3_reg->reg_offset             = reg_fields[11].integer.value;
 598	hpx3_reg->reg_mask_and           = reg_fields[12].integer.value;
 599	hpx3_reg->reg_mask_or            = reg_fields[13].integer.value;
 600}
 601
 602static acpi_status program_type3_hpx_record(struct pci_dev *dev,
 603					   union acpi_object *record)
 604{
 605	union acpi_object *fields = record->package.elements;
 606	u32 desc_count, expected_length, revision;
 607	union acpi_object *reg_fields;
 608	struct hpx_type3 hpx3;
 609	int i;
 610
 611	revision = fields[1].integer.value;
 612	switch (revision) {
 613	case 1:
 614		desc_count = fields[2].integer.value;
 615		expected_length = 3 + desc_count * 14;
 616
 617		if (record->package.count != expected_length)
 618			return AE_ERROR;
 619
 620		for (i = 2; i < expected_length; i++)
 621			if (fields[i].type != ACPI_TYPE_INTEGER)
 622				return AE_ERROR;
 623
 624		for (i = 0; i < desc_count; i++) {
 625			reg_fields = fields + 3 + i * 14;
 626			parse_hpx3_register(&hpx3, reg_fields);
 627			program_hpx_type3(dev, &hpx3);
 628		}
 629
 630		break;
 631	default:
 632		printk(KERN_WARNING
 633			"%s: Type 3 Revision %d record not supported\n",
 634			__func__, revision);
 635		return AE_ERROR;
 636	}
 637	return AE_OK;
 638}
 639
 640static acpi_status acpi_run_hpx(struct pci_dev *dev, acpi_handle handle)
 641{
 642	acpi_status status;
 643	struct acpi_buffer buffer = {ACPI_ALLOCATE_BUFFER, NULL};
 644	union acpi_object *package, *record, *fields;
 645	struct hpx_type0 hpx0;
 646	struct hpx_type1 hpx1;
 647	struct hpx_type2 hpx2;
 648	u32 type;
 649	int i;
 650
 651	status = acpi_evaluate_object(handle, "_HPX", NULL, &buffer);
 652	if (ACPI_FAILURE(status))
 653		return status;
 654
 655	package = (union acpi_object *)buffer.pointer;
 656	if (package->type != ACPI_TYPE_PACKAGE) {
 657		status = AE_ERROR;
 658		goto exit;
 659	}
 660
 661	for (i = 0; i < package->package.count; i++) {
 662		record = &package->package.elements[i];
 663		if (record->type != ACPI_TYPE_PACKAGE) {
 664			status = AE_ERROR;
 665			goto exit;
 666		}
 667
 668		fields = record->package.elements;
 669		if (fields[0].type != ACPI_TYPE_INTEGER ||
 670		    fields[1].type != ACPI_TYPE_INTEGER) {
 671			status = AE_ERROR;
 672			goto exit;
 673		}
 674
 675		type = fields[0].integer.value;
 676		switch (type) {
 677		case 0:
 678			memset(&hpx0, 0, sizeof(hpx0));
 679			status = decode_type0_hpx_record(record, &hpx0);
 680			if (ACPI_FAILURE(status))
 681				goto exit;
 682			program_hpx_type0(dev, &hpx0);
 683			break;
 684		case 1:
 685			memset(&hpx1, 0, sizeof(hpx1));
 686			status = decode_type1_hpx_record(record, &hpx1);
 687			if (ACPI_FAILURE(status))
 688				goto exit;
 689			program_hpx_type1(dev, &hpx1);
 690			break;
 691		case 2:
 692			memset(&hpx2, 0, sizeof(hpx2));
 693			status = decode_type2_hpx_record(record, &hpx2);
 694			if (ACPI_FAILURE(status))
 695				goto exit;
 696			program_hpx_type2(dev, &hpx2);
 697			break;
 698		case 3:
 699			status = program_type3_hpx_record(dev, record);
 700			if (ACPI_FAILURE(status))
 701				goto exit;
 702			break;
 703		default:
 704			pr_err("%s: Type %d record not supported\n",
 705			       __func__, type);
 706			status = AE_ERROR;
 707			goto exit;
 708		}
 709	}
 710 exit:
 711	kfree(buffer.pointer);
 712	return status;
 713}
 714
 715static acpi_status acpi_run_hpp(struct pci_dev *dev, acpi_handle handle)
 716{
 717	acpi_status status;
 718	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 719	union acpi_object *package, *fields;
 720	struct hpx_type0 hpx0;
 721	int i;
 722
 723	memset(&hpx0, 0, sizeof(hpx0));
 724
 725	status = acpi_evaluate_object(handle, "_HPP", NULL, &buffer);
 726	if (ACPI_FAILURE(status))
 727		return status;
 728
 729	package = (union acpi_object *) buffer.pointer;
 730	if (package->type != ACPI_TYPE_PACKAGE ||
 731	    package->package.count != 4) {
 732		status = AE_ERROR;
 733		goto exit;
 734	}
 735
 736	fields = package->package.elements;
 737	for (i = 0; i < 4; i++) {
 738		if (fields[i].type != ACPI_TYPE_INTEGER) {
 739			status = AE_ERROR;
 740			goto exit;
 741		}
 742	}
 743
 744	hpx0.revision        = 1;
 745	hpx0.cache_line_size = fields[0].integer.value;
 746	hpx0.latency_timer   = fields[1].integer.value;
 747	hpx0.enable_serr     = fields[2].integer.value;
 748	hpx0.enable_perr     = fields[3].integer.value;
 749
 750	program_hpx_type0(dev, &hpx0);
 751
 752exit:
 753	kfree(buffer.pointer);
 754	return status;
 755}
 756
 757/* pci_acpi_program_hp_params
 758 *
 759 * @dev - the pci_dev for which we want parameters
 760 */
 761int pci_acpi_program_hp_params(struct pci_dev *dev)
 762{
 763	acpi_status status;
 764	acpi_handle handle, phandle;
 765	struct pci_bus *pbus;
 766
 767	if (acpi_pci_disabled)
 768		return -ENODEV;
 769
 770	handle = NULL;
 771	for (pbus = dev->bus; pbus; pbus = pbus->parent) {
 772		handle = acpi_pci_get_bridge_handle(pbus);
 773		if (handle)
 774			break;
 775	}
 776
 777	/*
 778	 * _HPP settings apply to all child buses, until another _HPP is
 779	 * encountered. If we don't find an _HPP for the input pci dev,
 780	 * look for it in the parent device scope since that would apply to
 781	 * this pci dev.
 782	 */
 783	while (handle) {
 784		status = acpi_run_hpx(dev, handle);
 785		if (ACPI_SUCCESS(status))
 786			return 0;
 787		status = acpi_run_hpp(dev, handle);
 788		if (ACPI_SUCCESS(status))
 789			return 0;
 790		if (acpi_is_root_bridge(handle))
 791			break;
 792		status = acpi_get_parent(handle, &phandle);
 793		if (ACPI_FAILURE(status))
 794			break;
 795		handle = phandle;
 796	}
 797	return -ENODEV;
 798}
 799
 800/**
 801 * pciehp_is_native - Check whether a hotplug port is handled by the OS
 802 * @bridge: Hotplug port to check
 803 *
 804 * Returns true if the given @bridge is handled by the native PCIe hotplug
 805 * driver.
 806 */
 807bool pciehp_is_native(struct pci_dev *bridge)
 808{
 809	const struct pci_host_bridge *host;
 810
 811	if (!IS_ENABLED(CONFIG_HOTPLUG_PCI_PCIE))
 812		return false;
 813
 814	if (pcie_ports_native)
 815		return true;
 816
 817	host = pci_find_host_bridge(bridge->bus);
 818	return host->native_pcie_hotplug;
 819}
 820
 821/**
 822 * shpchp_is_native - Check whether a hotplug port is handled by the OS
 823 * @bridge: Hotplug port to check
 824 *
 825 * Returns true if the given @bridge is handled by the native SHPC hotplug
 826 * driver.
 827 */
 828bool shpchp_is_native(struct pci_dev *bridge)
 829{
 830	return bridge->shpc_managed;
 831}
 832
 833/**
 834 * pci_acpi_wake_bus - Root bus wakeup notification fork function.
 835 * @context: Device wakeup context.
 836 */
 837static void pci_acpi_wake_bus(struct acpi_device_wakeup_context *context)
 838{
 839	struct acpi_device *adev;
 840	struct acpi_pci_root *root;
 841
 842	adev = container_of(context, struct acpi_device, wakeup.context);
 843	root = acpi_driver_data(adev);
 844	pci_pme_wakeup_bus(root->bus);
 845}
 846
 847/**
 848 * pci_acpi_wake_dev - PCI device wakeup notification work function.
 849 * @context: Device wakeup context.
 850 */
 851static void pci_acpi_wake_dev(struct acpi_device_wakeup_context *context)
 852{
 853	struct pci_dev *pci_dev;
 854
 855	pci_dev = to_pci_dev(context->dev);
 856
 857	if (pci_dev->pme_poll)
 858		pci_dev->pme_poll = false;
 859
 860	if (pci_dev->current_state == PCI_D3cold) {
 861		pci_wakeup_event(pci_dev);
 862		pm_request_resume(&pci_dev->dev);
 863		return;
 864	}
 865
 866	/* Clear PME Status if set. */
 867	if (pci_dev->pme_support)
 868		pci_check_pme_status(pci_dev);
 869
 870	pci_wakeup_event(pci_dev);
 871	pm_request_resume(&pci_dev->dev);
 872
 873	pci_pme_wakeup_bus(pci_dev->subordinate);
 874}
 875
 876/**
 877 * pci_acpi_add_bus_pm_notifier - Register PM notifier for root PCI bus.
 878 * @dev: PCI root bridge ACPI device.
 879 */
 880acpi_status pci_acpi_add_bus_pm_notifier(struct acpi_device *dev)
 881{
 882	return acpi_add_pm_notifier(dev, NULL, pci_acpi_wake_bus);
 883}
 884
 885/**
 886 * pci_acpi_add_pm_notifier - Register PM notifier for given PCI device.
 887 * @dev: ACPI device to add the notifier for.
 888 * @pci_dev: PCI device to check for the PME status if an event is signaled.
 889 */
 890acpi_status pci_acpi_add_pm_notifier(struct acpi_device *dev,
 891				     struct pci_dev *pci_dev)
 892{
 893	return acpi_add_pm_notifier(dev, &pci_dev->dev, pci_acpi_wake_dev);
 894}
 895
 896/*
 897 * _SxD returns the D-state with the highest power
 898 * (lowest D-state number) supported in the S-state "x".
 899 *
 900 * If the devices does not have a _PRW
 901 * (Power Resources for Wake) supporting system wakeup from "x"
 902 * then the OS is free to choose a lower power (higher number
 903 * D-state) than the return value from _SxD.
 904 *
 905 * But if _PRW is enabled at S-state "x", the OS
 906 * must not choose a power lower than _SxD --
 907 * unless the device has an _SxW method specifying
 908 * the lowest power (highest D-state number) the device
 909 * may enter while still able to wake the system.
 910 *
 911 * ie. depending on global OS policy:
 912 *
 913 * if (_PRW at S-state x)
 914 *	choose from highest power _SxD to lowest power _SxW
 915 * else // no _PRW at S-state x
 916 *	choose highest power _SxD or any lower power
 917 */
 918
 919pci_power_t acpi_pci_choose_state(struct pci_dev *pdev)
 920{
 921	int acpi_state, d_max;
 922
 923	if (pdev->no_d3cold || !pdev->d3cold_allowed)
 924		d_max = ACPI_STATE_D3_HOT;
 925	else
 926		d_max = ACPI_STATE_D3_COLD;
 927	acpi_state = acpi_pm_device_sleep_state(&pdev->dev, NULL, d_max);
 928	if (acpi_state < 0)
 929		return PCI_POWER_ERROR;
 930
 931	switch (acpi_state) {
 932	case ACPI_STATE_D0:
 933		return PCI_D0;
 934	case ACPI_STATE_D1:
 935		return PCI_D1;
 936	case ACPI_STATE_D2:
 937		return PCI_D2;
 938	case ACPI_STATE_D3_HOT:
 939		return PCI_D3hot;
 940	case ACPI_STATE_D3_COLD:
 941		return PCI_D3cold;
 942	}
 943	return PCI_POWER_ERROR;
 944}
 945
 946static struct acpi_device *acpi_pci_find_companion(struct device *dev);
 947
 948void pci_set_acpi_fwnode(struct pci_dev *dev)
 949{
 950	if (!dev_fwnode(&dev->dev) && !pci_dev_is_added(dev))
 951		ACPI_COMPANION_SET(&dev->dev,
 952				   acpi_pci_find_companion(&dev->dev));
 953}
 954
 955/**
 956 * pci_dev_acpi_reset - do a function level reset using _RST method
 957 * @dev: device to reset
 958 * @probe: if true, return 0 if device supports _RST
 959 */
 960int pci_dev_acpi_reset(struct pci_dev *dev, bool probe)
 961{
 962	acpi_handle handle = ACPI_HANDLE(&dev->dev);
 963
 964	if (!handle || !acpi_has_method(handle, "_RST"))
 965		return -ENOTTY;
 966
 967	if (probe)
 968		return 0;
 969
 970	if (ACPI_FAILURE(acpi_evaluate_object(handle, "_RST", NULL, NULL))) {
 971		pci_warn(dev, "ACPI _RST failed\n");
 972		return -ENOTTY;
 973	}
 974
 975	return 0;
 976}
 977
 978bool acpi_pci_power_manageable(struct pci_dev *dev)
 979{
 980	struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
 981
 982	return adev && acpi_device_power_manageable(adev);
 983}
 984
 985bool acpi_pci_bridge_d3(struct pci_dev *dev)
 986{
 987	struct pci_dev *rpdev;
 988	struct acpi_device *adev, *rpadev;
 989	const union acpi_object *obj;
 990
 991	if (acpi_pci_disabled || !dev->is_pciehp)
 992		return false;
 993
 994	adev = ACPI_COMPANION(&dev->dev);
 995	if (adev) {
 996		/*
 997		 * If the bridge has _S0W, whether or not it can go into D3
 998		 * depends on what is returned by that object.  In particular,
 999		 * if the power state returned by _S0W is D2 or shallower,
1000		 * entering D3 should not be allowed.
1001		 */
1002		if (acpi_dev_power_state_for_wake(adev) <= ACPI_STATE_D2)
1003			return false;
1004
1005		/*
1006		 * Otherwise, assume that the bridge can enter D3 so long as it
1007		 * is power-manageable via ACPI.
1008		 */
1009		if (acpi_device_power_manageable(adev))
1010			return true;
1011	}
1012
1013	rpdev = pcie_find_root_port(dev);
1014	if (!rpdev)
1015		return false;
1016
1017	if (rpdev == dev)
1018		rpadev = adev;
1019	else
1020		rpadev = ACPI_COMPANION(&rpdev->dev);
1021
1022	if (!rpadev)
1023		return false;
1024
1025	/*
1026	 * If the Root Port cannot signal wakeup signals at all, i.e., it
1027	 * doesn't supply a wakeup GPE via _PRW, it cannot signal hotplug
1028	 * events from low-power states including D3hot and D3cold.
1029	 */
1030	if (!rpadev->wakeup.flags.valid)
1031		return false;
1032
1033	/*
1034	 * In the bridge-below-a-Root-Port case, evaluate _S0W for the Root Port
1035	 * to verify whether or not it can signal wakeup from D3.
1036	 */
1037	if (rpadev != adev &&
1038	    acpi_dev_power_state_for_wake(rpadev) <= ACPI_STATE_D2)
1039		return false;
1040
1041	/*
1042	 * The "HotPlugSupportInD3" property in a Root Port _DSD indicates
1043	 * the Port can signal hotplug events while in D3.  We assume any
1044	 * bridges *below* that Root Port can also signal hotplug events
1045	 * while in D3.
1046	 */
1047	if (!acpi_dev_get_property(rpadev, "HotPlugSupportInD3",
1048				   ACPI_TYPE_INTEGER, &obj) &&
1049	    obj->integer.value == 1)
1050		return true;
1051
1052	return false;
1053}
1054
1055static void acpi_pci_config_space_access(struct pci_dev *dev, bool enable)
1056{
1057	int val = enable ? ACPI_REG_CONNECT : ACPI_REG_DISCONNECT;
1058	int ret = acpi_evaluate_reg(ACPI_HANDLE(&dev->dev),
1059				    ACPI_ADR_SPACE_PCI_CONFIG, val);
1060	if (ret)
1061		pci_dbg(dev, "ACPI _REG %s evaluation failed (%d)\n",
1062			enable ? "connect" : "disconnect", ret);
1063}
1064
1065int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state)
1066{
1067	struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1068	static const u8 state_conv[] = {
1069		[PCI_D0] = ACPI_STATE_D0,
1070		[PCI_D1] = ACPI_STATE_D1,
1071		[PCI_D2] = ACPI_STATE_D2,
1072		[PCI_D3hot] = ACPI_STATE_D3_HOT,
1073		[PCI_D3cold] = ACPI_STATE_D3_COLD,
1074	};
1075	int error;
1076
1077	/* If the ACPI device has _EJ0, ignore the device */
1078	if (!adev || acpi_has_method(adev->handle, "_EJ0"))
1079		return -ENODEV;
1080
1081	switch (state) {
1082	case PCI_D0:
1083	case PCI_D1:
1084	case PCI_D2:
1085	case PCI_D3hot:
1086	case PCI_D3cold:
1087		break;
1088	default:
1089		return -EINVAL;
1090	}
1091
1092	if (state == PCI_D3cold) {
1093		if (dev_pm_qos_flags(&dev->dev, PM_QOS_FLAG_NO_POWER_OFF) ==
1094				PM_QOS_FLAGS_ALL)
1095			return -EBUSY;
1096
1097		/* Notify AML lack of PCI config space availability */
1098		acpi_pci_config_space_access(dev, false);
1099	}
1100
1101	error = acpi_device_set_power(adev, state_conv[state]);
1102	if (error)
1103		return error;
1104
1105	pci_dbg(dev, "power state changed by ACPI to %s\n",
1106	        acpi_power_state_string(adev->power.state));
1107
1108	/*
1109	 * Notify AML of PCI config space availability.  Config space is
1110	 * accessible in all states except D3cold; the only transitions
1111	 * that change availability are transitions to D3cold and from
1112	 * D3cold to D0.
1113	 */
1114	if (state == PCI_D0)
1115		acpi_pci_config_space_access(dev, true);
1116
1117	return 0;
1118}
1119
1120pci_power_t acpi_pci_get_power_state(struct pci_dev *dev)
1121{
1122	struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1123	static const pci_power_t state_conv[] = {
1124		[ACPI_STATE_D0]      = PCI_D0,
1125		[ACPI_STATE_D1]      = PCI_D1,
1126		[ACPI_STATE_D2]      = PCI_D2,
1127		[ACPI_STATE_D3_HOT]  = PCI_D3hot,
1128		[ACPI_STATE_D3_COLD] = PCI_D3cold,
1129	};
1130	int state;
1131
1132	if (!adev || !acpi_device_power_manageable(adev))
1133		return PCI_UNKNOWN;
1134
1135	state = adev->power.state;
1136	if (state == ACPI_STATE_UNKNOWN)
1137		return PCI_UNKNOWN;
1138
1139	return state_conv[state];
1140}
1141
1142void acpi_pci_refresh_power_state(struct pci_dev *dev)
1143{
1144	struct acpi_device *adev = ACPI_COMPANION(&dev->dev);
1145
1146	if (adev && acpi_device_power_manageable(adev))
1147		acpi_device_update_power(adev, NULL);
1148}
1149
1150static int acpi_pci_propagate_wakeup(struct pci_bus *bus, bool enable)
1151{
1152	while (bus->parent) {
1153		if (acpi_pm_device_can_wakeup(&bus->self->dev))
1154			return acpi_pm_set_device_wakeup(&bus->self->dev, enable);
1155
1156		bus = bus->parent;
1157	}
1158
1159	/* We have reached the root bus. */
1160	if (bus->bridge) {
1161		if (acpi_pm_device_can_wakeup(bus->bridge))
1162			return acpi_pm_set_device_wakeup(bus->bridge, enable);
1163	}
1164	return 0;
1165}
1166
1167int acpi_pci_wakeup(struct pci_dev *dev, bool enable)
1168{
1169	if (acpi_pci_disabled)
1170		return 0;
1171
1172	if (acpi_pm_device_can_wakeup(&dev->dev))
1173		return acpi_pm_set_device_wakeup(&dev->dev, enable);
1174
1175	return acpi_pci_propagate_wakeup(dev->bus, enable);
1176}
1177
1178bool acpi_pci_need_resume(struct pci_dev *dev)
1179{
1180	struct acpi_device *adev;
1181
1182	if (acpi_pci_disabled)
1183		return false;
1184
1185	/*
1186	 * In some cases (eg. Samsung 305V4A) leaving a bridge in suspend over
1187	 * system-wide suspend/resume confuses the platform firmware, so avoid
1188	 * doing that.  According to Section 16.1.6 of ACPI 6.2, endpoint
1189	 * devices are expected to be in D3 before invoking the S3 entry path
1190	 * from the firmware, so they should not be affected by this issue.
1191	 */
1192	if (pci_is_bridge(dev) && acpi_target_system_state() != ACPI_STATE_S0)
1193		return true;
1194
1195	adev = ACPI_COMPANION(&dev->dev);
1196	if (!adev || !acpi_device_power_manageable(adev))
1197		return false;
1198
1199	if (adev->wakeup.flags.valid &&
1200	    device_may_wakeup(&dev->dev) != !!adev->wakeup.prepare_count)
1201		return true;
1202
1203	if (acpi_target_system_state() == ACPI_STATE_S0)
1204		return false;
1205
1206	return !!adev->power.flags.dsw_present;
1207}
1208
1209void acpi_pci_add_bus(struct pci_bus *bus)
1210{
1211	union acpi_object *obj;
1212	struct pci_host_bridge *bridge;
1213
1214	if (acpi_pci_disabled || !bus->bridge || !ACPI_HANDLE(bus->bridge))
1215		return;
1216
1217	acpi_pci_slot_enumerate(bus);
1218	acpiphp_enumerate_slots(bus);
1219
1220	/*
1221	 * For a host bridge, check its _DSM for function 8 and if
1222	 * that is available, mark it in pci_host_bridge.
1223	 */
1224	if (!pci_is_root_bus(bus))
1225		return;
1226
1227	obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(bus->bridge), &pci_acpi_dsm_guid, 3,
1228				      DSM_PCI_POWER_ON_RESET_DELAY, NULL, ACPI_TYPE_INTEGER);
1229	if (!obj)
1230		return;
1231
1232	if (obj->integer.value == 1) {
1233		bridge = pci_find_host_bridge(bus);
1234		bridge->ignore_reset_delay = 1;
1235	}
1236	ACPI_FREE(obj);
1237}
1238
1239void acpi_pci_remove_bus(struct pci_bus *bus)
1240{
1241	if (acpi_pci_disabled || !bus->bridge)
1242		return;
1243
1244	acpiphp_remove_slots(bus);
1245	acpi_pci_slot_remove(bus);
1246}
1247
1248/* ACPI bus type */
1249
1250
1251static DECLARE_RWSEM(pci_acpi_companion_lookup_sem);
1252static struct acpi_device *(*pci_acpi_find_companion_hook)(struct pci_dev *);
1253
1254/**
1255 * pci_acpi_set_companion_lookup_hook - Set ACPI companion lookup callback.
1256 * @func: ACPI companion lookup callback pointer or NULL.
1257 *
1258 * Set a special ACPI companion lookup callback for PCI devices whose companion
1259 * objects in the ACPI namespace have _ADR with non-standard bus-device-function
1260 * encodings.
1261 *
1262 * Return 0 on success or a negative error code on failure (in which case no
1263 * changes are made).
1264 *
1265 * The caller is responsible for the appropriate ordering of the invocations of
1266 * this function with respect to the enumeration of the PCI devices needing the
1267 * callback installed by it.
1268 */
1269int pci_acpi_set_companion_lookup_hook(struct acpi_device *(*func)(struct pci_dev *))
1270{
1271	int ret;
1272
1273	if (!func)
1274		return -EINVAL;
1275
1276	down_write(&pci_acpi_companion_lookup_sem);
1277
1278	if (pci_acpi_find_companion_hook) {
1279		ret = -EBUSY;
1280	} else {
1281		pci_acpi_find_companion_hook = func;
1282		ret = 0;
1283	}
1284
1285	up_write(&pci_acpi_companion_lookup_sem);
1286
1287	return ret;
1288}
1289EXPORT_SYMBOL_GPL(pci_acpi_set_companion_lookup_hook);
1290
1291/**
1292 * pci_acpi_clear_companion_lookup_hook - Clear ACPI companion lookup callback.
1293 *
1294 * Clear the special ACPI companion lookup callback previously set by
1295 * pci_acpi_set_companion_lookup_hook().  Block until the last running instance
1296 * of the callback returns before clearing it.
1297 *
1298 * The caller is responsible for the appropriate ordering of the invocations of
1299 * this function with respect to the enumeration of the PCI devices needing the
1300 * callback cleared by it.
1301 */
1302void pci_acpi_clear_companion_lookup_hook(void)
1303{
1304	down_write(&pci_acpi_companion_lookup_sem);
1305
1306	pci_acpi_find_companion_hook = NULL;
1307
1308	up_write(&pci_acpi_companion_lookup_sem);
1309}
1310EXPORT_SYMBOL_GPL(pci_acpi_clear_companion_lookup_hook);
1311
1312static struct acpi_device *acpi_pci_find_companion(struct device *dev)
1313{
1314	struct pci_dev *pci_dev = to_pci_dev(dev);
1315	struct acpi_device *adev;
1316	bool check_children;
1317	u64 addr;
1318
1319	if (!dev->parent)
1320		return NULL;
1321
1322	down_read(&pci_acpi_companion_lookup_sem);
1323
1324	adev = pci_acpi_find_companion_hook ?
1325		pci_acpi_find_companion_hook(pci_dev) : NULL;
1326
1327	up_read(&pci_acpi_companion_lookup_sem);
1328
1329	if (adev)
1330		return adev;
1331
1332	check_children = pci_is_bridge(pci_dev);
1333	/* Please ref to ACPI spec for the syntax of _ADR */
1334	addr = (PCI_SLOT(pci_dev->devfn) << 16) | PCI_FUNC(pci_dev->devfn);
1335	adev = acpi_find_child_device(ACPI_COMPANION(dev->parent), addr,
1336				      check_children);
1337
1338	/*
1339	 * There may be ACPI device objects in the ACPI namespace that are
1340	 * children of the device object representing the host bridge, but don't
1341	 * represent PCI devices.  Both _HID and _ADR may be present for them,
1342	 * even though that is against the specification (for example, see
1343	 * Section 6.1 of ACPI 6.3), but in many cases the _ADR returns 0 which
1344	 * appears to indicate that they should not be taken into consideration
1345	 * as potential companions of PCI devices on the root bus.
1346	 *
1347	 * To catch this special case, disregard the returned device object if
1348	 * it has a valid _HID, addr is 0 and the PCI device at hand is on the
1349	 * root bus.
1350	 */
1351	if (adev && adev->pnp.type.platform_id && !addr &&
1352	    pci_is_root_bus(pci_dev->bus))
1353		return NULL;
1354
1355	return adev;
1356}
1357
1358/**
1359 * pci_acpi_optimize_delay - optimize PCI D3 and D3cold delay from ACPI
1360 * @pdev: the PCI device whose delay is to be updated
1361 * @handle: ACPI handle of this device
1362 *
1363 * Update the d3hot_delay and d3cold_delay of a PCI device from the ACPI _DSM
1364 * control method of either the device itself or the PCI host bridge.
1365 *
1366 * Function 8, "Reset Delay," applies to the entire hierarchy below a PCI
1367 * host bridge.  If it returns one, the OS may assume that all devices in
1368 * the hierarchy have already completed power-on reset delays.
1369 *
1370 * Function 9, "Device Readiness Durations," applies only to the object
1371 * where it is located.  It returns delay durations required after various
1372 * events if the device requires less time than the spec requires.  Delays
1373 * from this function take precedence over the Reset Delay function.
1374 *
1375 * These _DSM functions are defined by the draft ECN of January 28, 2014,
1376 * titled "ACPI additions for FW latency optimizations."
1377 */
1378static void pci_acpi_optimize_delay(struct pci_dev *pdev,
1379				    acpi_handle handle)
1380{
1381	struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
1382	int value;
1383	union acpi_object *obj, *elements;
1384
1385	if (bridge->ignore_reset_delay)
1386		pdev->d3cold_delay = 0;
1387
1388	obj = acpi_evaluate_dsm_typed(handle, &pci_acpi_dsm_guid, 3,
1389				      DSM_PCI_DEVICE_READINESS_DURATIONS, NULL,
1390				      ACPI_TYPE_PACKAGE);
1391	if (!obj)
1392		return;
1393
1394	if (obj->package.count == 5) {
1395		elements = obj->package.elements;
1396		if (elements[0].type == ACPI_TYPE_INTEGER) {
1397			value = (int)elements[0].integer.value / 1000;
1398			if (value < PCI_PM_D3COLD_WAIT)
1399				pdev->d3cold_delay = value;
1400		}
1401		if (elements[3].type == ACPI_TYPE_INTEGER) {
1402			value = (int)elements[3].integer.value / 1000;
1403			if (value < PCI_PM_D3HOT_WAIT)
1404				pdev->d3hot_delay = value;
1405		}
1406	}
1407	ACPI_FREE(obj);
1408}
1409
1410static void pci_acpi_set_external_facing(struct pci_dev *dev)
1411{
1412	u8 val;
1413
1414	if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1415		return;
1416	if (device_property_read_u8(&dev->dev, "ExternalFacingPort", &val))
1417		return;
1418
1419	/*
1420	 * These root ports expose PCIe (including DMA) outside of the
1421	 * system.  Everything downstream from them is external.
1422	 */
1423	if (val)
1424		dev->external_facing = 1;
1425}
1426
1427void pci_acpi_setup(struct device *dev, struct acpi_device *adev)
1428{
1429	struct pci_dev *pci_dev = to_pci_dev(dev);
1430
1431	pci_acpi_optimize_delay(pci_dev, adev->handle);
1432	pci_acpi_set_external_facing(pci_dev);
1433	pci_acpi_add_edr_notifier(pci_dev);
1434
1435	pci_acpi_add_pm_notifier(adev, pci_dev);
1436	if (!adev->wakeup.flags.valid)
1437		return;
1438
1439	device_set_wakeup_capable(dev, true);
1440	/*
1441	 * For bridges that can do D3 we enable wake automatically (as
1442	 * we do for the power management itself in that case). The
1443	 * reason is that the bridge may have additional methods such as
1444	 * _DSW that need to be called.
1445	 */
1446	if (pci_dev->bridge_d3)
1447		device_wakeup_enable(dev);
1448
1449	acpi_pci_wakeup(pci_dev, false);
1450	acpi_device_power_add_dependent(adev, dev);
1451
1452	if (pci_is_bridge(pci_dev))
1453		acpi_dev_power_up_children_with_adr(adev);
1454}
1455
1456void pci_acpi_cleanup(struct device *dev, struct acpi_device *adev)
1457{
1458	struct pci_dev *pci_dev = to_pci_dev(dev);
1459
1460	pci_acpi_remove_edr_notifier(pci_dev);
1461	pci_acpi_remove_pm_notifier(adev);
1462	if (adev->wakeup.flags.valid) {
1463		acpi_device_power_remove_dependent(adev, dev);
1464		if (pci_dev->bridge_d3)
1465			device_wakeup_disable(dev);
1466
1467		device_set_wakeup_capable(dev, false);
1468	}
1469}
1470
1471static struct fwnode_handle *(*pci_msi_get_fwnode_cb)(struct device *dev);
1472
1473/**
1474 * pci_msi_register_fwnode_provider - Register callback to retrieve fwnode
1475 * @fn:       Callback matching a device to a fwnode that identifies a PCI
1476 *            MSI domain.
1477 *
1478 * This should be called by irqchip driver, which is the parent of
1479 * the MSI domain to provide callback interface to query fwnode.
1480 */
1481void
1482pci_msi_register_fwnode_provider(struct fwnode_handle *(*fn)(struct device *))
1483{
1484	pci_msi_get_fwnode_cb = fn;
1485}
1486
1487/**
1488 * pci_host_bridge_acpi_msi_domain - Retrieve MSI domain of a PCI host bridge
1489 * @bus:      The PCI host bridge bus.
1490 *
1491 * This function uses the callback function registered by
1492 * pci_msi_register_fwnode_provider() to retrieve the irq_domain with
1493 * type DOMAIN_BUS_PCI_MSI of the specified host bridge bus.
1494 * This returns NULL on error or when the domain is not found.
1495 */
1496struct irq_domain *pci_host_bridge_acpi_msi_domain(struct pci_bus *bus)
1497{
1498	struct fwnode_handle *fwnode;
1499
1500	if (!pci_msi_get_fwnode_cb)
1501		return NULL;
1502
1503	fwnode = pci_msi_get_fwnode_cb(&bus->dev);
1504	if (!fwnode)
1505		return NULL;
1506
1507	return irq_find_matching_fwnode(fwnode, DOMAIN_BUS_PCI_MSI);
1508}
1509
1510static int __init acpi_pci_init(void)
1511{
1512	if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_MSI) {
1513		pr_info("ACPI FADT declares the system doesn't support MSI, so disable it\n");
1514		pci_no_msi();
1515	}
1516
1517	if (acpi_gbl_FADT.boot_flags & ACPI_FADT_NO_ASPM) {
1518		pr_info("ACPI FADT declares the system doesn't support PCIe ASPM, so disable it\n");
1519		pcie_no_aspm();
1520	}
1521
1522	if (acpi_pci_disabled)
1523		return 0;
1524
1525	acpi_pci_slot_init();
1526	acpiphp_init();
1527
1528	return 0;
1529}
1530arch_initcall(acpi_pci_init);
1531
1532#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
1533
1534/*
1535 * Try to assign the IRQ number when probing a new device
1536 */
1537int pcibios_alloc_irq(struct pci_dev *dev)
1538{
1539	if (!acpi_disabled)
1540		acpi_pci_irq_enable(dev);
1541
1542	return 0;
1543}
1544
1545struct acpi_pci_generic_root_info {
1546	struct acpi_pci_root_info	common;
1547	struct pci_config_window	*cfg;	/* config space mapping */
1548};
1549
1550int acpi_pci_bus_find_domain_nr(struct pci_bus *bus)
1551{
1552	struct pci_config_window *cfg = bus->sysdata;
1553	struct acpi_device *adev = to_acpi_device(cfg->parent);
1554	struct acpi_pci_root *root = acpi_driver_data(adev);
1555
1556	return root->segment;
1557}
1558
1559int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1560{
1561	struct pci_config_window *cfg;
1562	struct acpi_device *adev;
1563	struct device *bus_dev;
1564
1565	if (acpi_disabled)
1566		return 0;
1567
1568	cfg = bridge->bus->sysdata;
1569
1570	/*
1571	 * On Hyper-V there is no corresponding ACPI device for a root bridge,
1572	 * therefore ->parent is set as NULL by the driver. And set 'adev' as
1573	 * NULL in this case because there is no proper ACPI device.
1574	 */
1575	if (!cfg->parent)
1576		adev = NULL;
1577	else
1578		adev = to_acpi_device(cfg->parent);
1579
1580	bus_dev = &bridge->bus->dev;
1581
1582	ACPI_COMPANION_SET(&bridge->dev, adev);
1583	set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev)));
1584
1585	return 0;
1586}
1587
1588static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci)
1589{
1590	struct resource_entry *entry, *tmp;
1591	int status;
1592
1593	status = acpi_pci_probe_root_resources(ci);
1594	resource_list_for_each_entry_safe(entry, tmp, &ci->resources) {
1595		if (!(entry->res->flags & IORESOURCE_WINDOW))
1596			resource_list_destroy_entry(entry);
1597	}
1598	return status;
1599}
1600
1601/*
1602 * Lookup the bus range for the domain in MCFG, and set up config space
1603 * mapping.
1604 */
1605static struct pci_config_window *
1606pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root)
1607{
1608	struct device *dev = &root->device->dev;
1609	struct resource *bus_res = &root->secondary;
1610	u16 seg = root->segment;
1611	const struct pci_ecam_ops *ecam_ops;
1612	struct resource cfgres;
1613	struct acpi_device *adev;
1614	struct pci_config_window *cfg;
1615	int ret;
1616
1617	ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops);
1618	if (ret) {
1619		dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res);
1620		return NULL;
1621	}
1622
1623	adev = acpi_resource_consumer(&cfgres);
1624	if (adev)
1625		dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres,
1626			 dev_name(&adev->dev));
1627	else
1628		dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n",
1629			 &cfgres);
1630
1631	cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops);
1632	if (IS_ERR(cfg)) {
1633		dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res,
1634			PTR_ERR(cfg));
1635		return NULL;
1636	}
1637
1638	return cfg;
1639}
1640
1641/* release_info: free resources allocated by init_info */
1642static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci)
1643{
1644	struct acpi_pci_generic_root_info *ri;
1645
1646	ri = container_of(ci, struct acpi_pci_generic_root_info, common);
1647	pci_ecam_free(ri->cfg);
1648	kfree(ci->ops);
1649	kfree(ri);
1650}
1651
1652/* Interface called from ACPI code to setup PCI host controller */
1653struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
1654{
1655	struct acpi_pci_generic_root_info *ri;
1656	struct pci_bus *bus, *child;
1657	struct acpi_pci_root_ops *root_ops;
1658	struct pci_host_bridge *host;
1659
1660	ri = kzalloc(sizeof(*ri), GFP_KERNEL);
1661	if (!ri)
1662		return NULL;
1663
1664	root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL);
1665	if (!root_ops) {
1666		kfree(ri);
1667		return NULL;
1668	}
1669
1670	ri->cfg = pci_acpi_setup_ecam_mapping(root);
1671	if (!ri->cfg) {
1672		kfree(ri);
1673		kfree(root_ops);
1674		return NULL;
1675	}
1676
1677	root_ops->release_info = pci_acpi_generic_release_info;
1678	root_ops->prepare_resources = pci_acpi_root_prepare_resources;
1679	root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops;
1680	bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg);
1681	if (!bus)
1682		return NULL;
1683
1684	/* If we must preserve the resource configuration, claim now */
1685	host = pci_find_host_bridge(bus);
1686	if (host->preserve_config)
1687		pci_bus_claim_resources(bus);
1688
1689	/*
1690	 * Assign whatever was left unassigned. If we didn't claim above,
1691	 * this will reassign everything.
1692	 */
1693	pci_assign_unassigned_root_bus_resources(bus);
1694
1695	list_for_each_entry(child, &bus->children, node)
1696		pcie_bus_configure_settings(child);
1697
1698	return bus;
1699}
1700
1701void pcibios_add_bus(struct pci_bus *bus)
1702{
1703	acpi_pci_add_bus(bus);
1704}
1705
1706void pcibios_remove_bus(struct pci_bus *bus)
1707{
1708	acpi_pci_remove_bus(bus);
1709}
1710
1711#endif