of_property.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * Copyright (C) 2022-2023, Advanced Micro Devices, Inc.
  4 */
  5
  6#include <linux/pci.h>
  7#include <linux/of.h>
  8#include <linux/of_irq.h>
  9#include <linux/bitfield.h>
 10#include <linux/bits.h>
 11#include "pci.h"
 12
 13#define OF_PCI_ADDRESS_CELLS		3
 14#define OF_PCI_SIZE_CELLS		2
 15#define OF_PCI_MAX_INT_PIN		4
 16
 17struct of_pci_addr_pair {
 18	u32		phys_addr[OF_PCI_ADDRESS_CELLS];
 19	u32		size[OF_PCI_SIZE_CELLS];
 20};
 21
 22/*
 23 * Each entry in the ranges table is a tuple containing the child address,
 24 * the parent address, and the size of the region in the child address space.
 25 * Thus, for PCI, in each entry parent address is an address on the primary
 26 * side and the child address is the corresponding address on the secondary
 27 * side.
 28 */
 29struct of_pci_range_entry {
 30	u32		child_addr[OF_PCI_ADDRESS_CELLS];
 31	u32		parent_addr[OF_PCI_ADDRESS_CELLS];
 32	u32		size[OF_PCI_SIZE_CELLS];
 33};
 34
 35#define OF_PCI_ADDR_SPACE_IO		0x1
 36#define OF_PCI_ADDR_SPACE_MEM32		0x2
 37#define OF_PCI_ADDR_SPACE_MEM64		0x3
 38
 39#define OF_PCI_ADDR_FIELD_NONRELOC	BIT(31)
 40#define OF_PCI_ADDR_FIELD_SS		GENMASK(25, 24)
 41#define OF_PCI_ADDR_FIELD_PREFETCH	BIT(30)
 42#define OF_PCI_ADDR_FIELD_BUS		GENMASK(23, 16)
 43#define OF_PCI_ADDR_FIELD_DEV		GENMASK(15, 11)
 44#define OF_PCI_ADDR_FIELD_FUNC		GENMASK(10, 8)
 45#define OF_PCI_ADDR_FIELD_REG		GENMASK(7, 0)
 46
 47enum of_pci_prop_compatible {
 48	PROP_COMPAT_PCI_VVVV_DDDD,
 49	PROP_COMPAT_PCICLASS_CCSSPP,
 50	PROP_COMPAT_PCICLASS_CCSS,
 51	PROP_COMPAT_NUM,
 52};
 53
 54static void of_pci_set_address(struct pci_dev *pdev, u32 *prop, u64 addr,
 55			       u32 reg_num, u32 flags, bool reloc)
 56{
 57	if (pdev) {
 58		prop[0] = FIELD_PREP(OF_PCI_ADDR_FIELD_BUS, pdev->bus->number) |
 59			  FIELD_PREP(OF_PCI_ADDR_FIELD_DEV, PCI_SLOT(pdev->devfn)) |
 60			  FIELD_PREP(OF_PCI_ADDR_FIELD_FUNC, PCI_FUNC(pdev->devfn));
 61	} else
 62		prop[0] = 0;
 63
 64	prop[0] |= flags | reg_num;
 65	if (!reloc) {
 66		prop[0] |= OF_PCI_ADDR_FIELD_NONRELOC;
 67		prop[1] = upper_32_bits(addr);
 68		prop[2] = lower_32_bits(addr);
 69	}
 70}
 71
 72static int of_pci_get_addr_flags(const struct resource *res, u32 *flags)
 73{
 74	u32 ss;
 75
 76	if (res->flags & IORESOURCE_IO)
 77		ss = OF_PCI_ADDR_SPACE_IO;
 78	else if (res->flags & IORESOURCE_MEM_64)
 79		ss = OF_PCI_ADDR_SPACE_MEM64;
 80	else if (res->flags & IORESOURCE_MEM)
 81		ss = OF_PCI_ADDR_SPACE_MEM32;
 82	else
 83		return -EINVAL;
 84
 85	*flags = 0;
 86	if (res->flags & IORESOURCE_PREFETCH)
 87		*flags |= OF_PCI_ADDR_FIELD_PREFETCH;
 88
 89	*flags |= FIELD_PREP(OF_PCI_ADDR_FIELD_SS, ss);
 90
 91	return 0;
 92}
 93
 94static int of_pci_prop_bus_range(struct pci_dev *pdev,
 95				 struct of_changeset *ocs,
 96				 struct device_node *np)
 97{
 98	u32 bus_range[] = { pdev->subordinate->busn_res.start,
 99			    pdev->subordinate->busn_res.end };
100
101	return of_changeset_add_prop_u32_array(ocs, np, "bus-range", bus_range,
102					       ARRAY_SIZE(bus_range));
103}
104
105static int of_pci_prop_ranges(struct pci_dev *pdev, struct of_changeset *ocs,
106			      struct device_node *np)
107{
108	struct of_pci_range_entry *rp;
109	struct resource *res;
110	int i, j, ret;
111	u32 flags, num;
112	u64 val64;
113
114	if (pci_is_bridge(pdev)) {
115		num = PCI_BRIDGE_RESOURCE_NUM;
116		res = &pdev->resource[PCI_BRIDGE_RESOURCES];
117	} else {
118		num = PCI_STD_NUM_BARS;
119		res = &pdev->resource[PCI_STD_RESOURCES];
120	}
121
122	rp = kcalloc(num, sizeof(*rp), GFP_KERNEL);
123	if (!rp)
124		return -ENOMEM;
125
126	for (i = 0, j = 0; j < num; j++) {
127		if (!resource_size(&res[j]))
128			continue;
129
130		if (of_pci_get_addr_flags(&res[j], &flags))
131			continue;
132
133		val64 = pci_bus_address(pdev, &res[j] - pdev->resource);
134		of_pci_set_address(pdev, rp[i].parent_addr, val64, 0, flags,
135				   false);
136		if (pci_is_bridge(pdev)) {
137			memcpy(rp[i].child_addr, rp[i].parent_addr,
138			       sizeof(rp[i].child_addr));
139		} else {
140			/*
141			 * For endpoint device, the lower 64-bits of child
142			 * address is always zero.
143			 */
144			rp[i].child_addr[0] = j;
145		}
146
147		val64 = resource_size(&res[j]);
148		rp[i].size[0] = upper_32_bits(val64);
149		rp[i].size[1] = lower_32_bits(val64);
150
151		i++;
152	}
153
154	ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", (u32 *)rp,
155					      i * sizeof(*rp) / sizeof(u32));
156	kfree(rp);
157
158	return ret;
159}
160
161static int of_pci_prop_reg(struct pci_dev *pdev, struct of_changeset *ocs,
162			   struct device_node *np)
163{
164	struct of_pci_addr_pair reg = { 0 };
165
166	/* configuration space */
167	of_pci_set_address(pdev, reg.phys_addr, 0, 0, 0, true);
168
169	return of_changeset_add_prop_u32_array(ocs, np, "reg", (u32 *)&reg,
170					       sizeof(reg) / sizeof(u32));
171}
172
173static int of_pci_prop_interrupts(struct pci_dev *pdev,
174				  struct of_changeset *ocs,
175				  struct device_node *np)
176{
177	int ret;
178	u8 pin;
179
180	ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
181	if (ret != 0)
182		return ret;
183
184	if (!pin)
185		return 0;
186
187	return of_changeset_add_prop_u32(ocs, np, "interrupts", (u32)pin);
188}
189
190static int of_pci_prop_intr_ctrl(struct pci_dev *pdev, struct of_changeset *ocs,
191				 struct device_node *np)
192{
193	int ret;
194	u8 pin;
195
196	ret = pci_read_config_byte(pdev, PCI_INTERRUPT_PIN, &pin);
197	if (ret != 0)
198		return ret;
199
200	if (!pin)
201		return 0;
202
203	ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1);
204	if (ret)
205		return ret;
206
207	return of_changeset_add_prop_bool(ocs, np, "interrupt-controller");
208}
209
210static int of_pci_prop_intr_map(struct pci_dev *pdev, struct of_changeset *ocs,
211				struct device_node *np)
212{
213	u32 i, addr_sz[OF_PCI_MAX_INT_PIN] = { 0 }, map_sz = 0;
214	struct of_phandle_args out_irq[OF_PCI_MAX_INT_PIN];
215	__be32 laddr[OF_PCI_ADDRESS_CELLS] = { 0 };
216	u32 int_map_mask[] = { 0xffff00, 0, 0, 7 };
217	struct device_node *pnode;
218	struct pci_dev *child;
219	u32 *int_map, *mapp;
220	int ret;
221	u8 pin;
222
223	pnode = pci_device_to_OF_node(pdev->bus->self);
224	if (!pnode)
225		pnode = pci_bus_to_OF_node(pdev->bus);
226
227	if (!pnode) {
228		pci_err(pdev, "failed to get parent device node");
229		return -EINVAL;
230	}
231
232	laddr[0] = cpu_to_be32((pdev->bus->number << 16) | (pdev->devfn << 8));
233	for (pin = 1; pin <= OF_PCI_MAX_INT_PIN;  pin++) {
234		i = pin - 1;
235		out_irq[i].np = pnode;
236		out_irq[i].args_count = 1;
237		out_irq[i].args[0] = pin;
238		ret = of_irq_parse_raw(laddr, &out_irq[i]);
239		if (ret) {
240			out_irq[i].np = NULL;
241			pci_dbg(pdev, "parse irq %d failed, ret %d", pin, ret);
242			continue;
243		}
244		of_property_read_u32(out_irq[i].np, "#address-cells",
245				     &addr_sz[i]);
246	}
247
248	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
249		for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
250			i = pci_swizzle_interrupt_pin(child, pin) - 1;
251			if (!out_irq[i].np)
252				continue;
253			map_sz += 5 + addr_sz[i] + out_irq[i].args_count;
254		}
255	}
256
257	/*
258	 * Parsing interrupt failed for all pins. In this case, it does not
259	 * need to generate interrupt-map property.
260	 */
261	if (!map_sz)
262		return 0;
263
264	int_map = kcalloc(map_sz, sizeof(u32), GFP_KERNEL);
265	if (!int_map)
266		return -ENOMEM;
267	mapp = int_map;
268
269	list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
270		for (pin = 1; pin <= OF_PCI_MAX_INT_PIN; pin++) {
271			i = pci_swizzle_interrupt_pin(child, pin) - 1;
272			if (!out_irq[i].np)
273				continue;
274
275			*mapp = (child->bus->number << 16) |
276				(child->devfn << 8);
277			mapp += OF_PCI_ADDRESS_CELLS;
278			*mapp = pin;
279			mapp++;
280			*mapp = out_irq[i].np->phandle;
281			mapp++;
282
283			/*
284			 * A device address does not affect the device <->
285			 * interrupt-controller HW connection for all
286			 * modern interrupt controllers; moreover, the
287			 * kernel (i.e., of_irq_parse_raw()) ignores the
288			 * values in the parent unit address cells while
289			 * parsing the interrupt-map property because they
290			 * are irrelevant for interrupt mapping in modern
291			 * systems.
292			 *
293			 * Leave the parent unit address initialized to 0 --
294			 * just take into account the #address-cells size
295			 * to build the property properly.
296			 */
297			mapp += addr_sz[i];
298			memcpy(mapp, out_irq[i].args,
299			       out_irq[i].args_count * sizeof(u32));
300			mapp += out_irq[i].args_count;
301		}
302	}
303
304	ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map", int_map,
305					      map_sz);
306	if (ret)
307		goto failed;
308
309	ret = of_changeset_add_prop_u32(ocs, np, "#interrupt-cells", 1);
310	if (ret)
311		goto failed;
312
313	ret = of_changeset_add_prop_u32_array(ocs, np, "interrupt-map-mask",
314					      int_map_mask,
315					      ARRAY_SIZE(int_map_mask));
316	if (ret)
317		goto failed;
318
319	kfree(int_map);
320	return 0;
321
322failed:
323	kfree(int_map);
324	return ret;
325}
326
327static int of_pci_prop_compatible(struct pci_dev *pdev,
328				  struct of_changeset *ocs,
329				  struct device_node *np)
330{
331	const char *compat_strs[PROP_COMPAT_NUM] = { 0 };
332	int i, ret;
333
334	compat_strs[PROP_COMPAT_PCI_VVVV_DDDD] =
335		kasprintf(GFP_KERNEL, "pci%x,%x", pdev->vendor, pdev->device);
336	compat_strs[PROP_COMPAT_PCICLASS_CCSSPP] =
337		kasprintf(GFP_KERNEL, "pciclass,%06x", pdev->class);
338	compat_strs[PROP_COMPAT_PCICLASS_CCSS] =
339		kasprintf(GFP_KERNEL, "pciclass,%04x", pdev->class >> 8);
340
341	ret = of_changeset_add_prop_string_array(ocs, np, "compatible",
342						 compat_strs, PROP_COMPAT_NUM);
343	for (i = 0; i < PROP_COMPAT_NUM; i++)
344		kfree(compat_strs[i]);
345
346	return ret;
347}
348
349int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs,
350			  struct device_node *np)
351{
352	int ret;
353
354	/*
355	 * The added properties will be released when the
356	 * changeset is destroyed.
357	 */
358	if (pci_is_bridge(pdev)) {
359		ret = of_changeset_add_prop_string(ocs, np, "device_type",
360						   "pci");
361		if (ret)
362			return ret;
363
364		ret = of_pci_prop_bus_range(pdev, ocs, np);
365		if (ret)
366			return ret;
367
368		ret = of_pci_prop_intr_map(pdev, ocs, np);
369		if (ret)
370			return ret;
371	} else {
372		ret = of_pci_prop_intr_ctrl(pdev, ocs, np);
373		if (ret)
374			return ret;
375	}
376
377	ret = of_pci_prop_ranges(pdev, ocs, np);
378	if (ret)
379		return ret;
380
381	ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
382					OF_PCI_ADDRESS_CELLS);
383	if (ret)
384		return ret;
385
386	ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
387					OF_PCI_SIZE_CELLS);
388	if (ret)
389		return ret;
390
391	ret = of_pci_prop_reg(pdev, ocs, np);
392	if (ret)
393		return ret;
394
395	ret = of_pci_prop_compatible(pdev, ocs, np);
396	if (ret)
397		return ret;
398
399	ret = of_pci_prop_interrupts(pdev, ocs, np);
400	if (ret)
401		return ret;
402
403	return 0;
404}
405
406static bool of_pci_is_range_resource(const struct resource *res, u32 *flags)
407{
408	if (!(resource_type(res) & IORESOURCE_MEM) &&
409	    !(resource_type(res) & IORESOURCE_MEM_64))
410		return false;
411
412	if (of_pci_get_addr_flags(res, flags))
413		return false;
414
415	return true;
416}
417
418static int of_pci_host_bridge_prop_ranges(struct pci_host_bridge *bridge,
419					  struct of_changeset *ocs,
420					  struct device_node *np)
421{
422	struct resource_entry *window;
423	unsigned int ranges_sz = 0;
424	unsigned int n_range = 0;
425	struct resource *res;
426	int n_addr_cells;
427	u32 *ranges;
428	u64 val64;
429	u32 flags;
430	int ret;
431
432	n_addr_cells = of_n_addr_cells(np);
433	if (n_addr_cells <= 0 || n_addr_cells > 2)
434		return -EINVAL;
435
436	resource_list_for_each_entry(window, &bridge->windows) {
437		res = window->res;
438		if (!of_pci_is_range_resource(res, &flags))
439			continue;
440		n_range++;
441	}
442
443	if (!n_range)
444		return 0;
445
446	ranges = kcalloc(n_range,
447			 (OF_PCI_ADDRESS_CELLS + OF_PCI_SIZE_CELLS +
448			  n_addr_cells) * sizeof(*ranges),
449			 GFP_KERNEL);
450	if (!ranges)
451		return -ENOMEM;
452
453	resource_list_for_each_entry(window, &bridge->windows) {
454		res = window->res;
455		if (!of_pci_is_range_resource(res, &flags))
456			continue;
457
458		/* PCI bus address */
459		val64 = res->start;
460		of_pci_set_address(NULL, &ranges[ranges_sz],
461				   val64 - window->offset, 0, flags, false);
462		ranges_sz += OF_PCI_ADDRESS_CELLS;
463
464		/* Host bus address */
465		if (n_addr_cells == 2)
466			ranges[ranges_sz++] = upper_32_bits(val64);
467		ranges[ranges_sz++] = lower_32_bits(val64);
468
469		/* Size */
470		val64 = resource_size(res);
471		ranges[ranges_sz] = upper_32_bits(val64);
472		ranges[ranges_sz + 1] = lower_32_bits(val64);
473		ranges_sz += OF_PCI_SIZE_CELLS;
474	}
475
476	ret = of_changeset_add_prop_u32_array(ocs, np, "ranges", ranges,
477					      ranges_sz);
478	kfree(ranges);
479	return ret;
480}
481
482int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge,
483				      struct of_changeset *ocs,
484				      struct device_node *np)
485{
486	int ret;
487
488	ret = of_changeset_add_prop_string(ocs, np, "device_type", "pci");
489	if (ret)
490		return ret;
491
492	ret = of_changeset_add_prop_u32(ocs, np, "#address-cells",
493					OF_PCI_ADDRESS_CELLS);
494	if (ret)
495		return ret;
496
497	ret = of_changeset_add_prop_u32(ocs, np, "#size-cells",
498					OF_PCI_SIZE_CELLS);
499	if (ret)
500		return ret;
501
502	ret = of_pci_host_bridge_prop_ranges(bridge, ocs, np);
503	if (ret)
504		return ret;
505
506	return 0;
507}