pcie-xilinx-nwl.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * PCIe host controller driver for NWL PCIe Bridge
  4 * Based on pcie-xilinx.c, pci-tegra.c
  5 *
  6 * (C) Copyright 2014 - 2015, Xilinx, Inc.
  7 */
  8
  9#include <linux/clk.h>
 10#include <linux/delay.h>
 11#include <linux/interrupt.h>
 12#include <linux/irq.h>
 13#include <linux/irqchip/irq-msi-lib.h>
 14#include <linux/irqdomain.h>
 15#include <linux/kernel.h>
 16#include <linux/init.h>
 17#include <linux/msi.h>
 18#include <linux/of_address.h>
 19#include <linux/of_pci.h>
 20#include <linux/of_platform.h>
 21#include <linux/pci.h>
 22#include <linux/pci-ecam.h>
 23#include <linux/phy/phy.h>
 24#include <linux/platform_device.h>
 25#include <linux/irqchip/chained_irq.h>
 26
 27#include "../pci.h"
 28
 29/* Bridge core config registers */
 30#define BRCFG_PCIE_RX0			0x00000000
 31#define BRCFG_PCIE_RX1			0x00000004
 32#define BRCFG_INTERRUPT			0x00000010
 33#define BRCFG_PCIE_RX_MSG_FILTER	0x00000020
 34
 35/* Egress - Bridge translation registers */
 36#define E_BREG_CAPABILITIES		0x00000200
 37#define E_BREG_CONTROL			0x00000208
 38#define E_BREG_BASE_LO			0x00000210
 39#define E_BREG_BASE_HI			0x00000214
 40#define E_ECAM_CAPABILITIES		0x00000220
 41#define E_ECAM_CONTROL			0x00000228
 42#define E_ECAM_BASE_LO			0x00000230
 43#define E_ECAM_BASE_HI			0x00000234
 44
 45/* Ingress - address translations */
 46#define I_MSII_CAPABILITIES		0x00000300
 47#define I_MSII_CONTROL			0x00000308
 48#define I_MSII_BASE_LO			0x00000310
 49#define I_MSII_BASE_HI			0x00000314
 50
 51#define I_ISUB_CONTROL			0x000003E8
 52#define SET_ISUB_CONTROL		BIT(0)
 53/* Rxed msg fifo  - Interrupt status registers */
 54#define MSGF_MISC_STATUS		0x00000400
 55#define MSGF_MISC_MASK			0x00000404
 56#define MSGF_LEG_STATUS			0x00000420
 57#define MSGF_LEG_MASK			0x00000424
 58#define MSGF_MSI_STATUS_LO		0x00000440
 59#define MSGF_MSI_STATUS_HI		0x00000444
 60#define MSGF_MSI_MASK_LO		0x00000448
 61#define MSGF_MSI_MASK_HI		0x0000044C
 62
 63/* Msg filter mask bits */
 64#define CFG_ENABLE_PM_MSG_FWD		BIT(1)
 65#define CFG_ENABLE_INT_MSG_FWD		BIT(2)
 66#define CFG_ENABLE_ERR_MSG_FWD		BIT(3)
 67#define CFG_ENABLE_MSG_FILTER_MASK	(CFG_ENABLE_PM_MSG_FWD | \
 68					CFG_ENABLE_INT_MSG_FWD | \
 69					CFG_ENABLE_ERR_MSG_FWD)
 70
 71/* Misc interrupt status mask bits */
 72#define MSGF_MISC_SR_RXMSG_AVAIL	BIT(0)
 73#define MSGF_MISC_SR_RXMSG_OVER		BIT(1)
 74#define MSGF_MISC_SR_SLAVE_ERR		BIT(4)
 75#define MSGF_MISC_SR_MASTER_ERR		BIT(5)
 76#define MSGF_MISC_SR_I_ADDR_ERR		BIT(6)
 77#define MSGF_MISC_SR_E_ADDR_ERR		BIT(7)
 78#define MSGF_MISC_SR_FATAL_AER		BIT(16)
 79#define MSGF_MISC_SR_NON_FATAL_AER	BIT(17)
 80#define MSGF_MISC_SR_CORR_AER		BIT(18)
 81#define MSGF_MISC_SR_UR_DETECT		BIT(20)
 82#define MSGF_MISC_SR_NON_FATAL_DEV	BIT(22)
 83#define MSGF_MISC_SR_FATAL_DEV		BIT(23)
 84#define MSGF_MISC_SR_LINK_DOWN		BIT(24)
 85#define MSGF_MISC_SR_LINK_AUTO_BWIDTH	BIT(25)
 86#define MSGF_MISC_SR_LINK_BWIDTH	BIT(26)
 87
 88#define MSGF_MISC_SR_MASKALL		(MSGF_MISC_SR_RXMSG_AVAIL | \
 89					MSGF_MISC_SR_RXMSG_OVER | \
 90					MSGF_MISC_SR_SLAVE_ERR | \
 91					MSGF_MISC_SR_MASTER_ERR | \
 92					MSGF_MISC_SR_I_ADDR_ERR | \
 93					MSGF_MISC_SR_E_ADDR_ERR | \
 94					MSGF_MISC_SR_FATAL_AER | \
 95					MSGF_MISC_SR_NON_FATAL_AER | \
 96					MSGF_MISC_SR_CORR_AER | \
 97					MSGF_MISC_SR_UR_DETECT | \
 98					MSGF_MISC_SR_NON_FATAL_DEV | \
 99					MSGF_MISC_SR_FATAL_DEV | \
100					MSGF_MISC_SR_LINK_DOWN | \
101					MSGF_MISC_SR_LINK_AUTO_BWIDTH | \
102					MSGF_MISC_SR_LINK_BWIDTH)
103
104/* Legacy interrupt status mask bits */
105#define MSGF_LEG_SR_INTA		BIT(0)
106#define MSGF_LEG_SR_INTB		BIT(1)
107#define MSGF_LEG_SR_INTC		BIT(2)
108#define MSGF_LEG_SR_INTD		BIT(3)
109#define MSGF_LEG_SR_MASKALL		(MSGF_LEG_SR_INTA | MSGF_LEG_SR_INTB | \
110					MSGF_LEG_SR_INTC | MSGF_LEG_SR_INTD)
111
112/* MSI interrupt status mask bits */
113#define MSGF_MSI_SR_LO_MASK		GENMASK(31, 0)
114#define MSGF_MSI_SR_HI_MASK		GENMASK(31, 0)
115
116#define MSII_PRESENT			BIT(0)
117#define MSII_ENABLE			BIT(0)
118#define MSII_STATUS_ENABLE		BIT(15)
119
120/* Bridge config interrupt mask */
121#define BRCFG_INTERRUPT_MASK		BIT(0)
122#define BREG_PRESENT			BIT(0)
123#define BREG_ENABLE			BIT(0)
124#define BREG_ENABLE_FORCE		BIT(1)
125
126/* E_ECAM status mask bits */
127#define E_ECAM_PRESENT			BIT(0)
128#define E_ECAM_CR_ENABLE		BIT(0)
129#define E_ECAM_SIZE_LOC			GENMASK(20, 16)
130#define E_ECAM_SIZE_SHIFT		16
131#define NWL_ECAM_MAX_SIZE		16
132
133#define CFG_DMA_REG_BAR			GENMASK(2, 0)
134#define CFG_PCIE_CACHE			GENMASK(7, 0)
135
136#define INT_PCI_MSI_NR			(2 * 32)
137
138/* Readin the PS_LINKUP */
139#define PS_LINKUP_OFFSET		0x00000238
140#define PCIE_PHY_LINKUP_BIT		BIT(0)
141#define PHY_RDY_LINKUP_BIT		BIT(1)
142
143/* Parameters for the waiting for link up routine */
144#define LINK_WAIT_MAX_RETRIES          10
145#define LINK_WAIT_USLEEP_MIN           90000
146#define LINK_WAIT_USLEEP_MAX           100000
147
148struct nwl_msi {			/* MSI information */
149	DECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);
150	struct irq_domain *dev_domain;
151	struct mutex lock;		/* protect bitmap variable */
152	int irq_msi0;
153	int irq_msi1;
154};
155
156struct nwl_pcie {
157	struct device *dev;
158	void __iomem *breg_base;
159	void __iomem *pcireg_base;
160	void __iomem *ecam_base;
161	struct phy *phy[4];
162	phys_addr_t phys_breg_base;	/* Physical Bridge Register Base */
163	phys_addr_t phys_pcie_reg_base;	/* Physical PCIe Controller Base */
164	phys_addr_t phys_ecam_base;	/* Physical Configuration Base */
165	u32 breg_size;
166	u32 pcie_reg_size;
167	u32 ecam_size;
168	int irq_intx;
169	int irq_misc;
170	struct nwl_msi msi;
171	struct irq_domain *intx_irq_domain;
172	struct clk *clk;
173	raw_spinlock_t leg_mask_lock;
174};
175
176static inline u32 nwl_bridge_readl(struct nwl_pcie *pcie, u32 off)
177{
178	return readl(pcie->breg_base + off);
179}
180
181static inline void nwl_bridge_writel(struct nwl_pcie *pcie, u32 val, u32 off)
182{
183	writel(val, pcie->breg_base + off);
184}
185
186static bool nwl_pcie_link_up(struct nwl_pcie *pcie)
187{
188	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PCIE_PHY_LINKUP_BIT)
189		return true;
190	return false;
191}
192
193static bool nwl_phy_link_up(struct nwl_pcie *pcie)
194{
195	if (readl(pcie->pcireg_base + PS_LINKUP_OFFSET) & PHY_RDY_LINKUP_BIT)
196		return true;
197	return false;
198}
199
200static int nwl_wait_for_link(struct nwl_pcie *pcie)
201{
202	struct device *dev = pcie->dev;
203	int retries;
204
205	/* check if the link is up or not */
206	for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
207		if (nwl_phy_link_up(pcie))
208			return 0;
209		usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
210	}
211
212	dev_err(dev, "PHY link never came up\n");
213	return -ETIMEDOUT;
214}
215
216static bool nwl_pcie_valid_device(struct pci_bus *bus, unsigned int devfn)
217{
218	struct nwl_pcie *pcie = bus->sysdata;
219
220	/* Check link before accessing downstream ports */
221	if (!pci_is_root_bus(bus)) {
222		if (!nwl_pcie_link_up(pcie))
223			return false;
224	} else if (devfn > 0)
225		/* Only one device down on each root port */
226		return false;
227
228	return true;
229}
230
231/**
232 * nwl_pcie_map_bus - Get configuration base
233 *
234 * @bus: Bus structure of current bus
235 * @devfn: Device/function
236 * @where: Offset from base
237 *
238 * Return: Base address of the configuration space needed to be
239 *	   accessed.
240 */
241static void __iomem *nwl_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
242				      int where)
243{
244	struct nwl_pcie *pcie = bus->sysdata;
245
246	if (!nwl_pcie_valid_device(bus, devfn))
247		return NULL;
248
249	return pcie->ecam_base + PCIE_ECAM_OFFSET(bus->number, devfn, where);
250}
251
252/* PCIe operations */
253static struct pci_ops nwl_pcie_ops = {
254	.map_bus = nwl_pcie_map_bus,
255	.read  = pci_generic_config_read,
256	.write = pci_generic_config_write,
257};
258
259static irqreturn_t nwl_pcie_misc_handler(int irq, void *data)
260{
261	struct nwl_pcie *pcie = data;
262	struct device *dev = pcie->dev;
263	u32 misc_stat;
264
265	/* Checking for misc interrupts */
266	misc_stat = nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
267				     MSGF_MISC_SR_MASKALL;
268	if (!misc_stat)
269		return IRQ_NONE;
270
271	if (misc_stat & MSGF_MISC_SR_RXMSG_OVER)
272		dev_err_ratelimited(dev, "Received Message FIFO Overflow\n");
273
274	if (misc_stat & MSGF_MISC_SR_SLAVE_ERR)
275		dev_err_ratelimited(dev, "Slave error\n");
276
277	if (misc_stat & MSGF_MISC_SR_MASTER_ERR)
278		dev_err_ratelimited(dev, "Master error\n");
279
280	if (misc_stat & MSGF_MISC_SR_I_ADDR_ERR)
281		dev_err_ratelimited(dev, "In Misc Ingress address translation error\n");
282
283	if (misc_stat & MSGF_MISC_SR_E_ADDR_ERR)
284		dev_err_ratelimited(dev, "In Misc Egress address translation error\n");
285
286	if (misc_stat & MSGF_MISC_SR_FATAL_AER)
287		dev_err_ratelimited(dev, "Fatal Error in AER Capability\n");
288
289	if (misc_stat & MSGF_MISC_SR_NON_FATAL_AER)
290		dev_err_ratelimited(dev, "Non-Fatal Error in AER Capability\n");
291
292	if (misc_stat & MSGF_MISC_SR_CORR_AER)
293		dev_err_ratelimited(dev, "Correctable Error in AER Capability\n");
294
295	if (misc_stat & MSGF_MISC_SR_UR_DETECT)
296		dev_err_ratelimited(dev, "Unsupported request Detected\n");
297
298	if (misc_stat & MSGF_MISC_SR_NON_FATAL_DEV)
299		dev_err_ratelimited(dev, "Non-Fatal Error Detected\n");
300
301	if (misc_stat & MSGF_MISC_SR_FATAL_DEV)
302		dev_err_ratelimited(dev, "Fatal Error Detected\n");
303
304	if (misc_stat & MSGF_MISC_SR_LINK_AUTO_BWIDTH)
305		dev_info(dev, "Link Autonomous Bandwidth Management Status bit set\n");
306
307	if (misc_stat & MSGF_MISC_SR_LINK_BWIDTH)
308		dev_info(dev, "Link Bandwidth Management Status bit set\n");
309
310	/* Clear misc interrupt status */
311	nwl_bridge_writel(pcie, misc_stat, MSGF_MISC_STATUS);
312
313	return IRQ_HANDLED;
314}
315
316static void nwl_pcie_leg_handler(struct irq_desc *desc)
317{
318	struct irq_chip *chip = irq_desc_get_chip(desc);
319	struct nwl_pcie *pcie;
320	unsigned long status;
321	u32 bit;
322
323	chained_irq_enter(chip, desc);
324	pcie = irq_desc_get_handler_data(desc);
325
326	while ((status = nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
327				MSGF_LEG_SR_MASKALL) != 0) {
328		for_each_set_bit(bit, &status, PCI_NUM_INTX)
329			generic_handle_domain_irq(pcie->intx_irq_domain, bit);
330	}
331
332	chained_irq_exit(chip, desc);
333}
334
335static void nwl_pcie_handle_msi_irq(struct nwl_pcie *pcie, u32 status_reg)
336{
337	struct nwl_msi *msi = &pcie->msi;
338	unsigned long status;
339	u32 bit;
340
341	while ((status = nwl_bridge_readl(pcie, status_reg)) != 0) {
342		for_each_set_bit(bit, &status, 32) {
343			nwl_bridge_writel(pcie, 1 << bit, status_reg);
344			generic_handle_domain_irq(msi->dev_domain, bit);
345		}
346	}
347}
348
349static void nwl_pcie_msi_handler_high(struct irq_desc *desc)
350{
351	struct irq_chip *chip = irq_desc_get_chip(desc);
352	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
353
354	chained_irq_enter(chip, desc);
355	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_HI);
356	chained_irq_exit(chip, desc);
357}
358
359static void nwl_pcie_msi_handler_low(struct irq_desc *desc)
360{
361	struct irq_chip *chip = irq_desc_get_chip(desc);
362	struct nwl_pcie *pcie = irq_desc_get_handler_data(desc);
363
364	chained_irq_enter(chip, desc);
365	nwl_pcie_handle_msi_irq(pcie, MSGF_MSI_STATUS_LO);
366	chained_irq_exit(chip, desc);
367}
368
369static void nwl_mask_intx_irq(struct irq_data *data)
370{
371	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
372	unsigned long flags;
373	u32 mask;
374	u32 val;
375
376	mask = 1 << data->hwirq;
377	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
378	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
379	nwl_bridge_writel(pcie, (val & (~mask)), MSGF_LEG_MASK);
380	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
381}
382
383static void nwl_unmask_intx_irq(struct irq_data *data)
384{
385	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
386	unsigned long flags;
387	u32 mask;
388	u32 val;
389
390	mask = 1 << data->hwirq;
391	raw_spin_lock_irqsave(&pcie->leg_mask_lock, flags);
392	val = nwl_bridge_readl(pcie, MSGF_LEG_MASK);
393	nwl_bridge_writel(pcie, (val | mask), MSGF_LEG_MASK);
394	raw_spin_unlock_irqrestore(&pcie->leg_mask_lock, flags);
395}
396
397static struct irq_chip nwl_intx_irq_chip = {
398	.name = "nwl_pcie:legacy",
399	.irq_enable = nwl_unmask_intx_irq,
400	.irq_disable = nwl_mask_intx_irq,
401	.irq_mask = nwl_mask_intx_irq,
402	.irq_unmask = nwl_unmask_intx_irq,
403};
404
405static int nwl_intx_map(struct irq_domain *domain, unsigned int irq,
406			irq_hw_number_t hwirq)
407{
408	irq_set_chip_and_handler(irq, &nwl_intx_irq_chip, handle_level_irq);
409	irq_set_chip_data(irq, domain->host_data);
410	irq_set_status_flags(irq, IRQ_LEVEL);
411
412	return 0;
413}
414
415static const struct irq_domain_ops intx_domain_ops = {
416	.map = nwl_intx_map,
417	.xlate = pci_irqd_intx_xlate,
418};
419
420#ifdef CONFIG_PCI_MSI
421
422#define NWL_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS	| \
423				MSI_FLAG_USE_DEF_CHIP_OPS	| \
424				MSI_FLAG_NO_AFFINITY)
425
426#define NWL_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK		| \
427				 MSI_FLAG_MULTI_PCI_MSI)
428
429static const struct msi_parent_ops nwl_msi_parent_ops = {
430	.required_flags		= NWL_MSI_FLAGS_REQUIRED,
431	.supported_flags	= NWL_MSI_FLAGS_SUPPORTED,
432	.bus_select_token	= DOMAIN_BUS_PCI_MSI,
433	.prefix			= "nwl-",
434	.init_dev_msi_info	= msi_lib_init_dev_msi_info,
435};
436
437#endif
438
439static void nwl_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
440{
441	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
442	phys_addr_t msi_addr = pcie->phys_pcie_reg_base;
443
444	msg->address_lo = lower_32_bits(msi_addr);
445	msg->address_hi = upper_32_bits(msi_addr);
446	msg->data = data->hwirq;
447}
448
449static struct irq_chip nwl_irq_chip = {
450	.name = "Xilinx MSI",
451	.irq_compose_msi_msg = nwl_compose_msi_msg,
452};
453
454static int nwl_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
455				unsigned int nr_irqs, void *args)
456{
457	struct nwl_pcie *pcie = domain->host_data;
458	struct nwl_msi *msi = &pcie->msi;
459	int bit;
460	int i;
461
462	mutex_lock(&msi->lock);
463	bit = bitmap_find_free_region(msi->bitmap, INT_PCI_MSI_NR,
464				      get_count_order(nr_irqs));
465	if (bit < 0) {
466		mutex_unlock(&msi->lock);
467		return -ENOSPC;
468	}
469
470	for (i = 0; i < nr_irqs; i++) {
471		irq_domain_set_info(domain, virq + i, bit + i, &nwl_irq_chip,
472				    domain->host_data, handle_simple_irq,
473				    NULL, NULL);
474	}
475	mutex_unlock(&msi->lock);
476	return 0;
477}
478
479static void nwl_irq_domain_free(struct irq_domain *domain, unsigned int virq,
480				unsigned int nr_irqs)
481{
482	struct irq_data *data = irq_domain_get_irq_data(domain, virq);
483	struct nwl_pcie *pcie = irq_data_get_irq_chip_data(data);
484	struct nwl_msi *msi = &pcie->msi;
485
486	mutex_lock(&msi->lock);
487	bitmap_release_region(msi->bitmap, data->hwirq,
488			      get_count_order(nr_irqs));
489	mutex_unlock(&msi->lock);
490}
491
492static const struct irq_domain_ops dev_msi_domain_ops = {
493	.alloc  = nwl_irq_domain_alloc,
494	.free   = nwl_irq_domain_free,
495};
496
497static int nwl_pcie_init_msi_irq_domain(struct nwl_pcie *pcie)
498{
499#ifdef CONFIG_PCI_MSI
500	struct device *dev = pcie->dev;
501	struct nwl_msi *msi = &pcie->msi;
502	struct irq_domain_info info = {
503		.fwnode		= dev_fwnode(dev),
504		.ops		= &dev_msi_domain_ops,
505		.host_data	= pcie,
506		.size		= INT_PCI_MSI_NR,
507	};
508
509	msi->dev_domain  = msi_create_parent_irq_domain(&info, &nwl_msi_parent_ops);
510	if (!msi->dev_domain) {
511		dev_err(dev, "failed to create dev IRQ domain\n");
512		return -ENOMEM;
513	}
514#endif
515	return 0;
516}
517
518static void nwl_pcie_phy_power_off(struct nwl_pcie *pcie, int i)
519{
520	int err = phy_power_off(pcie->phy[i]);
521
522	if (err)
523		dev_err(pcie->dev, "could not power off phy %d (err=%d)\n", i,
524			err);
525}
526
527static void nwl_pcie_phy_exit(struct nwl_pcie *pcie, int i)
528{
529	int err = phy_exit(pcie->phy[i]);
530
531	if (err)
532		dev_err(pcie->dev, "could not exit phy %d (err=%d)\n", i, err);
533}
534
535static int nwl_pcie_phy_enable(struct nwl_pcie *pcie)
536{
537	int i, ret;
538
539	for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
540		ret = phy_init(pcie->phy[i]);
541		if (ret)
542			goto err;
543
544		ret = phy_power_on(pcie->phy[i]);
545		if (ret) {
546			nwl_pcie_phy_exit(pcie, i);
547			goto err;
548		}
549	}
550
551	return 0;
552
553err:
554	while (i--) {
555		nwl_pcie_phy_power_off(pcie, i);
556		nwl_pcie_phy_exit(pcie, i);
557	}
558
559	return ret;
560}
561
562static void nwl_pcie_phy_disable(struct nwl_pcie *pcie)
563{
564	int i;
565
566	for (i = ARRAY_SIZE(pcie->phy); i--;) {
567		nwl_pcie_phy_power_off(pcie, i);
568		nwl_pcie_phy_exit(pcie, i);
569	}
570}
571
572static int nwl_pcie_init_irq_domain(struct nwl_pcie *pcie)
573{
574	struct device *dev = pcie->dev;
575	struct device_node *node = dev->of_node;
576	struct device_node *intc_node;
577
578	intc_node = of_get_next_child(node, NULL);
579	if (!intc_node) {
580		dev_err(dev, "No legacy intc node found\n");
581		return -EINVAL;
582	}
583
584	pcie->intx_irq_domain = irq_domain_create_linear(of_fwnode_handle(intc_node), PCI_NUM_INTX,
585							 &intx_domain_ops, pcie);
586	of_node_put(intc_node);
587	if (!pcie->intx_irq_domain) {
588		dev_err(dev, "failed to create IRQ domain\n");
589		return -ENOMEM;
590	}
591
592	raw_spin_lock_init(&pcie->leg_mask_lock);
593	nwl_pcie_init_msi_irq_domain(pcie);
594	return 0;
595}
596
597static int nwl_pcie_enable_msi(struct nwl_pcie *pcie)
598{
599	struct device *dev = pcie->dev;
600	struct platform_device *pdev = to_platform_device(dev);
601	struct nwl_msi *msi = &pcie->msi;
602	unsigned long base;
603	int ret;
604
605	mutex_init(&msi->lock);
606
607	/* Get msi_1 IRQ number */
608	msi->irq_msi1 = platform_get_irq_byname(pdev, "msi1");
609	if (msi->irq_msi1 < 0)
610		return -EINVAL;
611
612	irq_set_chained_handler_and_data(msi->irq_msi1,
613					 nwl_pcie_msi_handler_high, pcie);
614
615	/* Get msi_0 IRQ number */
616	msi->irq_msi0 = platform_get_irq_byname(pdev, "msi0");
617	if (msi->irq_msi0 < 0)
618		return -EINVAL;
619
620	irq_set_chained_handler_and_data(msi->irq_msi0,
621					 nwl_pcie_msi_handler_low, pcie);
622
623	/* Check for msii_present bit */
624	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
625	if (!ret) {
626		dev_err(dev, "MSI not present\n");
627		return -EIO;
628	}
629
630	/* Enable MSII */
631	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
632			  MSII_ENABLE, I_MSII_CONTROL);
633
634	/* Enable MSII status */
635	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
636			  MSII_STATUS_ENABLE, I_MSII_CONTROL);
637
638	/* setup AFI/FPCI range */
639	base = pcie->phys_pcie_reg_base;
640	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
641	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);
642
643	/*
644	 * For high range MSI interrupts: disable, clear any pending,
645	 * and enable
646	 */
647	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_HI);
648
649	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie,  MSGF_MSI_STATUS_HI) &
650			  MSGF_MSI_SR_HI_MASK, MSGF_MSI_STATUS_HI);
651
652	nwl_bridge_writel(pcie, MSGF_MSI_SR_HI_MASK, MSGF_MSI_MASK_HI);
653
654	/*
655	 * For low range MSI interrupts: disable, clear any pending,
656	 * and enable
657	 */
658	nwl_bridge_writel(pcie, 0, MSGF_MSI_MASK_LO);
659
660	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MSI_STATUS_LO) &
661			  MSGF_MSI_SR_LO_MASK, MSGF_MSI_STATUS_LO);
662
663	nwl_bridge_writel(pcie, MSGF_MSI_SR_LO_MASK, MSGF_MSI_MASK_LO);
664
665	return 0;
666}
667
668static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)
669{
670	struct device *dev = pcie->dev;
671	struct platform_device *pdev = to_platform_device(dev);
672	u32 breg_val, ecam_val;
673	int err;
674
675	breg_val = nwl_bridge_readl(pcie, E_BREG_CAPABILITIES) & BREG_PRESENT;
676	if (!breg_val) {
677		dev_err(dev, "BREG is not present\n");
678		return breg_val;
679	}
680
681	/* Write bridge_off to breg base */
682	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_breg_base),
683			  E_BREG_BASE_LO);
684	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_breg_base),
685			  E_BREG_BASE_HI);
686
687	/* Enable BREG */
688	nwl_bridge_writel(pcie, ~BREG_ENABLE_FORCE & BREG_ENABLE,
689			  E_BREG_CONTROL);
690
691	/* Disable DMA channel registers */
692	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX0) |
693			  CFG_DMA_REG_BAR, BRCFG_PCIE_RX0);
694
695	/* Enable Ingress subtractive decode translation */
696	nwl_bridge_writel(pcie, SET_ISUB_CONTROL, I_ISUB_CONTROL);
697
698	/* Enable msg filtering details */
699	nwl_bridge_writel(pcie, CFG_ENABLE_MSG_FILTER_MASK,
700			  BRCFG_PCIE_RX_MSG_FILTER);
701
702	/* This routes the PCIe DMA traffic to go through CCI path */
703	if (of_dma_is_coherent(dev->of_node))
704		nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_PCIE_RX1) |
705				  CFG_PCIE_CACHE, BRCFG_PCIE_RX1);
706
707	err = nwl_wait_for_link(pcie);
708	if (err)
709		return err;
710
711	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CAPABILITIES) & E_ECAM_PRESENT;
712	if (!ecam_val) {
713		dev_err(dev, "ECAM is not present\n");
714		return ecam_val;
715	}
716
717	/* Enable ECAM */
718	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, E_ECAM_CONTROL) |
719			  E_ECAM_CR_ENABLE, E_ECAM_CONTROL);
720
721	ecam_val = nwl_bridge_readl(pcie, E_ECAM_CONTROL);
722	ecam_val &= ~E_ECAM_SIZE_LOC;
723	ecam_val |= NWL_ECAM_MAX_SIZE << E_ECAM_SIZE_SHIFT;
724	nwl_bridge_writel(pcie, ecam_val, E_ECAM_CONTROL);
725
726	nwl_bridge_writel(pcie, lower_32_bits(pcie->phys_ecam_base),
727			  E_ECAM_BASE_LO);
728	nwl_bridge_writel(pcie, upper_32_bits(pcie->phys_ecam_base),
729			  E_ECAM_BASE_HI);
730
731	if (nwl_pcie_link_up(pcie))
732		dev_info(dev, "Link is UP\n");
733	else
734		dev_info(dev, "Link is DOWN\n");
735
736	/* Get misc IRQ number */
737	pcie->irq_misc = platform_get_irq_byname(pdev, "misc");
738	if (pcie->irq_misc < 0)
739		return -EINVAL;
740
741	err = devm_request_irq(dev, pcie->irq_misc,
742			       nwl_pcie_misc_handler, IRQF_SHARED,
743			       "nwl_pcie:misc", pcie);
744	if (err) {
745		dev_err(dev, "fail to register misc IRQ#%d\n",
746			pcie->irq_misc);
747		return err;
748	}
749
750	/* Disable all misc interrupts */
751	nwl_bridge_writel(pcie, (u32)~MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
752
753	/* Clear pending misc interrupts */
754	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_MISC_STATUS) &
755			  MSGF_MISC_SR_MASKALL, MSGF_MISC_STATUS);
756
757	/* Enable all misc interrupts */
758	nwl_bridge_writel(pcie, MSGF_MISC_SR_MASKALL, MSGF_MISC_MASK);
759
760	/* Disable all INTX interrupts */
761	nwl_bridge_writel(pcie, (u32)~MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
762
763	/* Clear pending INTX interrupts */
764	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &
765			  MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);
766
767	/* Enable all INTX interrupts */
768	nwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);
769
770	/* Enable the bridge config interrupt */
771	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, BRCFG_INTERRUPT) |
772			  BRCFG_INTERRUPT_MASK, BRCFG_INTERRUPT);
773
774	return 0;
775}
776
777static int nwl_pcie_parse_dt(struct nwl_pcie *pcie,
778			     struct platform_device *pdev)
779{
780	struct device *dev = pcie->dev;
781	struct resource *res;
782	int i;
783
784	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "breg");
785	pcie->breg_base = devm_ioremap_resource(dev, res);
786	if (IS_ERR(pcie->breg_base))
787		return PTR_ERR(pcie->breg_base);
788	pcie->phys_breg_base = res->start;
789
790	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcireg");
791	pcie->pcireg_base = devm_ioremap_resource(dev, res);
792	if (IS_ERR(pcie->pcireg_base))
793		return PTR_ERR(pcie->pcireg_base);
794	pcie->phys_pcie_reg_base = res->start;
795
796	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
797	pcie->ecam_base = devm_pci_remap_cfg_resource(dev, res);
798	if (IS_ERR(pcie->ecam_base))
799		return PTR_ERR(pcie->ecam_base);
800	pcie->phys_ecam_base = res->start;
801
802	/* Get intx IRQ number */
803	pcie->irq_intx = platform_get_irq_byname(pdev, "intx");
804	if (pcie->irq_intx < 0)
805		return pcie->irq_intx;
806
807	irq_set_chained_handler_and_data(pcie->irq_intx,
808					 nwl_pcie_leg_handler, pcie);
809
810
811	for (i = 0; i < ARRAY_SIZE(pcie->phy); i++) {
812		pcie->phy[i] = devm_of_phy_get_by_index(dev, dev->of_node, i);
813		if (PTR_ERR(pcie->phy[i]) == -ENODEV) {
814			pcie->phy[i] = NULL;
815			break;
816		}
817
818		if (IS_ERR(pcie->phy[i]))
819			return PTR_ERR(pcie->phy[i]);
820	}
821
822	return 0;
823}
824
825static const struct of_device_id nwl_pcie_of_match[] = {
826	{ .compatible = "xlnx,nwl-pcie-2.11", },
827	{}
828};
829
830static int nwl_pcie_probe(struct platform_device *pdev)
831{
832	struct device *dev = &pdev->dev;
833	struct nwl_pcie *pcie;
834	struct pci_host_bridge *bridge;
835	int err;
836
837	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
838	if (!bridge)
839		return -ENODEV;
840
841	pcie = pci_host_bridge_priv(bridge);
842	platform_set_drvdata(pdev, pcie);
843
844	pcie->dev = dev;
845
846	err = nwl_pcie_parse_dt(pcie, pdev);
847	if (err) {
848		dev_err(dev, "Parsing DT failed\n");
849		return err;
850	}
851
852	pcie->clk = devm_clk_get(dev, NULL);
853	if (IS_ERR(pcie->clk))
854		return PTR_ERR(pcie->clk);
855
856	err = clk_prepare_enable(pcie->clk);
857	if (err) {
858		dev_err(dev, "can't enable PCIe ref clock\n");
859		return err;
860	}
861
862	err = nwl_pcie_phy_enable(pcie);
863	if (err) {
864		dev_err(dev, "could not enable PHYs\n");
865		goto err_clk;
866	}
867
868	err = nwl_pcie_bridge_init(pcie);
869	if (err) {
870		dev_err(dev, "HW Initialization failed\n");
871		goto err_phy;
872	}
873
874	err = nwl_pcie_init_irq_domain(pcie);
875	if (err) {
876		dev_err(dev, "Failed creating IRQ Domain\n");
877		goto err_phy;
878	}
879
880	bridge->sysdata = pcie;
881	bridge->ops = &nwl_pcie_ops;
882
883	if (IS_ENABLED(CONFIG_PCI_MSI)) {
884		err = nwl_pcie_enable_msi(pcie);
885		if (err < 0) {
886			dev_err(dev, "failed to enable MSI support: %d\n", err);
887			goto err_phy;
888		}
889	}
890
891	err = pci_host_probe(bridge);
892	if (!err)
893		return 0;
894
895err_phy:
896	nwl_pcie_phy_disable(pcie);
897err_clk:
898	clk_disable_unprepare(pcie->clk);
899	return err;
900}
901
902static void nwl_pcie_remove(struct platform_device *pdev)
903{
904	struct nwl_pcie *pcie = platform_get_drvdata(pdev);
905
906	nwl_pcie_phy_disable(pcie);
907	clk_disable_unprepare(pcie->clk);
908}
909
910static struct platform_driver nwl_pcie_driver = {
911	.driver = {
912		.name = "nwl-pcie",
913		.suppress_bind_attrs = true,
914		.of_match_table = nwl_pcie_of_match,
915	},
916	.probe = nwl_pcie_probe,
917	.remove = nwl_pcie_remove,
918};
919builtin_platform_driver(nwl_pcie_driver);