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pcie-rzg3s-host.c
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linux-6.19.14/drivers/pci/controller/pcie-rzg3s-host.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe driver for Renesas RZ/G3S SoCs 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 * 7 * Based on: 8 * drivers/pci/controller/pcie-rcar-host.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 */ 11 12#include <linux/bitfield.h> 13#include <linux/bitmap.h> 14#include <linux/bitops.h> 15#include <linux/cleanup.h> 16#include <linux/clk.h> 17#include <linux/delay.h> 18#include <linux/iopoll.h> 19#include <linux/interrupt.h> 20#include <linux/irq.h> 21#include <linux/irqchip/chained_irq.h> 22#include <linux/irqchip/irq-msi-lib.h> 23#include <linux/irqdomain.h> 24#include <linux/kernel.h> 25#include <linux/mfd/syscon.h> 26#include <linux/mutex.h> 27#include <linux/msi.h> 28#include <linux/of_irq.h> 29#include <linux/pci.h> 30#include <linux/platform_device.h> 31#include <linux/pm_runtime.h> 32#include <linux/regmap.h> 33#include <linux/reset.h> 34#include <linux/sizes.h> 35#include <linux/slab.h> 36#include <linux/units.h> 37 38#include "../pci.h" 39 40/* AXI registers */ 41#define RZG3S_PCI_REQDATA(id) (0x80 + (id) * 0x4) 42#define RZG3S_PCI_REQRCVDAT 0x8c 43 44#define RZG3S_PCI_REQADR1 0x90 45#define RZG3S_PCI_REQADR1_BUS GENMASK(31, 24) 46#define RZG3S_PCI_REQADR1_DEV GENMASK(23, 19) 47#define RZG3S_PCI_REQADR1_FUNC GENMASK(18, 16) 48#define RZG3S_PCI_REQADR1_REG GENMASK(11, 0) 49 50#define RZG3S_PCI_REQBE 0x98 51#define RZG3S_PCI_REQBE_BYTE_EN GENMASK(3, 0) 52 53#define RZG3S_PCI_REQISS 0x9c 54#define RZG3S_PCI_REQISS_MOR_STATUS GENMASK(18, 16) 55#define RZG3S_PCI_REQISS_TR_TYPE GENMASK(11, 8) 56#define RZG3S_PCI_REQISS_TR_TP0_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x4) 57#define RZG3S_PCI_REQISS_TR_TP0_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x5) 58#define RZG3S_PCI_REQISS_TR_TP1_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x6) 59#define RZG3S_PCI_REQISS_TR_TP1_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0x7) 60#define RZG3S_PCI_REQISS_REQ_ISSUE BIT(0) 61 62#define RZG3S_PCI_MSIRCVWADRL 0x100 63#define RZG3S_PCI_MSIRCVWADRL_MASK GENMASK(31, 3) 64#define RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA BIT(1) 65#define RZG3S_PCI_MSIRCVWADRL_ENA BIT(0) 66 67#define RZG3S_PCI_MSIRCVWADRU 0x104 68 69#define RZG3S_PCI_MSIRCVWMSKL 0x108 70#define RZG3S_PCI_MSIRCVWMSKL_MASK GENMASK(31, 2) 71 72#define RZG3S_PCI_PINTRCVIE 0x110 73#define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i) 74#define RZG3S_PCI_PINTRCVIE_MSI BIT(4) 75 76#define RZG3S_PCI_PINTRCVIS 0x114 77#define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i) 78#define RZG3S_PCI_PINTRCVIS_MSI BIT(4) 79 80#define RZG3S_PCI_MSGRCVIE 0x120 81#define RZG3S_PCI_MSGRCVIE_MSG_RCV BIT(24) 82 83#define RZG3S_PCI_MSGRCVIS 0x124 84#define RZG3S_PCI_MSGRCVIS_MRI BIT(24) 85 86#define RZG3S_PCI_PEIE0 0x200 87 88#define RZG3S_PCI_PEIS0 0x204 89#define RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER BIT(12) 90#define RZG3S_PCI_PEIS0_DL_UPDOWN BIT(9) 91 92#define RZG3S_PCI_PEIE1 0x208 93#define RZG3S_PCI_PEIS1 0x20c 94#define RZG3S_PCI_AMEIS 0x214 95#define RZG3S_PCI_ASEIS1 0x224 96 97#define RZG3S_PCI_PCSTAT1 0x408 98#define RZG3S_PCI_PCSTAT1_LTSSM_STATE GENMASK(14, 10) 99#define RZG3S_PCI_PCSTAT1_DL_DOWN_STS BIT(0) 100 101#define RZG3S_PCI_PCCTRL2 0x410 102#define RZG3S_PCI_PCCTRL2_LS_CHG GENMASK(9, 8) 103#define RZG3S_PCI_PCCTRL2_LS_CHG_REQ BIT(0) 104 105#define RZG3S_PCI_PCSTAT2 0x414 106#define RZG3S_PCI_PCSTAT2_LS_CHG_DONE BIT(28) 107#define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 1) 108 109#define RZG3S_PCI_PERM 0x300 110#define RZG3S_PCI_PERM_CFG_HWINIT_EN BIT(2) 111#define RZG3S_PCI_PERM_PIPE_PHY_REG_EN BIT(1) 112 113#define RZG3S_PCI_MSIRE(id) (0x600 + (id) * 0x10) 114#define RZG3S_PCI_MSIRE_ENA BIT(0) 115 116#define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10) 117#define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10) 118 119#define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20) 120#define RZG3S_PCI_AWBASEL_WIN_ENA BIT(0) 121 122#define RZG3S_PCI_AWBASEU(id) (0x1004 + (id) * 0x20) 123#define RZG3S_PCI_AWMASKL(id) (0x1008 + (id) * 0x20) 124#define RZG3S_PCI_AWMASKU(id) (0x100c + (id) * 0x20) 125#define RZG3S_PCI_ADESTL(id) (0x1010 + (id) * 0x20) 126#define RZG3S_PCI_ADESTU(id) (0x1014 + (id) * 0x20) 127 128#define RZG3S_PCI_PWBASEL(id) (0x1100 + (id) * 0x20) 129#define RZG3S_PCI_PWBASEL_ENA BIT(0) 130 131#define RZG3S_PCI_PWBASEU(id) (0x1104 + (id) * 0x20) 132#define RZG3S_PCI_PDESTL(id) (0x1110 + (id) * 0x20) 133#define RZG3S_PCI_PDESTU(id) (0x1114 + (id) * 0x20) 134#define RZG3S_PCI_PWMASKL(id) (0x1108 + (id) * 0x20) 135#define RZG3S_PCI_PWMASKU(id) (0x110c + (id) * 0x20) 136 137/* PHY control registers */ 138#define RZG3S_PCI_PHY_XCFGD(id) (0x2000 + (id) * 0x10) 139#define RZG3S_PCI_PHY_XCFGD_NUM 39 140 141#define RZG3S_PCI_PHY_XCFGA_CMN(id) (0x2400 + (id) * 0x10) 142#define RZG3S_PCI_PHY_XCFGA_CMN_NUM 16 143 144#define RZG3S_PCI_PHY_XCFGA_RX(id) (0x2500 + (id) * 0x10) 145#define RZG3S_PCI_PHY_XCFGA_RX_NUM 13 146 147#define RZG3S_PCI_PHY_XCFGA_TX 0x25d0 148 149#define RZG3S_PCI_PHY_XCFG_CTRL 0x2a20 150#define RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL BIT(0) 151 152/* PCIe registers */ 153#define RZG3S_PCI_CFG_BASE 0x6000 154#define RZG3S_PCI_CFG_BARMSK00L 0xa0 155#define RZG3S_PCI_CFG_BARMSK00U 0xa4 156 157#define RZG3S_PCI_CFG_PCIEC 0x60 158 159/* System controller registers */ 160#define RZG3S_SYS_PCIE_RST_RSM_B 0xd74 161#define RZG3S_SYS_PCIE_RST_RSM_B_MASK BIT(0) 162 163/* Maximum number of windows */ 164#define RZG3S_MAX_WINDOWS 8 165 166/* Number of MSI interrupts per register */ 167#define RZG3S_PCI_MSI_INT_PER_REG 32 168/* The number of MSI interrupts */ 169#define RZG3S_PCI_MSI_INT_NR RZG3S_PCI_MSI_INT_PER_REG 170 171/* Timeouts experimentally determined */ 172#define RZG3S_REQ_ISSUE_TIMEOUT_US 2500 173 174/** 175 * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure 176 * @domain: IRQ domain 177 * @map: bitmap with the allocated MSIs 178 * @dma_addr: address of the allocated MSI window 179 * @window_base: base address of the MSI window 180 * @pages: allocated pages for MSI window mapping 181 * @map_lock: lock for bitmap with the allocated MSIs 182 * @irq: MSI interrupt 183 */ 184struct rzg3s_pcie_msi { 185 struct irq_domain *domain; 186 DECLARE_BITMAP(map, RZG3S_PCI_MSI_INT_NR); 187 dma_addr_t dma_addr; 188 dma_addr_t window_base; 189 unsigned long pages; 190 struct mutex map_lock; 191 int irq; 192}; 193 194struct rzg3s_pcie_host; 195 196/** 197 * struct rzg3s_pcie_soc_data - SoC specific data 198 * @init_phy: PHY initialization function 199 * @power_resets: array with the resets that need to be de-asserted after 200 * power-on 201 * @cfg_resets: array with the resets that need to be de-asserted after 202 * configuration 203 * @num_power_resets: number of power resets 204 * @num_cfg_resets: number of configuration resets 205 */ 206struct rzg3s_pcie_soc_data { 207 int (*init_phy)(struct rzg3s_pcie_host *host); 208 const char * const *power_resets; 209 const char * const *cfg_resets; 210 u8 num_power_resets; 211 u8 num_cfg_resets; 212}; 213 214/** 215 * struct rzg3s_pcie_port - RZ/G3S PCIe Root Port data structure 216 * @refclk: PCIe reference clock 217 * @vendor_id: Vendor ID 218 * @device_id: Device ID 219 */ 220struct rzg3s_pcie_port { 221 struct clk *refclk; 222 u32 vendor_id; 223 u32 device_id; 224}; 225 226/** 227 * struct rzg3s_pcie_host - RZ/G3S PCIe data structure 228 * @axi: base address for AXI registers 229 * @pcie: base address for PCIe registers 230 * @dev: struct device 231 * @power_resets: reset control signals that should be set after power up 232 * @cfg_resets: reset control signals that should be set after configuration 233 * @sysc: SYSC regmap 234 * @intx_domain: INTx IRQ domain 235 * @data: SoC specific data 236 * @msi: MSI data structure 237 * @port: PCIe Root Port 238 * @hw_lock: lock for access to the HW resources 239 * @intx_irqs: INTx interrupts 240 * @max_link_speed: maximum supported link speed 241 */ 242struct rzg3s_pcie_host { 243 void __iomem *axi; 244 void __iomem *pcie; 245 struct device *dev; 246 struct reset_control_bulk_data *power_resets; 247 struct reset_control_bulk_data *cfg_resets; 248 struct regmap *sysc; 249 struct irq_domain *intx_domain; 250 const struct rzg3s_pcie_soc_data *data; 251 struct rzg3s_pcie_msi msi; 252 struct rzg3s_pcie_port port; 253 raw_spinlock_t hw_lock; 254 int intx_irqs[PCI_NUM_INTX]; 255 int max_link_speed; 256}; 257 258#define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host, msi) 259 260static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mask, 261 u32 val) 262{ 263 u32 tmp; 264 265 tmp = readl_relaxed(base + offset); 266 tmp &= ~mask; 267 tmp |= val & mask; 268 writel_relaxed(tmp, base + offset); 269} 270 271static int rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host) 272{ 273 u32 val; 274 int ret; 275 276 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS, 277 RZG3S_PCI_REQISS_REQ_ISSUE, 278 RZG3S_PCI_REQISS_REQ_ISSUE); 279 ret = readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val, 280 !(val & RZG3S_PCI_REQISS_REQ_ISSUE), 281 5, RZG3S_REQ_ISSUE_TIMEOUT_US); 282 283 if (val & RZG3S_PCI_REQISS_MOR_STATUS) 284 return -EIO; 285 286 return ret; 287} 288 289static void rzg3s_pcie_child_prepare_bus(struct pci_bus *bus, 290 unsigned int devfn, int where) 291{ 292 struct rzg3s_pcie_host *host = bus->sysdata; 293 unsigned int dev, func, reg; 294 295 dev = PCI_SLOT(devfn); 296 func = PCI_FUNC(devfn); 297 reg = where & ~0x3; 298 299 /* Set the destination */ 300 writel_relaxed(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) | 301 FIELD_PREP(RZG3S_PCI_REQADR1_DEV, dev) | 302 FIELD_PREP(RZG3S_PCI_REQADR1_FUNC, func) | 303 FIELD_PREP(RZG3S_PCI_REQADR1_REG, reg), 304 host->axi + RZG3S_PCI_REQADR1); 305 306 /* Set byte enable */ 307 writel_relaxed(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE); 308} 309 310static int rzg3s_pcie_child_read_conf(struct rzg3s_pcie_host *host, 311 struct pci_bus *bus, unsigned int devfn, 312 int where, u32 *data) 313{ 314 bool type0 = pci_is_root_bus(bus->parent) ? true : false; 315 int ret; 316 317 rzg3s_pcie_child_prepare_bus(bus, devfn, where); 318 319 /* Set the type of request */ 320 writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_RD : 321 RZG3S_PCI_REQISS_TR_TP1_RD, 322 host->axi + RZG3S_PCI_REQISS); 323 324 /* Issue the request and wait to finish */ 325 ret = rzg3s_pcie_child_issue_request(host); 326 if (ret) 327 return PCIBIOS_SET_FAILED; 328 329 /* Read the data */ 330 *data = readl_relaxed(host->axi + RZG3S_PCI_REQRCVDAT); 331 332 return PCIBIOS_SUCCESSFUL; 333} 334 335/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 336static int rzg3s_pcie_child_read(struct pci_bus *bus, unsigned int devfn, 337 int where, int size, u32 *val) 338{ 339 struct rzg3s_pcie_host *host = bus->sysdata; 340 int ret; 341 342 ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, val); 343 if (ret != PCIBIOS_SUCCESSFUL) 344 return ret; 345 346 if (size <= 2) 347 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); 348 349 return PCIBIOS_SUCCESSFUL; 350} 351 352static int rzg3s_pcie_child_write_conf(struct rzg3s_pcie_host *host, 353 struct pci_bus *bus, unsigned int devfn, 354 int where, u32 data) 355{ 356 bool type0 = pci_is_root_bus(bus->parent) ? true : false; 357 int ret; 358 359 rzg3s_pcie_child_prepare_bus(bus, devfn, where); 360 361 /* Set the write data */ 362 writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(0)); 363 writel_relaxed(0, host->axi + RZG3S_PCI_REQDATA(1)); 364 writel_relaxed(data, host->axi + RZG3S_PCI_REQDATA(2)); 365 366 /* Set the type of request */ 367 writel_relaxed(type0 ? RZG3S_PCI_REQISS_TR_TP0_WR : 368 RZG3S_PCI_REQISS_TR_TP1_WR, 369 host->axi + RZG3S_PCI_REQISS); 370 371 /* Issue the request and wait to finish */ 372 ret = rzg3s_pcie_child_issue_request(host); 373 if (ret) 374 return PCIBIOS_SET_FAILED; 375 376 return PCIBIOS_SUCCESSFUL; 377} 378 379/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 380static int rzg3s_pcie_child_write(struct pci_bus *bus, unsigned int devfn, 381 int where, int size, u32 val) 382{ 383 struct rzg3s_pcie_host *host = bus->sysdata; 384 u32 data, shift; 385 int ret; 386 387 if (size == 4) 388 return rzg3s_pcie_child_write_conf(host, bus, devfn, where, val); 389 390 /* 391 * Controller does 32 bit accesses. To do byte accesses software need 392 * to do read/modify/write. This may have potential side effects. For 393 * example, software may perform a 16-bit write. If the hardware only 394 * supports 32-bit accesses, we must do a 32-bit read, merge in the 16 395 * bits we intend to write, followed by a 32-bit write. If the 16 bits 396 * we *don't* intend to write happen to have any RW1C 397 * (write-one-to-clear) bits set, we just inadvertently cleared 398 * something we shouldn't have. 399 */ 400 if (!bus->unsafe_warn) { 401 dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#x may corrupt adjacent RW1C bits\n", 402 size, pci_domain_nr(bus), bus->number, 403 PCI_SLOT(devfn), PCI_FUNC(devfn), where); 404 bus->unsafe_warn = 1; 405 } 406 407 ret = rzg3s_pcie_child_read_conf(host, bus, devfn, where, &data); 408 if (ret != PCIBIOS_SUCCESSFUL) 409 return ret; 410 411 if (size == 1) { 412 shift = BITS_PER_BYTE * (where & 3); 413 data &= ~(0xff << shift); 414 data |= ((val & 0xff) << shift); 415 } else if (size == 2) { 416 shift = BITS_PER_BYTE * (where & 2); 417 data &= ~(0xffff << shift); 418 data |= ((val & 0xffff) << shift); 419 } else { 420 data = val; 421 } 422 423 return rzg3s_pcie_child_write_conf(host, bus, devfn, where, data); 424} 425 426static struct pci_ops rzg3s_pcie_child_ops = { 427 .read = rzg3s_pcie_child_read, 428 .write = rzg3s_pcie_child_write, 429}; 430 431static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus, 432 unsigned int devfn, int where) 433{ 434 struct rzg3s_pcie_host *host = bus->sysdata; 435 436 if (devfn) 437 return NULL; 438 439 return host->pcie + where; 440} 441 442static struct pci_ops rzg3s_pcie_root_ops = { 443 .read = pci_generic_config_read, 444 .write = pci_generic_config_write, 445 .map_bus = rzg3s_pcie_root_map_bus, 446}; 447 448static void rzg3s_pcie_intx_irq_handler(struct irq_desc *desc) 449{ 450 struct rzg3s_pcie_host *host = irq_desc_get_handler_data(desc); 451 struct irq_chip *chip = irq_desc_get_chip(desc); 452 unsigned int irq = irq_desc_get_irq(desc); 453 u32 intx = irq - host->intx_irqs[0]; 454 455 chained_irq_enter(chip, desc); 456 generic_handle_domain_irq(host->intx_domain, intx); 457 chained_irq_exit(chip, desc); 458} 459 460static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data) 461{ 462 u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; 463 DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR) = {0}; 464 struct rzg3s_pcie_host *host = data; 465 struct rzg3s_pcie_msi *msi = &host->msi; 466 unsigned long bit; 467 u32 status; 468 469 status = readl_relaxed(host->axi + RZG3S_PCI_PINTRCVIS); 470 if (!(status & RZG3S_PCI_PINTRCVIS_MSI)) 471 return IRQ_NONE; 472 473 /* Clear the MSI */ 474 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, 475 RZG3S_PCI_PINTRCVIS_MSI, 476 RZG3S_PCI_PINTRCVIS_MSI); 477 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS, 478 RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI); 479 480 for (u8 reg_id = 0; reg_id < regs; reg_id++) { 481 status = readl_relaxed(host->axi + RZG3S_PCI_MSIRS(reg_id)); 482 bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG, 483 RZG3S_PCI_MSI_INT_PER_REG); 484 } 485 486 for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) { 487 int ret; 488 489 ret = generic_handle_domain_irq(msi->domain, bit); 490 if (ret) { 491 u8 reg_bit = bit % RZG3S_PCI_MSI_INT_PER_REG; 492 u8 reg_id = bit / RZG3S_PCI_MSI_INT_PER_REG; 493 494 /* Unknown MSI, just clear it */ 495 writel_relaxed(BIT(reg_bit), 496 host->axi + RZG3S_PCI_MSIRS(reg_id)); 497 } 498 } 499 500 return IRQ_HANDLED; 501} 502 503static void rzg3s_pcie_msi_irq_ack(struct irq_data *d) 504{ 505 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); 506 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 507 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; 508 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; 509 510 guard(raw_spinlock_irqsave)(&host->hw_lock); 511 512 writel_relaxed(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); 513} 514 515static void rzg3s_pcie_msi_irq_mask(struct irq_data *d) 516{ 517 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); 518 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 519 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; 520 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; 521 522 guard(raw_spinlock_irqsave)(&host->hw_lock); 523 524 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), 525 BIT(reg_bit)); 526} 527 528static void rzg3s_pcie_msi_irq_unmask(struct irq_data *d) 529{ 530 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(d); 531 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 532 u8 reg_bit = d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; 533 u8 reg_id = d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; 534 535 guard(raw_spinlock_irqsave)(&host->hw_lock); 536 537 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), 538 0); 539} 540 541static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data, 542 struct msi_msg *msg) 543{ 544 struct rzg3s_pcie_msi *msi = irq_data_get_irq_chip_data(data); 545 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 546 u32 lo, hi; 547 548 /* 549 * Enable and msg data enable bits are part of the address lo. Drop 550 * them along with the unused bit. 551 */ 552 lo = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRL) & 553 RZG3S_PCI_MSIRCVWADRL_MASK; 554 hi = readl_relaxed(host->axi + RZG3S_PCI_MSIRCVWADRU); 555 556 msg->address_lo = lo; 557 msg->address_hi = hi; 558 msg->data = data->hwirq; 559} 560 561static struct irq_chip rzg3s_pcie_msi_bottom_chip = { 562 .name = "rzg3s-pcie-msi", 563 .irq_ack = rzg3s_pcie_msi_irq_ack, 564 .irq_mask = rzg3s_pcie_msi_irq_mask, 565 .irq_unmask = rzg3s_pcie_msi_irq_unmask, 566 .irq_compose_msi_msg = rzg3s_pcie_irq_compose_msi_msg, 567}; 568 569static int rzg3s_pcie_msi_domain_alloc(struct irq_domain *domain, 570 unsigned int virq, unsigned int nr_irqs, 571 void *args) 572{ 573 struct rzg3s_pcie_msi *msi = domain->host_data; 574 int hwirq; 575 576 scoped_guard(mutex, &msi->map_lock) { 577 hwirq = bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR, 578 order_base_2(nr_irqs)); 579 } 580 581 if (hwirq < 0) 582 return -ENOSPC; 583 584 for (unsigned int i = 0; i < nr_irqs; i++) { 585 irq_domain_set_info(domain, virq + i, hwirq + i, 586 &rzg3s_pcie_msi_bottom_chip, 587 domain->host_data, handle_edge_irq, NULL, 588 NULL); 589 } 590 591 return 0; 592} 593 594static void rzg3s_pcie_msi_domain_free(struct irq_domain *domain, 595 unsigned int virq, unsigned int nr_irqs) 596{ 597 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 598 struct rzg3s_pcie_msi *msi = domain->host_data; 599 600 guard(mutex)(&msi->map_lock); 601 602 bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs)); 603} 604 605static const struct irq_domain_ops rzg3s_pcie_msi_domain_ops = { 606 .alloc = rzg3s_pcie_msi_domain_alloc, 607 .free = rzg3s_pcie_msi_domain_free, 608}; 609 610#define RZG3S_PCIE_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 611 MSI_FLAG_USE_DEF_CHIP_OPS | \ 612 MSI_FLAG_NO_AFFINITY | \ 613 MSI_FLAG_PCI_MSI_MASK_PARENT) 614 615#define RZG3S_PCIE_MSI_FLAGS_SUPPORTED (MSI_FLAG_MULTI_PCI_MSI | \ 616 MSI_GENERIC_FLAGS_MASK) 617 618static const struct msi_parent_ops rzg3s_pcie_msi_parent_ops = { 619 .required_flags = RZG3S_PCIE_MSI_FLAGS_REQUIRED, 620 .supported_flags = RZG3S_PCIE_MSI_FLAGS_SUPPORTED, 621 .bus_select_token = DOMAIN_BUS_PCI_MSI, 622 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 623 .prefix = "RZG3S-", 624 .init_dev_msi_info = msi_lib_init_dev_msi_info, 625}; 626 627static int rzg3s_pcie_msi_allocate_domains(struct rzg3s_pcie_msi *msi) 628{ 629 struct rzg3s_pcie_host *host = rzg3s_msi_to_host(msi); 630 struct device *dev = host->dev; 631 struct irq_domain_info info = { 632 .fwnode = dev_fwnode(dev), 633 .ops = &rzg3s_pcie_msi_domain_ops, 634 .size = RZG3S_PCI_MSI_INT_NR, 635 .host_data = msi, 636 }; 637 638 msi->domain = msi_create_parent_irq_domain(&info, 639 &rzg3s_pcie_msi_parent_ops); 640 if (!msi->domain) 641 return dev_err_probe(dev, -ENOMEM, 642 "failed to create IRQ domain\n"); 643 644 return 0; 645} 646 647static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host) 648{ 649 u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; 650 struct rzg3s_pcie_msi *msi = &host->msi; 651 652 /* 653 * Set MSI window size. HW will set the window to 654 * RZG3S_PCI_MSI_INT_NR * 4 bytes. 655 */ 656 writel_relaxed(FIELD_PREP(RZG3S_PCI_MSIRCVWMSKL_MASK, 657 RZG3S_PCI_MSI_INT_NR - 1), 658 host->axi + RZG3S_PCI_MSIRCVWMSKL); 659 660 /* Set MSI window address and enable MSI window */ 661 writel_relaxed(upper_32_bits(msi->window_base), 662 host->axi + RZG3S_PCI_MSIRCVWADRU); 663 writel_relaxed(lower_32_bits(msi->window_base) | 664 RZG3S_PCI_MSIRCVWADRL_ENA | 665 RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA, 666 host->axi + RZG3S_PCI_MSIRCVWADRL); 667 668 /* Set MSI receive enable */ 669 for (u8 reg_id = 0; reg_id < regs; reg_id++) { 670 writel_relaxed(RZG3S_PCI_MSIRE_ENA, 671 host->axi + RZG3S_PCI_MSIRE(reg_id)); 672 } 673 674 /* Enable message receive interrupts */ 675 writel_relaxed(RZG3S_PCI_MSGRCVIE_MSG_RCV, 676 host->axi + RZG3S_PCI_MSGRCVIE); 677 678 /* Enable MSI */ 679 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 680 RZG3S_PCI_PINTRCVIE_MSI, 681 RZG3S_PCI_PINTRCVIE_MSI); 682 683 return 0; 684} 685 686static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host) 687{ 688 size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32); 689 struct rzg3s_pcie_msi *msi = &host->msi; 690 struct device *dev = host->dev; 691 int id, ret; 692 693 msi->pages = __get_free_pages(GFP_KERNEL | GFP_DMA, 0); 694 if (!msi->pages) 695 return -ENOMEM; 696 697 msi->dma_addr = dma_map_single(dev, (void *)msi->pages, size * 2, 698 DMA_BIDIRECTIONAL); 699 if (dma_mapping_error(dev, msi->dma_addr)) { 700 ret = -ENOMEM; 701 goto free_pages; 702 } 703 704 /* 705 * According to the RZ/G3S HW manual (Rev.1.10, section 34.4.5.2 Setting 706 * the MSI Window) the MSI window needs to fall within one of the 707 * enabled AXI windows. Find an enabled AXI window to setup the MSI 708 * window. 709 */ 710 for (id = 0; id < RZG3S_MAX_WINDOWS; id++) { 711 u64 base, basel, baseu; 712 u64 mask, maskl, masku; 713 714 basel = readl_relaxed(host->axi + RZG3S_PCI_AWBASEL(id)); 715 /* Skip checking this AXI window if it's not enabled */ 716 if (!(basel & RZG3S_PCI_AWBASEL_WIN_ENA)) 717 continue; 718 719 baseu = readl_relaxed(host->axi + RZG3S_PCI_AWBASEU(id)); 720 base = baseu << 32 | basel; 721 722 maskl = readl_relaxed(host->axi + RZG3S_PCI_AWMASKL(id)); 723 masku = readl_relaxed(host->axi + RZG3S_PCI_AWMASKU(id)); 724 mask = masku << 32 | maskl; 725 726 if (msi->dma_addr < base || msi->dma_addr > base + mask) 727 continue; 728 729 break; 730 } 731 732 if (id == RZG3S_MAX_WINDOWS) { 733 ret = -EINVAL; 734 goto dma_unmap; 735 } 736 737 /* The MSI base address must be aligned to the MSI size */ 738 msi->window_base = ALIGN(msi->dma_addr, size); 739 if (msi->window_base < msi->dma_addr) { 740 ret = -EINVAL; 741 goto dma_unmap; 742 } 743 744 rzg3s_pcie_msi_hw_setup(host); 745 746 return 0; 747 748dma_unmap: 749 dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); 750free_pages: 751 free_pages(msi->pages, 0); 752 return ret; 753} 754 755static void rzg3s_pcie_msi_hw_teardown(struct rzg3s_pcie_host *host) 756{ 757 u8 regs = RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; 758 759 /* Disable MSI */ 760 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 761 RZG3S_PCI_PINTRCVIE_MSI, 0); 762 763 /* Disable message receive interrupts */ 764 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE, 765 RZG3S_PCI_MSGRCVIE_MSG_RCV, 0); 766 767 /* Disable MSI receive enable */ 768 for (u8 reg_id = 0; reg_id < regs; reg_id++) 769 writel_relaxed(0, host->axi + RZG3S_PCI_MSIRE(reg_id)); 770 771 /* Disable MSI window */ 772 writel_relaxed(0, host->axi + RZG3S_PCI_MSIRCVWADRL); 773} 774 775static void rzg3s_pcie_teardown_msi(struct rzg3s_pcie_host *host) 776{ 777 size_t size = RZG3S_PCI_MSI_INT_NR * sizeof(u32); 778 struct rzg3s_pcie_msi *msi = &host->msi; 779 780 rzg3s_pcie_msi_hw_teardown(host); 781 782 free_irq(msi->irq, host); 783 irq_domain_remove(msi->domain); 784 785 /* Free unused memory */ 786 dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); 787 free_pages(msi->pages, 0); 788} 789 790static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host) 791{ 792 struct platform_device *pdev = to_platform_device(host->dev); 793 struct rzg3s_pcie_msi *msi = &host->msi; 794 struct device *dev = host->dev; 795 const char *devname; 796 int ret; 797 798 ret = devm_mutex_init(dev, &msi->map_lock); 799 if (ret) 800 return ret; 801 802 msi->irq = platform_get_irq_byname(pdev, "msi"); 803 if (msi->irq < 0) 804 return dev_err_probe(dev, msi->irq, "Failed to get MSI IRQ!\n"); 805 806 devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev)); 807 if (!devname) 808 return -ENOMEM; 809 810 ret = rzg3s_pcie_msi_allocate_domains(msi); 811 if (ret) 812 return ret; 813 814 /* 815 * Don't use devm_request_irq() as the driver uses non-devm helpers 816 * to control clocks. Mixing them may lead to subtle bugs. 817 */ 818 ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host); 819 if (ret) { 820 dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret); 821 goto free_domains; 822 } 823 824 ret = rzg3s_pcie_msi_setup(host); 825 if (ret) { 826 dev_err_probe(dev, ret, "Failed to setup MSI!\n"); 827 goto free_irq; 828 } 829 830 return 0; 831 832free_irq: 833 free_irq(msi->irq, host); 834free_domains: 835 irq_domain_remove(msi->domain); 836 return ret; 837} 838 839static void rzg3s_pcie_intx_irq_ack(struct irq_data *d) 840{ 841 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); 842 843 guard(raw_spinlock_irqsave)(&host->hw_lock); 844 845 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, 846 RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), 847 RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); 848} 849 850static void rzg3s_pcie_intx_irq_mask(struct irq_data *d) 851{ 852 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); 853 854 guard(raw_spinlock_irqsave)(&host->hw_lock); 855 856 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 857 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 0); 858} 859 860static void rzg3s_pcie_intx_irq_unmask(struct irq_data *d) 861{ 862 struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d); 863 864 guard(raw_spinlock_irqsave)(&host->hw_lock); 865 866 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, 867 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 868 RZG3S_PCI_PINTRCVIE_INTX(d->hwirq)); 869} 870 871static struct irq_chip rzg3s_pcie_intx_irq_chip = { 872 .name = "PCIe INTx", 873 .irq_ack = rzg3s_pcie_intx_irq_ack, 874 .irq_mask = rzg3s_pcie_intx_irq_mask, 875 .irq_unmask = rzg3s_pcie_intx_irq_unmask, 876}; 877 878static int rzg3s_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 879 irq_hw_number_t hwirq) 880{ 881 irq_set_chip_and_handler(irq, &rzg3s_pcie_intx_irq_chip, 882 handle_level_irq); 883 irq_set_chip_data(irq, domain->host_data); 884 885 return 0; 886} 887 888static const struct irq_domain_ops rzg3s_pcie_intx_domain_ops = { 889 .map = rzg3s_pcie_intx_map, 890 .xlate = irq_domain_xlate_onetwocell, 891}; 892 893static int rzg3s_pcie_init_irqdomain(struct rzg3s_pcie_host *host) 894{ 895 struct device *dev = host->dev; 896 struct platform_device *pdev = to_platform_device(dev); 897 898 for (int i = 0; i < PCI_NUM_INTX; i++) { 899 char irq_name[5] = {0}; 900 int irq; 901 902 scnprintf(irq_name, ARRAY_SIZE(irq_name), "int%c", 'a' + i); 903 904 irq = platform_get_irq_byname(pdev, irq_name); 905 if (irq < 0) 906 return dev_err_probe(dev, -EINVAL, 907 "Failed to parse and map INT%c IRQ\n", 908 'A' + i); 909 910 host->intx_irqs[i] = irq; 911 irq_set_chained_handler_and_data(irq, 912 rzg3s_pcie_intx_irq_handler, 913 host); 914 } 915 916 host->intx_domain = irq_domain_create_linear(dev_fwnode(dev), 917 PCI_NUM_INTX, 918 &rzg3s_pcie_intx_domain_ops, 919 host); 920 if (!host->intx_domain) 921 return dev_err_probe(dev, -EINVAL, 922 "Failed to add irq domain for INTx IRQs\n"); 923 irq_domain_update_bus_token(host->intx_domain, DOMAIN_BUS_WIRED); 924 925 if (IS_ENABLED(CONFIG_PCI_MSI)) { 926 int ret = rzg3s_pcie_init_msi(host); 927 928 if (ret) { 929 irq_domain_remove(host->intx_domain); 930 return ret; 931 } 932 } 933 934 return 0; 935} 936 937static void rzg3s_pcie_teardown_irqdomain(struct rzg3s_pcie_host *host) 938{ 939 if (IS_ENABLED(CONFIG_PCI_MSI)) 940 rzg3s_pcie_teardown_msi(host); 941 942 irq_domain_remove(host->intx_domain); 943} 944 945static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) 946{ 947 u32 remote_supported_link_speeds, max_supported_link_speeds; 948 u32 cs2, tmp, pcie_cap = RZG3S_PCI_CFG_PCIEC; 949 u32 cur_link_speed, link_speed; 950 u8 ltssm_state_l0 = 0xc; 951 int ret; 952 u16 ls; 953 954 /* 955 * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution 956 * when Changing the Speed Spontaneously) link speed change can be done 957 * only when the LTSSM is in L0. 958 */ 959 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, tmp, 960 FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp) == ltssm_state_l0, 961 PCIE_LINK_WAIT_SLEEP_MS * MILLI, 962 PCIE_LINK_WAIT_SLEEP_MS * MILLI * 963 PCIE_LINK_WAIT_MAX_RETRIES); 964 if (ret) 965 return ret; 966 967 ls = readw_relaxed(host->pcie + pcie_cap + PCI_EXP_LNKSTA); 968 cs2 = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); 969 970 switch (pcie_link_speed[host->max_link_speed]) { 971 case PCIE_SPEED_5_0GT: 972 max_supported_link_speeds = GENMASK(PCI_EXP_LNKSTA_CLS_5_0GB - 1, 0); 973 link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; 974 break; 975 default: 976 /* Should not happen */ 977 return -EINVAL; 978 } 979 980 cur_link_speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, ls); 981 remote_supported_link_speeds = FIELD_GET(RZG3S_PCI_PCSTAT2_SDRIRE, cs2); 982 /* Drop reserved bits */ 983 remote_supported_link_speeds &= max_supported_link_speeds; 984 985 /* 986 * Return if max link speed is already set or the connected device 987 * doesn't support it. 988 */ 989 if (cur_link_speed == host->max_link_speed || 990 remote_supported_link_speeds != max_supported_link_speeds) 991 return 0; 992 993 /* Set target Link speed */ 994 rzg3s_pcie_update_bits(host->pcie, pcie_cap + PCI_EXP_LNKCTL2, 995 PCI_EXP_LNKCTL2_TLS, 996 FIELD_PREP(PCI_EXP_LNKCTL2_TLS, link_speed)); 997 998 /* Request link speed change */ 999 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, 1000 RZG3S_PCI_PCCTRL2_LS_CHG_REQ | 1001 RZG3S_PCI_PCCTRL2_LS_CHG, 1002 RZG3S_PCI_PCCTRL2_LS_CHG_REQ | 1003 FIELD_PREP(RZG3S_PCI_PCCTRL2_LS_CHG, 1004 link_speed - 1)); 1005 1006 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT2, cs2, 1007 (cs2 & RZG3S_PCI_PCSTAT2_LS_CHG_DONE), 1008 PCIE_LINK_WAIT_SLEEP_MS * MILLI, 1009 PCIE_LINK_WAIT_SLEEP_MS * MILLI * 1010 PCIE_LINK_WAIT_MAX_RETRIES); 1011 1012 /* 1013 * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution 1014 * when Changing the Speed Spontaneously) the PCI_PCCTRL2_LS_CHG_REQ 1015 * should be de-asserted after checking for PCI_PCSTAT2_LS_CHG_DONE. 1016 */ 1017 rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, 1018 RZG3S_PCI_PCCTRL2_LS_CHG_REQ, 0); 1019 1020 return ret; 1021} 1022 1023static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) 1024{ 1025 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 1026 struct resource_entry *ft; 1027 struct resource *bus; 1028 u8 subordinate_bus; 1029 u8 secondary_bus; 1030 u8 primary_bus; 1031 1032 ft = resource_list_first_type(&bridge->windows, IORESOURCE_BUS); 1033 if (!ft) 1034 return -ENODEV; 1035 1036 bus = ft->res; 1037 primary_bus = bus->start; 1038 secondary_bus = bus->start + 1; 1039 subordinate_bus = bus->end; 1040 1041 /* Enable access control to the CFGU */ 1042 writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, 1043 host->axi + RZG3S_PCI_PERM); 1044 1045 /* HW manual recommends to write 0xffffffff on initialization */ 1046 writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); 1047 writel_relaxed(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); 1048 1049 /* Disable access control to the CFGU */ 1050 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 1051 1052 /* Update bus info */ 1053 writeb_relaxed(primary_bus, host->pcie + PCI_PRIMARY_BUS); 1054 writeb_relaxed(secondary_bus, host->pcie + PCI_SECONDARY_BUS); 1055 writeb_relaxed(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS); 1056 1057 return 0; 1058} 1059 1060static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host) 1061{ 1062 /* 1063 * According to the HW manual of the RZ/G3S (Rev.1.10, sections 1064 * corresponding to all registers written with ~0U), the hardware 1065 * ignores value written to unused bits. Writing ~0U to these registers 1066 * should be safe. 1067 */ 1068 1069 /* Clear the link state and PM transitions */ 1070 writel_relaxed(RZG3S_PCI_PEIS0_DL_UPDOWN | 1071 RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER, 1072 host->axi + RZG3S_PCI_PEIS0); 1073 1074 /* Disable all interrupts */ 1075 writel_relaxed(0, host->axi + RZG3S_PCI_PEIE0); 1076 1077 /* Clear all parity and ecc error interrupts */ 1078 writel_relaxed(~0U, host->axi + RZG3S_PCI_PEIS1); 1079 1080 /* Disable all parity and ecc error interrupts */ 1081 writel_relaxed(0, host->axi + RZG3S_PCI_PEIE1); 1082 1083 /* Clear all AXI master error interrupts */ 1084 writel_relaxed(~0U, host->axi + RZG3S_PCI_AMEIS); 1085 1086 /* Clear all AXI slave error interrupts */ 1087 writel_relaxed(~0U, host->axi + RZG3S_PCI_ASEIS1); 1088 1089 /* Clear all message receive interrupts */ 1090 writel_relaxed(~0U, host->axi + RZG3S_PCI_MSGRCVIS); 1091} 1092 1093static int rzg3s_pcie_power_resets_deassert(struct rzg3s_pcie_host *host) 1094{ 1095 const struct rzg3s_pcie_soc_data *data = host->data; 1096 1097 /* 1098 * According to the RZ/G3S HW manual (Rev.1.10, section 1099 * 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from 1100 * power on to the de-assertion of reset. 1101 */ 1102 fsleep(5000); 1103 return reset_control_bulk_deassert(data->num_power_resets, 1104 host->power_resets); 1105} 1106 1107static int rzg3s_pcie_resets_prepare_and_get(struct rzg3s_pcie_host *host) 1108{ 1109 const struct rzg3s_pcie_soc_data *data = host->data; 1110 unsigned int i; 1111 int ret; 1112 1113 host->power_resets = devm_kmalloc_array(host->dev, 1114 data->num_power_resets, 1115 sizeof(*host->power_resets), 1116 GFP_KERNEL); 1117 if (!host->power_resets) 1118 return -ENOMEM; 1119 1120 for (i = 0; i < data->num_power_resets; i++) 1121 host->power_resets[i].id = data->power_resets[i]; 1122 1123 host->cfg_resets = devm_kmalloc_array(host->dev, 1124 data->num_cfg_resets, 1125 sizeof(*host->cfg_resets), 1126 GFP_KERNEL); 1127 if (!host->cfg_resets) 1128 return -ENOMEM; 1129 1130 for (i = 0; i < data->num_cfg_resets; i++) 1131 host->cfg_resets[i].id = data->cfg_resets[i]; 1132 1133 ret = devm_reset_control_bulk_get_exclusive(host->dev, 1134 data->num_power_resets, 1135 host->power_resets); 1136 if (ret) 1137 return ret; 1138 1139 return devm_reset_control_bulk_get_exclusive(host->dev, 1140 data->num_cfg_resets, 1141 host->cfg_resets); 1142} 1143 1144static int rzg3s_pcie_host_parse_port(struct rzg3s_pcie_host *host) 1145{ 1146 struct device_node *of_port __free(device_node) = 1147 of_get_next_child(host->dev->of_node, NULL); 1148 struct rzg3s_pcie_port *port = &host->port; 1149 int ret; 1150 1151 ret = of_property_read_u32(of_port, "vendor-id", &port->vendor_id); 1152 if (ret) 1153 return ret; 1154 1155 ret = of_property_read_u32(of_port, "device-id", &port->device_id); 1156 if (ret) 1157 return ret; 1158 1159 port->refclk = of_clk_get_by_name(of_port, "ref"); 1160 if (IS_ERR(port->refclk)) 1161 return PTR_ERR(port->refclk); 1162 1163 return 0; 1164} 1165 1166static int rzg3s_pcie_host_init_port(struct rzg3s_pcie_host *host) 1167{ 1168 struct rzg3s_pcie_port *port = &host->port; 1169 struct device *dev = host->dev; 1170 int ret; 1171 1172 /* Enable access control to the CFGU */ 1173 writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN, 1174 host->axi + RZG3S_PCI_PERM); 1175 1176 /* Update vendor ID and device ID */ 1177 writew_relaxed(port->vendor_id, host->pcie + PCI_VENDOR_ID); 1178 writew_relaxed(port->device_id, host->pcie + PCI_DEVICE_ID); 1179 1180 /* Disable access control to the CFGU */ 1181 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 1182 1183 ret = clk_prepare_enable(port->refclk); 1184 if (ret) 1185 return dev_err_probe(dev, ret, "Failed to enable refclk!\n"); 1186 1187 /* Set the PHY, if any */ 1188 if (host->data->init_phy) { 1189 ret = host->data->init_phy(host); 1190 if (ret) { 1191 dev_err_probe(dev, ret, "Failed to set the PHY!\n"); 1192 goto refclk_disable; 1193 } 1194 } 1195 1196 return 0; 1197 1198refclk_disable: 1199 clk_disable_unprepare(port->refclk); 1200 return ret; 1201} 1202 1203static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host) 1204{ 1205 u32 val; 1206 int ret; 1207 1208 /* Initialize the PCIe related registers */ 1209 ret = rzg3s_pcie_config_init(host); 1210 if (ret) 1211 return ret; 1212 1213 ret = rzg3s_pcie_host_init_port(host); 1214 if (ret) 1215 return ret; 1216 1217 /* Initialize the interrupts */ 1218 rzg3s_pcie_irq_init(host); 1219 1220 ret = reset_control_bulk_deassert(host->data->num_cfg_resets, 1221 host->cfg_resets); 1222 if (ret) 1223 goto disable_port_refclk; 1224 1225 /* Wait for link up */ 1226 ret = readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val, 1227 !(val & RZG3S_PCI_PCSTAT1_DL_DOWN_STS), 1228 PCIE_LINK_WAIT_SLEEP_MS * MILLI, 1229 PCIE_LINK_WAIT_SLEEP_MS * MILLI * 1230 PCIE_LINK_WAIT_MAX_RETRIES); 1231 if (ret) 1232 goto cfg_resets_deassert; 1233 1234 val = readl_relaxed(host->axi + RZG3S_PCI_PCSTAT2); 1235 dev_info(host->dev, "PCIe link status [0x%x]\n", val); 1236 1237 return 0; 1238 1239cfg_resets_deassert: 1240 reset_control_bulk_assert(host->data->num_cfg_resets, 1241 host->cfg_resets); 1242disable_port_refclk: 1243 clk_disable_unprepare(host->port.refclk); 1244 return ret; 1245} 1246 1247static void rzg3s_pcie_set_inbound_window(struct rzg3s_pcie_host *host, 1248 u64 cpu_addr, u64 pci_addr, u64 size, 1249 int id) 1250{ 1251 /* Set CPU window base address */ 1252 writel_relaxed(upper_32_bits(cpu_addr), 1253 host->axi + RZG3S_PCI_ADESTU(id)); 1254 writel_relaxed(lower_32_bits(cpu_addr), 1255 host->axi + RZG3S_PCI_ADESTL(id)); 1256 1257 /* Set window size */ 1258 writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id)); 1259 writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id)); 1260 1261 /* Set PCIe window base address and enable the window */ 1262 writel_relaxed(upper_32_bits(pci_addr), 1263 host->axi + RZG3S_PCI_AWBASEU(id)); 1264 writel_relaxed(lower_32_bits(pci_addr) | RZG3S_PCI_AWBASEL_WIN_ENA, 1265 host->axi + RZG3S_PCI_AWBASEL(id)); 1266} 1267 1268static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host, 1269 struct resource_entry *entry, 1270 int *index) 1271{ 1272 u64 pci_addr = entry->res->start - entry->offset; 1273 u64 cpu_addr = entry->res->start; 1274 u64 cpu_end = entry->res->end; 1275 u64 size_id = 0; 1276 int id = *index; 1277 u64 size; 1278 1279 while (cpu_addr < cpu_end) { 1280 if (id >= RZG3S_MAX_WINDOWS) 1281 return dev_err_probe(host->dev, -ENOSPC, 1282 "Failed to map inbound window for resource (%s)\n", 1283 entry->res->name); 1284 1285 size = resource_size(entry->res) - size_id; 1286 1287 /* 1288 * According to the RZ/G3S HW manual (Rev.1.10, 1289 * section 34.3.1.71 AXI Window Mask (Lower) Registers) the min 1290 * size is 4K. 1291 */ 1292 size = max(size, SZ_4K); 1293 1294 /* 1295 * According the RZ/G3S HW manual (Rev.1.10, sections: 1296 * - 34.3.1.69 AXI Window Base (Lower) Registers 1297 * - 34.3.1.71 AXI Window Mask (Lower) Registers 1298 * - 34.3.1.73 AXI Destination (Lower) Registers) 1299 * the CPU addr, PCIe addr, size should be 4K aligned and be a 1300 * power of 2. 1301 */ 1302 size = ALIGN(size, SZ_4K); 1303 size = roundup_pow_of_two(size); 1304 1305 cpu_addr = ALIGN(cpu_addr, SZ_4K); 1306 pci_addr = ALIGN(pci_addr, SZ_4K); 1307 1308 /* 1309 * According to the RZ/G3S HW manual (Rev.1.10, section 1310 * 34.3.1.71 AXI Window Mask (Lower) Registers) HW expects first 1311 * 12 LSB bits to be 0xfff. Subtract 1 from size for this. 1312 */ 1313 rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr, 1314 size - 1, id); 1315 1316 pci_addr += size; 1317 cpu_addr += size; 1318 size_id = size; 1319 id++; 1320 } 1321 *index = id; 1322 1323 return 0; 1324} 1325 1326static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host) 1327{ 1328 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 1329 struct resource_entry *entry; 1330 int i = 0, ret; 1331 1332 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 1333 ret = rzg3s_pcie_set_inbound_windows(host, entry, &i); 1334 if (ret) 1335 return ret; 1336 } 1337 1338 return 0; 1339} 1340 1341static void rzg3s_pcie_set_outbound_window(struct rzg3s_pcie_host *host, 1342 struct resource_entry *win, int id) 1343{ 1344 struct resource *res = win->res; 1345 resource_size_t size = resource_size(res); 1346 resource_size_t res_start; 1347 1348 if (res->flags & IORESOURCE_IO) 1349 res_start = pci_pio_to_address(res->start) - win->offset; 1350 else 1351 res_start = res->start - win->offset; 1352 1353 /* 1354 * According to the RZ/G3S HW manual (Rev.1.10, section 34.3.1.75 PCIe 1355 * Window Base (Lower) Registers) the window base address need to be 4K 1356 * aligned. 1357 */ 1358 res_start = ALIGN(res_start, SZ_4K); 1359 1360 size = ALIGN(size, SZ_4K); 1361 size = roundup_pow_of_two(size) - 1; 1362 1363 /* Set PCIe destination */ 1364 writel_relaxed(upper_32_bits(res_start), 1365 host->axi + RZG3S_PCI_PDESTU(id)); 1366 writel_relaxed(lower_32_bits(res_start), 1367 host->axi + RZG3S_PCI_PDESTL(id)); 1368 1369 /* Set PCIe window mask */ 1370 writel_relaxed(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id)); 1371 writel_relaxed(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id)); 1372 1373 /* Set PCIe window base and enable the window */ 1374 writel_relaxed(upper_32_bits(res_start), 1375 host->axi + RZG3S_PCI_PWBASEU(id)); 1376 writel_relaxed(lower_32_bits(res_start) | RZG3S_PCI_PWBASEL_ENA, 1377 host->axi + RZG3S_PCI_PWBASEL(id)); 1378} 1379 1380static int rzg3s_pcie_parse_map_ranges(struct rzg3s_pcie_host *host) 1381{ 1382 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 1383 struct resource_entry *win; 1384 int i = 0; 1385 1386 resource_list_for_each_entry(win, &bridge->windows) { 1387 struct resource *res = win->res; 1388 1389 if (i >= RZG3S_MAX_WINDOWS) 1390 return dev_err_probe(host->dev, -ENOSPC, 1391 "Failed to map outbound window for resource (%s)\n", 1392 res->name); 1393 1394 if (!res->flags) 1395 continue; 1396 1397 switch (resource_type(res)) { 1398 case IORESOURCE_IO: 1399 case IORESOURCE_MEM: 1400 rzg3s_pcie_set_outbound_window(host, win, i); 1401 i++; 1402 break; 1403 } 1404 } 1405 1406 return 0; 1407} 1408 1409static int rzg3s_soc_pcie_init_phy(struct rzg3s_pcie_host *host) 1410{ 1411 static const u32 xcfgd_settings[RZG3S_PCI_PHY_XCFGD_NUM] = { 1412 [8] = 0xe0006801, 0x007f7e30, 0x183e0000, 0x978ff500, 1413 0xec000000, 0x009f1400, 0x0000d009, 1414 [17] = 0x78000000, 1415 [19] = 0x00880000, 0x000005c0, 0x07000000, 0x00780920, 1416 0xc9400ce2, 0x90000c0c, 0x000c1414, 0x00005034, 1417 0x00006000, 0x00000001, 1418 }; 1419 static const u32 xcfga_cmn_settings[RZG3S_PCI_PHY_XCFGA_CMN_NUM] = { 1420 0x00000d10, 0x08310100, 0x00c21404, 0x013c0010, 0x01874440, 1421 0x1a216082, 0x00103440, 0x00000080, 0x00000010, 0x0c1000c1, 1422 0x1000c100, 0x0222000c, 0x00640019, 0x00a00028, 0x01d11228, 1423 0x0201001d, 1424 }; 1425 static const u32 xcfga_rx_settings[RZG3S_PCI_PHY_XCFGA_RX_NUM] = { 1426 0x07d55000, 0x030e3f00, 0x00000288, 0x102c5880, 0x0000000b, 1427 0x04141441, 0x00641641, 0x00d63d63, 0x00641641, 0x01970377, 1428 0x00190287, 0x00190028, 0x00000028, 1429 }; 1430 unsigned int i; 1431 1432 /* 1433 * Enable access permission for physical layer control and status 1434 * registers. 1435 */ 1436 writel_relaxed(RZG3S_PCI_PERM_PIPE_PHY_REG_EN, 1437 host->axi + RZG3S_PCI_PERM); 1438 1439 for (i = 0; i < RZG3S_PCI_PHY_XCFGD_NUM; i++) { 1440 writel_relaxed(xcfgd_settings[i], 1441 host->axi + RZG3S_PCI_PHY_XCFGD(i)); 1442 } 1443 1444 for (i = 0; i < RZG3S_PCI_PHY_XCFGA_CMN_NUM; i++) { 1445 writel_relaxed(xcfga_cmn_settings[i], 1446 host->axi + RZG3S_PCI_PHY_XCFGA_CMN(i)); 1447 } 1448 1449 for (i = 0; i < RZG3S_PCI_PHY_XCFGA_RX_NUM; i++) { 1450 writel_relaxed(xcfga_rx_settings[i], 1451 host->axi + RZG3S_PCI_PHY_XCFGA_RX(i)); 1452 } 1453 1454 writel_relaxed(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX); 1455 1456 /* Select PHY settings values */ 1457 writel_relaxed(RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL, 1458 host->axi + RZG3S_PCI_PHY_XCFG_CTRL); 1459 1460 /* 1461 * Disable access permission for physical layer control and status 1462 * registers. 1463 */ 1464 writel_relaxed(0, host->axi + RZG3S_PCI_PERM); 1465 1466 return 0; 1467} 1468 1469static int 1470rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, 1471 int (*init_irqdomain)(struct rzg3s_pcie_host *host), 1472 void (*teardown_irqdomain)(struct rzg3s_pcie_host *host)) 1473{ 1474 struct device *dev = host->dev; 1475 int ret; 1476 1477 /* Set inbound windows */ 1478 ret = rzg3s_pcie_parse_map_dma_ranges(host); 1479 if (ret) 1480 return dev_err_probe(dev, ret, 1481 "Failed to set inbound windows!\n"); 1482 1483 /* Set outbound windows */ 1484 ret = rzg3s_pcie_parse_map_ranges(host); 1485 if (ret) 1486 return dev_err_probe(dev, ret, 1487 "Failed to set outbound windows!\n"); 1488 1489 ret = init_irqdomain(host); 1490 if (ret) 1491 return dev_err_probe(dev, ret, "Failed to init IRQ domain\n"); 1492 1493 ret = rzg3s_pcie_host_init(host); 1494 if (ret) { 1495 dev_err_probe(dev, ret, "Failed to initialize the HW!\n"); 1496 goto teardown_irqdomain; 1497 } 1498 1499 ret = rzg3s_pcie_set_max_link_speed(host); 1500 if (ret) 1501 dev_info(dev, "Failed to set max link speed\n"); 1502 1503 msleep(PCIE_RESET_CONFIG_WAIT_MS); 1504 1505 return 0; 1506 1507teardown_irqdomain: 1508 teardown_irqdomain(host); 1509 1510 return ret; 1511} 1512 1513static int rzg3s_pcie_probe(struct platform_device *pdev) 1514{ 1515 struct pci_host_bridge *bridge; 1516 struct device *dev = &pdev->dev; 1517 struct device_node *np = dev->of_node; 1518 struct device_node *sysc_np __free(device_node) = 1519 of_parse_phandle(np, "renesas,sysc", 0); 1520 struct rzg3s_pcie_host *host; 1521 int ret; 1522 1523 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 1524 if (!bridge) 1525 return -ENOMEM; 1526 1527 host = pci_host_bridge_priv(bridge); 1528 host->dev = dev; 1529 host->data = device_get_match_data(dev); 1530 platform_set_drvdata(pdev, host); 1531 1532 host->axi = devm_platform_ioremap_resource(pdev, 0); 1533 if (IS_ERR(host->axi)) 1534 return PTR_ERR(host->axi); 1535 host->pcie = host->axi + RZG3S_PCI_CFG_BASE; 1536 1537 host->max_link_speed = of_pci_get_max_link_speed(np); 1538 if (host->max_link_speed < 0) 1539 host->max_link_speed = 2; 1540 1541 ret = rzg3s_pcie_host_parse_port(host); 1542 if (ret) 1543 return ret; 1544 1545 host->sysc = syscon_node_to_regmap(sysc_np); 1546 if (IS_ERR(host->sysc)) { 1547 ret = PTR_ERR(host->sysc); 1548 goto port_refclk_put; 1549 } 1550 1551 ret = regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1552 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1553 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); 1554 if (ret) 1555 goto port_refclk_put; 1556 1557 ret = rzg3s_pcie_resets_prepare_and_get(host); 1558 if (ret) 1559 goto sysc_signal_restore; 1560 1561 ret = rzg3s_pcie_power_resets_deassert(host); 1562 if (ret) 1563 goto sysc_signal_restore; 1564 1565 pm_runtime_enable(dev); 1566 1567 /* 1568 * Controller clocks are part of a clock power domain. Enable them 1569 * through runtime PM. 1570 */ 1571 ret = pm_runtime_resume_and_get(dev); 1572 if (ret) 1573 goto rpm_disable; 1574 1575 raw_spin_lock_init(&host->hw_lock); 1576 1577 ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_init_irqdomain, 1578 rzg3s_pcie_teardown_irqdomain); 1579 if (ret) 1580 goto rpm_put; 1581 1582 bridge->sysdata = host; 1583 bridge->ops = &rzg3s_pcie_root_ops; 1584 bridge->child_ops = &rzg3s_pcie_child_ops; 1585 ret = pci_host_probe(bridge); 1586 if (ret) 1587 goto host_probe_teardown; 1588 1589 return 0; 1590 1591host_probe_teardown: 1592 rzg3s_pcie_teardown_irqdomain(host); 1593 reset_control_bulk_deassert(host->data->num_cfg_resets, 1594 host->cfg_resets); 1595rpm_put: 1596 pm_runtime_put_sync(dev); 1597rpm_disable: 1598 pm_runtime_disable(dev); 1599 reset_control_bulk_assert(host->data->num_power_resets, 1600 host->power_resets); 1601sysc_signal_restore: 1602 /* 1603 * SYSC RST_RSM_B signal need to be asserted before turning off the 1604 * power to the PHY. 1605 */ 1606 regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1607 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1608 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); 1609port_refclk_put: 1610 clk_put(host->port.refclk); 1611 1612 return ret; 1613} 1614 1615static int rzg3s_pcie_suspend_noirq(struct device *dev) 1616{ 1617 struct rzg3s_pcie_host *host = dev_get_drvdata(dev); 1618 const struct rzg3s_pcie_soc_data *data = host->data; 1619 struct rzg3s_pcie_port *port = &host->port; 1620 struct regmap *sysc = host->sysc; 1621 int ret; 1622 1623 ret = pm_runtime_put_sync(dev); 1624 if (ret) 1625 return ret; 1626 1627 clk_disable_unprepare(port->refclk); 1628 1629 ret = reset_control_bulk_assert(data->num_power_resets, 1630 host->power_resets); 1631 if (ret) 1632 goto refclk_restore; 1633 1634 ret = reset_control_bulk_assert(data->num_cfg_resets, 1635 host->cfg_resets); 1636 if (ret) 1637 goto power_resets_restore; 1638 1639 ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1640 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1641 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); 1642 if (ret) 1643 goto cfg_resets_restore; 1644 1645 return 0; 1646 1647 /* Restore the previous state if any error happens */ 1648cfg_resets_restore: 1649 reset_control_bulk_deassert(data->num_cfg_resets, 1650 host->cfg_resets); 1651power_resets_restore: 1652 reset_control_bulk_deassert(data->num_power_resets, 1653 host->power_resets); 1654refclk_restore: 1655 clk_prepare_enable(port->refclk); 1656 pm_runtime_resume_and_get(dev); 1657 return ret; 1658} 1659 1660static int rzg3s_pcie_resume_noirq(struct device *dev) 1661{ 1662 struct rzg3s_pcie_host *host = dev_get_drvdata(dev); 1663 const struct rzg3s_pcie_soc_data *data = host->data; 1664 struct regmap *sysc = host->sysc; 1665 int ret; 1666 1667 ret = regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1668 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1669 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); 1670 if (ret) 1671 return ret; 1672 1673 ret = rzg3s_pcie_power_resets_deassert(host); 1674 if (ret) 1675 goto assert_rst_rsm_b; 1676 1677 ret = pm_runtime_resume_and_get(dev); 1678 if (ret) 1679 goto assert_power_resets; 1680 1681 ret = rzg3s_pcie_host_setup(host, rzg3s_pcie_msi_hw_setup, 1682 rzg3s_pcie_msi_hw_teardown); 1683 if (ret) 1684 goto rpm_put; 1685 1686 return 0; 1687 1688 /* 1689 * If any error happens there is no way to recover the IP. Put it in the 1690 * lowest possible power state. 1691 */ 1692rpm_put: 1693 pm_runtime_put_sync(dev); 1694assert_power_resets: 1695 reset_control_bulk_assert(data->num_power_resets, 1696 host->power_resets); 1697assert_rst_rsm_b: 1698 regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, 1699 RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1700 FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); 1701 return ret; 1702} 1703 1704static const struct dev_pm_ops rzg3s_pcie_pm_ops = { 1705 NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq, 1706 rzg3s_pcie_resume_noirq) 1707}; 1708 1709static const char * const rzg3s_soc_power_resets[] = { 1710 "aresetn", "rst_cfg_b", "rst_load_b", 1711}; 1712 1713static const char * const rzg3s_soc_cfg_resets[] = { 1714 "rst_b", "rst_ps_b", "rst_gp_b", "rst_rsm_b", 1715}; 1716 1717static const struct rzg3s_pcie_soc_data rzg3s_soc_data = { 1718 .power_resets = rzg3s_soc_power_resets, 1719 .num_power_resets = ARRAY_SIZE(rzg3s_soc_power_resets), 1720 .cfg_resets = rzg3s_soc_cfg_resets, 1721 .num_cfg_resets = ARRAY_SIZE(rzg3s_soc_cfg_resets), 1722 .init_phy = rzg3s_soc_pcie_init_phy, 1723}; 1724 1725static const struct of_device_id rzg3s_pcie_of_match[] = { 1726 { 1727 .compatible = "renesas,r9a08g045-pcie", 1728 .data = &rzg3s_soc_data, 1729 }, 1730 {} 1731}; 1732 1733static struct platform_driver rzg3s_pcie_driver = { 1734 .driver = { 1735 .name = "rzg3s-pcie-host", 1736 .of_match_table = rzg3s_pcie_of_match, 1737 .pm = pm_ptr(&rzg3s_pcie_pm_ops), 1738 .suppress_bind_attrs = true, 1739 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1740 }, 1741 .probe = rzg3s_pcie_probe, 1742}; 1743builtin_platform_driver(rzg3s_pcie_driver);
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