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pcie-rcar-host.c
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linux-6.19.14/drivers/pci/controller/pcie-rcar-host.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * PCIe driver for Renesas R-Car SoCs 4 * Copyright (C) 2014-2020 Renesas Electronics Europe Ltd 5 * 6 * Based on: 7 * arch/sh/drivers/pci/pcie-sh7786.c 8 * arch/sh/drivers/pci/ops-sh7786.c 9 * Copyright (C) 2009 - 2011 Paul Mundt 10 * 11 * Author: Phil Edworthy <phil.edworthy@renesas.com> 12 */ 13 14#include <linux/bitops.h> 15#include <linux/cleanup.h> 16#include <linux/clk.h> 17#include <linux/clk-provider.h> 18#include <linux/delay.h> 19#include <linux/interrupt.h> 20#include <linux/irq.h> 21#include <linux/irqchip/irq-msi-lib.h> 22#include <linux/irqdomain.h> 23#include <linux/kernel.h> 24#include <linux/init.h> 25#include <linux/iopoll.h> 26#include <linux/msi.h> 27#include <linux/of_address.h> 28#include <linux/of_irq.h> 29#include <linux/of_platform.h> 30#include <linux/pci.h> 31#include <linux/phy/phy.h> 32#include <linux/platform_device.h> 33#include <linux/pm_runtime.h> 34#include <linux/regulator/consumer.h> 35 36#include "pcie-rcar.h" 37 38struct rcar_msi { 39 DECLARE_BITMAP(used, INT_PCI_MSI_NR); 40 struct irq_domain *domain; 41 struct mutex map_lock; 42 raw_spinlock_t mask_lock; 43 int irq1; 44 int irq2; 45}; 46 47/* Structure representing the PCIe interface */ 48struct rcar_pcie_host { 49 struct rcar_pcie pcie; 50 struct phy *phy; 51 struct clk *bus_clk; 52 struct rcar_msi msi; 53 int (*phy_init_fn)(struct rcar_pcie_host *host); 54}; 55 56static int rcar_pcie_wakeup(struct device *pcie_dev, void __iomem *pcie_base) 57{ 58 u32 pmsr, val; 59 int ret = 0; 60 61 if (!pcie_base || pm_runtime_suspended(pcie_dev)) 62 return -EINVAL; 63 64 pmsr = readl(pcie_base + PMSR); 65 66 /* 67 * Test if the PCIe controller received PM_ENTER_L1 DLLP and 68 * the PCIe controller is not in L1 link state. If true, apply 69 * fix, which will put the controller into L1 link state, from 70 * which it can return to L0s/L0 on its own. 71 */ 72 if ((pmsr & PMEL1RX) && ((pmsr & PMSTATE) != PMSTATE_L1)) { 73 writel(L1IATN, pcie_base + PMCTLR); 74 ret = readl_poll_timeout_atomic(pcie_base + PMSR, val, 75 val & L1FAEG, 10, 1000); 76 if (ret) { 77 dev_warn_ratelimited(pcie_dev, 78 "Timeout waiting for L1 link state, ret=%d\n", 79 ret); 80 } 81 writel(L1FAEG | PMEL1RX, pcie_base + PMSR); 82 } 83 84 return ret; 85} 86 87static struct rcar_pcie_host *msi_to_host(struct rcar_msi *msi) 88{ 89 return container_of(msi, struct rcar_pcie_host, msi); 90} 91 92static u32 rcar_read_conf(struct rcar_pcie *pcie, int where) 93{ 94 unsigned int shift = BITS_PER_BYTE * (where & 3); 95 u32 val = rcar_pci_read_reg(pcie, where & ~3); 96 97 return val >> shift; 98} 99 100#ifdef CONFIG_ARM 101#define __rcar_pci_rw_reg_workaround(instr) \ 102 " .arch armv7-a\n" \ 103 "1: " instr " %1, [%2]\n" \ 104 "2: isb\n" \ 105 "3: .pushsection .text.fixup,\"ax\"\n" \ 106 " .align 2\n" \ 107 "4: mov %0, #" __stringify(PCIBIOS_SET_FAILED) "\n" \ 108 " b 3b\n" \ 109 " .popsection\n" \ 110 " .pushsection __ex_table,\"a\"\n" \ 111 " .align 3\n" \ 112 " .long 1b, 4b\n" \ 113 " .long 2b, 4b\n" \ 114 " .popsection\n" 115#endif 116 117static int rcar_pci_write_reg_workaround(struct rcar_pcie *pcie, u32 val, 118 unsigned int reg) 119{ 120 int error = PCIBIOS_SUCCESSFUL; 121#ifdef CONFIG_ARM 122 asm volatile( 123 __rcar_pci_rw_reg_workaround("str") 124 : "+r"(error):"r"(val), "r"(pcie->base + reg) : "memory"); 125#else 126 rcar_pci_write_reg(pcie, val, reg); 127#endif 128 return error; 129} 130 131static int rcar_pci_read_reg_workaround(struct rcar_pcie *pcie, u32 *val, 132 unsigned int reg) 133{ 134 int error = PCIBIOS_SUCCESSFUL; 135#ifdef CONFIG_ARM 136 asm volatile( 137 __rcar_pci_rw_reg_workaround("ldr") 138 : "+r"(error), "=r"(*val) : "r"(pcie->base + reg) : "memory"); 139 140 if (error != PCIBIOS_SUCCESSFUL) 141 PCI_SET_ERROR_RESPONSE(val); 142#else 143 *val = rcar_pci_read_reg(pcie, reg); 144#endif 145 return error; 146} 147 148/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 149static int rcar_pcie_config_access(struct rcar_pcie_host *host, 150 unsigned char access_type, struct pci_bus *bus, 151 unsigned int devfn, int where, u32 *data) 152{ 153 struct rcar_pcie *pcie = &host->pcie; 154 unsigned int dev, func, reg, index; 155 int ret; 156 157 /* Wake the bus up in case it is in L1 state. */ 158 ret = rcar_pcie_wakeup(pcie->dev, pcie->base); 159 if (ret) { 160 PCI_SET_ERROR_RESPONSE(data); 161 return PCIBIOS_SET_FAILED; 162 } 163 164 dev = PCI_SLOT(devfn); 165 func = PCI_FUNC(devfn); 166 reg = where & ~3; 167 index = reg / 4; 168 169 /* 170 * While each channel has its own memory-mapped extended config 171 * space, it's generally only accessible when in endpoint mode. 172 * When in root complex mode, the controller is unable to target 173 * itself with either type 0 or type 1 accesses, and indeed, any 174 * controller-initiated target transfer to its own config space 175 * results in a completer abort. 176 * 177 * Each channel effectively only supports a single device, but as 178 * the same channel <-> device access works for any PCI_SLOT() 179 * value, we cheat a bit here and bind the controller's config 180 * space to devfn 0 in order to enable self-enumeration. In this 181 * case the regular ECAR/ECDR path is sidelined and the mangled 182 * config access itself is initiated as an internal bus transaction. 183 */ 184 if (pci_is_root_bus(bus)) { 185 if (dev != 0) 186 return PCIBIOS_DEVICE_NOT_FOUND; 187 188 if (access_type == RCAR_PCI_ACCESS_READ) 189 *data = rcar_pci_read_reg(pcie, PCICONF(index)); 190 else 191 rcar_pci_write_reg(pcie, *data, PCICONF(index)); 192 193 return PCIBIOS_SUCCESSFUL; 194 } 195 196 /* Clear errors */ 197 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR); 198 199 /* Set the PIO address */ 200 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) | 201 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR); 202 203 /* Enable the configuration access */ 204 if (pci_is_root_bus(bus->parent)) 205 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE0, PCIECCTLR); 206 else 207 rcar_pci_write_reg(pcie, PCIECCTLR_CCIE | TYPE1, PCIECCTLR); 208 209 /* Check for errors */ 210 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST) 211 return PCIBIOS_DEVICE_NOT_FOUND; 212 213 /* Check for master and target aborts */ 214 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) & 215 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT)) 216 return PCIBIOS_DEVICE_NOT_FOUND; 217 218 if (access_type == RCAR_PCI_ACCESS_READ) 219 ret = rcar_pci_read_reg_workaround(pcie, data, PCIECDR); 220 else 221 ret = rcar_pci_write_reg_workaround(pcie, *data, PCIECDR); 222 223 /* Disable the configuration access */ 224 rcar_pci_write_reg(pcie, 0, PCIECCTLR); 225 226 return ret; 227} 228 229static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn, 230 int where, int size, u32 *val) 231{ 232 struct rcar_pcie_host *host = bus->sysdata; 233 int ret; 234 235 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 236 bus, devfn, where, val); 237 if (ret != PCIBIOS_SUCCESSFUL) 238 return ret; 239 240 if (size == 1) 241 *val = (*val >> (BITS_PER_BYTE * (where & 3))) & 0xff; 242 else if (size == 2) 243 *val = (*val >> (BITS_PER_BYTE * (where & 2))) & 0xffff; 244 245 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 246 bus->number, devfn, where, size, *val); 247 248 return ret; 249} 250 251/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ 252static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn, 253 int where, int size, u32 val) 254{ 255 struct rcar_pcie_host *host = bus->sysdata; 256 unsigned int shift; 257 u32 data; 258 int ret; 259 260 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_READ, 261 bus, devfn, where, &data); 262 if (ret != PCIBIOS_SUCCESSFUL) 263 return ret; 264 265 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08x\n", 266 bus->number, devfn, where, size, val); 267 268 if (size == 1) { 269 shift = BITS_PER_BYTE * (where & 3); 270 data &= ~(0xff << shift); 271 data |= ((val & 0xff) << shift); 272 } else if (size == 2) { 273 shift = BITS_PER_BYTE * (where & 2); 274 data &= ~(0xffff << shift); 275 data |= ((val & 0xffff) << shift); 276 } else 277 data = val; 278 279 ret = rcar_pcie_config_access(host, RCAR_PCI_ACCESS_WRITE, 280 bus, devfn, where, &data); 281 282 return ret; 283} 284 285static struct pci_ops rcar_pcie_ops = { 286 .read = rcar_pcie_read_conf, 287 .write = rcar_pcie_write_conf, 288}; 289 290static void rcar_pcie_force_speedup(struct rcar_pcie *pcie) 291{ 292 struct device *dev = pcie->dev; 293 unsigned int timeout = 1000; 294 u32 macsr; 295 296 if ((rcar_pci_read_reg(pcie, MACS2R) & LINK_SPEED) != LINK_SPEED_5_0GTS) 297 return; 298 299 if (rcar_pci_read_reg(pcie, MACCTLR) & SPEED_CHANGE) { 300 dev_err(dev, "Speed change already in progress\n"); 301 return; 302 } 303 304 macsr = rcar_pci_read_reg(pcie, MACSR); 305 if ((macsr & LINK_SPEED) == LINK_SPEED_5_0GTS) 306 goto done; 307 308 /* Set target link speed to 5.0 GT/s */ 309 rcar_rmw32(pcie, EXPCAP(12), PCI_EXP_LNKSTA_CLS, 310 PCI_EXP_LNKSTA_CLS_5_0GB); 311 312 /* Set speed change reason as intentional factor */ 313 rcar_rmw32(pcie, MACCGSPSETR, SPCNGRSN, 0); 314 315 /* Clear SPCHGFIN, SPCHGSUC, and SPCHGFAIL */ 316 if (macsr & (SPCHGFIN | SPCHGSUC | SPCHGFAIL)) 317 rcar_pci_write_reg(pcie, macsr, MACSR); 318 319 /* Start link speed change */ 320 rcar_rmw32(pcie, MACCTLR, SPEED_CHANGE, SPEED_CHANGE); 321 322 while (timeout--) { 323 macsr = rcar_pci_read_reg(pcie, MACSR); 324 if (macsr & SPCHGFIN) { 325 /* Clear the interrupt bits */ 326 rcar_pci_write_reg(pcie, macsr, MACSR); 327 328 if (macsr & SPCHGFAIL) 329 dev_err(dev, "Speed change failed\n"); 330 331 goto done; 332 } 333 334 msleep(1); 335 } 336 337 dev_err(dev, "Speed change timed out\n"); 338 339done: 340 dev_info(dev, "Current link speed is %s GT/s\n", 341 (macsr & LINK_SPEED) == LINK_SPEED_5_0GTS ? "5" : "2.5"); 342} 343 344static void rcar_pcie_hw_enable(struct rcar_pcie_host *host) 345{ 346 struct rcar_pcie *pcie = &host->pcie; 347 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 348 struct resource_entry *win; 349 LIST_HEAD(res); 350 int i = 0; 351 352 /* Try setting 5 GT/s link speed */ 353 rcar_pcie_force_speedup(pcie); 354 355 /* Setup PCI resources */ 356 resource_list_for_each_entry(win, &bridge->windows) { 357 struct resource *res = win->res; 358 359 if (!res->flags) 360 continue; 361 362 switch (resource_type(res)) { 363 case IORESOURCE_IO: 364 case IORESOURCE_MEM: 365 rcar_pcie_set_outbound(pcie, i, win); 366 i++; 367 break; 368 } 369 } 370} 371 372static int rcar_pcie_enable(struct rcar_pcie_host *host) 373{ 374 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 375 376 rcar_pcie_hw_enable(host); 377 378 pci_add_flags(PCI_REASSIGN_ALL_BUS); 379 380 bridge->sysdata = host; 381 bridge->ops = &rcar_pcie_ops; 382 383 return pci_host_probe(bridge); 384} 385 386static int phy_wait_for_ack(struct rcar_pcie *pcie) 387{ 388 struct device *dev = pcie->dev; 389 unsigned int timeout = 100; 390 391 while (timeout--) { 392 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK) 393 return 0; 394 395 udelay(100); 396 } 397 398 dev_err(dev, "Access to PCIe phy timed out\n"); 399 400 return -ETIMEDOUT; 401} 402 403static void phy_write_reg(struct rcar_pcie *pcie, 404 unsigned int rate, u32 addr, 405 unsigned int lane, u32 data) 406{ 407 u32 phyaddr; 408 409 phyaddr = WRITE_CMD | 410 ((rate & 1) << RATE_POS) | 411 ((lane & 0xf) << LANE_POS) | 412 ((addr & 0xff) << ADR_POS); 413 414 /* Set write data */ 415 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR); 416 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR); 417 418 /* Ignore errors as they will be dealt with if the data link is down */ 419 phy_wait_for_ack(pcie); 420 421 /* Clear command */ 422 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR); 423 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR); 424 425 /* Ignore errors as they will be dealt with if the data link is down */ 426 phy_wait_for_ack(pcie); 427} 428 429static int rcar_pcie_hw_init(struct rcar_pcie *pcie) 430{ 431 int err; 432 433 /* Begin initialization */ 434 rcar_pci_write_reg(pcie, 0, PCIETCTLR); 435 436 /* Set mode */ 437 rcar_pci_write_reg(pcie, 1, PCIEMSR); 438 439 err = rcar_pcie_wait_for_phyrdy(pcie); 440 if (err) 441 return err; 442 443 /* 444 * Initial header for port config space is type 1, set the device 445 * class to match. Hardware takes care of propagating the IDSETR 446 * settings, so there is no need to bother with a quirk. 447 */ 448 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI_NORMAL << 8, IDSETR1); 449 450 /* 451 * Setup Secondary Bus Number & Subordinate Bus Number, even though 452 * they aren't used, to avoid bridge being detected as broken. 453 */ 454 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1); 455 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1); 456 457 /* Initialize default capabilities. */ 458 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP); 459 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS), 460 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4); 461 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), PCI_HEADER_TYPE_MASK, 462 PCI_HEADER_TYPE_BRIDGE); 463 464 /* Enable data link layer active state reporting */ 465 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC, 466 PCI_EXP_LNKCAP_DLLLARC); 467 468 /* Write out the physical slot number = 0 */ 469 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0); 470 471 /* Set the completion timer timeout to the maximum 50ms. */ 472 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50); 473 474 /* Terminate list of capabilities (Next Capability Offset=0) */ 475 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0); 476 477 /* Enable MSI */ 478 if (IS_ENABLED(CONFIG_PCI_MSI)) 479 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR); 480 481 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 482 483 /* Finish initialization - establish a PCI Express link */ 484 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 485 486 /* This will timeout if we don't have a link. */ 487 err = rcar_pcie_wait_for_dl(pcie); 488 if (err) 489 return err; 490 491 /* Enable INTx interrupts */ 492 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8); 493 494 wmb(); 495 496 return 0; 497} 498 499static int rcar_pcie_phy_init_h1(struct rcar_pcie_host *host) 500{ 501 struct rcar_pcie *pcie = &host->pcie; 502 503 /* Initialize the phy */ 504 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191); 505 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180); 506 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188); 507 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188); 508 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014); 509 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014); 510 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0); 511 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB); 512 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062); 513 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000); 514 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000); 515 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806); 516 517 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5); 518 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F); 519 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000); 520 521 return 0; 522} 523 524static int rcar_pcie_phy_init_gen2(struct rcar_pcie_host *host) 525{ 526 struct rcar_pcie *pcie = &host->pcie; 527 528 /* 529 * These settings come from the R-Car Series, 2nd Generation User's 530 * Manual, section 50.3.1 (2) Initialization of the physical layer. 531 */ 532 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR); 533 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA); 534 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 535 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 536 537 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR); 538 /* The following value is for DC connection, no termination resistor */ 539 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA); 540 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL); 541 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL); 542 543 return 0; 544} 545 546static int rcar_pcie_phy_init_gen3(struct rcar_pcie_host *host) 547{ 548 int err; 549 550 err = phy_init(host->phy); 551 if (err) 552 return err; 553 554 err = phy_power_on(host->phy); 555 if (err) 556 phy_exit(host->phy); 557 558 return err; 559} 560 561static irqreturn_t rcar_pcie_msi_irq(int irq, void *data) 562{ 563 struct rcar_pcie_host *host = data; 564 struct rcar_pcie *pcie = &host->pcie; 565 struct rcar_msi *msi = &host->msi; 566 struct device *dev = pcie->dev; 567 unsigned long reg; 568 569 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 570 571 /* MSI & INTx share an interrupt - we only handle MSI here */ 572 if (!reg) 573 return IRQ_NONE; 574 575 while (reg) { 576 unsigned int index = find_first_bit(®, 32); 577 int ret; 578 579 ret = generic_handle_domain_irq(msi->domain, index); 580 if (ret) { 581 /* Unknown MSI, just clear it */ 582 dev_dbg(dev, "unexpected MSI\n"); 583 rcar_pci_write_reg(pcie, BIT(index), PCIEMSIFR); 584 } 585 586 /* see if there's any more pending in this vector */ 587 reg = rcar_pci_read_reg(pcie, PCIEMSIFR); 588 } 589 590 return IRQ_HANDLED; 591} 592 593static void rcar_msi_irq_ack(struct irq_data *d) 594{ 595 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 596 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 597 598 /* clear the interrupt */ 599 rcar_pci_write_reg(pcie, BIT(d->hwirq), PCIEMSIFR); 600} 601 602static void rcar_msi_irq_mask(struct irq_data *d) 603{ 604 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 605 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 606 u32 value; 607 608 scoped_guard(raw_spinlock_irqsave, &msi->mask_lock) { 609 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 610 value &= ~BIT(d->hwirq); 611 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 612 } 613} 614 615static void rcar_msi_irq_unmask(struct irq_data *d) 616{ 617 struct rcar_msi *msi = irq_data_get_irq_chip_data(d); 618 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 619 u32 value; 620 621 scoped_guard(raw_spinlock_irqsave, &msi->mask_lock) { 622 value = rcar_pci_read_reg(pcie, PCIEMSIIER); 623 value |= BIT(d->hwirq); 624 rcar_pci_write_reg(pcie, value, PCIEMSIIER); 625 } 626} 627 628static void rcar_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) 629{ 630 struct rcar_msi *msi = irq_data_get_irq_chip_data(data); 631 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 632 633 msg->address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE; 634 msg->address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR); 635 msg->data = data->hwirq; 636} 637 638static struct irq_chip rcar_msi_bottom_chip = { 639 .name = "R-Car MSI", 640 .irq_ack = rcar_msi_irq_ack, 641 .irq_mask = rcar_msi_irq_mask, 642 .irq_unmask = rcar_msi_irq_unmask, 643 .irq_compose_msi_msg = rcar_compose_msi_msg, 644}; 645 646static int rcar_msi_domain_alloc(struct irq_domain *domain, unsigned int virq, 647 unsigned int nr_irqs, void *args) 648{ 649 struct rcar_msi *msi = domain->host_data; 650 unsigned int i; 651 int hwirq; 652 653 mutex_lock(&msi->map_lock); 654 655 hwirq = bitmap_find_free_region(msi->used, INT_PCI_MSI_NR, order_base_2(nr_irqs)); 656 657 mutex_unlock(&msi->map_lock); 658 659 if (hwirq < 0) 660 return -ENOSPC; 661 662 for (i = 0; i < nr_irqs; i++) 663 irq_domain_set_info(domain, virq + i, hwirq + i, 664 &rcar_msi_bottom_chip, domain->host_data, 665 handle_edge_irq, NULL, NULL); 666 667 return 0; 668} 669 670static void rcar_msi_domain_free(struct irq_domain *domain, unsigned int virq, 671 unsigned int nr_irqs) 672{ 673 struct irq_data *d = irq_domain_get_irq_data(domain, virq); 674 struct rcar_msi *msi = domain->host_data; 675 676 mutex_lock(&msi->map_lock); 677 678 bitmap_release_region(msi->used, d->hwirq, order_base_2(nr_irqs)); 679 680 mutex_unlock(&msi->map_lock); 681} 682 683static const struct irq_domain_ops rcar_msi_domain_ops = { 684 .alloc = rcar_msi_domain_alloc, 685 .free = rcar_msi_domain_free, 686}; 687 688#define RCAR_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ 689 MSI_FLAG_USE_DEF_CHIP_OPS | \ 690 MSI_FLAG_PCI_MSI_MASK_PARENT | \ 691 MSI_FLAG_NO_AFFINITY) 692 693#define RCAR_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ 694 MSI_FLAG_MULTI_PCI_MSI) 695 696static const struct msi_parent_ops rcar_msi_parent_ops = { 697 .required_flags = RCAR_MSI_FLAGS_REQUIRED, 698 .supported_flags = RCAR_MSI_FLAGS_SUPPORTED, 699 .bus_select_token = DOMAIN_BUS_PCI_MSI, 700 .chip_flags = MSI_CHIP_FLAG_SET_ACK, 701 .prefix = "RCAR-", 702 .init_dev_msi_info = msi_lib_init_dev_msi_info, 703}; 704 705static int rcar_allocate_domains(struct rcar_msi *msi) 706{ 707 struct rcar_pcie *pcie = &msi_to_host(msi)->pcie; 708 struct irq_domain_info info = { 709 .fwnode = dev_fwnode(pcie->dev), 710 .ops = &rcar_msi_domain_ops, 711 .host_data = msi, 712 .size = INT_PCI_MSI_NR, 713 }; 714 715 msi->domain = msi_create_parent_irq_domain(&info, &rcar_msi_parent_ops); 716 if (!msi->domain) { 717 dev_err(pcie->dev, "failed to create IRQ domain\n"); 718 return -ENOMEM; 719 } 720 721 return 0; 722} 723 724static void rcar_free_domains(struct rcar_msi *msi) 725{ 726 irq_domain_remove(msi->domain); 727} 728 729static int rcar_pcie_enable_msi(struct rcar_pcie_host *host) 730{ 731 struct rcar_pcie *pcie = &host->pcie; 732 struct device *dev = pcie->dev; 733 struct rcar_msi *msi = &host->msi; 734 struct resource res; 735 int err; 736 737 mutex_init(&msi->map_lock); 738 raw_spin_lock_init(&msi->mask_lock); 739 740 err = of_address_to_resource(dev->of_node, 0, &res); 741 if (err) 742 return err; 743 744 err = rcar_allocate_domains(msi); 745 if (err) 746 return err; 747 748 /* Two IRQs are for MSI, but they are also used for non-MSI IRQs */ 749 err = devm_request_irq(dev, msi->irq1, rcar_pcie_msi_irq, 750 IRQF_SHARED | IRQF_NO_THREAD, 751 rcar_msi_bottom_chip.name, host); 752 if (err < 0) { 753 dev_err(dev, "failed to request IRQ: %d\n", err); 754 goto err; 755 } 756 757 err = devm_request_irq(dev, msi->irq2, rcar_pcie_msi_irq, 758 IRQF_SHARED | IRQF_NO_THREAD, 759 rcar_msi_bottom_chip.name, host); 760 if (err < 0) { 761 dev_err(dev, "failed to request IRQ: %d\n", err); 762 goto err; 763 } 764 765 /* Disable all MSIs */ 766 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 767 768 /* 769 * Setup MSI data target using RC base address, which is guaranteed 770 * to be in the low 32bit range on any R-Car HW. 771 */ 772 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 773 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 774 775 return 0; 776 777err: 778 rcar_free_domains(msi); 779 return err; 780} 781 782static void rcar_pcie_teardown_msi(struct rcar_pcie_host *host) 783{ 784 struct rcar_pcie *pcie = &host->pcie; 785 786 /* Disable all MSI interrupts */ 787 rcar_pci_write_reg(pcie, 0, PCIEMSIIER); 788 789 /* Disable address decoding of the MSI interrupt, MSIFE */ 790 rcar_pci_write_reg(pcie, 0, PCIEMSIALR); 791 792 rcar_free_domains(&host->msi); 793} 794 795static int rcar_pcie_get_resources(struct rcar_pcie_host *host) 796{ 797 struct rcar_pcie *pcie = &host->pcie; 798 struct device *dev = pcie->dev; 799 struct resource res; 800 int err, i; 801 802 host->phy = devm_phy_optional_get(dev, "pcie"); 803 if (IS_ERR(host->phy)) 804 return PTR_ERR(host->phy); 805 806 err = of_address_to_resource(dev->of_node, 0, &res); 807 if (err) 808 return err; 809 810 pcie->base = devm_ioremap_resource(dev, &res); 811 if (IS_ERR(pcie->base)) 812 return PTR_ERR(pcie->base); 813 814 host->bus_clk = devm_clk_get(dev, "pcie_bus"); 815 if (IS_ERR(host->bus_clk)) { 816 dev_err(dev, "cannot get pcie bus clock\n"); 817 return PTR_ERR(host->bus_clk); 818 } 819 820 i = irq_of_parse_and_map(dev->of_node, 0); 821 if (!i) { 822 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 823 err = -ENOENT; 824 goto err_irq1; 825 } 826 host->msi.irq1 = i; 827 828 i = irq_of_parse_and_map(dev->of_node, 1); 829 if (!i) { 830 dev_err(dev, "cannot get platform resources for msi interrupt\n"); 831 err = -ENOENT; 832 goto err_irq2; 833 } 834 host->msi.irq2 = i; 835 836 return 0; 837 838err_irq2: 839 irq_dispose_mapping(host->msi.irq1); 840err_irq1: 841 return err; 842} 843 844static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie, 845 struct resource_entry *entry, 846 int *index) 847{ 848 u64 restype = entry->res->flags; 849 u64 cpu_addr = entry->res->start; 850 u64 cpu_end = entry->res->end; 851 u64 pci_addr = entry->res->start - entry->offset; 852 u32 flags = LAM_64BIT | LAR_ENABLE; 853 u64 mask; 854 u64 size = resource_size(entry->res); 855 int idx = *index; 856 857 if (restype & IORESOURCE_PREFETCH) 858 flags |= LAM_PREFETCH; 859 860 while (cpu_addr < cpu_end) { 861 if (idx >= MAX_NR_INBOUND_MAPS - 1) { 862 dev_err(pcie->dev, "Failed to map inbound regions!\n"); 863 return -EINVAL; 864 } 865 866 /* 867 * If the size of the range is larger than the alignment of 868 * the start address, we have to use multiple entries to 869 * perform the mapping. 870 */ 871 if (cpu_addr > 0) { 872 unsigned long nr_zeros = __ffs64(cpu_addr); 873 u64 alignment = 1ULL << nr_zeros; 874 875 size = min(size, alignment); 876 } 877 878 /* Hardware supports max 4GiB inbound region */ 879 size = min(size, 1ULL << 32); 880 881 mask = roundup_pow_of_two(size) - 1; 882 mask &= ~0xf; 883 884 rcar_pcie_set_inbound(pcie, cpu_addr, pci_addr, 885 lower_32_bits(mask) | flags, idx, true); 886 887 pci_addr += size; 888 cpu_addr += size; 889 idx += 2; 890 } 891 *index = idx; 892 893 return 0; 894} 895 896static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie_host *host) 897{ 898 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(host); 899 struct resource_entry *entry; 900 int index = 0, err = 0; 901 902 resource_list_for_each_entry(entry, &bridge->dma_ranges) { 903 err = rcar_pcie_inbound_ranges(&host->pcie, entry, &index); 904 if (err) 905 break; 906 } 907 908 return err; 909} 910 911static const struct of_device_id rcar_pcie_of_match[] = { 912 { .compatible = "renesas,pcie-r8a7779", 913 .data = rcar_pcie_phy_init_h1 }, 914 { .compatible = "renesas,pcie-r8a7790", 915 .data = rcar_pcie_phy_init_gen2 }, 916 { .compatible = "renesas,pcie-r8a7791", 917 .data = rcar_pcie_phy_init_gen2 }, 918 { .compatible = "renesas,pcie-rcar-gen2", 919 .data = rcar_pcie_phy_init_gen2 }, 920 { .compatible = "renesas,pcie-r8a7795", 921 .data = rcar_pcie_phy_init_gen3 }, 922 { .compatible = "renesas,pcie-rcar-gen3", 923 .data = rcar_pcie_phy_init_gen3 }, 924 {}, 925}; 926 927/* Design note 346 from Linear Technology says order is not important. */ 928static const char * const rcar_pcie_supplies[] = { 929 "vpcie1v5", 930 "vpcie3v3", 931 "vpcie12v", 932}; 933 934static int rcar_pcie_probe(struct platform_device *pdev) 935{ 936 struct device *dev = &pdev->dev; 937 struct pci_host_bridge *bridge; 938 struct rcar_pcie_host *host; 939 struct rcar_pcie *pcie; 940 unsigned int i; 941 u32 data; 942 int err; 943 944 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*host)); 945 if (!bridge) 946 return -ENOMEM; 947 948 host = pci_host_bridge_priv(bridge); 949 pcie = &host->pcie; 950 pcie->dev = dev; 951 platform_set_drvdata(pdev, host); 952 953 for (i = 0; i < ARRAY_SIZE(rcar_pcie_supplies); i++) { 954 err = devm_regulator_get_enable_optional(dev, rcar_pcie_supplies[i]); 955 if (err < 0 && err != -ENODEV) 956 return dev_err_probe(dev, err, "failed to enable regulator: %s\n", 957 rcar_pcie_supplies[i]); 958 } 959 960 pm_runtime_enable(pcie->dev); 961 err = pm_runtime_get_sync(pcie->dev); 962 if (err < 0) { 963 dev_err(pcie->dev, "pm_runtime_get_sync failed\n"); 964 goto err_pm_put; 965 } 966 967 err = rcar_pcie_get_resources(host); 968 if (err < 0) { 969 dev_err(dev, "failed to request resources: %d\n", err); 970 goto err_pm_put; 971 } 972 973 err = clk_prepare_enable(host->bus_clk); 974 if (err) { 975 dev_err(dev, "failed to enable bus clock: %d\n", err); 976 goto err_unmap_msi_irqs; 977 } 978 979 err = rcar_pcie_parse_map_dma_ranges(host); 980 if (err) 981 goto err_clk_disable; 982 983 host->phy_init_fn = of_device_get_match_data(dev); 984 err = host->phy_init_fn(host); 985 if (err) { 986 dev_err(dev, "failed to init PCIe PHY\n"); 987 goto err_clk_disable; 988 } 989 990 /* Failure to get a link might just be that no cards are inserted */ 991 if (rcar_pcie_hw_init(pcie)) { 992 dev_info(dev, "PCIe link down\n"); 993 err = -ENODEV; 994 goto err_phy_shutdown; 995 } 996 997 data = rcar_pci_read_reg(pcie, MACSR); 998 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 999 1000 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1001 err = rcar_pcie_enable_msi(host); 1002 if (err < 0) { 1003 dev_err(dev, 1004 "failed to enable MSI support: %d\n", 1005 err); 1006 goto err_phy_shutdown; 1007 } 1008 } 1009 1010 err = rcar_pcie_enable(host); 1011 if (err) 1012 goto err_msi_teardown; 1013 1014 return 0; 1015 1016err_msi_teardown: 1017 if (IS_ENABLED(CONFIG_PCI_MSI)) 1018 rcar_pcie_teardown_msi(host); 1019 1020err_phy_shutdown: 1021 if (host->phy) { 1022 phy_power_off(host->phy); 1023 phy_exit(host->phy); 1024 } 1025 1026err_clk_disable: 1027 clk_disable_unprepare(host->bus_clk); 1028 1029err_unmap_msi_irqs: 1030 irq_dispose_mapping(host->msi.irq2); 1031 irq_dispose_mapping(host->msi.irq1); 1032 1033err_pm_put: 1034 pm_runtime_put(dev); 1035 pm_runtime_disable(dev); 1036 1037 return err; 1038} 1039 1040static int rcar_pcie_resume(struct device *dev) 1041{ 1042 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1043 struct rcar_pcie *pcie = &host->pcie; 1044 unsigned int data; 1045 int err; 1046 1047 err = rcar_pcie_parse_map_dma_ranges(host); 1048 if (err) 1049 return 0; 1050 1051 /* Failure to get a link might just be that no cards are inserted */ 1052 err = host->phy_init_fn(host); 1053 if (err) { 1054 dev_info(dev, "PCIe link down\n"); 1055 return 0; 1056 } 1057 1058 data = rcar_pci_read_reg(pcie, MACSR); 1059 dev_info(dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f); 1060 1061 /* Enable MSI */ 1062 if (IS_ENABLED(CONFIG_PCI_MSI)) { 1063 struct resource res; 1064 u32 val; 1065 1066 of_address_to_resource(dev->of_node, 0, &res); 1067 rcar_pci_write_reg(pcie, upper_32_bits(res.start), PCIEMSIAUR); 1068 rcar_pci_write_reg(pcie, lower_32_bits(res.start) | MSIFE, PCIEMSIALR); 1069 1070 bitmap_to_arr32(&val, host->msi.used, INT_PCI_MSI_NR); 1071 rcar_pci_write_reg(pcie, val, PCIEMSIIER); 1072 } 1073 1074 rcar_pcie_hw_enable(host); 1075 1076 return 0; 1077} 1078 1079static int rcar_pcie_resume_noirq(struct device *dev) 1080{ 1081 struct rcar_pcie_host *host = dev_get_drvdata(dev); 1082 struct rcar_pcie *pcie = &host->pcie; 1083 1084 if (rcar_pci_read_reg(pcie, PMSR) && 1085 !(rcar_pci_read_reg(pcie, PCIETCTLR) & DL_DOWN)) 1086 return 0; 1087 1088 /* Re-establish the PCIe link */ 1089 rcar_pci_write_reg(pcie, MACCTLR_INIT_VAL, MACCTLR); 1090 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR); 1091 return rcar_pcie_wait_for_dl(pcie); 1092} 1093 1094static const struct dev_pm_ops rcar_pcie_pm_ops = { 1095 SYSTEM_SLEEP_PM_OPS(NULL, rcar_pcie_resume) 1096 .resume_noirq = rcar_pcie_resume_noirq, 1097}; 1098 1099static struct platform_driver rcar_pcie_driver = { 1100 .driver = { 1101 .name = "rcar-pcie", 1102 .of_match_table = rcar_pcie_of_match, 1103 .pm = &rcar_pcie_pm_ops, 1104 .suppress_bind_attrs = true, 1105 }, 1106 .probe = rcar_pcie_probe, 1107}; 1108 1109#ifdef CONFIG_ARM 1110static int rcar_pcie_aarch32_abort_handler(unsigned long addr, 1111 unsigned int fsr, struct pt_regs *regs) 1112{ 1113 return !fixup_exception(regs); 1114} 1115 1116static const struct of_device_id rcar_pcie_abort_handler_of_match[] __initconst = { 1117 { .compatible = "renesas,pcie-r8a7779" }, 1118 { .compatible = "renesas,pcie-r8a7790" }, 1119 { .compatible = "renesas,pcie-r8a7791" }, 1120 { .compatible = "renesas,pcie-rcar-gen2" }, 1121 {}, 1122}; 1123 1124static int __init rcar_pcie_init(void) 1125{ 1126 if (of_find_matching_node(NULL, rcar_pcie_abort_handler_of_match)) { 1127#ifdef CONFIG_ARM_LPAE 1128 hook_fault_code(17, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1129 "asynchronous external abort"); 1130#else 1131 hook_fault_code(22, rcar_pcie_aarch32_abort_handler, SIGBUS, 0, 1132 "imprecise external abort"); 1133#endif 1134 } 1135 1136 return platform_driver_register(&rcar_pcie_driver); 1137} 1138device_initcall(rcar_pcie_init); 1139#else 1140builtin_platform_driver(rcar_pcie_driver); 1141#endif
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