pcie-mt7621.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * BRIEF MODULE DESCRIPTION
  4 *     PCI init for Ralink RT2880 solution
  5 *
  6 * Copyright 2007 Ralink Inc. (bruce_chang@ralinktech.com.tw)
  7 *
  8 * May 2007 Bruce Chang
  9 * Initial Release
 10 *
 11 * May 2009 Bruce Chang
 12 * support RT2880/RT3883 PCIe
 13 *
 14 * May 2011 Bruce Chang
 15 * support RT6855/MT7620 PCIe
 16 */
 17
 18#include <linux/bitops.h>
 19#include <linux/clk.h>
 20#include <linux/delay.h>
 21#include <linux/gpio/consumer.h>
 22#include <linux/module.h>
 23#include <linux/of.h>
 24#include <linux/of_address.h>
 25#include <linux/of_pci.h>
 26#include <linux/of_platform.h>
 27#include <linux/pci.h>
 28#include <linux/phy/phy.h>
 29#include <linux/platform_device.h>
 30#include <linux/reset.h>
 31#include <linux/sys_soc.h>
 32
 33#include "../pci.h"
 34
 35/* MediaTek-specific configuration registers */
 36#define PCIE_FTS_NUM			0x70c
 37#define PCIE_FTS_NUM_MASK		GENMASK(15, 8)
 38#define PCIE_FTS_NUM_L0(x)		(((x) & 0xff) << 8)
 39
 40/* Host-PCI bridge registers */
 41#define RALINK_PCI_PCICFG_ADDR		0x0000
 42#define RALINK_PCI_PCIMSK_ADDR		0x000c
 43#define RALINK_PCI_CONFIG_ADDR		0x0020
 44#define RALINK_PCI_CONFIG_DATA		0x0024
 45#define RALINK_PCI_MEMBASE		0x0028
 46#define RALINK_PCI_IOBASE		0x002c
 47
 48/* PCIe RC control registers */
 49#define RALINK_PCI_ID			0x0030
 50#define RALINK_PCI_CLASS		0x0034
 51#define RALINK_PCI_SUBID		0x0038
 52#define RALINK_PCI_STATUS		0x0050
 53
 54/* Some definition values */
 55#define PCIE_REVISION_ID		BIT(0)
 56#define PCIE_CLASS_CODE			(0x60400 << 8)
 57#define PCIE_BAR_MAP_MAX		GENMASK(30, 16)
 58#define PCIE_BAR_ENABLE			BIT(0)
 59#define PCIE_PORT_INT_EN(x)		BIT(20 + (x))
 60#define PCIE_PORT_LINKUP		BIT(0)
 61#define PCIE_PORT_CNT			3
 62
 63#define INIT_PORTS_DELAY_MS		100
 64#define PERST_DELAY_MS			100
 65
 66/**
 67 * struct mt7621_pcie_port - PCIe port information
 68 * @base: I/O mapped register base
 69 * @list: port list
 70 * @pcie: pointer to PCIe host info
 71 * @clk: pointer to the port clock gate
 72 * @phy: pointer to PHY control block
 73 * @pcie_rst: pointer to port reset control
 74 * @gpio_rst: gpio reset
 75 * @slot: port slot
 76 * @enabled: indicates if port is enabled
 77 */
 78struct mt7621_pcie_port {
 79	void __iomem *base;
 80	struct list_head list;
 81	struct mt7621_pcie *pcie;
 82	struct clk *clk;
 83	struct phy *phy;
 84	struct reset_control *pcie_rst;
 85	struct gpio_desc *gpio_rst;
 86	u32 slot;
 87	bool enabled;
 88};
 89
 90/**
 91 * struct mt7621_pcie - PCIe host information
 92 * @base: IO Mapped Register Base
 93 * @dev: Pointer to PCIe device
 94 * @ports: pointer to PCIe port information
 95 * @resets_inverted: depends on chip revision
 96 * reset lines are inverted.
 97 */
 98struct mt7621_pcie {
 99	struct device *dev;
100	void __iomem *base;
101	struct list_head ports;
102	bool resets_inverted;
103};
104
105static inline u32 pcie_read(struct mt7621_pcie *pcie, u32 reg)
106{
107	return readl_relaxed(pcie->base + reg);
108}
109
110static inline void pcie_write(struct mt7621_pcie *pcie, u32 val, u32 reg)
111{
112	writel_relaxed(val, pcie->base + reg);
113}
114
115static inline u32 pcie_port_read(struct mt7621_pcie_port *port, u32 reg)
116{
117	return readl_relaxed(port->base + reg);
118}
119
120static inline void pcie_port_write(struct mt7621_pcie_port *port,
121				   u32 val, u32 reg)
122{
123	writel_relaxed(val, port->base + reg);
124}
125
126static void __iomem *mt7621_pcie_map_bus(struct pci_bus *bus,
127					 unsigned int devfn, int where)
128{
129	struct mt7621_pcie *pcie = bus->sysdata;
130	u32 address = PCI_CONF1_EXT_ADDRESS(bus->number, PCI_SLOT(devfn),
131					    PCI_FUNC(devfn), where);
132
133	writel_relaxed(address, pcie->base + RALINK_PCI_CONFIG_ADDR);
134
135	return pcie->base + RALINK_PCI_CONFIG_DATA + (where & 3);
136}
137
138static struct pci_ops mt7621_pcie_ops = {
139	.map_bus	= mt7621_pcie_map_bus,
140	.read		= pci_generic_config_read,
141	.write		= pci_generic_config_write,
142};
143
144static u32 read_config(struct mt7621_pcie *pcie, unsigned int dev, u32 reg)
145{
146	u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
147
148	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
149	return pcie_read(pcie, RALINK_PCI_CONFIG_DATA);
150}
151
152static void write_config(struct mt7621_pcie *pcie, unsigned int dev,
153			 u32 reg, u32 val)
154{
155	u32 address = PCI_CONF1_EXT_ADDRESS(0, dev, 0, reg);
156
157	pcie_write(pcie, address, RALINK_PCI_CONFIG_ADDR);
158	pcie_write(pcie, val, RALINK_PCI_CONFIG_DATA);
159}
160
161static inline void mt7621_rst_gpio_pcie_assert(struct mt7621_pcie_port *port)
162{
163	if (port->gpio_rst)
164		gpiod_set_value(port->gpio_rst, 1);
165}
166
167static inline void mt7621_rst_gpio_pcie_deassert(struct mt7621_pcie_port *port)
168{
169	if (port->gpio_rst)
170		gpiod_set_value(port->gpio_rst, 0);
171}
172
173static inline bool mt7621_pcie_port_is_linkup(struct mt7621_pcie_port *port)
174{
175	return (pcie_port_read(port, RALINK_PCI_STATUS) & PCIE_PORT_LINKUP) != 0;
176}
177
178static inline void mt7621_control_assert(struct mt7621_pcie_port *port)
179{
180	struct mt7621_pcie *pcie = port->pcie;
181
182	if (pcie->resets_inverted)
183		reset_control_assert(port->pcie_rst);
184	else
185		reset_control_deassert(port->pcie_rst);
186}
187
188static inline void mt7621_control_deassert(struct mt7621_pcie_port *port)
189{
190	struct mt7621_pcie *pcie = port->pcie;
191
192	if (pcie->resets_inverted)
193		reset_control_deassert(port->pcie_rst);
194	else
195		reset_control_assert(port->pcie_rst);
196}
197
198static int mt7621_pcie_parse_port(struct mt7621_pcie *pcie,
199				  struct device_node *node,
200				  int slot)
201{
202	struct mt7621_pcie_port *port;
203	struct device *dev = pcie->dev;
204	struct platform_device *pdev = to_platform_device(dev);
205	char name[11];
206	int err;
207
208	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
209	if (!port)
210		return -ENOMEM;
211
212	port->base = devm_platform_ioremap_resource(pdev, slot + 1);
213	if (IS_ERR(port->base))
214		return PTR_ERR(port->base);
215
216	port->clk = devm_get_clk_from_child(dev, node, NULL);
217	if (IS_ERR(port->clk)) {
218		dev_err(dev, "failed to get pcie%d clock\n", slot);
219		return PTR_ERR(port->clk);
220	}
221
222	port->pcie_rst = of_reset_control_get_exclusive(node, NULL);
223	if (PTR_ERR(port->pcie_rst) == -EPROBE_DEFER) {
224		dev_err(dev, "failed to get pcie%d reset control\n", slot);
225		return PTR_ERR(port->pcie_rst);
226	}
227
228	snprintf(name, sizeof(name), "pcie-phy%d", slot);
229	port->phy = devm_of_phy_get(dev, node, name);
230	if (IS_ERR(port->phy)) {
231		dev_err(dev, "failed to get pcie-phy%d\n", slot);
232		err = PTR_ERR(port->phy);
233		goto remove_reset;
234	}
235
236	port->gpio_rst = devm_gpiod_get_index_optional(dev, "reset", slot,
237						       GPIOD_OUT_LOW);
238	if (IS_ERR(port->gpio_rst)) {
239		dev_err(dev, "failed to get GPIO for PCIe%d\n", slot);
240		err = PTR_ERR(port->gpio_rst);
241		goto remove_reset;
242	}
243
244	port->slot = slot;
245	port->pcie = pcie;
246
247	INIT_LIST_HEAD(&port->list);
248	list_add_tail(&port->list, &pcie->ports);
249
250	return 0;
251
252remove_reset:
253	reset_control_put(port->pcie_rst);
254	return err;
255}
256
257static int mt7621_pcie_parse_dt(struct mt7621_pcie *pcie)
258{
259	struct device *dev = pcie->dev;
260	struct platform_device *pdev = to_platform_device(dev);
261	struct device_node *node = dev->of_node;
262	int err;
263
264	pcie->base = devm_platform_ioremap_resource(pdev, 0);
265	if (IS_ERR(pcie->base))
266		return PTR_ERR(pcie->base);
267
268	for_each_available_child_of_node_scoped(node, child) {
269		int slot;
270
271		err = of_pci_get_devfn(child);
272		if (err < 0)
273			return dev_err_probe(dev, err, "failed to parse devfn\n");
274
275		slot = PCI_SLOT(err);
276
277		err = mt7621_pcie_parse_port(pcie, child, slot);
278		if (err)
279			return err;
280	}
281
282	return 0;
283}
284
285static int mt7621_pcie_init_port(struct mt7621_pcie_port *port)
286{
287	struct mt7621_pcie *pcie = port->pcie;
288	struct device *dev = pcie->dev;
289	u32 slot = port->slot;
290	int err;
291
292	err = phy_init(port->phy);
293	if (err) {
294		dev_err(dev, "failed to initialize port%d phy\n", slot);
295		return err;
296	}
297
298	err = phy_power_on(port->phy);
299	if (err) {
300		dev_err(dev, "failed to power on port%d phy\n", slot);
301		phy_exit(port->phy);
302		return err;
303	}
304
305	port->enabled = true;
306
307	return 0;
308}
309
310static void mt7621_pcie_reset_assert(struct mt7621_pcie *pcie)
311{
312	struct mt7621_pcie_port *port;
313
314	list_for_each_entry(port, &pcie->ports, list) {
315		/* PCIe RC reset assert */
316		mt7621_control_assert(port);
317
318		/* PCIe EP reset assert */
319		mt7621_rst_gpio_pcie_assert(port);
320	}
321
322	msleep(PERST_DELAY_MS);
323}
324
325static void mt7621_pcie_reset_rc_deassert(struct mt7621_pcie *pcie)
326{
327	struct mt7621_pcie_port *port;
328
329	list_for_each_entry(port, &pcie->ports, list)
330		mt7621_control_deassert(port);
331}
332
333static void mt7621_pcie_reset_ep_deassert(struct mt7621_pcie *pcie)
334{
335	struct mt7621_pcie_port *port;
336
337	list_for_each_entry(port, &pcie->ports, list)
338		mt7621_rst_gpio_pcie_deassert(port);
339
340	msleep(PERST_DELAY_MS);
341}
342
343static int mt7621_pcie_init_ports(struct mt7621_pcie *pcie)
344{
345	struct device *dev = pcie->dev;
346	struct mt7621_pcie_port *port, *tmp;
347	u8 num_disabled = 0;
348	int err;
349
350	mt7621_pcie_reset_assert(pcie);
351	mt7621_pcie_reset_rc_deassert(pcie);
352
353	list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
354		u32 slot = port->slot;
355
356		if (slot == 1) {
357			port->enabled = true;
358			continue;
359		}
360
361		err = mt7621_pcie_init_port(port);
362		if (err) {
363			dev_err(dev, "initializing port %d failed\n", slot);
364			list_del(&port->list);
365		}
366	}
367
368	msleep(INIT_PORTS_DELAY_MS);
369	mt7621_pcie_reset_ep_deassert(pcie);
370
371	tmp = NULL;
372	list_for_each_entry(port, &pcie->ports, list) {
373		u32 slot = port->slot;
374
375		if (!mt7621_pcie_port_is_linkup(port)) {
376			dev_info(dev, "pcie%d no card, disable it (RST & CLK)\n",
377				 slot);
378			mt7621_control_assert(port);
379			port->enabled = false;
380			num_disabled++;
381
382			if (slot == 0) {
383				tmp = port;
384				continue;
385			}
386
387			if (slot == 1 && tmp && !tmp->enabled)
388				phy_power_off(tmp->phy);
389		}
390	}
391
392	return (num_disabled != PCIE_PORT_CNT) ? 0 : -ENODEV;
393}
394
395static void mt7621_pcie_enable_port(struct mt7621_pcie_port *port)
396{
397	struct mt7621_pcie *pcie = port->pcie;
398	u32 slot = port->slot;
399	u32 val;
400
401	/* enable pcie interrupt */
402	val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
403	val |= PCIE_PORT_INT_EN(slot);
404	pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
405
406	/* map 2G DDR region */
407	pcie_port_write(port, PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
408			PCI_BASE_ADDRESS_0);
409
410	/* configure class code and revision ID */
411	pcie_port_write(port, PCIE_CLASS_CODE | PCIE_REVISION_ID,
412			RALINK_PCI_CLASS);
413
414	/* configure RC FTS number to 250 when it leaves L0s */
415	val = read_config(pcie, slot, PCIE_FTS_NUM);
416	val &= ~PCIE_FTS_NUM_MASK;
417	val |= PCIE_FTS_NUM_L0(0x50);
418	write_config(pcie, slot, PCIE_FTS_NUM, val);
419}
420
421static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
422{
423	struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
424	struct device *dev = pcie->dev;
425	struct mt7621_pcie_port *port;
426	struct resource_entry *entry;
427	int err;
428
429	entry = resource_list_first_type(&host->windows, IORESOURCE_IO);
430	if (!entry) {
431		dev_err(dev, "cannot get io resource\n");
432		return -EINVAL;
433	}
434
435	/* Setup MEMWIN and IOWIN */
436	pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
437	pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
438
439	list_for_each_entry(port, &pcie->ports, list) {
440		if (port->enabled) {
441			err = clk_prepare_enable(port->clk);
442			if (err) {
443				dev_err(dev, "enabling clk pcie%d\n",
444					port->slot);
445				return err;
446			}
447
448			mt7621_pcie_enable_port(port);
449			dev_info(dev, "PCIE%d enabled\n", port->slot);
450		}
451	}
452
453	return 0;
454}
455
456static int mt7621_pcie_register_host(struct pci_host_bridge *host)
457{
458	struct mt7621_pcie *pcie = pci_host_bridge_priv(host);
459
460	host->ops = &mt7621_pcie_ops;
461	host->sysdata = pcie;
462	return pci_host_probe(host);
463}
464
465static const struct soc_device_attribute mt7621_pcie_quirks_match[] = {
466	{ .soc_id = "mt7621", .revision = "E2" },
467	{ /* sentinel */ }
468};
469
470static int mt7621_pcie_probe(struct platform_device *pdev)
471{
472	struct device *dev = &pdev->dev;
473	const struct soc_device_attribute *attr;
474	struct mt7621_pcie_port *port;
475	struct mt7621_pcie *pcie;
476	struct pci_host_bridge *bridge;
477	int err;
478
479	if (!dev->of_node)
480		return -ENODEV;
481
482	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
483	if (!bridge)
484		return -ENOMEM;
485
486	pcie = pci_host_bridge_priv(bridge);
487	pcie->dev = dev;
488	platform_set_drvdata(pdev, pcie);
489	INIT_LIST_HEAD(&pcie->ports);
490
491	attr = soc_device_match(mt7621_pcie_quirks_match);
492	if (attr)
493		pcie->resets_inverted = true;
494
495	err = mt7621_pcie_parse_dt(pcie);
496	if (err) {
497		dev_err(dev, "parsing DT failed\n");
498		return err;
499	}
500
501	err = mt7621_pcie_init_ports(pcie);
502	if (err) {
503		dev_err(dev, "nothing connected in virtual bridges\n");
504		return 0;
505	}
506
507	err = mt7621_pcie_enable_ports(bridge);
508	if (err) {
509		dev_err(dev, "error enabling pcie ports\n");
510		goto remove_resets;
511	}
512
513	return mt7621_pcie_register_host(bridge);
514
515remove_resets:
516	list_for_each_entry(port, &pcie->ports, list)
517		reset_control_put(port->pcie_rst);
518
519	return err;
520}
521
522static void mt7621_pcie_remove(struct platform_device *pdev)
523{
524	struct mt7621_pcie *pcie = platform_get_drvdata(pdev);
525	struct mt7621_pcie_port *port;
526
527	list_for_each_entry(port, &pcie->ports, list)
528		reset_control_put(port->pcie_rst);
529}
530
531static const struct of_device_id mt7621_pcie_ids[] = {
532	{ .compatible = "mediatek,mt7621-pci" },
533	{},
534};
535MODULE_DEVICE_TABLE(of, mt7621_pcie_ids);
536
537static struct platform_driver mt7621_pcie_driver = {
538	.probe = mt7621_pcie_probe,
539	.remove = mt7621_pcie_remove,
540	.driver = {
541		.name = "mt7621-pci",
542		.of_match_table = mt7621_pcie_ids,
543	},
544};
545builtin_platform_driver(mt7621_pcie_driver);
546
547MODULE_DESCRIPTION("MediaTek MT7621 PCIe host controller driver");
548MODULE_LICENSE("GPL v2");