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pcie-altera.c
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linux-6.19.14/drivers/pci/controller/pcie-altera.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved 4 * 5 * Author: Ley Foon Tan <lftan@altera.com> 6 * Description: Altera PCIe host controller driver 7 */ 8 9#include <linux/bitfield.h> 10#include <linux/delay.h> 11#include <linux/interrupt.h> 12#include <linux/irqchip/chained_irq.h> 13#include <linux/irqdomain.h> 14#include <linux/init.h> 15#include <linux/module.h> 16#include <linux/of.h> 17#include <linux/of_pci.h> 18#include <linux/pci.h> 19#include <linux/platform_device.h> 20#include <linux/slab.h> 21 22#include "../pci.h" 23 24#define RP_TX_REG0 0x2000 25#define RP_TX_REG1 0x2004 26#define RP_TX_CNTRL 0x2008 27#define RP_TX_EOP 0x2 28#define RP_TX_SOP 0x1 29#define RP_RXCPL_STATUS 0x2010 30#define RP_RXCPL_EOP 0x2 31#define RP_RXCPL_SOP 0x1 32#define RP_RXCPL_REG0 0x2014 33#define RP_RXCPL_REG1 0x2018 34#define P2A_INT_STATUS 0x3060 35#define P2A_INT_STS_ALL 0xf 36#define P2A_INT_ENABLE 0x3070 37#define P2A_INT_ENA_ALL 0xf 38#define RP_LTSSM 0x3c64 39#define RP_LTSSM_MASK 0x1f 40#define LTSSM_L0 0xf 41 42#define S10_RP_TX_CNTRL 0x2004 43#define S10_RP_RXCPL_REG 0x2008 44#define S10_RP_RXCPL_STATUS 0x200C 45#define S10_RP_CFG_ADDR(pcie, reg) \ 46 (((pcie)->hip_base) + (reg) + (1 << 20)) 47#define S10_RP_SECONDARY(pcie) \ 48 readb(S10_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) 49 50/* TLP configuration type 0 and 1 */ 51#define TLP_FMTTYPE_CFGRD0 0x04 /* Configuration Read Type 0 */ 52#define TLP_FMTTYPE_CFGWR0 0x44 /* Configuration Write Type 0 */ 53#define TLP_FMTTYPE_CFGRD1 0x05 /* Configuration Read Type 1 */ 54#define TLP_FMTTYPE_CFGWR1 0x45 /* Configuration Write Type 1 */ 55#define TLP_PAYLOAD_SIZE 0x01 56#define TLP_READ_TAG 0x1d 57#define TLP_WRITE_TAG 0x10 58#define RP_DEVFN 0 59#define TLP_CFG_DW0(pcie, cfg) \ 60 (((cfg) << 24) | \ 61 TLP_PAYLOAD_SIZE) 62#define TLP_CFG_DW1(pcie, tag, be) \ 63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be)) 64#define TLP_CFG_DW2(bus, devfn, offset) \ 65 (((bus) << 24) | ((devfn) << 16) | (offset)) 66#define TLP_COMP_STATUS(s) (((s) >> 13) & 7) 67#define TLP_BYTE_COUNT(s) (((s) >> 0) & 0xfff) 68#define TLP_HDR_SIZE 3 69#define TLP_LOOP 500 70 71#define LINK_UP_TIMEOUT HZ 72#define LINK_RETRAIN_TIMEOUT HZ 73 74#define DWORD_MASK 3 75 76#define S10_TLP_FMTTYPE_CFGRD0 0x05 77#define S10_TLP_FMTTYPE_CFGRD1 0x04 78#define S10_TLP_FMTTYPE_CFGWR0 0x45 79#define S10_TLP_FMTTYPE_CFGWR1 0x44 80 81#define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg)) 82#define AGLX_RP_SECONDARY(pcie) \ 83 readb(AGLX_RP_CFG_ADDR(pcie, PCI_SECONDARY_BUS)) 84 85#define AGLX_BDF_REG 0x00002004 86#define AGLX_ROOT_PORT_IRQ_STATUS 0x14c 87#define AGLX_ROOT_PORT_IRQ_ENABLE 0x150 88#define CFG_AER BIT(4) 89 90#define AGLX_CFG_TARGET GENMASK(13, 12) 91#define AGLX_CFG_TARGET_TYPE0 0 92#define AGLX_CFG_TARGET_TYPE1 1 93#define AGLX_CFG_TARGET_LOCAL_2000 2 94#define AGLX_CFG_TARGET_LOCAL_3000 3 95 96enum altera_pcie_version { 97 ALTERA_PCIE_V1 = 0, 98 ALTERA_PCIE_V2, 99 ALTERA_PCIE_V3, 100}; 101 102struct altera_pcie { 103 struct platform_device *pdev; 104 void __iomem *cra_base; 105 void __iomem *hip_base; 106 int irq; 107 u8 root_bus_nr; 108 struct irq_domain *irq_domain; 109 struct resource bus_range; 110 const struct altera_pcie_data *pcie_data; 111}; 112 113struct altera_pcie_ops { 114 int (*tlp_read_pkt)(struct altera_pcie *pcie, u32 *value); 115 void (*tlp_write_pkt)(struct altera_pcie *pcie, u32 *headers, 116 u32 data, bool align); 117 bool (*get_link_status)(struct altera_pcie *pcie); 118 int (*rp_read_cfg)(struct altera_pcie *pcie, int where, 119 int size, u32 *value); 120 int (*rp_write_cfg)(struct altera_pcie *pcie, u8 busno, 121 int where, int size, u32 value); 122 int (*ep_read_cfg)(struct altera_pcie *pcie, u8 busno, 123 unsigned int devfn, int where, int size, u32 *value); 124 int (*ep_write_cfg)(struct altera_pcie *pcie, u8 busno, 125 unsigned int devfn, int where, int size, u32 value); 126 void (*rp_isr)(struct irq_desc *desc); 127}; 128 129struct altera_pcie_data { 130 const struct altera_pcie_ops *ops; 131 enum altera_pcie_version version; 132 u32 cap_offset; /* PCIe capability structure register offset */ 133 u32 cfgrd0; 134 u32 cfgrd1; 135 u32 cfgwr0; 136 u32 cfgwr1; 137 u32 port_conf_offset; 138 u32 port_irq_status_offset; 139 u32 port_irq_enable_offset; 140}; 141 142struct tlp_rp_regpair_t { 143 u32 ctrl; 144 u32 reg0; 145 u32 reg1; 146}; 147 148static inline void cra_writel(struct altera_pcie *pcie, const u32 value, 149 const u32 reg) 150{ 151 writel_relaxed(value, pcie->cra_base + reg); 152} 153 154static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg) 155{ 156 return readl_relaxed(pcie->cra_base + reg); 157} 158 159static inline void cra_writew(struct altera_pcie *pcie, const u32 value, 160 const u32 reg) 161{ 162 writew_relaxed(value, pcie->cra_base + reg); 163} 164 165static inline u32 cra_readw(struct altera_pcie *pcie, const u32 reg) 166{ 167 return readw_relaxed(pcie->cra_base + reg); 168} 169 170static inline void cra_writeb(struct altera_pcie *pcie, const u32 value, 171 const u32 reg) 172{ 173 writeb_relaxed(value, pcie->cra_base + reg); 174} 175 176static inline u32 cra_readb(struct altera_pcie *pcie, const u32 reg) 177{ 178 return readb_relaxed(pcie->cra_base + reg); 179} 180 181static bool altera_pcie_link_up(struct altera_pcie *pcie) 182{ 183 return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0); 184} 185 186static bool s10_altera_pcie_link_up(struct altera_pcie *pcie) 187{ 188 void __iomem *addr = S10_RP_CFG_ADDR(pcie, 189 pcie->pcie_data->cap_offset + 190 PCI_EXP_LNKSTA); 191 192 return !!(readw(addr) & PCI_EXP_LNKSTA_DLLLA); 193} 194 195static bool aglx_altera_pcie_link_up(struct altera_pcie *pcie) 196{ 197 void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, 198 pcie->pcie_data->cap_offset + 199 PCI_EXP_LNKSTA); 200 201 return (readw_relaxed(addr) & PCI_EXP_LNKSTA_DLLLA); 202} 203 204/* 205 * Altera PCIe port uses BAR0 of RC's configuration space as the translation 206 * from PCI bus to native BUS. Entire DDR region is mapped into PCIe space 207 * using these registers, so it can be reached by DMA from EP devices. 208 * This BAR0 will also access to MSI vector when receiving MSI/MSI-X interrupt 209 * from EP devices, eventually trigger interrupt to GIC. The BAR0 of bridge 210 * should be hidden during enumeration to avoid the sizing and resource 211 * allocation by PCIe core. 212 */ 213static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn, 214 int offset) 215{ 216 if (pci_is_root_bus(bus) && (devfn == 0) && 217 (offset == PCI_BASE_ADDRESS_0)) 218 return true; 219 220 return false; 221} 222 223static void tlp_write_tx(struct altera_pcie *pcie, 224 struct tlp_rp_regpair_t *tlp_rp_regdata) 225{ 226 cra_writel(pcie, tlp_rp_regdata->reg0, RP_TX_REG0); 227 cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); 228 cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL); 229} 230 231static void s10_tlp_write_tx(struct altera_pcie *pcie, u32 reg0, u32 ctrl) 232{ 233 cra_writel(pcie, reg0, RP_TX_REG0); 234 cra_writel(pcie, ctrl, S10_RP_TX_CNTRL); 235} 236 237static bool altera_pcie_valid_device(struct altera_pcie *pcie, 238 struct pci_bus *bus, int dev) 239{ 240 /* If there is no link, then there is no device */ 241 if (bus->number != pcie->root_bus_nr) { 242 if (!pcie->pcie_data->ops->get_link_status(pcie)) 243 return false; 244 } 245 246 /* access only one slot on each root port */ 247 if (bus->number == pcie->root_bus_nr && dev > 0) 248 return false; 249 250 return true; 251} 252 253static int tlp_read_packet(struct altera_pcie *pcie, u32 *value) 254{ 255 int i; 256 bool sop = false; 257 u32 ctrl; 258 u32 reg0, reg1; 259 u32 comp_status = 1; 260 261 /* 262 * Minimum 2 loops to read TLP headers and 1 loop to read data 263 * payload. 264 */ 265 for (i = 0; i < TLP_LOOP; i++) { 266 ctrl = cra_readl(pcie, RP_RXCPL_STATUS); 267 if ((ctrl & RP_RXCPL_SOP) || (ctrl & RP_RXCPL_EOP) || sop) { 268 reg0 = cra_readl(pcie, RP_RXCPL_REG0); 269 reg1 = cra_readl(pcie, RP_RXCPL_REG1); 270 271 if (ctrl & RP_RXCPL_SOP) { 272 sop = true; 273 comp_status = TLP_COMP_STATUS(reg1); 274 } 275 276 if (ctrl & RP_RXCPL_EOP) { 277 if (comp_status) 278 return PCIBIOS_DEVICE_NOT_FOUND; 279 280 if (value) 281 *value = reg0; 282 283 return PCIBIOS_SUCCESSFUL; 284 } 285 } 286 udelay(5); 287 } 288 289 return PCIBIOS_DEVICE_NOT_FOUND; 290} 291 292static int s10_tlp_read_packet(struct altera_pcie *pcie, u32 *value) 293{ 294 u32 ctrl; 295 u32 comp_status; 296 u32 dw[4]; 297 u32 count; 298 struct device *dev = &pcie->pdev->dev; 299 300 for (count = 0; count < TLP_LOOP; count++) { 301 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); 302 if (ctrl & RP_RXCPL_SOP) { 303 /* Read first DW */ 304 dw[0] = cra_readl(pcie, S10_RP_RXCPL_REG); 305 break; 306 } 307 308 udelay(5); 309 } 310 311 /* SOP detection failed, return error */ 312 if (count == TLP_LOOP) 313 return PCIBIOS_DEVICE_NOT_FOUND; 314 315 count = 1; 316 317 /* Poll for EOP */ 318 while (count < ARRAY_SIZE(dw)) { 319 ctrl = cra_readl(pcie, S10_RP_RXCPL_STATUS); 320 dw[count++] = cra_readl(pcie, S10_RP_RXCPL_REG); 321 if (ctrl & RP_RXCPL_EOP) { 322 comp_status = TLP_COMP_STATUS(dw[1]); 323 if (comp_status) 324 return PCIBIOS_DEVICE_NOT_FOUND; 325 326 if (value && TLP_BYTE_COUNT(dw[1]) == sizeof(u32) && 327 count == 4) 328 *value = dw[3]; 329 330 return PCIBIOS_SUCCESSFUL; 331 } 332 } 333 334 dev_warn(dev, "Malformed TLP packet\n"); 335 336 return PCIBIOS_DEVICE_NOT_FOUND; 337} 338 339static void tlp_write_packet(struct altera_pcie *pcie, u32 *headers, 340 u32 data, bool align) 341{ 342 struct tlp_rp_regpair_t tlp_rp_regdata; 343 344 tlp_rp_regdata.reg0 = headers[0]; 345 tlp_rp_regdata.reg1 = headers[1]; 346 tlp_rp_regdata.ctrl = RP_TX_SOP; 347 tlp_write_tx(pcie, &tlp_rp_regdata); 348 349 if (align) { 350 tlp_rp_regdata.reg0 = headers[2]; 351 tlp_rp_regdata.reg1 = 0; 352 tlp_rp_regdata.ctrl = 0; 353 tlp_write_tx(pcie, &tlp_rp_regdata); 354 355 tlp_rp_regdata.reg0 = data; 356 tlp_rp_regdata.reg1 = 0; 357 } else { 358 tlp_rp_regdata.reg0 = headers[2]; 359 tlp_rp_regdata.reg1 = data; 360 } 361 362 tlp_rp_regdata.ctrl = RP_TX_EOP; 363 tlp_write_tx(pcie, &tlp_rp_regdata); 364} 365 366static void s10_tlp_write_packet(struct altera_pcie *pcie, u32 *headers, 367 u32 data, bool dummy) 368{ 369 s10_tlp_write_tx(pcie, headers[0], RP_TX_SOP); 370 s10_tlp_write_tx(pcie, headers[1], 0); 371 s10_tlp_write_tx(pcie, headers[2], 0); 372 s10_tlp_write_tx(pcie, data, RP_TX_EOP); 373} 374 375static void get_tlp_header(struct altera_pcie *pcie, u8 bus, u32 devfn, 376 int where, u8 byte_en, bool read, u32 *headers) 377{ 378 u8 cfg; 379 u8 cfg0 = read ? pcie->pcie_data->cfgrd0 : pcie->pcie_data->cfgwr0; 380 u8 cfg1 = read ? pcie->pcie_data->cfgrd1 : pcie->pcie_data->cfgwr1; 381 u8 tag = read ? TLP_READ_TAG : TLP_WRITE_TAG; 382 383 if (pcie->pcie_data->version == ALTERA_PCIE_V1) 384 cfg = (bus == pcie->root_bus_nr) ? cfg0 : cfg1; 385 else 386 cfg = (bus > S10_RP_SECONDARY(pcie)) ? cfg0 : cfg1; 387 388 headers[0] = TLP_CFG_DW0(pcie, cfg); 389 headers[1] = TLP_CFG_DW1(pcie, tag, byte_en); 390 headers[2] = TLP_CFG_DW2(bus, devfn, where); 391} 392 393static int tlp_cfg_dword_read(struct altera_pcie *pcie, u8 bus, u32 devfn, 394 int where, u8 byte_en, u32 *value) 395{ 396 u32 headers[TLP_HDR_SIZE]; 397 398 get_tlp_header(pcie, bus, devfn, where, byte_en, true, 399 headers); 400 401 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 0, false); 402 403 return pcie->pcie_data->ops->tlp_read_pkt(pcie, value); 404} 405 406static int tlp_cfg_dword_write(struct altera_pcie *pcie, u8 bus, u32 devfn, 407 int where, u8 byte_en, u32 value) 408{ 409 u32 headers[TLP_HDR_SIZE]; 410 int ret; 411 412 get_tlp_header(pcie, bus, devfn, where, byte_en, false, 413 headers); 414 415 /* check alignment to Qword */ 416 if ((where & 0x7) == 0) 417 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 418 value, true); 419 else 420 pcie->pcie_data->ops->tlp_write_pkt(pcie, headers, 421 value, false); 422 423 ret = pcie->pcie_data->ops->tlp_read_pkt(pcie, NULL); 424 if (ret != PCIBIOS_SUCCESSFUL) 425 return ret; 426 427 /* 428 * Monitor changes to PCI_PRIMARY_BUS register on root port 429 * and update local copy of root bus number accordingly. 430 */ 431 if ((bus == pcie->root_bus_nr) && (where == PCI_PRIMARY_BUS)) 432 pcie->root_bus_nr = (u8)(value); 433 434 return PCIBIOS_SUCCESSFUL; 435} 436 437static int s10_rp_read_cfg(struct altera_pcie *pcie, int where, 438 int size, u32 *value) 439{ 440 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); 441 442 switch (size) { 443 case 1: 444 *value = readb(addr); 445 break; 446 case 2: 447 *value = readw(addr); 448 break; 449 default: 450 *value = readl(addr); 451 break; 452 } 453 454 return PCIBIOS_SUCCESSFUL; 455} 456 457static int s10_rp_write_cfg(struct altera_pcie *pcie, u8 busno, 458 int where, int size, u32 value) 459{ 460 void __iomem *addr = S10_RP_CFG_ADDR(pcie, where); 461 462 switch (size) { 463 case 1: 464 writeb(value, addr); 465 break; 466 case 2: 467 writew(value, addr); 468 break; 469 default: 470 writel(value, addr); 471 break; 472 } 473 474 /* 475 * Monitor changes to PCI_PRIMARY_BUS register on root port 476 * and update local copy of root bus number accordingly. 477 */ 478 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS) 479 pcie->root_bus_nr = value & 0xff; 480 481 return PCIBIOS_SUCCESSFUL; 482} 483 484static int aglx_rp_read_cfg(struct altera_pcie *pcie, int where, 485 int size, u32 *value) 486{ 487 void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where); 488 489 switch (size) { 490 case 1: 491 *value = readb_relaxed(addr); 492 break; 493 case 2: 494 *value = readw_relaxed(addr); 495 break; 496 default: 497 *value = readl_relaxed(addr); 498 break; 499 } 500 501 /* Interrupt PIN not programmed in hardware, set to INTA. */ 502 if (where == PCI_INTERRUPT_PIN && size == 1 && !(*value)) 503 *value = 0x01; 504 else if (where == PCI_INTERRUPT_LINE && !(*value & 0xff00)) 505 *value |= 0x0100; 506 507 return PCIBIOS_SUCCESSFUL; 508} 509 510static int aglx_rp_write_cfg(struct altera_pcie *pcie, u8 busno, 511 int where, int size, u32 value) 512{ 513 void __iomem *addr = AGLX_RP_CFG_ADDR(pcie, where); 514 515 switch (size) { 516 case 1: 517 writeb_relaxed(value, addr); 518 break; 519 case 2: 520 writew_relaxed(value, addr); 521 break; 522 default: 523 writel_relaxed(value, addr); 524 break; 525 } 526 527 /* 528 * Monitor changes to PCI_PRIMARY_BUS register on Root Port 529 * and update local copy of root bus number accordingly. 530 */ 531 if (busno == pcie->root_bus_nr && where == PCI_PRIMARY_BUS) 532 pcie->root_bus_nr = value & 0xff; 533 534 return PCIBIOS_SUCCESSFUL; 535} 536 537static int aglx_ep_write_cfg(struct altera_pcie *pcie, u8 busno, 538 unsigned int devfn, int where, int size, u32 value) 539{ 540 cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG); 541 if (busno > AGLX_RP_SECONDARY(pcie)) 542 where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1); 543 544 switch (size) { 545 case 1: 546 cra_writeb(pcie, value, where); 547 break; 548 case 2: 549 cra_writew(pcie, value, where); 550 break; 551 default: 552 cra_writel(pcie, value, where); 553 break; 554 } 555 556 return PCIBIOS_SUCCESSFUL; 557} 558 559static int aglx_ep_read_cfg(struct altera_pcie *pcie, u8 busno, 560 unsigned int devfn, int where, int size, u32 *value) 561{ 562 cra_writel(pcie, ((busno << 8) | devfn), AGLX_BDF_REG); 563 if (busno > AGLX_RP_SECONDARY(pcie)) 564 where |= FIELD_PREP(AGLX_CFG_TARGET, AGLX_CFG_TARGET_TYPE1); 565 566 switch (size) { 567 case 1: 568 *value = cra_readb(pcie, where); 569 break; 570 case 2: 571 *value = cra_readw(pcie, where); 572 break; 573 default: 574 *value = cra_readl(pcie, where); 575 break; 576 } 577 578 return PCIBIOS_SUCCESSFUL; 579} 580 581static int _altera_pcie_cfg_read(struct altera_pcie *pcie, u8 busno, 582 unsigned int devfn, int where, int size, 583 u32 *value) 584{ 585 int ret; 586 u32 data; 587 u8 byte_en; 588 589 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_read_cfg) 590 return pcie->pcie_data->ops->rp_read_cfg(pcie, where, 591 size, value); 592 593 if (pcie->pcie_data->ops->ep_read_cfg) 594 return pcie->pcie_data->ops->ep_read_cfg(pcie, busno, devfn, 595 where, size, value); 596 597 switch (size) { 598 case 1: 599 byte_en = 1 << (where & 3); 600 break; 601 case 2: 602 byte_en = 3 << (where & 3); 603 break; 604 default: 605 byte_en = 0xf; 606 break; 607 } 608 609 ret = tlp_cfg_dword_read(pcie, busno, devfn, 610 (where & ~DWORD_MASK), byte_en, &data); 611 if (ret != PCIBIOS_SUCCESSFUL) 612 return ret; 613 614 switch (size) { 615 case 1: 616 *value = (data >> (8 * (where & 0x3))) & 0xff; 617 break; 618 case 2: 619 *value = (data >> (8 * (where & 0x2))) & 0xffff; 620 break; 621 default: 622 *value = data; 623 break; 624 } 625 626 return PCIBIOS_SUCCESSFUL; 627} 628 629static int _altera_pcie_cfg_write(struct altera_pcie *pcie, u8 busno, 630 unsigned int devfn, int where, int size, 631 u32 value) 632{ 633 u32 data32; 634 u32 shift = 8 * (where & 3); 635 u8 byte_en; 636 637 if (busno == pcie->root_bus_nr && pcie->pcie_data->ops->rp_write_cfg) 638 return pcie->pcie_data->ops->rp_write_cfg(pcie, busno, 639 where, size, value); 640 641 if (pcie->pcie_data->ops->ep_write_cfg) 642 return pcie->pcie_data->ops->ep_write_cfg(pcie, busno, devfn, 643 where, size, value); 644 645 switch (size) { 646 case 1: 647 data32 = (value & 0xff) << shift; 648 byte_en = 1 << (where & 3); 649 break; 650 case 2: 651 data32 = (value & 0xffff) << shift; 652 byte_en = 3 << (where & 3); 653 break; 654 default: 655 data32 = value; 656 byte_en = 0xf; 657 break; 658 } 659 660 return tlp_cfg_dword_write(pcie, busno, devfn, (where & ~DWORD_MASK), 661 byte_en, data32); 662} 663 664static int altera_pcie_cfg_read(struct pci_bus *bus, unsigned int devfn, 665 int where, int size, u32 *value) 666{ 667 struct altera_pcie *pcie = bus->sysdata; 668 669 if (altera_pcie_hide_rc_bar(bus, devfn, where)) 670 return PCIBIOS_BAD_REGISTER_NUMBER; 671 672 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) 673 return PCIBIOS_DEVICE_NOT_FOUND; 674 675 return _altera_pcie_cfg_read(pcie, bus->number, devfn, where, size, 676 value); 677} 678 679static int altera_pcie_cfg_write(struct pci_bus *bus, unsigned int devfn, 680 int where, int size, u32 value) 681{ 682 struct altera_pcie *pcie = bus->sysdata; 683 684 if (altera_pcie_hide_rc_bar(bus, devfn, where)) 685 return PCIBIOS_BAD_REGISTER_NUMBER; 686 687 if (!altera_pcie_valid_device(pcie, bus, PCI_SLOT(devfn))) 688 return PCIBIOS_DEVICE_NOT_FOUND; 689 690 return _altera_pcie_cfg_write(pcie, bus->number, devfn, where, size, 691 value); 692} 693 694static struct pci_ops altera_pcie_ops = { 695 .read = altera_pcie_cfg_read, 696 .write = altera_pcie_cfg_write, 697}; 698 699static int altera_read_cap_word(struct altera_pcie *pcie, u8 busno, 700 unsigned int devfn, int offset, u16 *value) 701{ 702 u32 data; 703 int ret; 704 705 ret = _altera_pcie_cfg_read(pcie, busno, devfn, 706 pcie->pcie_data->cap_offset + offset, 707 sizeof(*value), 708 &data); 709 *value = data; 710 return ret; 711} 712 713static int altera_write_cap_word(struct altera_pcie *pcie, u8 busno, 714 unsigned int devfn, int offset, u16 value) 715{ 716 return _altera_pcie_cfg_write(pcie, busno, devfn, 717 pcie->pcie_data->cap_offset + offset, 718 sizeof(value), 719 value); 720} 721 722static void altera_wait_link_retrain(struct altera_pcie *pcie) 723{ 724 struct device *dev = &pcie->pdev->dev; 725 u16 reg16; 726 unsigned long start_jiffies; 727 728 /* Wait for link training end. */ 729 start_jiffies = jiffies; 730 for (;;) { 731 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, 732 PCI_EXP_LNKSTA, ®16); 733 if (!(reg16 & PCI_EXP_LNKSTA_LT)) 734 break; 735 736 if (time_after(jiffies, start_jiffies + LINK_RETRAIN_TIMEOUT)) { 737 dev_err(dev, "link retrain timeout\n"); 738 break; 739 } 740 udelay(100); 741 } 742 743 /* Wait for link is up */ 744 start_jiffies = jiffies; 745 for (;;) { 746 if (pcie->pcie_data->ops->get_link_status(pcie)) 747 break; 748 749 if (time_after(jiffies, start_jiffies + LINK_UP_TIMEOUT)) { 750 dev_err(dev, "link up timeout\n"); 751 break; 752 } 753 udelay(100); 754 } 755} 756 757static void altera_pcie_retrain(struct altera_pcie *pcie) 758{ 759 u16 linkcap, linkstat, linkctl; 760 761 if (!pcie->pcie_data->ops->get_link_status(pcie)) 762 return; 763 764 /* 765 * Set the retrain bit if the PCIe rootport support > 2.5GB/s, but 766 * current speed is 2.5 GB/s. 767 */ 768 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKCAP, 769 &linkcap); 770 if ((linkcap & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) 771 return; 772 773 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, PCI_EXP_LNKSTA, 774 &linkstat); 775 if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { 776 altera_read_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, 777 PCI_EXP_LNKCTL, &linkctl); 778 linkctl |= PCI_EXP_LNKCTL_RL; 779 altera_write_cap_word(pcie, pcie->root_bus_nr, RP_DEVFN, 780 PCI_EXP_LNKCTL, linkctl); 781 782 altera_wait_link_retrain(pcie); 783 } 784} 785 786static int altera_pcie_intx_map(struct irq_domain *domain, unsigned int irq, 787 irq_hw_number_t hwirq) 788{ 789 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq); 790 irq_set_chip_data(irq, domain->host_data); 791 return 0; 792} 793 794static const struct irq_domain_ops intx_domain_ops = { 795 .map = altera_pcie_intx_map, 796 .xlate = pci_irqd_intx_xlate, 797}; 798 799static void altera_pcie_isr(struct irq_desc *desc) 800{ 801 struct irq_chip *chip = irq_desc_get_chip(desc); 802 struct altera_pcie *pcie; 803 struct device *dev; 804 unsigned long status; 805 u32 bit; 806 int ret; 807 808 chained_irq_enter(chip, desc); 809 pcie = irq_desc_get_handler_data(desc); 810 dev = &pcie->pdev->dev; 811 812 while ((status = cra_readl(pcie, P2A_INT_STATUS) 813 & P2A_INT_STS_ALL) != 0) { 814 for_each_set_bit(bit, &status, PCI_NUM_INTX) { 815 /* clear interrupts */ 816 cra_writel(pcie, 1 << bit, P2A_INT_STATUS); 817 818 ret = generic_handle_domain_irq(pcie->irq_domain, bit); 819 if (ret) 820 dev_err_ratelimited(dev, "unexpected IRQ, INT%d\n", bit); 821 } 822 } 823 chained_irq_exit(chip, desc); 824} 825 826static void aglx_isr(struct irq_desc *desc) 827{ 828 struct irq_chip *chip = irq_desc_get_chip(desc); 829 struct altera_pcie *pcie; 830 struct device *dev; 831 u32 status; 832 int ret; 833 834 chained_irq_enter(chip, desc); 835 pcie = irq_desc_get_handler_data(desc); 836 dev = &pcie->pdev->dev; 837 838 status = readl(pcie->hip_base + pcie->pcie_data->port_conf_offset + 839 pcie->pcie_data->port_irq_status_offset); 840 841 if (status & CFG_AER) { 842 writel(CFG_AER, (pcie->hip_base + pcie->pcie_data->port_conf_offset + 843 pcie->pcie_data->port_irq_status_offset)); 844 845 ret = generic_handle_domain_irq(pcie->irq_domain, 0); 846 if (ret) 847 dev_err_ratelimited(dev, "unexpected IRQ %d\n", pcie->irq); 848 } 849 chained_irq_exit(chip, desc); 850} 851 852static int altera_pcie_init_irq_domain(struct altera_pcie *pcie) 853{ 854 struct device *dev = &pcie->pdev->dev; 855 856 /* Setup INTx */ 857 pcie->irq_domain = irq_domain_create_linear(dev_fwnode(dev), PCI_NUM_INTX, 858 &intx_domain_ops, pcie); 859 if (!pcie->irq_domain) { 860 dev_err(dev, "Failed to get a INTx IRQ domain\n"); 861 return -ENOMEM; 862 } 863 864 return 0; 865} 866 867static void altera_pcie_irq_teardown(struct altera_pcie *pcie) 868{ 869 irq_set_chained_handler_and_data(pcie->irq, NULL, NULL); 870 irq_domain_remove(pcie->irq_domain); 871 irq_dispose_mapping(pcie->irq); 872} 873 874static int altera_pcie_parse_dt(struct altera_pcie *pcie) 875{ 876 struct platform_device *pdev = pcie->pdev; 877 878 pcie->cra_base = devm_platform_ioremap_resource_byname(pdev, "Cra"); 879 if (IS_ERR(pcie->cra_base)) 880 return PTR_ERR(pcie->cra_base); 881 882 if (pcie->pcie_data->version == ALTERA_PCIE_V2 || 883 pcie->pcie_data->version == ALTERA_PCIE_V3) { 884 pcie->hip_base = devm_platform_ioremap_resource_byname(pdev, "Hip"); 885 if (IS_ERR(pcie->hip_base)) 886 return PTR_ERR(pcie->hip_base); 887 } 888 889 /* setup IRQ */ 890 pcie->irq = platform_get_irq(pdev, 0); 891 if (pcie->irq < 0) 892 return pcie->irq; 893 894 irq_set_chained_handler_and_data(pcie->irq, pcie->pcie_data->ops->rp_isr, pcie); 895 return 0; 896} 897 898static void altera_pcie_host_init(struct altera_pcie *pcie) 899{ 900 altera_pcie_retrain(pcie); 901} 902 903static const struct altera_pcie_ops altera_pcie_ops_1_0 = { 904 .tlp_read_pkt = tlp_read_packet, 905 .tlp_write_pkt = tlp_write_packet, 906 .get_link_status = altera_pcie_link_up, 907 .rp_isr = altera_pcie_isr, 908}; 909 910static const struct altera_pcie_ops altera_pcie_ops_2_0 = { 911 .tlp_read_pkt = s10_tlp_read_packet, 912 .tlp_write_pkt = s10_tlp_write_packet, 913 .get_link_status = s10_altera_pcie_link_up, 914 .rp_read_cfg = s10_rp_read_cfg, 915 .rp_write_cfg = s10_rp_write_cfg, 916 .rp_isr = altera_pcie_isr, 917}; 918 919static const struct altera_pcie_ops altera_pcie_ops_3_0 = { 920 .rp_read_cfg = aglx_rp_read_cfg, 921 .rp_write_cfg = aglx_rp_write_cfg, 922 .get_link_status = aglx_altera_pcie_link_up, 923 .ep_read_cfg = aglx_ep_read_cfg, 924 .ep_write_cfg = aglx_ep_write_cfg, 925 .rp_isr = aglx_isr, 926}; 927 928static const struct altera_pcie_data altera_pcie_1_0_data = { 929 .ops = &altera_pcie_ops_1_0, 930 .cap_offset = 0x80, 931 .version = ALTERA_PCIE_V1, 932 .cfgrd0 = TLP_FMTTYPE_CFGRD0, 933 .cfgrd1 = TLP_FMTTYPE_CFGRD1, 934 .cfgwr0 = TLP_FMTTYPE_CFGWR0, 935 .cfgwr1 = TLP_FMTTYPE_CFGWR1, 936}; 937 938static const struct altera_pcie_data altera_pcie_2_0_data = { 939 .ops = &altera_pcie_ops_2_0, 940 .version = ALTERA_PCIE_V2, 941 .cap_offset = 0x70, 942 .cfgrd0 = S10_TLP_FMTTYPE_CFGRD0, 943 .cfgrd1 = S10_TLP_FMTTYPE_CFGRD1, 944 .cfgwr0 = S10_TLP_FMTTYPE_CFGWR0, 945 .cfgwr1 = S10_TLP_FMTTYPE_CFGWR1, 946}; 947 948static const struct altera_pcie_data altera_pcie_3_0_f_tile_data = { 949 .ops = &altera_pcie_ops_3_0, 950 .version = ALTERA_PCIE_V3, 951 .cap_offset = 0x70, 952 .port_conf_offset = 0x14000, 953 .port_irq_status_offset = AGLX_ROOT_PORT_IRQ_STATUS, 954 .port_irq_enable_offset = AGLX_ROOT_PORT_IRQ_ENABLE, 955}; 956 957static const struct altera_pcie_data altera_pcie_3_0_p_tile_data = { 958 .ops = &altera_pcie_ops_3_0, 959 .version = ALTERA_PCIE_V3, 960 .cap_offset = 0x70, 961 .port_conf_offset = 0x104000, 962 .port_irq_status_offset = AGLX_ROOT_PORT_IRQ_STATUS, 963 .port_irq_enable_offset = AGLX_ROOT_PORT_IRQ_ENABLE, 964}; 965 966static const struct altera_pcie_data altera_pcie_3_0_r_tile_data = { 967 .ops = &altera_pcie_ops_3_0, 968 .version = ALTERA_PCIE_V3, 969 .cap_offset = 0x70, 970 .port_conf_offset = 0x1300, 971 .port_irq_status_offset = 0x0, 972 .port_irq_enable_offset = 0x4, 973}; 974 975static const struct of_device_id altera_pcie_of_match[] = { 976 {.compatible = "altr,pcie-root-port-1.0", 977 .data = &altera_pcie_1_0_data }, 978 {.compatible = "altr,pcie-root-port-2.0", 979 .data = &altera_pcie_2_0_data }, 980 {.compatible = "altr,pcie-root-port-3.0-f-tile", 981 .data = &altera_pcie_3_0_f_tile_data }, 982 {.compatible = "altr,pcie-root-port-3.0-p-tile", 983 .data = &altera_pcie_3_0_p_tile_data }, 984 {.compatible = "altr,pcie-root-port-3.0-r-tile", 985 .data = &altera_pcie_3_0_r_tile_data }, 986 {}, 987}; 988 989static int altera_pcie_probe(struct platform_device *pdev) 990{ 991 struct device *dev = &pdev->dev; 992 struct altera_pcie *pcie; 993 struct pci_host_bridge *bridge; 994 int ret; 995 const struct altera_pcie_data *data; 996 997 bridge = devm_pci_alloc_host_bridge(dev, sizeof(*pcie)); 998 if (!bridge) 999 return -ENOMEM; 1000 1001 pcie = pci_host_bridge_priv(bridge); 1002 pcie->pdev = pdev; 1003 platform_set_drvdata(pdev, pcie); 1004 1005 data = of_device_get_match_data(&pdev->dev); 1006 if (!data) 1007 return -ENODEV; 1008 1009 pcie->pcie_data = data; 1010 1011 ret = altera_pcie_parse_dt(pcie); 1012 if (ret) { 1013 dev_err(dev, "Parsing DT failed\n"); 1014 return ret; 1015 } 1016 1017 ret = altera_pcie_init_irq_domain(pcie); 1018 if (ret) { 1019 dev_err(dev, "Failed creating IRQ Domain\n"); 1020 return ret; 1021 } 1022 1023 if (pcie->pcie_data->version == ALTERA_PCIE_V1 || 1024 pcie->pcie_data->version == ALTERA_PCIE_V2) { 1025 /* clear all interrupts */ 1026 cra_writel(pcie, P2A_INT_STS_ALL, P2A_INT_STATUS); 1027 /* enable all interrupts */ 1028 cra_writel(pcie, P2A_INT_ENA_ALL, P2A_INT_ENABLE); 1029 altera_pcie_host_init(pcie); 1030 } else if (pcie->pcie_data->version == ALTERA_PCIE_V3) { 1031 writel(CFG_AER, 1032 pcie->hip_base + pcie->pcie_data->port_conf_offset + 1033 pcie->pcie_data->port_irq_enable_offset); 1034 } 1035 1036 bridge->sysdata = pcie; 1037 bridge->busnr = pcie->root_bus_nr; 1038 bridge->ops = &altera_pcie_ops; 1039 1040 return pci_host_probe(bridge); 1041} 1042 1043static void altera_pcie_remove(struct platform_device *pdev) 1044{ 1045 struct altera_pcie *pcie = platform_get_drvdata(pdev); 1046 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); 1047 1048 pci_stop_root_bus(bridge->bus); 1049 pci_remove_root_bus(bridge->bus); 1050 altera_pcie_irq_teardown(pcie); 1051} 1052 1053static struct platform_driver altera_pcie_driver = { 1054 .probe = altera_pcie_probe, 1055 .remove = altera_pcie_remove, 1056 .driver = { 1057 .name = "altera-pcie", 1058 .of_match_table = altera_pcie_of_match, 1059 }, 1060}; 1061 1062MODULE_DEVICE_TABLE(of, altera_pcie_of_match); 1063module_platform_driver(altera_pcie_driver); 1064MODULE_DESCRIPTION("Altera PCIe host controller driver"); 1065MODULE_LICENSE("GPL v2");
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