pci-xgene.c

  1// SPDX-License-Identifier: GPL-2.0+
  2/*
  3 * APM X-Gene PCIe Driver
  4 *
  5 * Copyright (c) 2014 Applied Micro Circuits Corporation.
  6 *
  7 * Author: Tanmay Inamdar <tinamdar@apm.com>.
  8 */
  9#include <linux/clk.h>
 10#include <linux/delay.h>
 11#include <linux/io.h>
 12#include <linux/jiffies.h>
 13#include <linux/memblock.h>
 14#include <linux/init.h>
 15#include <linux/irqdomain.h>
 16#include <linux/of.h>
 17#include <linux/of_address.h>
 18#include <linux/of_pci.h>
 19#include <linux/pci.h>
 20#include <linux/pci-acpi.h>
 21#include <linux/pci-ecam.h>
 22#include <linux/platform_device.h>
 23#include <linux/slab.h>
 24
 25#include "../pci.h"
 26
 27#define PCIECORE_CTLANDSTATUS		0x50
 28#define PIM1_1L				0x80
 29#define IBAR2				0x98
 30#define IR2MSK				0x9c
 31#define PIM2_1L				0xa0
 32#define IBAR3L				0xb4
 33#define IR3MSKL				0xbc
 34#define PIM3_1L				0xc4
 35#define OMR1BARL			0x100
 36#define OMR2BARL			0x118
 37#define OMR3BARL			0x130
 38#define CFGBARL				0x154
 39#define CFGBARH				0x158
 40#define CFGCTL				0x15c
 41#define RTDID				0x160
 42#define BRIDGE_CFG_0			0x2000
 43#define BRIDGE_CFG_4			0x2010
 44#define BRIDGE_STATUS_0			0x2600
 45
 46#define LINK_UP_MASK			0x00000100
 47#define AXI_EP_CFG_ACCESS		0x10000
 48#define EN_COHERENCY			0xF0000000
 49#define EN_REG				0x00000001
 50#define OB_LO_IO			0x00000002
 51#define XGENE_PCIE_DEVICEID		0xE004
 52#define PIPE_PHY_RATE_RD(src)		((0xc000 & (u32)(src)) >> 0xe)
 53
 54#define XGENE_V1_PCI_EXP_CAP		0x40
 55
 56/* PCIe IP version */
 57#define XGENE_PCIE_IP_VER_1		1
 58#define XGENE_PCIE_IP_VER_2		2
 59
 60struct xgene_pcie {
 61	struct device_node	*node;
 62	struct device		*dev;
 63	struct clk		*clk;
 64	void __iomem		*csr_base;
 65	void __iomem		*cfg_base;
 66	unsigned long		cfg_addr;
 67	bool			link_up;
 68	u32			version;
 69};
 70
 71static u32 xgene_pcie_readl(struct xgene_pcie *port, u32 reg)
 72{
 73	return readl(port->csr_base + reg);
 74}
 75
 76static void xgene_pcie_writel(struct xgene_pcie *port, u32 reg, u32 val)
 77{
 78	writel(val, port->csr_base + reg);
 79}
 80
 81static inline u32 pcie_bar_low_val(u32 addr, u32 flags)
 82{
 83	return (addr & PCI_BASE_ADDRESS_MEM_MASK) | flags;
 84}
 85
 86static inline struct xgene_pcie *pcie_bus_to_port(struct pci_bus *bus)
 87{
 88	struct pci_config_window *cfg;
 89
 90	if (acpi_disabled)
 91		return (struct xgene_pcie *)(bus->sysdata);
 92
 93	cfg = bus->sysdata;
 94	return (struct xgene_pcie *)(cfg->priv);
 95}
 96
 97/*
 98 * When the address bit [17:16] is 2'b01, the Configuration access will be
 99 * treated as Type 1 and it will be forwarded to external PCIe device.
100 */
101static void __iomem *xgene_pcie_get_cfg_base(struct pci_bus *bus)
102{
103	struct xgene_pcie *port = pcie_bus_to_port(bus);
104
105	if (bus->number >= (bus->primary + 1))
106		return port->cfg_base + AXI_EP_CFG_ACCESS;
107
108	return port->cfg_base;
109}
110
111/*
112 * For Configuration request, RTDID register is used as Bus Number,
113 * Device Number and Function number of the header fields.
114 */
115static void xgene_pcie_set_rtdid_reg(struct pci_bus *bus, uint devfn)
116{
117	struct xgene_pcie *port = pcie_bus_to_port(bus);
118	unsigned int b, d, f;
119	u32 rtdid_val = 0;
120
121	b = bus->number;
122	d = PCI_SLOT(devfn);
123	f = PCI_FUNC(devfn);
124
125	if (!pci_is_root_bus(bus))
126		rtdid_val = (b << 8) | (d << 3) | f;
127
128	xgene_pcie_writel(port, RTDID, rtdid_val);
129	/* read the register back to ensure flush */
130	xgene_pcie_readl(port, RTDID);
131}
132
133/*
134 * X-Gene PCIe port uses BAR0-BAR1 of RC's configuration space as
135 * the translation from PCI bus to native BUS.  Entire DDR region
136 * is mapped into PCIe space using these registers, so it can be
137 * reached by DMA from EP devices.  The BAR0/1 of bridge should be
138 * hidden during enumeration to avoid the sizing and resource allocation
139 * by PCIe core.
140 */
141static bool xgene_pcie_hide_rc_bars(struct pci_bus *bus, int offset)
142{
143	if (pci_is_root_bus(bus) && ((offset == PCI_BASE_ADDRESS_0) ||
144				     (offset == PCI_BASE_ADDRESS_1)))
145		return true;
146
147	return false;
148}
149
150static void __iomem *xgene_pcie_map_bus(struct pci_bus *bus, unsigned int devfn,
151					int offset)
152{
153	if ((pci_is_root_bus(bus) && devfn != 0) ||
154	    xgene_pcie_hide_rc_bars(bus, offset))
155		return NULL;
156
157	xgene_pcie_set_rtdid_reg(bus, devfn);
158	return xgene_pcie_get_cfg_base(bus) + offset;
159}
160
161static int xgene_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
162				    int where, int size, u32 *val)
163{
164	struct xgene_pcie *port = pcie_bus_to_port(bus);
165	int ret;
166
167	ret = pci_generic_config_read32(bus, devfn, where & ~0x3, 4, val);
168	if (ret != PCIBIOS_SUCCESSFUL)
169		return ret;
170
171	/*
172	 * The v1 controller has a bug in its Configuration Request Retry
173	 * Status (RRS) logic: when RRS Software Visibility is enabled and
174	 * we read the Vendor and Device ID of a non-existent device, the
175	 * controller fabricates return data of 0xFFFF0001 ("device exists
176	 * but is not ready") instead of 0xFFFFFFFF (PCI_ERROR_RESPONSE)
177	 * ("device does not exist").  This causes the PCI core to retry
178	 * the read until it times out.  Avoid this by not claiming to
179	 * support RRS SV.
180	 */
181	if (pci_is_root_bus(bus) && (port->version == XGENE_PCIE_IP_VER_1) &&
182	    ((where & ~0x3) == XGENE_V1_PCI_EXP_CAP + PCI_EXP_RTCTL))
183		*val &= ~(PCI_EXP_RTCAP_RRS_SV << 16);
184
185	if (size <= 2)
186		*val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
187
188	return PCIBIOS_SUCCESSFUL;
189}
190
191#if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
192static int xgene_get_csr_resource(struct acpi_device *adev,
193				  struct resource *res)
194{
195	struct device *dev = &adev->dev;
196	struct resource_entry *entry;
197	struct list_head list;
198	unsigned long flags;
199	int ret;
200
201	INIT_LIST_HEAD(&list);
202	flags = IORESOURCE_MEM;
203	ret = acpi_dev_get_resources(adev, &list,
204				     acpi_dev_filter_resource_type_cb,
205				     (void *) flags);
206	if (ret < 0) {
207		dev_err(dev, "failed to parse _CRS method, error code %d\n",
208			ret);
209		return ret;
210	}
211
212	if (ret == 0) {
213		dev_err(dev, "no IO and memory resources present in _CRS\n");
214		return -EINVAL;
215	}
216
217	entry = list_first_entry(&list, struct resource_entry, node);
218	*res = *entry->res;
219	acpi_dev_free_resource_list(&list);
220	return 0;
221}
222
223static int xgene_pcie_ecam_init(struct pci_config_window *cfg, u32 ipversion)
224{
225	struct device *dev = cfg->parent;
226	struct acpi_device *adev = to_acpi_device(dev);
227	struct xgene_pcie *port;
228	struct resource csr;
229	int ret;
230
231	port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
232	if (!port)
233		return -ENOMEM;
234
235	ret = xgene_get_csr_resource(adev, &csr);
236	if (ret) {
237		dev_err(dev, "can't get CSR resource\n");
238		return ret;
239	}
240	port->csr_base = devm_pci_remap_cfg_resource(dev, &csr);
241	if (IS_ERR(port->csr_base))
242		return PTR_ERR(port->csr_base);
243
244	port->cfg_base = cfg->win;
245	port->version = ipversion;
246
247	cfg->priv = port;
248	return 0;
249}
250
251static int xgene_v1_pcie_ecam_init(struct pci_config_window *cfg)
252{
253	return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_1);
254}
255
256const struct pci_ecam_ops xgene_v1_pcie_ecam_ops = {
257	.init		= xgene_v1_pcie_ecam_init,
258	.pci_ops	= {
259		.map_bus	= xgene_pcie_map_bus,
260		.read		= xgene_pcie_config_read32,
261		.write		= pci_generic_config_write,
262	}
263};
264
265static int xgene_v2_pcie_ecam_init(struct pci_config_window *cfg)
266{
267	return xgene_pcie_ecam_init(cfg, XGENE_PCIE_IP_VER_2);
268}
269
270const struct pci_ecam_ops xgene_v2_pcie_ecam_ops = {
271	.init		= xgene_v2_pcie_ecam_init,
272	.pci_ops	= {
273		.map_bus	= xgene_pcie_map_bus,
274		.read		= xgene_pcie_config_read32,
275		.write		= pci_generic_config_write,
276	}
277};
278#endif
279
280static u64 xgene_pcie_set_ib_mask(struct xgene_pcie *port, u32 addr,
281				  u32 flags, u64 size)
282{
283	u64 mask = (~(size - 1) & PCI_BASE_ADDRESS_MEM_MASK) | flags;
284	u32 val32 = 0;
285	u32 val;
286
287	val32 = xgene_pcie_readl(port, addr);
288	val = (val32 & 0x0000ffff) | (lower_32_bits(mask) << 16);
289	xgene_pcie_writel(port, addr, val);
290
291	val32 = xgene_pcie_readl(port, addr + 0x04);
292	val = (val32 & 0xffff0000) | (lower_32_bits(mask) >> 16);
293	xgene_pcie_writel(port, addr + 0x04, val);
294
295	val32 = xgene_pcie_readl(port, addr + 0x04);
296	val = (val32 & 0x0000ffff) | (upper_32_bits(mask) << 16);
297	xgene_pcie_writel(port, addr + 0x04, val);
298
299	val32 = xgene_pcie_readl(port, addr + 0x08);
300	val = (val32 & 0xffff0000) | (upper_32_bits(mask) >> 16);
301	xgene_pcie_writel(port, addr + 0x08, val);
302
303	return mask;
304}
305
306static void xgene_pcie_linkup(struct xgene_pcie *port,
307			      u32 *lanes, u32 *speed)
308{
309	u32 val32;
310
311	port->link_up = false;
312	val32 = xgene_pcie_readl(port, PCIECORE_CTLANDSTATUS);
313	if (val32 & LINK_UP_MASK) {
314		port->link_up = true;
315		*speed = PIPE_PHY_RATE_RD(val32);
316		val32 = xgene_pcie_readl(port, BRIDGE_STATUS_0);
317		*lanes = val32 >> 26;
318	}
319}
320
321static int xgene_pcie_init_port(struct xgene_pcie *port)
322{
323	struct device *dev = port->dev;
324	int rc;
325
326	port->clk = clk_get(dev, NULL);
327	if (IS_ERR(port->clk)) {
328		dev_err(dev, "clock not available\n");
329		return -ENODEV;
330	}
331
332	rc = clk_prepare_enable(port->clk);
333	if (rc) {
334		dev_err(dev, "clock enable failed\n");
335		return rc;
336	}
337
338	return 0;
339}
340
341static int xgene_pcie_map_reg(struct xgene_pcie *port,
342			      struct platform_device *pdev)
343{
344	struct device *dev = port->dev;
345	struct resource *res;
346
347	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "csr");
348	port->csr_base = devm_pci_remap_cfg_resource(dev, res);
349	if (IS_ERR(port->csr_base))
350		return PTR_ERR(port->csr_base);
351
352	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
353	port->cfg_base = devm_ioremap_resource(dev, res);
354	if (IS_ERR(port->cfg_base))
355		return PTR_ERR(port->cfg_base);
356	port->cfg_addr = res->start;
357
358	return 0;
359}
360
361static void xgene_pcie_setup_ob_reg(struct xgene_pcie *port,
362				    struct resource *res, u32 offset,
363				    u64 cpu_addr, u64 pci_addr)
364{
365	struct device *dev = port->dev;
366	resource_size_t size = resource_size(res);
367	u64 restype = resource_type(res);
368	u64 mask = 0;
369	u32 min_size;
370	u32 flag = EN_REG;
371
372	if (restype == IORESOURCE_MEM) {
373		min_size = SZ_128M;
374	} else {
375		min_size = 128;
376		flag |= OB_LO_IO;
377	}
378
379	if (size >= min_size)
380		mask = ~(size - 1) | flag;
381	else
382		dev_warn(dev, "res size 0x%llx less than minimum 0x%x\n",
383			 (u64)size, min_size);
384
385	xgene_pcie_writel(port, offset, lower_32_bits(cpu_addr));
386	xgene_pcie_writel(port, offset + 0x04, upper_32_bits(cpu_addr));
387	xgene_pcie_writel(port, offset + 0x08, lower_32_bits(mask));
388	xgene_pcie_writel(port, offset + 0x0c, upper_32_bits(mask));
389	xgene_pcie_writel(port, offset + 0x10, lower_32_bits(pci_addr));
390	xgene_pcie_writel(port, offset + 0x14, upper_32_bits(pci_addr));
391}
392
393static void xgene_pcie_setup_cfg_reg(struct xgene_pcie *port)
394{
395	u64 addr = port->cfg_addr;
396
397	xgene_pcie_writel(port, CFGBARL, lower_32_bits(addr));
398	xgene_pcie_writel(port, CFGBARH, upper_32_bits(addr));
399	xgene_pcie_writel(port, CFGCTL, EN_REG);
400}
401
402static int xgene_pcie_map_ranges(struct xgene_pcie *port)
403{
404	struct pci_host_bridge *bridge = pci_host_bridge_from_priv(port);
405	struct resource_entry *window;
406	struct device *dev = port->dev;
407
408	resource_list_for_each_entry(window, &bridge->windows) {
409		struct resource *res = window->res;
410		u64 restype = resource_type(res);
411
412		dev_dbg(dev, "%pR\n", res);
413
414		switch (restype) {
415		case IORESOURCE_IO:
416			xgene_pcie_setup_ob_reg(port, res, OMR3BARL,
417						pci_pio_to_address(res->start),
418						res->start - window->offset);
419			break;
420		case IORESOURCE_MEM:
421			if (res->flags & IORESOURCE_PREFETCH)
422				xgene_pcie_setup_ob_reg(port, res, OMR2BARL,
423							res->start,
424							res->start -
425							window->offset);
426			else
427				xgene_pcie_setup_ob_reg(port, res, OMR1BARL,
428							res->start,
429							res->start -
430							window->offset);
431			break;
432		case IORESOURCE_BUS:
433			break;
434		default:
435			dev_err(dev, "invalid resource %pR\n", res);
436			return -EINVAL;
437		}
438	}
439	xgene_pcie_setup_cfg_reg(port);
440	return 0;
441}
442
443static void xgene_pcie_setup_pims(struct xgene_pcie *port, u32 pim_reg,
444				  u64 pim, u64 size)
445{
446	xgene_pcie_writel(port, pim_reg, lower_32_bits(pim));
447	xgene_pcie_writel(port, pim_reg + 0x04,
448			  upper_32_bits(pim) | EN_COHERENCY);
449	xgene_pcie_writel(port, pim_reg + 0x10, lower_32_bits(size));
450	xgene_pcie_writel(port, pim_reg + 0x14, upper_32_bits(size));
451}
452
453/*
454 * X-Gene PCIe support maximum 3 inbound memory regions
455 * This function helps to select a region based on size of region
456 */
457static int xgene_pcie_select_ib_reg(u8 *ib_reg_mask, u64 size)
458{
459	if ((size > 4) && (size < SZ_16M) && !(*ib_reg_mask & (1 << 1))) {
460		*ib_reg_mask |= (1 << 1);
461		return 1;
462	}
463
464	if ((size > SZ_1K) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 0))) {
465		*ib_reg_mask |= (1 << 0);
466		return 0;
467	}
468
469	if ((size > SZ_1M) && (size < SZ_1T) && !(*ib_reg_mask & (1 << 2))) {
470		*ib_reg_mask |= (1 << 2);
471		return 2;
472	}
473
474	return -EINVAL;
475}
476
477static void xgene_pcie_setup_ib_reg(struct xgene_pcie *port,
478				    struct of_pci_range *range, u8 *ib_reg_mask)
479{
480	void __iomem *cfg_base = port->cfg_base;
481	struct device *dev = port->dev;
482	void __iomem *bar_addr;
483	u32 pim_reg;
484	u64 cpu_addr = range->cpu_addr;
485	u64 pci_addr = range->pci_addr;
486	u64 size = range->size;
487	u64 mask = ~(size - 1) | EN_REG;
488	u32 flags = PCI_BASE_ADDRESS_MEM_TYPE_64;
489	u32 bar_low;
490	int region;
491
492	region = xgene_pcie_select_ib_reg(ib_reg_mask, range->size);
493	if (region < 0) {
494		dev_warn(dev, "invalid pcie dma-range config\n");
495		return;
496	}
497
498	if (range->flags & IORESOURCE_PREFETCH)
499		flags |= PCI_BASE_ADDRESS_MEM_PREFETCH;
500
501	bar_low = pcie_bar_low_val((u32)cpu_addr, flags);
502	switch (region) {
503	case 0:
504		xgene_pcie_set_ib_mask(port, BRIDGE_CFG_4, flags, size);
505		bar_addr = cfg_base + PCI_BASE_ADDRESS_0;
506		writel(bar_low, bar_addr);
507		writel(upper_32_bits(cpu_addr), bar_addr + 0x4);
508		pim_reg = PIM1_1L;
509		break;
510	case 1:
511		xgene_pcie_writel(port, IBAR2, bar_low);
512		xgene_pcie_writel(port, IR2MSK, lower_32_bits(mask));
513		pim_reg = PIM2_1L;
514		break;
515	case 2:
516		xgene_pcie_writel(port, IBAR3L, bar_low);
517		xgene_pcie_writel(port, IBAR3L + 0x4, upper_32_bits(cpu_addr));
518		xgene_pcie_writel(port, IR3MSKL, lower_32_bits(mask));
519		xgene_pcie_writel(port, IR3MSKL + 0x4, upper_32_bits(mask));
520		pim_reg = PIM3_1L;
521		break;
522	}
523
524	xgene_pcie_setup_pims(port, pim_reg, pci_addr, ~(size - 1));
525}
526
527static int xgene_pcie_parse_map_dma_ranges(struct xgene_pcie *port)
528{
529	struct device_node *np = port->node;
530	struct of_pci_range range;
531	struct of_pci_range_parser parser;
532	struct device *dev = port->dev;
533	u8 ib_reg_mask = 0;
534
535	if (of_pci_dma_range_parser_init(&parser, np)) {
536		dev_err(dev, "missing dma-ranges property\n");
537		return -EINVAL;
538	}
539
540	/* Get the dma-ranges from DT */
541	for_each_of_pci_range(&parser, &range) {
542		u64 end = range.cpu_addr + range.size - 1;
543
544		dev_dbg(dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
545			range.flags, range.cpu_addr, end, range.pci_addr);
546		xgene_pcie_setup_ib_reg(port, &range, &ib_reg_mask);
547	}
548	return 0;
549}
550
551/* clear BAR configuration which was done by firmware */
552static void xgene_pcie_clear_config(struct xgene_pcie *port)
553{
554	int i;
555
556	for (i = PIM1_1L; i <= CFGCTL; i += 4)
557		xgene_pcie_writel(port, i, 0);
558}
559
560static int xgene_pcie_setup(struct xgene_pcie *port)
561{
562	struct device *dev = port->dev;
563	u32 val, lanes = 0, speed = 0;
564	int ret;
565
566	xgene_pcie_clear_config(port);
567
568	/* setup the vendor and device IDs correctly */
569	val = (XGENE_PCIE_DEVICEID << 16) | PCI_VENDOR_ID_AMCC;
570	xgene_pcie_writel(port, BRIDGE_CFG_0, val);
571
572	ret = xgene_pcie_map_ranges(port);
573	if (ret)
574		return ret;
575
576	ret = xgene_pcie_parse_map_dma_ranges(port);
577	if (ret)
578		return ret;
579
580	xgene_pcie_linkup(port, &lanes, &speed);
581	if (!port->link_up)
582		dev_info(dev, "(rc) link down\n");
583	else
584		dev_info(dev, "(rc) x%d gen-%d link up\n", lanes, speed + 1);
585	return 0;
586}
587
588static struct pci_ops xgene_pcie_ops = {
589	.map_bus = xgene_pcie_map_bus,
590	.read = xgene_pcie_config_read32,
591	.write = pci_generic_config_write32,
592};
593
594static bool xgene_check_pcie_msi_ready(void)
595{
596	struct device_node *np;
597	struct irq_domain *d;
598
599	if (!IS_ENABLED(CONFIG_PCI_XGENE_MSI))
600		return true;
601
602	np = of_find_compatible_node(NULL, NULL, "apm,xgene1-msi");
603	if (!np)
604		return true;
605
606	d = irq_find_matching_host(np, DOMAIN_BUS_PCI_MSI);
607	of_node_put(np);
608
609	return d && irq_domain_is_msi_parent(d);
610}
611
612static int xgene_pcie_probe(struct platform_device *pdev)
613{
614	struct device *dev = &pdev->dev;
615	struct device_node *dn = dev->of_node;
616	struct xgene_pcie *port;
617	struct pci_host_bridge *bridge;
618	int ret;
619
620	if (!xgene_check_pcie_msi_ready())
621		return dev_err_probe(&pdev->dev, -EPROBE_DEFER,
622				     "MSI driver not ready\n");
623
624	bridge = devm_pci_alloc_host_bridge(dev, sizeof(*port));
625	if (!bridge)
626		return -ENOMEM;
627
628	port = pci_host_bridge_priv(bridge);
629
630	port->node = of_node_get(dn);
631	port->dev = dev;
632	port->version = XGENE_PCIE_IP_VER_1;
633
634	ret = xgene_pcie_map_reg(port, pdev);
635	if (ret)
636		return ret;
637
638	ret = xgene_pcie_init_port(port);
639	if (ret)
640		return ret;
641
642	ret = xgene_pcie_setup(port);
643	if (ret)
644		return ret;
645
646	bridge->sysdata = port;
647	bridge->ops = &xgene_pcie_ops;
648
649	return pci_host_probe(bridge);
650}
651
652static const struct of_device_id xgene_pcie_match_table[] = {
653	{.compatible = "apm,xgene-pcie",},
654	{},
655};
656
657static struct platform_driver xgene_pcie_driver = {
658	.driver = {
659		.name = "xgene-pcie",
660		.of_match_table = xgene_pcie_match_table,
661		.suppress_bind_attrs = true,
662	},
663	.probe = xgene_pcie_probe,
664};
665builtin_platform_driver(xgene_pcie_driver);