pcie-rcar-gen4.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * PCIe controller driver for Renesas R-Car Gen4 Series SoCs
  4 * Copyright (C) 2022-2023 Renesas Electronics Corporation
  5 *
  6 * The r8a779g0 (R-Car V4H) controller requires a specific firmware to be
  7 * provided, to initialize the PHY. Otherwise, the PCIe controller will not
  8 * work.
  9 */
 10
 11#include <linux/delay.h>
 12#include <linux/firmware.h>
 13#include <linux/interrupt.h>
 14#include <linux/io.h>
 15#include <linux/iopoll.h>
 16#include <linux/module.h>
 17#include <linux/of.h>
 18#include <linux/pci.h>
 19#include <linux/platform_device.h>
 20#include <linux/pm_runtime.h>
 21#include <linux/reset.h>
 22
 23#include "../../pci.h"
 24#include "pcie-designware.h"
 25
 26/* Renesas-specific */
 27/* PCIe Mode Setting Register 0 */
 28#define PCIEMSR0		0x0000
 29#define APP_SRIS_MODE		BIT(6)
 30#define DEVICE_TYPE_EP		0
 31#define DEVICE_TYPE_RC		BIT(4)
 32#define BIFUR_MOD_SET_ON	BIT(0)
 33
 34/* PCIe Interrupt Status 0 */
 35#define PCIEINTSTS0		0x0084
 36
 37/* PCIe Interrupt Status 0 Enable */
 38#define PCIEINTSTS0EN		0x0310
 39#define MSI_CTRL_INT		BIT(26)
 40#define SMLH_LINK_UP		BIT(7)
 41#define RDLH_LINK_UP		BIT(6)
 42
 43/* PCIe DMA Interrupt Status Enable */
 44#define PCIEDMAINTSTSEN		0x0314
 45#define PCIEDMAINTSTSEN_INIT	GENMASK(15, 0)
 46
 47/* Port Logic Registers 89 */
 48#define PRTLGC89		0x0b70
 49
 50/* Port Logic Registers 90 */
 51#define PRTLGC90		0x0b74
 52
 53/* PCIe Reset Control Register 1 */
 54#define PCIERSTCTRL1		0x0014
 55#define APP_HOLD_PHY_RST	BIT(16)
 56#define APP_LTSSM_ENABLE	BIT(0)
 57
 58/* PCIe Power Management Control */
 59#define PCIEPWRMNGCTRL		0x0070
 60#define APP_CLK_REQ_N		BIT(11)
 61#define APP_CLK_PM_EN		BIT(10)
 62
 63#define RCAR_NUM_SPEED_CHANGE_RETRIES	10
 64#define RCAR_MAX_LINK_SPEED		4
 65
 66#define RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET	0x1000
 67#define RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET	0x800
 68
 69#define RCAR_GEN4_PCIE_FIRMWARE_NAME		"rcar_gen4_pcie.bin"
 70#define RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR	0xc000
 71MODULE_FIRMWARE(RCAR_GEN4_PCIE_FIRMWARE_NAME);
 72
 73struct rcar_gen4_pcie;
 74struct rcar_gen4_pcie_drvdata {
 75	void (*additional_common_init)(struct rcar_gen4_pcie *rcar);
 76	int (*ltssm_control)(struct rcar_gen4_pcie *rcar, bool enable);
 77	enum dw_pcie_device_mode mode;
 78};
 79
 80struct rcar_gen4_pcie {
 81	struct dw_pcie dw;
 82	void __iomem *base;
 83	void __iomem *phy_base;
 84	struct platform_device *pdev;
 85	const struct rcar_gen4_pcie_drvdata *drvdata;
 86};
 87#define to_rcar_gen4_pcie(_dw)	container_of(_dw, struct rcar_gen4_pcie, dw)
 88
 89/* Common */
 90static bool rcar_gen4_pcie_link_up(struct dw_pcie *dw)
 91{
 92	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
 93	u32 val, mask;
 94
 95	val = readl(rcar->base + PCIEINTSTS0);
 96	mask = RDLH_LINK_UP | SMLH_LINK_UP;
 97
 98	return (val & mask) == mask;
 99}
100
101/*
102 * Manually initiate the speed change. Return 0 if change succeeded; otherwise
103 * -ETIMEDOUT.
104 */
105static int rcar_gen4_pcie_speed_change(struct dw_pcie *dw)
106{
107	u32 val;
108	int i;
109
110	val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
111	val &= ~PORT_LOGIC_SPEED_CHANGE;
112	dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
113
114	val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
115	val |= PORT_LOGIC_SPEED_CHANGE;
116	dw_pcie_writel_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
117
118	for (i = 0; i < RCAR_NUM_SPEED_CHANGE_RETRIES; i++) {
119		val = dw_pcie_readl_dbi(dw, PCIE_LINK_WIDTH_SPEED_CONTROL);
120		if (!(val & PORT_LOGIC_SPEED_CHANGE))
121			return 0;
122		usleep_range(10000, 11000);
123	}
124
125	return -ETIMEDOUT;
126}
127
128/*
129 * Enable LTSSM of this controller and manually initiate the speed change.
130 * Always return 0.
131 */
132static int rcar_gen4_pcie_start_link(struct dw_pcie *dw)
133{
134	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
135	int i, changes, ret;
136
137	if (rcar->drvdata->ltssm_control) {
138		ret = rcar->drvdata->ltssm_control(rcar, true);
139		if (ret)
140			return ret;
141	}
142
143	/*
144	 * Require direct speed change with retrying here if the max_link_speed
145	 * is PCIe Gen2 or higher.
146	 */
147	changes = min_not_zero(dw->max_link_speed, RCAR_MAX_LINK_SPEED) - 1;
148
149	/*
150	 * Since dw_pcie_setup_rc() sets it once, PCIe Gen2 will be trained.
151	 * So, this needs remaining times for up to PCIe Gen4 if RC mode.
152	 */
153	if (changes && rcar->drvdata->mode == DW_PCIE_RC_TYPE)
154		changes--;
155
156	for (i = 0; i < changes; i++) {
157		/* It may not be connected in EP mode yet. So, break the loop */
158		if (rcar_gen4_pcie_speed_change(dw))
159			break;
160	}
161
162	return 0;
163}
164
165static void rcar_gen4_pcie_stop_link(struct dw_pcie *dw)
166{
167	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
168
169	if (rcar->drvdata->ltssm_control)
170		rcar->drvdata->ltssm_control(rcar, false);
171}
172
173static int rcar_gen4_pcie_common_init(struct rcar_gen4_pcie *rcar)
174{
175	struct dw_pcie *dw = &rcar->dw;
176	u32 val;
177	int ret;
178
179	ret = clk_bulk_prepare_enable(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
180	if (ret) {
181		dev_err(dw->dev, "Enabling core clocks failed\n");
182		return ret;
183	}
184
185	if (!reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc)) {
186		reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
187		/*
188		 * R-Car V4H Reference Manual R19UH0186EJ0130 Rev.1.30 Apr.
189		 * 21, 2025 page 585 Figure 9.3.2 Software Reset flow (B)
190		 * indicates that for peripherals in HSC domain, after
191		 * reset has been asserted by writing a matching reset bit
192		 * into register SRCR, it is mandatory to wait 1ms.
193		 */
194		fsleep(1000);
195	}
196
197	val = readl(rcar->base + PCIEMSR0);
198	if (rcar->drvdata->mode == DW_PCIE_RC_TYPE) {
199		val |= DEVICE_TYPE_RC;
200	} else if (rcar->drvdata->mode == DW_PCIE_EP_TYPE) {
201		val |= DEVICE_TYPE_EP;
202	} else {
203		ret = -EINVAL;
204		goto err_unprepare;
205	}
206
207	if (dw->num_lanes < 4)
208		val |= BIFUR_MOD_SET_ON;
209
210	writel(val, rcar->base + PCIEMSR0);
211
212	ret = reset_control_deassert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
213	if (ret)
214		goto err_unprepare;
215
216	/*
217	 * Assure the reset is latched and the core is ready for DBI access.
218	 * On R-Car V4H, the PCIe reset is asynchronous and does not take
219	 * effect immediately, but needs a short time to complete. In case
220	 * DBI access happens in that short time, that access generates an
221	 * SError. To make sure that condition can never happen, read back the
222	 * state of the reset, which should turn the asynchronous reset into
223	 * synchronous one, and wait a little over 1ms to add additional
224	 * safety margin.
225	 */
226	reset_control_status(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
227	fsleep(1000);
228
229	if (rcar->drvdata->additional_common_init)
230		rcar->drvdata->additional_common_init(rcar);
231
232	return 0;
233
234err_unprepare:
235	clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
236
237	return ret;
238}
239
240static void rcar_gen4_pcie_common_deinit(struct rcar_gen4_pcie *rcar)
241{
242	struct dw_pcie *dw = &rcar->dw;
243
244	reset_control_assert(dw->core_rsts[DW_PCIE_PWR_RST].rstc);
245	clk_bulk_disable_unprepare(DW_PCIE_NUM_CORE_CLKS, dw->core_clks);
246}
247
248static int rcar_gen4_pcie_prepare(struct rcar_gen4_pcie *rcar)
249{
250	struct device *dev = rcar->dw.dev;
251	int err;
252
253	pm_runtime_enable(dev);
254	err = pm_runtime_resume_and_get(dev);
255	if (err < 0) {
256		dev_err(dev, "Runtime resume failed\n");
257		pm_runtime_disable(dev);
258	}
259
260	return err;
261}
262
263static void rcar_gen4_pcie_unprepare(struct rcar_gen4_pcie *rcar)
264{
265	struct device *dev = rcar->dw.dev;
266
267	pm_runtime_put(dev);
268	pm_runtime_disable(dev);
269}
270
271static int rcar_gen4_pcie_get_resources(struct rcar_gen4_pcie *rcar)
272{
273	rcar->phy_base = devm_platform_ioremap_resource_byname(rcar->pdev, "phy");
274	if (IS_ERR(rcar->phy_base))
275		return PTR_ERR(rcar->phy_base);
276
277	/* Renesas-specific registers */
278	rcar->base = devm_platform_ioremap_resource_byname(rcar->pdev, "app");
279
280	return PTR_ERR_OR_ZERO(rcar->base);
281}
282
283static const struct dw_pcie_ops dw_pcie_ops = {
284	.start_link = rcar_gen4_pcie_start_link,
285	.stop_link = rcar_gen4_pcie_stop_link,
286	.link_up = rcar_gen4_pcie_link_up,
287};
288
289static struct rcar_gen4_pcie *rcar_gen4_pcie_alloc(struct platform_device *pdev)
290{
291	struct device *dev = &pdev->dev;
292	struct rcar_gen4_pcie *rcar;
293
294	rcar = devm_kzalloc(dev, sizeof(*rcar), GFP_KERNEL);
295	if (!rcar)
296		return ERR_PTR(-ENOMEM);
297
298	rcar->dw.ops = &dw_pcie_ops;
299	rcar->dw.dev = dev;
300	rcar->pdev = pdev;
301	rcar->dw.edma.mf = EDMA_MF_EDMA_UNROLL;
302	dw_pcie_cap_set(&rcar->dw, REQ_RES);
303	platform_set_drvdata(pdev, rcar);
304
305	return rcar;
306}
307
308/* Host mode */
309static int rcar_gen4_pcie_host_init(struct dw_pcie_rp *pp)
310{
311	struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
312	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
313	int ret;
314	u32 val;
315
316	gpiod_set_value_cansleep(dw->pe_rst, 1);
317
318	ret = rcar_gen4_pcie_common_init(rcar);
319	if (ret)
320		return ret;
321
322	/*
323	 * According to the section 3.5.7.2 "RC Mode" in DWC PCIe Dual Mode
324	 * Rev.5.20a and 3.5.6.1 "RC mode" in DWC PCIe RC databook v5.20a, we
325	 * should disable two BARs to avoid unnecessary memory assignment
326	 * during device enumeration.
327	 */
328	dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_0, 0x0);
329	dw_pcie_writel_dbi2(dw, PCI_BASE_ADDRESS_1, 0x0);
330
331	/* Enable MSI interrupt signal */
332	val = readl(rcar->base + PCIEINTSTS0EN);
333	val |= MSI_CTRL_INT;
334	writel(val, rcar->base + PCIEINTSTS0EN);
335
336	msleep(PCIE_T_PVPERL_MS);	/* pe_rst requires 100msec delay */
337
338	gpiod_set_value_cansleep(dw->pe_rst, 0);
339
340	return 0;
341}
342
343static void rcar_gen4_pcie_host_deinit(struct dw_pcie_rp *pp)
344{
345	struct dw_pcie *dw = to_dw_pcie_from_pp(pp);
346	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
347
348	gpiod_set_value_cansleep(dw->pe_rst, 1);
349	rcar_gen4_pcie_common_deinit(rcar);
350}
351
352static const struct dw_pcie_host_ops rcar_gen4_pcie_host_ops = {
353	.init = rcar_gen4_pcie_host_init,
354	.deinit = rcar_gen4_pcie_host_deinit,
355};
356
357static int rcar_gen4_add_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
358{
359	struct dw_pcie_rp *pp = &rcar->dw.pp;
360
361	if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_HOST))
362		return -ENODEV;
363
364	pp->num_vectors = MAX_MSI_IRQS;
365	pp->ops = &rcar_gen4_pcie_host_ops;
366
367	return dw_pcie_host_init(pp);
368}
369
370static void rcar_gen4_remove_dw_pcie_rp(struct rcar_gen4_pcie *rcar)
371{
372	dw_pcie_host_deinit(&rcar->dw.pp);
373}
374
375/* Endpoint mode */
376static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep)
377{
378	struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
379	struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw);
380	int ret;
381
382	ret = rcar_gen4_pcie_common_init(rcar);
383	if (ret)
384		return;
385
386	writel(PCIEDMAINTSTSEN_INIT, rcar->base + PCIEDMAINTSTSEN);
387}
388
389static void rcar_gen4_pcie_ep_init(struct dw_pcie_ep *ep)
390{
391	struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
392	enum pci_barno bar;
393
394	for (bar = 0; bar < PCI_STD_NUM_BARS; bar++)
395		dw_pcie_ep_reset_bar(pci, bar);
396}
397
398static void rcar_gen4_pcie_ep_deinit(struct rcar_gen4_pcie *rcar)
399{
400	writel(0, rcar->base + PCIEDMAINTSTSEN);
401	rcar_gen4_pcie_common_deinit(rcar);
402}
403
404static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
405				       unsigned int type, u16 interrupt_num)
406{
407	struct dw_pcie *dw = to_dw_pcie_from_ep(ep);
408
409	switch (type) {
410	case PCI_IRQ_INTX:
411		return dw_pcie_ep_raise_intx_irq(ep, func_no);
412	case PCI_IRQ_MSI:
413		return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
414	default:
415		dev_err(dw->dev, "Unknown IRQ type\n");
416		return -EINVAL;
417	}
418
419	return 0;
420}
421
422static const struct pci_epc_features rcar_gen4_pcie_epc_features = {
423	DWC_EPC_COMMON_FEATURES,
424	.msi_capable = true,
425	.bar[BAR_1] = { .type = BAR_RESERVED, },
426	.bar[BAR_3] = { .type = BAR_RESERVED, },
427	.bar[BAR_4] = { .type = BAR_FIXED, .fixed_size = 256 },
428	.bar[BAR_5] = { .type = BAR_RESERVED, },
429	.align = SZ_1M,
430};
431
432static const struct pci_epc_features*
433rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep)
434{
435	return &rcar_gen4_pcie_epc_features;
436}
437
438static unsigned int rcar_gen4_pcie_ep_get_dbi_offset(struct dw_pcie_ep *ep,
439						       u8 func_no)
440{
441	return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI_OFFSET;
442}
443
444static unsigned int rcar_gen4_pcie_ep_get_dbi2_offset(struct dw_pcie_ep *ep,
445						      u8 func_no)
446{
447	return func_no * RCAR_GEN4_PCIE_EP_FUNC_DBI2_OFFSET;
448}
449
450static const struct dw_pcie_ep_ops pcie_ep_ops = {
451	.pre_init = rcar_gen4_pcie_ep_pre_init,
452	.init = rcar_gen4_pcie_ep_init,
453	.raise_irq = rcar_gen4_pcie_ep_raise_irq,
454	.get_features = rcar_gen4_pcie_ep_get_features,
455	.get_dbi_offset = rcar_gen4_pcie_ep_get_dbi_offset,
456	.get_dbi2_offset = rcar_gen4_pcie_ep_get_dbi2_offset,
457};
458
459static int rcar_gen4_add_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
460{
461	struct dw_pcie_ep *ep = &rcar->dw.ep;
462	struct device *dev = rcar->dw.dev;
463	int ret;
464
465	if (!IS_ENABLED(CONFIG_PCIE_RCAR_GEN4_EP))
466		return -ENODEV;
467
468	ep->ops = &pcie_ep_ops;
469
470	ret = dw_pcie_ep_init(ep);
471	if (ret) {
472		rcar_gen4_pcie_ep_deinit(rcar);
473		return ret;
474	}
475
476	ret = dw_pcie_ep_init_registers(ep);
477	if (ret) {
478		dev_err(dev, "Failed to initialize DWC endpoint registers\n");
479		dw_pcie_ep_deinit(ep);
480		rcar_gen4_pcie_ep_deinit(rcar);
481	}
482
483	pci_epc_init_notify(ep->epc);
484
485	return ret;
486}
487
488static void rcar_gen4_remove_dw_pcie_ep(struct rcar_gen4_pcie *rcar)
489{
490	dw_pcie_ep_deinit(&rcar->dw.ep);
491	rcar_gen4_pcie_ep_deinit(rcar);
492}
493
494/* Common */
495static int rcar_gen4_add_dw_pcie(struct rcar_gen4_pcie *rcar)
496{
497	rcar->drvdata = of_device_get_match_data(&rcar->pdev->dev);
498	if (!rcar->drvdata)
499		return -EINVAL;
500
501	switch (rcar->drvdata->mode) {
502	case DW_PCIE_RC_TYPE:
503		return rcar_gen4_add_dw_pcie_rp(rcar);
504	case DW_PCIE_EP_TYPE:
505		return rcar_gen4_add_dw_pcie_ep(rcar);
506	default:
507		return -EINVAL;
508	}
509}
510
511static int rcar_gen4_pcie_probe(struct platform_device *pdev)
512{
513	struct rcar_gen4_pcie *rcar;
514	int err;
515
516	rcar = rcar_gen4_pcie_alloc(pdev);
517	if (IS_ERR(rcar))
518		return PTR_ERR(rcar);
519
520	err = rcar_gen4_pcie_get_resources(rcar);
521	if (err)
522		return err;
523
524	err = rcar_gen4_pcie_prepare(rcar);
525	if (err)
526		return err;
527
528	err = rcar_gen4_add_dw_pcie(rcar);
529	if (err)
530		goto err_unprepare;
531
532	return 0;
533
534err_unprepare:
535	rcar_gen4_pcie_unprepare(rcar);
536
537	return err;
538}
539
540static void rcar_gen4_remove_dw_pcie(struct rcar_gen4_pcie *rcar)
541{
542	switch (rcar->drvdata->mode) {
543	case DW_PCIE_RC_TYPE:
544		rcar_gen4_remove_dw_pcie_rp(rcar);
545		break;
546	case DW_PCIE_EP_TYPE:
547		rcar_gen4_remove_dw_pcie_ep(rcar);
548		break;
549	default:
550		break;
551	}
552}
553
554static void rcar_gen4_pcie_remove(struct platform_device *pdev)
555{
556	struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev);
557
558	rcar_gen4_remove_dw_pcie(rcar);
559	rcar_gen4_pcie_unprepare(rcar);
560}
561
562static int r8a779f0_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)
563{
564	u32 val;
565
566	val = readl(rcar->base + PCIERSTCTRL1);
567	if (enable) {
568		val |= APP_LTSSM_ENABLE;
569		val &= ~APP_HOLD_PHY_RST;
570	} else {
571		/*
572		 * Since the datasheet of R-Car doesn't mention how to assert
573		 * the APP_HOLD_PHY_RST, don't assert it again. Otherwise,
574		 * hang-up issue happened in the dw_edma_core_off() when
575		 * the controller didn't detect a PCI device.
576		 */
577		val &= ~APP_LTSSM_ENABLE;
578	}
579	writel(val, rcar->base + PCIERSTCTRL1);
580
581	return 0;
582}
583
584static void rcar_gen4_pcie_additional_common_init(struct rcar_gen4_pcie *rcar)
585{
586	struct dw_pcie *dw = &rcar->dw;
587	u32 val;
588
589	val = dw_pcie_readl_dbi(dw, PCIE_PORT_LANE_SKEW);
590	val &= ~PORT_LANE_SKEW_INSERT_MASK;
591	if (dw->num_lanes < 4)
592		val |= BIT(6);
593	dw_pcie_writel_dbi(dw, PCIE_PORT_LANE_SKEW, val);
594
595	val = readl(rcar->base + PCIEPWRMNGCTRL);
596	val |= APP_CLK_REQ_N | APP_CLK_PM_EN;
597	writel(val, rcar->base + PCIEPWRMNGCTRL);
598}
599
600static void rcar_gen4_pcie_phy_reg_update_bits(struct rcar_gen4_pcie *rcar,
601					       u32 offset, u32 mask, u32 val)
602{
603	u32 tmp;
604
605	tmp = readl(rcar->phy_base + offset);
606	tmp &= ~mask;
607	tmp |= val;
608	writel(tmp, rcar->phy_base + offset);
609}
610
611/*
612 * SoC datasheet suggests checking port logic register bits during firmware
613 * write. If read returns non-zero value, then this function returns -EAGAIN
614 * indicating that the write needs to be done again. If read returns zero,
615 * then return 0 to indicate success.
616 */
617static int rcar_gen4_pcie_reg_test_bit(struct rcar_gen4_pcie *rcar,
618				       u32 offset, u32 mask)
619{
620	struct dw_pcie *dw = &rcar->dw;
621
622	if (dw_pcie_readl_dbi(dw, offset) & mask)
623		return -EAGAIN;
624
625	return 0;
626}
627
628static int rcar_gen4_pcie_download_phy_firmware(struct rcar_gen4_pcie *rcar)
629{
630	/* The check_addr values are magical numbers in the datasheet */
631	static const u32 check_addr[] = {
632		0x00101018,
633		0x00101118,
634		0x00101021,
635		0x00101121,
636	};
637	struct dw_pcie *dw = &rcar->dw;
638	const struct firmware *fw;
639	unsigned int i, timeout;
640	u32 data;
641	int ret;
642
643	ret = request_firmware(&fw, RCAR_GEN4_PCIE_FIRMWARE_NAME, dw->dev);
644	if (ret) {
645		dev_err(dw->dev, "Failed to load firmware (%s): %d\n",
646			RCAR_GEN4_PCIE_FIRMWARE_NAME, ret);
647		return ret;
648	}
649
650	for (i = 0; i < (fw->size / 2); i++) {
651		data = fw->data[(i * 2) + 1] << 8 | fw->data[i * 2];
652		timeout = 100;
653		do {
654			dw_pcie_writel_dbi(dw, PRTLGC89, RCAR_GEN4_PCIE_FIRMWARE_BASE_ADDR + i);
655			dw_pcie_writel_dbi(dw, PRTLGC90, data);
656			if (!rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30)))
657				break;
658			if (!(--timeout)) {
659				ret = -ETIMEDOUT;
660				goto exit;
661			}
662			usleep_range(100, 200);
663		} while (1);
664	}
665
666	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(17), BIT(17));
667
668	for (i = 0; i < ARRAY_SIZE(check_addr); i++) {
669		timeout = 100;
670		do {
671			dw_pcie_writel_dbi(dw, PRTLGC89, check_addr[i]);
672			ret = rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC89, BIT(30));
673			ret |= rcar_gen4_pcie_reg_test_bit(rcar, PRTLGC90, BIT(0));
674			if (!ret)
675				break;
676			if (!(--timeout)) {
677				ret = -ETIMEDOUT;
678				goto exit;
679			}
680			usleep_range(100, 200);
681		} while (1);
682	}
683
684exit:
685	release_firmware(fw);
686
687	return ret;
688}
689
690static int rcar_gen4_pcie_ltssm_control(struct rcar_gen4_pcie *rcar, bool enable)
691{
692	struct dw_pcie *dw = &rcar->dw;
693	u32 val;
694	int ret;
695
696	if (!enable) {
697		val = readl(rcar->base + PCIERSTCTRL1);
698		val &= ~APP_LTSSM_ENABLE;
699		writel(val, rcar->base + PCIERSTCTRL1);
700
701		return 0;
702	}
703
704	val = dw_pcie_readl_dbi(dw, PCIE_PORT_FORCE);
705	val |= PORT_FORCE_DO_DESKEW_FOR_SRIS;
706	dw_pcie_writel_dbi(dw, PCIE_PORT_FORCE, val);
707
708	val = readl(rcar->base + PCIEMSR0);
709	val |= APP_SRIS_MODE;
710	writel(val, rcar->base + PCIEMSR0);
711
712	/*
713	 * The R-Car Gen4 datasheet doesn't describe the PHY registers' name.
714	 * But, the initialization procedure describes these offsets. So,
715	 * this driver has magical offset numbers.
716	 */
717	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(28), 0);
718	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(20), 0);
719	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(12), 0);
720	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x700, BIT(4), 0);
721
722	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(23, 22), BIT(22));
723	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(18, 16), GENMASK(17, 16));
724	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(7, 6), BIT(6));
725	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x148, GENMASK(2, 0), GENMASK(1, 0));
726	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x1d4, GENMASK(16, 15), GENMASK(16, 15));
727	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x514, BIT(26), BIT(26));
728	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(16), 0);
729	rcar_gen4_pcie_phy_reg_update_bits(rcar, 0x0f8, BIT(19), BIT(19));
730
731	val = readl(rcar->base + PCIERSTCTRL1);
732	val &= ~APP_HOLD_PHY_RST;
733	writel(val, rcar->base + PCIERSTCTRL1);
734
735	ret = readl_poll_timeout(rcar->phy_base + 0x0f8, val, val & BIT(18), 100, 10000);
736	if (ret < 0)
737		return ret;
738
739	ret = rcar_gen4_pcie_download_phy_firmware(rcar);
740	if (ret)
741		return ret;
742
743	val = readl(rcar->base + PCIERSTCTRL1);
744	val |= APP_LTSSM_ENABLE;
745	writel(val, rcar->base + PCIERSTCTRL1);
746
747	return 0;
748}
749
750static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie = {
751	.ltssm_control = r8a779f0_pcie_ltssm_control,
752	.mode = DW_PCIE_RC_TYPE,
753};
754
755static struct rcar_gen4_pcie_drvdata drvdata_r8a779f0_pcie_ep = {
756	.ltssm_control = r8a779f0_pcie_ltssm_control,
757	.mode = DW_PCIE_EP_TYPE,
758};
759
760static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie = {
761	.additional_common_init = rcar_gen4_pcie_additional_common_init,
762	.ltssm_control = rcar_gen4_pcie_ltssm_control,
763	.mode = DW_PCIE_RC_TYPE,
764};
765
766static struct rcar_gen4_pcie_drvdata drvdata_rcar_gen4_pcie_ep = {
767	.additional_common_init = rcar_gen4_pcie_additional_common_init,
768	.ltssm_control = rcar_gen4_pcie_ltssm_control,
769	.mode = DW_PCIE_EP_TYPE,
770};
771
772static const struct of_device_id rcar_gen4_pcie_of_match[] = {
773	{
774		.compatible = "renesas,r8a779f0-pcie",
775		.data = &drvdata_r8a779f0_pcie,
776	},
777	{
778		.compatible = "renesas,r8a779f0-pcie-ep",
779		.data = &drvdata_r8a779f0_pcie_ep,
780	},
781	{
782		.compatible = "renesas,rcar-gen4-pcie",
783		.data = &drvdata_rcar_gen4_pcie,
784	},
785	{
786		.compatible = "renesas,rcar-gen4-pcie-ep",
787		.data = &drvdata_rcar_gen4_pcie_ep,
788	},
789	{},
790};
791MODULE_DEVICE_TABLE(of, rcar_gen4_pcie_of_match);
792
793static struct platform_driver rcar_gen4_pcie_driver = {
794	.driver = {
795		.name = "pcie-rcar-gen4",
796		.of_match_table = rcar_gen4_pcie_of_match,
797		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
798	},
799	.probe = rcar_gen4_pcie_probe,
800	.remove = rcar_gen4_pcie_remove,
801};
802module_platform_driver(rcar_gen4_pcie_driver);
803
804MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe controller driver");
805MODULE_LICENSE("GPL");