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pcie-qcom.c
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linux-6.19.14/drivers/pci/controller/dwc/pcie-qcom.c
1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Qualcomm PCIe root complex driver 4 * 5 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved. 6 * Copyright 2015 Linaro Limited. 7 * 8 * Author: Stanimir Varbanov <svarbanov@mm-sol.com> 9 */ 10 11#include <linux/clk.h> 12#include <linux/crc8.h> 13#include <linux/debugfs.h> 14#include <linux/delay.h> 15#include <linux/gpio/consumer.h> 16#include <linux/interconnect.h> 17#include <linux/interrupt.h> 18#include <linux/io.h> 19#include <linux/iopoll.h> 20#include <linux/kernel.h> 21#include <linux/limits.h> 22#include <linux/init.h> 23#include <linux/of.h> 24#include <linux/of_pci.h> 25#include <linux/pci.h> 26#include <linux/pci-ecam.h> 27#include <linux/pm_opp.h> 28#include <linux/pm_runtime.h> 29#include <linux/platform_device.h> 30#include <linux/phy/pcie.h> 31#include <linux/phy/phy.h> 32#include <linux/regulator/consumer.h> 33#include <linux/reset.h> 34#include <linux/slab.h> 35#include <linux/types.h> 36#include <linux/units.h> 37 38#include "../../pci.h" 39#include "../pci-host-common.h" 40#include "pcie-designware.h" 41#include "pcie-qcom-common.h" 42 43/* PARF registers */ 44#define PARF_SYS_CTRL 0x00 45#define PARF_PM_CTRL 0x20 46#define PARF_PCS_DEEMPH 0x34 47#define PARF_PCS_SWING 0x38 48#define PARF_PHY_CTRL 0x40 49#define PARF_PHY_REFCLK 0x4c 50#define PARF_CONFIG_BITS 0x50 51#define PARF_DBI_BASE_ADDR 0x168 52#define PARF_SLV_ADDR_SPACE_SIZE 0x16c 53#define PARF_MHI_CLOCK_RESET_CTRL 0x174 54#define PARF_AXI_MSTR_WR_ADDR_HALT 0x178 55#define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 56#define PARF_Q2A_FLUSH 0x1ac 57#define PARF_LTSSM 0x1b0 58#define PARF_SID_OFFSET 0x234 59#define PARF_BDF_TRANSLATE_CFG 0x24c 60#define PARF_DBI_BASE_ADDR_V2 0x350 61#define PARF_DBI_BASE_ADDR_V2_HI 0x354 62#define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 63#define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c 64#define PARF_NO_SNOOP_OVERRIDE 0x3d4 65#define PARF_ATU_BASE_ADDR 0x634 66#define PARF_ATU_BASE_ADDR_HI 0x638 67#define PARF_DEVICE_TYPE 0x1000 68#define PARF_BDF_TO_SID_TABLE_N 0x2000 69#define PARF_BDF_TO_SID_CFG 0x2c00 70 71/* ELBI registers */ 72#define ELBI_SYS_CTRL 0x04 73 74/* DBI registers */ 75#define AXI_MSTR_RESP_COMP_CTRL0 0x818 76#define AXI_MSTR_RESP_COMP_CTRL1 0x81c 77 78/* MHI registers */ 79#define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 80#define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c 81#define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 82#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 83#define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 84 85/* PARF_SYS_CTRL register fields */ 86#define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) 87#define MST_WAKEUP_EN BIT(13) 88#define SLV_WAKEUP_EN BIT(12) 89#define MSTR_ACLK_CGC_DIS BIT(10) 90#define SLV_ACLK_CGC_DIS BIT(9) 91#define CORE_CLK_CGC_DIS BIT(6) 92#define AUX_PWR_DET BIT(4) 93#define L23_CLK_RMV_DIS BIT(2) 94#define L1_CLK_RMV_DIS BIT(1) 95 96/* PARF_PM_CTRL register fields */ 97#define REQ_NOT_ENTR_L1 BIT(5) 98 99/* PARF_PCS_DEEMPH register fields */ 100#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) FIELD_PREP(GENMASK(21, 16), x) 101#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) FIELD_PREP(GENMASK(13, 8), x) 102#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) FIELD_PREP(GENMASK(5, 0), x) 103 104/* PARF_PCS_SWING register fields */ 105#define PCS_SWING_TX_SWING_FULL(x) FIELD_PREP(GENMASK(14, 8), x) 106#define PCS_SWING_TX_SWING_LOW(x) FIELD_PREP(GENMASK(6, 0), x) 107 108/* PARF_PHY_CTRL register fields */ 109#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK GENMASK(20, 16) 110#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) FIELD_PREP(PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK, x) 111#define PHY_TEST_PWR_DOWN BIT(0) 112 113/* PARF_PHY_REFCLK register fields */ 114#define PHY_REFCLK_SSP_EN BIT(16) 115#define PHY_REFCLK_USE_PAD BIT(12) 116 117/* PARF_CONFIG_BITS register fields */ 118#define PHY_RX0_EQ(x) FIELD_PREP(GENMASK(26, 24), x) 119 120/* PARF_SLV_ADDR_SPACE_SIZE register value */ 121#define SLV_ADDR_SPACE_SZ 0x80000000 122 123/* PARF_MHI_CLOCK_RESET_CTRL register fields */ 124#define AHB_CLK_EN BIT(0) 125#define MSTR_AXI_CLK_EN BIT(1) 126#define BYPASS BIT(4) 127 128/* PARF_AXI_MSTR_WR_ADDR_HALT register fields */ 129#define EN BIT(31) 130 131/* PARF_LTSSM register fields */ 132#define LTSSM_EN BIT(8) 133 134/* PARF_NO_SNOOP_OVERRIDE register fields */ 135#define WR_NO_SNOOP_OVERRIDE_EN BIT(1) 136#define RD_NO_SNOOP_OVERRIDE_EN BIT(3) 137 138/* PARF_DEVICE_TYPE register fields */ 139#define DEVICE_TYPE_RC 0x4 140 141/* PARF_BDF_TO_SID_CFG fields */ 142#define BDF_TO_SID_BYPASS BIT(0) 143 144/* ELBI_SYS_CTRL register fields */ 145#define ELBI_SYS_CTRL_LT_ENABLE BIT(0) 146 147/* AXI_MSTR_RESP_COMP_CTRL0 register fields */ 148#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K 0x4 149#define CFG_REMOTE_RD_REQ_BRIDGE_SIZE_4K 0x5 150 151/* AXI_MSTR_RESP_COMP_CTRL1 register fields */ 152#define CFG_BRIDGE_SB_INIT BIT(0) 153 154/* PCI_EXP_SLTCAP register fields */ 155#define PCIE_CAP_SLOT_POWER_LIMIT_VAL FIELD_PREP(PCI_EXP_SLTCAP_SPLV, 250) 156#define PCIE_CAP_SLOT_POWER_LIMIT_SCALE FIELD_PREP(PCI_EXP_SLTCAP_SPLS, 1) 157#define PCIE_CAP_SLOT_VAL (PCI_EXP_SLTCAP_ABP | \ 158 PCI_EXP_SLTCAP_PCP | \ 159 PCI_EXP_SLTCAP_MRLSP | \ 160 PCI_EXP_SLTCAP_AIP | \ 161 PCI_EXP_SLTCAP_PIP | \ 162 PCI_EXP_SLTCAP_HPS | \ 163 PCI_EXP_SLTCAP_EIP | \ 164 PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ 165 PCIE_CAP_SLOT_POWER_LIMIT_SCALE) 166 167#define PERST_DELAY_US 1000 168 169#define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) 170 171#define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ 172 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed])) 173 174struct qcom_pcie_resources_1_0_0 { 175 struct clk_bulk_data *clks; 176 int num_clks; 177 struct reset_control *core; 178 struct regulator *vdda; 179}; 180 181#define QCOM_PCIE_2_1_0_MAX_RESETS 6 182#define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 183struct qcom_pcie_resources_2_1_0 { 184 struct clk_bulk_data *clks; 185 int num_clks; 186 struct reset_control_bulk_data resets[QCOM_PCIE_2_1_0_MAX_RESETS]; 187 int num_resets; 188 struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; 189}; 190 191#define QCOM_PCIE_2_3_2_MAX_SUPPLY 2 192struct qcom_pcie_resources_2_3_2 { 193 struct clk_bulk_data *clks; 194 int num_clks; 195 struct regulator_bulk_data supplies[QCOM_PCIE_2_3_2_MAX_SUPPLY]; 196}; 197 198#define QCOM_PCIE_2_3_3_MAX_RESETS 7 199struct qcom_pcie_resources_2_3_3 { 200 struct clk_bulk_data *clks; 201 int num_clks; 202 struct reset_control_bulk_data rst[QCOM_PCIE_2_3_3_MAX_RESETS]; 203}; 204 205#define QCOM_PCIE_2_4_0_MAX_RESETS 12 206struct qcom_pcie_resources_2_4_0 { 207 struct clk_bulk_data *clks; 208 int num_clks; 209 struct reset_control_bulk_data resets[QCOM_PCIE_2_4_0_MAX_RESETS]; 210 int num_resets; 211}; 212 213#define QCOM_PCIE_2_7_0_MAX_SUPPLIES 2 214struct qcom_pcie_resources_2_7_0 { 215 struct clk_bulk_data *clks; 216 int num_clks; 217 struct regulator_bulk_data supplies[QCOM_PCIE_2_7_0_MAX_SUPPLIES]; 218 struct reset_control *rst; 219}; 220 221struct qcom_pcie_resources_2_9_0 { 222 struct clk_bulk_data *clks; 223 int num_clks; 224 struct reset_control *rst; 225}; 226 227union qcom_pcie_resources { 228 struct qcom_pcie_resources_1_0_0 v1_0_0; 229 struct qcom_pcie_resources_2_1_0 v2_1_0; 230 struct qcom_pcie_resources_2_3_2 v2_3_2; 231 struct qcom_pcie_resources_2_3_3 v2_3_3; 232 struct qcom_pcie_resources_2_4_0 v2_4_0; 233 struct qcom_pcie_resources_2_7_0 v2_7_0; 234 struct qcom_pcie_resources_2_9_0 v2_9_0; 235}; 236 237struct qcom_pcie; 238 239struct qcom_pcie_ops { 240 int (*get_resources)(struct qcom_pcie *pcie); 241 int (*init)(struct qcom_pcie *pcie); 242 int (*post_init)(struct qcom_pcie *pcie); 243 void (*host_post_init)(struct qcom_pcie *pcie); 244 void (*deinit)(struct qcom_pcie *pcie); 245 void (*ltssm_enable)(struct qcom_pcie *pcie); 246 int (*config_sid)(struct qcom_pcie *pcie); 247}; 248 249 /** 250 * struct qcom_pcie_cfg - Per SoC config struct 251 * @ops: qcom PCIe ops structure 252 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache 253 * snooping 254 * @firmware_managed: Set if the Root Complex is firmware managed 255 */ 256struct qcom_pcie_cfg { 257 const struct qcom_pcie_ops *ops; 258 bool override_no_snoop; 259 bool firmware_managed; 260 bool no_l0s; 261}; 262 263struct qcom_pcie_port { 264 struct list_head list; 265 struct gpio_desc *reset; 266 struct phy *phy; 267}; 268 269struct qcom_pcie { 270 struct dw_pcie *pci; 271 void __iomem *parf; /* DT parf */ 272 void __iomem *mhi; 273 union qcom_pcie_resources res; 274 struct icc_path *icc_mem; 275 struct icc_path *icc_cpu; 276 const struct qcom_pcie_cfg *cfg; 277 struct dentry *debugfs; 278 struct list_head ports; 279 bool suspended; 280 bool use_pm_opp; 281}; 282 283#define to_qcom_pcie(x) dev_get_drvdata((x)->dev) 284 285static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) 286{ 287 struct qcom_pcie_port *port; 288 int val = assert ? 1 : 0; 289 290 list_for_each_entry(port, &pcie->ports, list) 291 gpiod_set_value_cansleep(port->reset, val); 292 293 usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); 294} 295 296static void qcom_ep_reset_assert(struct qcom_pcie *pcie) 297{ 298 qcom_perst_assert(pcie, true); 299} 300 301static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) 302{ 303 /* Ensure that PERST has been asserted for at least 100 ms */ 304 msleep(PCIE_T_PVPERL_MS); 305 qcom_perst_assert(pcie, false); 306} 307 308static int qcom_pcie_start_link(struct dw_pcie *pci) 309{ 310 struct qcom_pcie *pcie = to_qcom_pcie(pci); 311 312 qcom_pcie_common_set_equalization(pci); 313 314 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT) 315 qcom_pcie_common_set_16gt_lane_margining(pci); 316 317 /* Enable Link Training state machine */ 318 if (pcie->cfg->ops->ltssm_enable) 319 pcie->cfg->ops->ltssm_enable(pcie); 320 321 return 0; 322} 323 324static void qcom_pcie_clear_aspm_l0s(struct dw_pcie *pci) 325{ 326 struct qcom_pcie *pcie = to_qcom_pcie(pci); 327 u16 offset; 328 u32 val; 329 330 if (!pcie->cfg->no_l0s) 331 return; 332 333 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 334 335 dw_pcie_dbi_ro_wr_en(pci); 336 337 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 338 val &= ~PCI_EXP_LNKCAP_ASPM_L0S; 339 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 340 341 dw_pcie_dbi_ro_wr_dis(pci); 342} 343 344static void qcom_pcie_clear_hpc(struct dw_pcie *pci) 345{ 346 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 347 u32 val; 348 349 dw_pcie_dbi_ro_wr_en(pci); 350 351 val = readl(pci->dbi_base + offset + PCI_EXP_SLTCAP); 352 val &= ~PCI_EXP_SLTCAP_HPC; 353 writel(val, pci->dbi_base + offset + PCI_EXP_SLTCAP); 354 355 dw_pcie_dbi_ro_wr_dis(pci); 356} 357 358static void qcom_pcie_configure_dbi_base(struct qcom_pcie *pcie) 359{ 360 struct dw_pcie *pci = pcie->pci; 361 362 if (pci->dbi_phys_addr) { 363 /* 364 * PARF_DBI_BASE_ADDR register is in CPU domain and require to 365 * be programmed with CPU physical address. 366 */ 367 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + 368 PARF_DBI_BASE_ADDR); 369 writel(SLV_ADDR_SPACE_SZ, pcie->parf + 370 PARF_SLV_ADDR_SPACE_SIZE); 371 } 372} 373 374static void qcom_pcie_configure_dbi_atu_base(struct qcom_pcie *pcie) 375{ 376 struct dw_pcie *pci = pcie->pci; 377 378 if (pci->dbi_phys_addr) { 379 /* 380 * PARF_DBI_BASE_ADDR_V2 and PARF_ATU_BASE_ADDR registers are 381 * in CPU domain and require to be programmed with CPU 382 * physical addresses. 383 */ 384 writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf + 385 PARF_DBI_BASE_ADDR_V2); 386 writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf + 387 PARF_DBI_BASE_ADDR_V2_HI); 388 389 if (pci->atu_phys_addr) { 390 writel(lower_32_bits(pci->atu_phys_addr), pcie->parf + 391 PARF_ATU_BASE_ADDR); 392 writel(upper_32_bits(pci->atu_phys_addr), pcie->parf + 393 PARF_ATU_BASE_ADDR_HI); 394 } 395 396 writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2); 397 writel(SLV_ADDR_SPACE_SZ, pcie->parf + 398 PARF_SLV_ADDR_SPACE_SIZE_V2_HI); 399 } 400} 401 402static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) 403{ 404 struct dw_pcie *pci = pcie->pci; 405 u32 val; 406 407 if (!pci->elbi_base) { 408 dev_err(pci->dev, "ELBI is not present\n"); 409 return; 410 } 411 /* enable link training */ 412 val = readl(pci->elbi_base + ELBI_SYS_CTRL); 413 val |= ELBI_SYS_CTRL_LT_ENABLE; 414 writel(val, pci->elbi_base + ELBI_SYS_CTRL); 415} 416 417static int qcom_pcie_get_resources_2_1_0(struct qcom_pcie *pcie) 418{ 419 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 420 struct dw_pcie *pci = pcie->pci; 421 struct device *dev = pci->dev; 422 bool is_apq = of_device_is_compatible(dev->of_node, "qcom,pcie-apq8064"); 423 int ret; 424 425 res->supplies[0].supply = "vdda"; 426 res->supplies[1].supply = "vdda_phy"; 427 res->supplies[2].supply = "vdda_refclk"; 428 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 429 res->supplies); 430 if (ret) 431 return ret; 432 433 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 434 if (res->num_clks < 0) { 435 dev_err(dev, "Failed to get clocks\n"); 436 return res->num_clks; 437 } 438 439 res->resets[0].id = "pci"; 440 res->resets[1].id = "axi"; 441 res->resets[2].id = "ahb"; 442 res->resets[3].id = "por"; 443 res->resets[4].id = "phy"; 444 res->resets[5].id = "ext"; 445 446 /* ext is optional on APQ8016 */ 447 res->num_resets = is_apq ? 5 : 6; 448 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 449 if (ret < 0) 450 return ret; 451 452 return 0; 453} 454 455static void qcom_pcie_deinit_2_1_0(struct qcom_pcie *pcie) 456{ 457 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 458 459 clk_bulk_disable_unprepare(res->num_clks, res->clks); 460 reset_control_bulk_assert(res->num_resets, res->resets); 461 462 writel(1, pcie->parf + PARF_PHY_CTRL); 463 464 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 465} 466 467static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) 468{ 469 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 470 struct dw_pcie *pci = pcie->pci; 471 struct device *dev = pci->dev; 472 int ret; 473 474 /* reset the PCIe interface as uboot can leave it undefined state */ 475 ret = reset_control_bulk_assert(res->num_resets, res->resets); 476 if (ret < 0) { 477 dev_err(dev, "cannot assert resets\n"); 478 return ret; 479 } 480 481 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 482 if (ret < 0) { 483 dev_err(dev, "cannot enable regulators\n"); 484 return ret; 485 } 486 487 ret = reset_control_bulk_deassert(res->num_resets, res->resets); 488 if (ret < 0) { 489 dev_err(dev, "cannot deassert resets\n"); 490 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 491 return ret; 492 } 493 494 return 0; 495} 496 497static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) 498{ 499 struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; 500 struct dw_pcie *pci = pcie->pci; 501 struct device *dev = pci->dev; 502 struct device_node *node = dev->of_node; 503 u32 val; 504 int ret; 505 506 /* enable PCIe clocks and resets */ 507 val = readl(pcie->parf + PARF_PHY_CTRL); 508 val &= ~PHY_TEST_PWR_DOWN; 509 writel(val, pcie->parf + PARF_PHY_CTRL); 510 511 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 512 if (ret) 513 return ret; 514 515 if (of_device_is_compatible(node, "qcom,pcie-ipq8064") || 516 of_device_is_compatible(node, "qcom,pcie-ipq8064-v2")) { 517 writel(PCS_DEEMPH_TX_DEEMPH_GEN1(24) | 518 PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(24) | 519 PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(34), 520 pcie->parf + PARF_PCS_DEEMPH); 521 writel(PCS_SWING_TX_SWING_FULL(120) | 522 PCS_SWING_TX_SWING_LOW(120), 523 pcie->parf + PARF_PCS_SWING); 524 writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS); 525 } 526 527 if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) { 528 /* set TX termination offset */ 529 val = readl(pcie->parf + PARF_PHY_CTRL); 530 val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK; 531 val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7); 532 writel(val, pcie->parf + PARF_PHY_CTRL); 533 } 534 535 /* enable external reference clock */ 536 val = readl(pcie->parf + PARF_PHY_REFCLK); 537 /* USE_PAD is required only for ipq806x */ 538 if (!of_device_is_compatible(node, "qcom,pcie-apq8064")) 539 val &= ~PHY_REFCLK_USE_PAD; 540 val |= PHY_REFCLK_SSP_EN; 541 writel(val, pcie->parf + PARF_PHY_REFCLK); 542 543 /* wait for clock acquisition */ 544 usleep_range(1000, 1500); 545 546 /* Set the Max TLP size to 2K, instead of using default of 4K */ 547 writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, 548 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL0); 549 writel(CFG_BRIDGE_SB_INIT, 550 pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); 551 552 qcom_pcie_clear_hpc(pcie->pci); 553 554 return 0; 555} 556 557static int qcom_pcie_get_resources_1_0_0(struct qcom_pcie *pcie) 558{ 559 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 560 struct dw_pcie *pci = pcie->pci; 561 struct device *dev = pci->dev; 562 563 res->vdda = devm_regulator_get(dev, "vdda"); 564 if (IS_ERR(res->vdda)) 565 return PTR_ERR(res->vdda); 566 567 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 568 if (res->num_clks < 0) { 569 dev_err(dev, "Failed to get clocks\n"); 570 return res->num_clks; 571 } 572 573 res->core = devm_reset_control_get_exclusive(dev, "core"); 574 return PTR_ERR_OR_ZERO(res->core); 575} 576 577static void qcom_pcie_deinit_1_0_0(struct qcom_pcie *pcie) 578{ 579 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 580 581 reset_control_assert(res->core); 582 clk_bulk_disable_unprepare(res->num_clks, res->clks); 583 regulator_disable(res->vdda); 584} 585 586static int qcom_pcie_init_1_0_0(struct qcom_pcie *pcie) 587{ 588 struct qcom_pcie_resources_1_0_0 *res = &pcie->res.v1_0_0; 589 struct dw_pcie *pci = pcie->pci; 590 struct device *dev = pci->dev; 591 int ret; 592 593 ret = reset_control_deassert(res->core); 594 if (ret) { 595 dev_err(dev, "cannot deassert core reset\n"); 596 return ret; 597 } 598 599 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 600 if (ret) { 601 dev_err(dev, "cannot prepare/enable clocks\n"); 602 goto err_assert_reset; 603 } 604 605 ret = regulator_enable(res->vdda); 606 if (ret) { 607 dev_err(dev, "cannot enable vdda regulator\n"); 608 goto err_disable_clks; 609 } 610 611 return 0; 612 613err_disable_clks: 614 clk_bulk_disable_unprepare(res->num_clks, res->clks); 615err_assert_reset: 616 reset_control_assert(res->core); 617 618 return ret; 619} 620 621static int qcom_pcie_post_init_1_0_0(struct qcom_pcie *pcie) 622{ 623 qcom_pcie_configure_dbi_base(pcie); 624 625 if (IS_ENABLED(CONFIG_PCI_MSI)) { 626 u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 627 628 val |= EN; 629 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT); 630 } 631 632 qcom_pcie_clear_hpc(pcie->pci); 633 634 return 0; 635} 636 637static int qcom_pcie_assert_perst(struct dw_pcie *pci, bool assert) 638{ 639 struct qcom_pcie *pcie = to_qcom_pcie(pci); 640 641 if (assert) 642 qcom_ep_reset_assert(pcie); 643 else 644 qcom_ep_reset_deassert(pcie); 645 646 return 0; 647} 648 649static void qcom_pcie_2_3_2_ltssm_enable(struct qcom_pcie *pcie) 650{ 651 u32 val; 652 653 /* enable link training */ 654 val = readl(pcie->parf + PARF_LTSSM); 655 val |= LTSSM_EN; 656 writel(val, pcie->parf + PARF_LTSSM); 657} 658 659static int qcom_pcie_get_resources_2_3_2(struct qcom_pcie *pcie) 660{ 661 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 662 struct dw_pcie *pci = pcie->pci; 663 struct device *dev = pci->dev; 664 int ret; 665 666 res->supplies[0].supply = "vdda"; 667 res->supplies[1].supply = "vddpe-3v3"; 668 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 669 res->supplies); 670 if (ret) 671 return ret; 672 673 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 674 if (res->num_clks < 0) { 675 dev_err(dev, "Failed to get clocks\n"); 676 return res->num_clks; 677 } 678 679 return 0; 680} 681 682static void qcom_pcie_deinit_2_3_2(struct qcom_pcie *pcie) 683{ 684 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 685 686 clk_bulk_disable_unprepare(res->num_clks, res->clks); 687 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 688} 689 690static int qcom_pcie_init_2_3_2(struct qcom_pcie *pcie) 691{ 692 struct qcom_pcie_resources_2_3_2 *res = &pcie->res.v2_3_2; 693 struct dw_pcie *pci = pcie->pci; 694 struct device *dev = pci->dev; 695 int ret; 696 697 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 698 if (ret < 0) { 699 dev_err(dev, "cannot enable regulators\n"); 700 return ret; 701 } 702 703 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 704 if (ret) { 705 dev_err(dev, "cannot prepare/enable clocks\n"); 706 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 707 return ret; 708 } 709 710 return 0; 711} 712 713static int qcom_pcie_post_init_2_3_2(struct qcom_pcie *pcie) 714{ 715 u32 val; 716 717 /* enable PCIe clocks and resets */ 718 val = readl(pcie->parf + PARF_PHY_CTRL); 719 val &= ~PHY_TEST_PWR_DOWN; 720 writel(val, pcie->parf + PARF_PHY_CTRL); 721 722 qcom_pcie_configure_dbi_base(pcie); 723 724 /* MAC PHY_POWERDOWN MUX DISABLE */ 725 val = readl(pcie->parf + PARF_SYS_CTRL); 726 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 727 writel(val, pcie->parf + PARF_SYS_CTRL); 728 729 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 730 val |= BYPASS; 731 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 732 733 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 734 val |= EN; 735 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 736 737 qcom_pcie_clear_hpc(pcie->pci); 738 739 return 0; 740} 741 742static int qcom_pcie_get_resources_2_4_0(struct qcom_pcie *pcie) 743{ 744 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 745 struct dw_pcie *pci = pcie->pci; 746 struct device *dev = pci->dev; 747 bool is_ipq = of_device_is_compatible(dev->of_node, "qcom,pcie-ipq4019"); 748 int ret; 749 750 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 751 if (res->num_clks < 0) { 752 dev_err(dev, "Failed to get clocks\n"); 753 return res->num_clks; 754 } 755 756 res->resets[0].id = "axi_m"; 757 res->resets[1].id = "axi_s"; 758 res->resets[2].id = "axi_m_sticky"; 759 res->resets[3].id = "pipe_sticky"; 760 res->resets[4].id = "pwr"; 761 res->resets[5].id = "ahb"; 762 res->resets[6].id = "pipe"; 763 res->resets[7].id = "axi_m_vmid"; 764 res->resets[8].id = "axi_s_xpu"; 765 res->resets[9].id = "parf"; 766 res->resets[10].id = "phy"; 767 res->resets[11].id = "phy_ahb"; 768 769 res->num_resets = is_ipq ? 12 : 6; 770 771 ret = devm_reset_control_bulk_get_exclusive(dev, res->num_resets, res->resets); 772 if (ret < 0) 773 return ret; 774 775 return 0; 776} 777 778static void qcom_pcie_deinit_2_4_0(struct qcom_pcie *pcie) 779{ 780 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 781 782 reset_control_bulk_assert(res->num_resets, res->resets); 783 clk_bulk_disable_unprepare(res->num_clks, res->clks); 784} 785 786static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) 787{ 788 struct qcom_pcie_resources_2_4_0 *res = &pcie->res.v2_4_0; 789 struct dw_pcie *pci = pcie->pci; 790 struct device *dev = pci->dev; 791 int ret; 792 793 ret = reset_control_bulk_assert(res->num_resets, res->resets); 794 if (ret < 0) { 795 dev_err(dev, "cannot assert resets\n"); 796 return ret; 797 } 798 799 usleep_range(10000, 12000); 800 801 ret = reset_control_bulk_deassert(res->num_resets, res->resets); 802 if (ret < 0) { 803 dev_err(dev, "cannot deassert resets\n"); 804 return ret; 805 } 806 807 usleep_range(10000, 12000); 808 809 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 810 if (ret) { 811 reset_control_bulk_assert(res->num_resets, res->resets); 812 return ret; 813 } 814 815 return 0; 816} 817 818static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) 819{ 820 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 821 struct dw_pcie *pci = pcie->pci; 822 struct device *dev = pci->dev; 823 int ret; 824 825 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 826 if (res->num_clks < 0) { 827 dev_err(dev, "Failed to get clocks\n"); 828 return res->num_clks; 829 } 830 831 res->rst[0].id = "axi_m"; 832 res->rst[1].id = "axi_s"; 833 res->rst[2].id = "pipe"; 834 res->rst[3].id = "axi_m_sticky"; 835 res->rst[4].id = "sticky"; 836 res->rst[5].id = "ahb"; 837 res->rst[6].id = "sleep"; 838 839 ret = devm_reset_control_bulk_get_exclusive(dev, ARRAY_SIZE(res->rst), res->rst); 840 if (ret < 0) 841 return ret; 842 843 return 0; 844} 845 846static void qcom_pcie_deinit_2_3_3(struct qcom_pcie *pcie) 847{ 848 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 849 850 clk_bulk_disable_unprepare(res->num_clks, res->clks); 851} 852 853static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie) 854{ 855 struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; 856 struct dw_pcie *pci = pcie->pci; 857 struct device *dev = pci->dev; 858 int ret; 859 860 ret = reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 861 if (ret < 0) { 862 dev_err(dev, "cannot assert resets\n"); 863 return ret; 864 } 865 866 usleep_range(2000, 2500); 867 868 ret = reset_control_bulk_deassert(ARRAY_SIZE(res->rst), res->rst); 869 if (ret < 0) { 870 dev_err(dev, "cannot deassert resets\n"); 871 return ret; 872 } 873 874 /* 875 * Don't have a way to see if the reset has completed. 876 * Wait for some time. 877 */ 878 usleep_range(2000, 2500); 879 880 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 881 if (ret) { 882 dev_err(dev, "cannot prepare/enable clocks\n"); 883 goto err_assert_resets; 884 } 885 886 return 0; 887 888err_assert_resets: 889 /* 890 * Not checking for failure, will anyway return 891 * the original failure in 'ret'. 892 */ 893 reset_control_bulk_assert(ARRAY_SIZE(res->rst), res->rst); 894 895 return ret; 896} 897 898static int qcom_pcie_post_init_2_3_3(struct qcom_pcie *pcie) 899{ 900 struct dw_pcie *pci = pcie->pci; 901 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 902 u32 val; 903 904 val = readl(pcie->parf + PARF_PHY_CTRL); 905 val &= ~PHY_TEST_PWR_DOWN; 906 writel(val, pcie->parf + PARF_PHY_CTRL); 907 908 qcom_pcie_configure_dbi_atu_base(pcie); 909 910 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS 911 | SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 912 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 913 pcie->parf + PARF_SYS_CTRL); 914 writel(0, pcie->parf + PARF_Q2A_FLUSH); 915 916 writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND); 917 918 dw_pcie_dbi_ro_wr_en(pci); 919 920 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 921 922 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 923 val &= ~PCI_EXP_LNKCAP_ASPMS; 924 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 925 926 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 927 PCI_EXP_DEVCTL2); 928 929 dw_pcie_dbi_ro_wr_dis(pci); 930 931 return 0; 932} 933 934static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) 935{ 936 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 937 struct dw_pcie *pci = pcie->pci; 938 struct device *dev = pci->dev; 939 int ret; 940 941 res->rst = devm_reset_control_array_get_exclusive(dev); 942 if (IS_ERR(res->rst)) 943 return PTR_ERR(res->rst); 944 945 res->supplies[0].supply = "vdda"; 946 res->supplies[1].supply = "vddpe-3v3"; 947 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(res->supplies), 948 res->supplies); 949 if (ret) 950 return ret; 951 952 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 953 if (res->num_clks < 0) { 954 dev_err(dev, "Failed to get clocks\n"); 955 return res->num_clks; 956 } 957 958 return 0; 959} 960 961static int qcom_pcie_init_2_7_0(struct qcom_pcie *pcie) 962{ 963 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 964 struct dw_pcie *pci = pcie->pci; 965 struct device *dev = pci->dev; 966 u32 val; 967 int ret; 968 969 ret = regulator_bulk_enable(ARRAY_SIZE(res->supplies), res->supplies); 970 if (ret < 0) { 971 dev_err(dev, "cannot enable regulators\n"); 972 return ret; 973 } 974 975 ret = clk_bulk_prepare_enable(res->num_clks, res->clks); 976 if (ret < 0) 977 goto err_disable_regulators; 978 979 ret = reset_control_assert(res->rst); 980 if (ret) { 981 dev_err(dev, "reset assert failed (%d)\n", ret); 982 goto err_disable_clocks; 983 } 984 985 usleep_range(1000, 1500); 986 987 ret = reset_control_deassert(res->rst); 988 if (ret) { 989 dev_err(dev, "reset deassert failed (%d)\n", ret); 990 goto err_disable_clocks; 991 } 992 993 /* Wait for reset to complete, required on SM8450 */ 994 usleep_range(1000, 1500); 995 996 /* configure PCIe to RC mode */ 997 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 998 999 /* enable PCIe clocks and resets */ 1000 val = readl(pcie->parf + PARF_PHY_CTRL); 1001 val &= ~PHY_TEST_PWR_DOWN; 1002 writel(val, pcie->parf + PARF_PHY_CTRL); 1003 1004 qcom_pcie_configure_dbi_atu_base(pcie); 1005 1006 /* MAC PHY_POWERDOWN MUX DISABLE */ 1007 val = readl(pcie->parf + PARF_SYS_CTRL); 1008 val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; 1009 writel(val, pcie->parf + PARF_SYS_CTRL); 1010 1011 val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 1012 val |= BYPASS; 1013 writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 1014 1015 /* Enable L1 and L1SS */ 1016 val = readl(pcie->parf + PARF_PM_CTRL); 1017 val &= ~REQ_NOT_ENTR_L1; 1018 writel(val, pcie->parf + PARF_PM_CTRL); 1019 1020 pci->l1ss_support = true; 1021 1022 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 1023 val |= EN; 1024 writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); 1025 1026 return 0; 1027err_disable_clocks: 1028 clk_bulk_disable_unprepare(res->num_clks, res->clks); 1029err_disable_regulators: 1030 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 1031 1032 return ret; 1033} 1034 1035static int qcom_pcie_post_init_2_7_0(struct qcom_pcie *pcie) 1036{ 1037 const struct qcom_pcie_cfg *pcie_cfg = pcie->cfg; 1038 1039 if (pcie_cfg->override_no_snoop) 1040 writel(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN, 1041 pcie->parf + PARF_NO_SNOOP_OVERRIDE); 1042 1043 qcom_pcie_clear_hpc(pcie->pci); 1044 1045 return 0; 1046} 1047 1048static int qcom_pcie_enable_aspm(struct pci_dev *pdev, void *userdata) 1049{ 1050 /* 1051 * Downstream devices need to be in D0 state before enabling PCI PM 1052 * substates. 1053 */ 1054 pci_set_power_state_locked(pdev, PCI_D0); 1055 pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); 1056 1057 return 0; 1058} 1059 1060static void qcom_pcie_host_post_init_2_7_0(struct qcom_pcie *pcie) 1061{ 1062 struct dw_pcie_rp *pp = &pcie->pci->pp; 1063 1064 pci_walk_bus(pp->bridge->bus, qcom_pcie_enable_aspm, NULL); 1065} 1066 1067static void qcom_pcie_deinit_2_7_0(struct qcom_pcie *pcie) 1068{ 1069 struct qcom_pcie_resources_2_7_0 *res = &pcie->res.v2_7_0; 1070 1071 clk_bulk_disable_unprepare(res->num_clks, res->clks); 1072 1073 regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); 1074} 1075 1076static int qcom_pcie_config_sid_1_9_0(struct qcom_pcie *pcie) 1077{ 1078 /* iommu map structure */ 1079 struct { 1080 u32 bdf; 1081 u32 phandle; 1082 u32 smmu_sid; 1083 u32 smmu_sid_len; 1084 } *map; 1085 void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N; 1086 struct device *dev = pcie->pci->dev; 1087 u8 qcom_pcie_crc8_table[CRC8_TABLE_SIZE]; 1088 int i, nr_map, size = 0; 1089 u32 smmu_sid_base; 1090 u32 val; 1091 1092 of_get_property(dev->of_node, "iommu-map", &size); 1093 if (!size) 1094 return 0; 1095 1096 /* Enable BDF to SID translation by disabling bypass mode (default) */ 1097 val = readl(pcie->parf + PARF_BDF_TO_SID_CFG); 1098 val &= ~BDF_TO_SID_BYPASS; 1099 writel(val, pcie->parf + PARF_BDF_TO_SID_CFG); 1100 1101 map = kzalloc(size, GFP_KERNEL); 1102 if (!map) 1103 return -ENOMEM; 1104 1105 of_property_read_u32_array(dev->of_node, "iommu-map", (u32 *)map, 1106 size / sizeof(u32)); 1107 1108 nr_map = size / (sizeof(*map)); 1109 1110 crc8_populate_msb(qcom_pcie_crc8_table, QCOM_PCIE_CRC8_POLYNOMIAL); 1111 1112 /* Registers need to be zero out first */ 1113 memset_io(bdf_to_sid_base, 0, CRC8_TABLE_SIZE * sizeof(u32)); 1114 1115 /* Extract the SMMU SID base from the first entry of iommu-map */ 1116 smmu_sid_base = map[0].smmu_sid; 1117 1118 /* Look for an available entry to hold the mapping */ 1119 for (i = 0; i < nr_map; i++) { 1120 __be16 bdf_be = cpu_to_be16(map[i].bdf); 1121 u32 val; 1122 u8 hash; 1123 1124 hash = crc8(qcom_pcie_crc8_table, (u8 *)&bdf_be, sizeof(bdf_be), 0); 1125 1126 val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1127 1128 /* If the register is already populated, look for next available entry */ 1129 while (val) { 1130 u8 current_hash = hash++; 1131 u8 next_mask = 0xff; 1132 1133 /* If NEXT field is NULL then update it with next hash */ 1134 if (!(val & next_mask)) { 1135 val |= (u32)hash; 1136 writel(val, bdf_to_sid_base + current_hash * sizeof(u32)); 1137 } 1138 1139 val = readl(bdf_to_sid_base + hash * sizeof(u32)); 1140 } 1141 1142 /* BDF [31:16] | SID [15:8] | NEXT [7:0] */ 1143 val = map[i].bdf << 16 | (map[i].smmu_sid - smmu_sid_base) << 8 | 0; 1144 writel(val, bdf_to_sid_base + hash * sizeof(u32)); 1145 } 1146 1147 kfree(map); 1148 1149 return 0; 1150} 1151 1152static int qcom_pcie_get_resources_2_9_0(struct qcom_pcie *pcie) 1153{ 1154 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1155 struct dw_pcie *pci = pcie->pci; 1156 struct device *dev = pci->dev; 1157 1158 res->num_clks = devm_clk_bulk_get_all(dev, &res->clks); 1159 if (res->num_clks < 0) { 1160 dev_err(dev, "Failed to get clocks\n"); 1161 return res->num_clks; 1162 } 1163 1164 res->rst = devm_reset_control_array_get_exclusive(dev); 1165 if (IS_ERR(res->rst)) 1166 return PTR_ERR(res->rst); 1167 1168 return 0; 1169} 1170 1171static void qcom_pcie_deinit_2_9_0(struct qcom_pcie *pcie) 1172{ 1173 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1174 1175 clk_bulk_disable_unprepare(res->num_clks, res->clks); 1176} 1177 1178static int qcom_pcie_init_2_9_0(struct qcom_pcie *pcie) 1179{ 1180 struct qcom_pcie_resources_2_9_0 *res = &pcie->res.v2_9_0; 1181 struct device *dev = pcie->pci->dev; 1182 int ret; 1183 1184 ret = reset_control_assert(res->rst); 1185 if (ret) { 1186 dev_err(dev, "reset assert failed (%d)\n", ret); 1187 return ret; 1188 } 1189 1190 /* 1191 * Delay periods before and after reset deassert are working values 1192 * from downstream Codeaurora kernel 1193 */ 1194 usleep_range(2000, 2500); 1195 1196 ret = reset_control_deassert(res->rst); 1197 if (ret) { 1198 dev_err(dev, "reset deassert failed (%d)\n", ret); 1199 return ret; 1200 } 1201 1202 usleep_range(2000, 2500); 1203 1204 return clk_bulk_prepare_enable(res->num_clks, res->clks); 1205} 1206 1207static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) 1208{ 1209 struct dw_pcie *pci = pcie->pci; 1210 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1211 u32 val; 1212 int i; 1213 1214 val = readl(pcie->parf + PARF_PHY_CTRL); 1215 val &= ~PHY_TEST_PWR_DOWN; 1216 writel(val, pcie->parf + PARF_PHY_CTRL); 1217 1218 qcom_pcie_configure_dbi_atu_base(pcie); 1219 1220 writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE); 1221 writel(BYPASS | MSTR_AXI_CLK_EN | AHB_CLK_EN, 1222 pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); 1223 writel(GEN3_RELATED_OFF_RXEQ_RGRDLESS_RXTS | 1224 GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL, 1225 pci->dbi_base + GEN3_RELATED_OFF); 1226 1227 writel(MST_WAKEUP_EN | SLV_WAKEUP_EN | MSTR_ACLK_CGC_DIS | 1228 SLV_ACLK_CGC_DIS | CORE_CLK_CGC_DIS | 1229 AUX_PWR_DET | L23_CLK_RMV_DIS | L1_CLK_RMV_DIS, 1230 pcie->parf + PARF_SYS_CTRL); 1231 1232 writel(0, pcie->parf + PARF_Q2A_FLUSH); 1233 1234 dw_pcie_dbi_ro_wr_en(pci); 1235 1236 writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); 1237 1238 val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); 1239 val &= ~PCI_EXP_LNKCAP_ASPMS; 1240 writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP); 1241 1242 writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + 1243 PCI_EXP_DEVCTL2); 1244 1245 dw_pcie_dbi_ro_wr_dis(pci); 1246 1247 for (i = 0; i < 256; i++) 1248 writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); 1249 1250 return 0; 1251} 1252 1253static bool qcom_pcie_link_up(struct dw_pcie *pci) 1254{ 1255 u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1256 u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1257 1258 return val & PCI_EXP_LNKSTA_DLLLA; 1259} 1260 1261static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) 1262{ 1263 struct qcom_pcie_port *port; 1264 1265 list_for_each_entry(port, &pcie->ports, list) 1266 phy_power_off(port->phy); 1267} 1268 1269static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) 1270{ 1271 struct qcom_pcie_port *port; 1272 int ret; 1273 1274 list_for_each_entry(port, &pcie->ports, list) { 1275 ret = phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); 1276 if (ret) 1277 return ret; 1278 1279 ret = phy_power_on(port->phy); 1280 if (ret) { 1281 qcom_pcie_phy_power_off(pcie); 1282 return ret; 1283 } 1284 } 1285 1286 return 0; 1287} 1288 1289static int qcom_pcie_host_init(struct dw_pcie_rp *pp) 1290{ 1291 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1292 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1293 int ret; 1294 1295 qcom_ep_reset_assert(pcie); 1296 1297 ret = pcie->cfg->ops->init(pcie); 1298 if (ret) 1299 return ret; 1300 1301 ret = qcom_pcie_phy_power_on(pcie); 1302 if (ret) 1303 goto err_deinit; 1304 1305 if (pcie->cfg->ops->post_init) { 1306 ret = pcie->cfg->ops->post_init(pcie); 1307 if (ret) 1308 goto err_disable_phy; 1309 } 1310 1311 qcom_pcie_clear_aspm_l0s(pcie->pci); 1312 1313 qcom_ep_reset_deassert(pcie); 1314 1315 if (pcie->cfg->ops->config_sid) { 1316 ret = pcie->cfg->ops->config_sid(pcie); 1317 if (ret) 1318 goto err_assert_reset; 1319 } 1320 1321 return 0; 1322 1323err_assert_reset: 1324 qcom_ep_reset_assert(pcie); 1325err_disable_phy: 1326 qcom_pcie_phy_power_off(pcie); 1327err_deinit: 1328 pcie->cfg->ops->deinit(pcie); 1329 1330 return ret; 1331} 1332 1333static void qcom_pcie_host_deinit(struct dw_pcie_rp *pp) 1334{ 1335 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1336 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1337 1338 qcom_ep_reset_assert(pcie); 1339 qcom_pcie_phy_power_off(pcie); 1340 pcie->cfg->ops->deinit(pcie); 1341} 1342 1343static void qcom_pcie_host_post_init(struct dw_pcie_rp *pp) 1344{ 1345 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); 1346 struct qcom_pcie *pcie = to_qcom_pcie(pci); 1347 1348 if (pcie->cfg->ops->host_post_init) 1349 pcie->cfg->ops->host_post_init(pcie); 1350} 1351 1352static const struct dw_pcie_host_ops qcom_pcie_dw_ops = { 1353 .init = qcom_pcie_host_init, 1354 .deinit = qcom_pcie_host_deinit, 1355 .post_init = qcom_pcie_host_post_init, 1356}; 1357 1358/* Qcom IP rev.: 2.1.0 Synopsys IP rev.: 4.01a */ 1359static const struct qcom_pcie_ops ops_2_1_0 = { 1360 .get_resources = qcom_pcie_get_resources_2_1_0, 1361 .init = qcom_pcie_init_2_1_0, 1362 .post_init = qcom_pcie_post_init_2_1_0, 1363 .deinit = qcom_pcie_deinit_2_1_0, 1364 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 1365}; 1366 1367/* Qcom IP rev.: 1.0.0 Synopsys IP rev.: 4.11a */ 1368static const struct qcom_pcie_ops ops_1_0_0 = { 1369 .get_resources = qcom_pcie_get_resources_1_0_0, 1370 .init = qcom_pcie_init_1_0_0, 1371 .post_init = qcom_pcie_post_init_1_0_0, 1372 .deinit = qcom_pcie_deinit_1_0_0, 1373 .ltssm_enable = qcom_pcie_2_1_0_ltssm_enable, 1374}; 1375 1376/* Qcom IP rev.: 2.3.2 Synopsys IP rev.: 4.21a */ 1377static const struct qcom_pcie_ops ops_2_3_2 = { 1378 .get_resources = qcom_pcie_get_resources_2_3_2, 1379 .init = qcom_pcie_init_2_3_2, 1380 .post_init = qcom_pcie_post_init_2_3_2, 1381 .deinit = qcom_pcie_deinit_2_3_2, 1382 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1383}; 1384 1385/* Qcom IP rev.: 2.4.0 Synopsys IP rev.: 4.20a */ 1386static const struct qcom_pcie_ops ops_2_4_0 = { 1387 .get_resources = qcom_pcie_get_resources_2_4_0, 1388 .init = qcom_pcie_init_2_4_0, 1389 .post_init = qcom_pcie_post_init_2_3_2, 1390 .deinit = qcom_pcie_deinit_2_4_0, 1391 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1392}; 1393 1394/* Qcom IP rev.: 2.3.3 Synopsys IP rev.: 4.30a */ 1395static const struct qcom_pcie_ops ops_2_3_3 = { 1396 .get_resources = qcom_pcie_get_resources_2_3_3, 1397 .init = qcom_pcie_init_2_3_3, 1398 .post_init = qcom_pcie_post_init_2_3_3, 1399 .deinit = qcom_pcie_deinit_2_3_3, 1400 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1401}; 1402 1403/* Qcom IP rev.: 2.7.0 Synopsys IP rev.: 4.30a */ 1404static const struct qcom_pcie_ops ops_2_7_0 = { 1405 .get_resources = qcom_pcie_get_resources_2_7_0, 1406 .init = qcom_pcie_init_2_7_0, 1407 .post_init = qcom_pcie_post_init_2_7_0, 1408 .deinit = qcom_pcie_deinit_2_7_0, 1409 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1410}; 1411 1412/* Qcom IP rev.: 1.9.0 */ 1413static const struct qcom_pcie_ops ops_1_9_0 = { 1414 .get_resources = qcom_pcie_get_resources_2_7_0, 1415 .init = qcom_pcie_init_2_7_0, 1416 .post_init = qcom_pcie_post_init_2_7_0, 1417 .host_post_init = qcom_pcie_host_post_init_2_7_0, 1418 .deinit = qcom_pcie_deinit_2_7_0, 1419 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1420 .config_sid = qcom_pcie_config_sid_1_9_0, 1421}; 1422 1423/* Qcom IP rev.: 1.21.0 Synopsys IP rev.: 5.60a */ 1424static const struct qcom_pcie_ops ops_1_21_0 = { 1425 .get_resources = qcom_pcie_get_resources_2_7_0, 1426 .init = qcom_pcie_init_2_7_0, 1427 .post_init = qcom_pcie_post_init_2_7_0, 1428 .host_post_init = qcom_pcie_host_post_init_2_7_0, 1429 .deinit = qcom_pcie_deinit_2_7_0, 1430 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1431}; 1432 1433/* Qcom IP rev.: 2.9.0 Synopsys IP rev.: 5.00a */ 1434static const struct qcom_pcie_ops ops_2_9_0 = { 1435 .get_resources = qcom_pcie_get_resources_2_9_0, 1436 .init = qcom_pcie_init_2_9_0, 1437 .post_init = qcom_pcie_post_init_2_9_0, 1438 .deinit = qcom_pcie_deinit_2_9_0, 1439 .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, 1440}; 1441 1442static const struct qcom_pcie_cfg cfg_1_0_0 = { 1443 .ops = &ops_1_0_0, 1444}; 1445 1446static const struct qcom_pcie_cfg cfg_1_9_0 = { 1447 .ops = &ops_1_9_0, 1448}; 1449 1450static const struct qcom_pcie_cfg cfg_1_34_0 = { 1451 .ops = &ops_1_9_0, 1452 .override_no_snoop = true, 1453}; 1454 1455static const struct qcom_pcie_cfg cfg_2_1_0 = { 1456 .ops = &ops_2_1_0, 1457}; 1458 1459static const struct qcom_pcie_cfg cfg_2_3_2 = { 1460 .ops = &ops_2_3_2, 1461 .no_l0s = true, 1462}; 1463 1464static const struct qcom_pcie_cfg cfg_2_3_3 = { 1465 .ops = &ops_2_3_3, 1466}; 1467 1468static const struct qcom_pcie_cfg cfg_2_4_0 = { 1469 .ops = &ops_2_4_0, 1470}; 1471 1472static const struct qcom_pcie_cfg cfg_2_7_0 = { 1473 .ops = &ops_2_7_0, 1474}; 1475 1476static const struct qcom_pcie_cfg cfg_2_9_0 = { 1477 .ops = &ops_2_9_0, 1478}; 1479 1480static const struct qcom_pcie_cfg cfg_sc8280xp = { 1481 .ops = &ops_1_21_0, 1482 .no_l0s = true, 1483}; 1484 1485static const struct qcom_pcie_cfg cfg_fw_managed = { 1486 .firmware_managed = true, 1487}; 1488 1489static const struct dw_pcie_ops dw_pcie_ops = { 1490 .link_up = qcom_pcie_link_up, 1491 .start_link = qcom_pcie_start_link, 1492 .assert_perst = qcom_pcie_assert_perst, 1493}; 1494 1495static int qcom_pcie_icc_init(struct qcom_pcie *pcie) 1496{ 1497 struct dw_pcie *pci = pcie->pci; 1498 int ret; 1499 1500 pcie->icc_mem = devm_of_icc_get(pci->dev, "pcie-mem"); 1501 if (IS_ERR(pcie->icc_mem)) 1502 return PTR_ERR(pcie->icc_mem); 1503 1504 pcie->icc_cpu = devm_of_icc_get(pci->dev, "cpu-pcie"); 1505 if (IS_ERR(pcie->icc_cpu)) 1506 return PTR_ERR(pcie->icc_cpu); 1507 /* 1508 * Some Qualcomm platforms require interconnect bandwidth constraints 1509 * to be set before enabling interconnect clocks. 1510 * 1511 * Set an initial peak bandwidth corresponding to single-lane Gen 1 1512 * for the pcie-mem path. 1513 */ 1514 ret = icc_set_bw(pcie->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1)); 1515 if (ret) { 1516 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1517 ret); 1518 return ret; 1519 } 1520 1521 /* 1522 * Since the CPU-PCIe path is only used for activities like register 1523 * access of the host controller and endpoint Config/BAR space access, 1524 * HW team has recommended to use a minimal bandwidth of 1KBps just to 1525 * keep the path active. 1526 */ 1527 ret = icc_set_bw(pcie->icc_cpu, 0, kBps_to_icc(1)); 1528 if (ret) { 1529 dev_err(pci->dev, "Failed to set bandwidth for CPU-PCIe interconnect path: %d\n", 1530 ret); 1531 icc_set_bw(pcie->icc_mem, 0, 0); 1532 return ret; 1533 } 1534 1535 return 0; 1536} 1537 1538static void qcom_pcie_icc_opp_update(struct qcom_pcie *pcie) 1539{ 1540 u32 offset, status, width, speed; 1541 struct dw_pcie *pci = pcie->pci; 1542 struct dev_pm_opp_key key = {}; 1543 unsigned long freq_kbps; 1544 struct dev_pm_opp *opp; 1545 int ret, freq_mbps; 1546 1547 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); 1548 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA); 1549 1550 /* Only update constraints if link is up. */ 1551 if (!(status & PCI_EXP_LNKSTA_DLLLA)) 1552 return; 1553 1554 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status); 1555 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status); 1556 1557 if (pcie->icc_mem) { 1558 ret = icc_set_bw(pcie->icc_mem, 0, 1559 width * QCOM_PCIE_LINK_SPEED_TO_BW(speed)); 1560 if (ret) { 1561 dev_err(pci->dev, "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1562 ret); 1563 } 1564 } else if (pcie->use_pm_opp) { 1565 freq_mbps = pcie_dev_speed_mbps(pcie_link_speed[speed]); 1566 if (freq_mbps < 0) 1567 return; 1568 1569 freq_kbps = freq_mbps * KILO; 1570 opp = dev_pm_opp_find_level_exact(pci->dev, speed); 1571 if (IS_ERR(opp)) { 1572 /* opp-level is not defined use only frequency */ 1573 opp = dev_pm_opp_find_freq_exact(pci->dev, freq_kbps * width, 1574 true); 1575 } else { 1576 /* put opp-level OPP */ 1577 dev_pm_opp_put(opp); 1578 1579 key.freq = freq_kbps * width; 1580 key.level = speed; 1581 key.bw = 0; 1582 opp = dev_pm_opp_find_key_exact(pci->dev, &key, true); 1583 } 1584 if (!IS_ERR(opp)) { 1585 ret = dev_pm_opp_set_opp(pci->dev, opp); 1586 if (ret) 1587 dev_err(pci->dev, "Failed to set OPP for freq (%lu): %d\n", 1588 freq_kbps * width, ret); 1589 dev_pm_opp_put(opp); 1590 } 1591 } 1592} 1593 1594static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) 1595{ 1596 struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); 1597 1598 seq_printf(s, "L0s transition count: %u\n", 1599 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L0S)); 1600 1601 seq_printf(s, "L1 transition count: %u\n", 1602 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L1)); 1603 1604 seq_printf(s, "L1.1 transition count: %u\n", 1605 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1)); 1606 1607 seq_printf(s, "L1.2 transition count: %u\n", 1608 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2)); 1609 1610 seq_printf(s, "L2 transition count: %u\n", 1611 readl_relaxed(pcie->mhi + PARF_DEBUG_CNT_PM_LINKST_IN_L2)); 1612 1613 return 0; 1614} 1615 1616static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) 1617{ 1618 struct dw_pcie *pci = pcie->pci; 1619 struct device *dev = pci->dev; 1620 char *name; 1621 1622 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node); 1623 if (!name) 1624 return; 1625 1626 pcie->debugfs = debugfs_create_dir(name, NULL); 1627 debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, 1628 qcom_pcie_link_transition_count); 1629} 1630 1631static void qcom_pci_free_msi(void *ptr) 1632{ 1633 struct dw_pcie_rp *pp = (struct dw_pcie_rp *)ptr; 1634 1635 if (pp && pp->has_msi_ctrl) 1636 dw_pcie_free_msi(pp); 1637} 1638 1639static int qcom_pcie_ecam_host_init(struct pci_config_window *cfg) 1640{ 1641 struct device *dev = cfg->parent; 1642 struct dw_pcie_rp *pp; 1643 struct dw_pcie *pci; 1644 int ret; 1645 1646 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1647 if (!pci) 1648 return -ENOMEM; 1649 1650 pci->dev = dev; 1651 pp = &pci->pp; 1652 pci->dbi_base = cfg->win; 1653 pp->num_vectors = MSI_DEF_NUM_VECTORS; 1654 1655 ret = dw_pcie_msi_host_init(pp); 1656 if (ret) 1657 return ret; 1658 1659 pp->has_msi_ctrl = true; 1660 dw_pcie_msi_init(pp); 1661 1662 return devm_add_action_or_reset(dev, qcom_pci_free_msi, pp); 1663} 1664 1665static const struct pci_ecam_ops pci_qcom_ecam_ops = { 1666 .init = qcom_pcie_ecam_host_init, 1667 .pci_ops = { 1668 .map_bus = pci_ecam_map_bus, 1669 .read = pci_generic_config_read, 1670 .write = pci_generic_config_write, 1671 } 1672}; 1673 1674static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node *node) 1675{ 1676 struct device *dev = pcie->pci->dev; 1677 struct qcom_pcie_port *port; 1678 struct gpio_desc *reset; 1679 struct phy *phy; 1680 int ret; 1681 1682 reset = devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), 1683 "reset", GPIOD_OUT_HIGH, "PERST#"); 1684 if (IS_ERR(reset)) 1685 return PTR_ERR(reset); 1686 1687 phy = devm_of_phy_get(dev, node, NULL); 1688 if (IS_ERR(phy)) 1689 return PTR_ERR(phy); 1690 1691 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1692 if (!port) 1693 return -ENOMEM; 1694 1695 ret = phy_init(phy); 1696 if (ret) 1697 return ret; 1698 1699 port->reset = reset; 1700 port->phy = phy; 1701 INIT_LIST_HEAD(&port->list); 1702 list_add_tail(&port->list, &pcie->ports); 1703 1704 return 0; 1705} 1706 1707static int qcom_pcie_parse_ports(struct qcom_pcie *pcie) 1708{ 1709 struct device *dev = pcie->pci->dev; 1710 struct qcom_pcie_port *port, *tmp; 1711 int ret = -ENOENT; 1712 1713 for_each_available_child_of_node_scoped(dev->of_node, of_port) { 1714 if (!of_node_is_type(of_port, "pci")) 1715 continue; 1716 ret = qcom_pcie_parse_port(pcie, of_port); 1717 if (ret) 1718 goto err_port_del; 1719 } 1720 1721 return ret; 1722 1723err_port_del: 1724 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1725 phy_exit(port->phy); 1726 list_del(&port->list); 1727 } 1728 1729 return ret; 1730} 1731 1732static int qcom_pcie_parse_legacy_binding(struct qcom_pcie *pcie) 1733{ 1734 struct device *dev = pcie->pci->dev; 1735 struct qcom_pcie_port *port; 1736 struct gpio_desc *reset; 1737 struct phy *phy; 1738 int ret; 1739 1740 phy = devm_phy_optional_get(dev, "pciephy"); 1741 if (IS_ERR(phy)) 1742 return PTR_ERR(phy); 1743 1744 reset = devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); 1745 if (IS_ERR(reset)) 1746 return PTR_ERR(reset); 1747 1748 ret = phy_init(phy); 1749 if (ret) 1750 return ret; 1751 1752 port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); 1753 if (!port) 1754 return -ENOMEM; 1755 1756 port->reset = reset; 1757 port->phy = phy; 1758 INIT_LIST_HEAD(&port->list); 1759 list_add_tail(&port->list, &pcie->ports); 1760 1761 return 0; 1762} 1763 1764static int qcom_pcie_probe(struct platform_device *pdev) 1765{ 1766 const struct qcom_pcie_cfg *pcie_cfg; 1767 unsigned long max_freq = ULONG_MAX; 1768 struct qcom_pcie_port *port, *tmp; 1769 struct device *dev = &pdev->dev; 1770 struct dev_pm_opp *opp; 1771 struct qcom_pcie *pcie; 1772 struct dw_pcie_rp *pp; 1773 struct resource *res; 1774 struct dw_pcie *pci; 1775 int ret; 1776 1777 pcie_cfg = of_device_get_match_data(dev); 1778 if (!pcie_cfg) { 1779 dev_err(dev, "No platform data\n"); 1780 return -ENODATA; 1781 } 1782 1783 if (!pcie_cfg->firmware_managed && !pcie_cfg->ops) { 1784 dev_err(dev, "No platform ops\n"); 1785 return -ENODATA; 1786 } 1787 1788 pm_runtime_enable(dev); 1789 ret = pm_runtime_get_sync(dev); 1790 if (ret < 0) 1791 goto err_pm_runtime_put; 1792 1793 if (pcie_cfg->firmware_managed) { 1794 struct pci_host_bridge *bridge; 1795 struct pci_config_window *cfg; 1796 1797 bridge = devm_pci_alloc_host_bridge(dev, 0); 1798 if (!bridge) { 1799 ret = -ENOMEM; 1800 goto err_pm_runtime_put; 1801 } 1802 1803 /* Parse and map our ECAM configuration space area */ 1804 cfg = pci_host_common_ecam_create(dev, bridge, 1805 &pci_qcom_ecam_ops); 1806 if (IS_ERR(cfg)) { 1807 ret = PTR_ERR(cfg); 1808 goto err_pm_runtime_put; 1809 } 1810 1811 bridge->sysdata = cfg; 1812 bridge->ops = (struct pci_ops *)&pci_qcom_ecam_ops.pci_ops; 1813 bridge->msi_domain = true; 1814 1815 ret = pci_host_probe(bridge); 1816 if (ret) 1817 goto err_pm_runtime_put; 1818 1819 return 0; 1820 } 1821 1822 pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); 1823 if (!pcie) { 1824 ret = -ENOMEM; 1825 goto err_pm_runtime_put; 1826 } 1827 1828 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL); 1829 if (!pci) { 1830 ret = -ENOMEM; 1831 goto err_pm_runtime_put; 1832 } 1833 1834 INIT_LIST_HEAD(&pcie->ports); 1835 1836 pci->dev = dev; 1837 pci->ops = &dw_pcie_ops; 1838 pp = &pci->pp; 1839 1840 pcie->pci = pci; 1841 1842 pcie->cfg = pcie_cfg; 1843 1844 pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf"); 1845 if (IS_ERR(pcie->parf)) { 1846 ret = PTR_ERR(pcie->parf); 1847 goto err_pm_runtime_put; 1848 } 1849 1850 /* MHI region is optional */ 1851 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mhi"); 1852 if (res) { 1853 pcie->mhi = devm_ioremap_resource(dev, res); 1854 if (IS_ERR(pcie->mhi)) { 1855 ret = PTR_ERR(pcie->mhi); 1856 goto err_pm_runtime_put; 1857 } 1858 } 1859 1860 /* OPP table is optional */ 1861 ret = devm_pm_opp_of_add_table(dev); 1862 if (ret && ret != -ENODEV) { 1863 dev_err_probe(dev, ret, "Failed to add OPP table\n"); 1864 goto err_pm_runtime_put; 1865 } 1866 1867 /* 1868 * Before the PCIe link is initialized, vote for highest OPP in the OPP 1869 * table, so that we are voting for maximum voltage corner for the 1870 * link to come up in maximum supported speed. At the end of the 1871 * probe(), OPP will be updated using qcom_pcie_icc_opp_update(). 1872 */ 1873 if (!ret) { 1874 opp = dev_pm_opp_find_freq_floor(dev, &max_freq); 1875 if (IS_ERR(opp)) { 1876 ret = PTR_ERR(opp); 1877 dev_err_probe(pci->dev, ret, 1878 "Unable to find max freq OPP\n"); 1879 goto err_pm_runtime_put; 1880 } else { 1881 ret = dev_pm_opp_set_opp(dev, opp); 1882 } 1883 1884 dev_pm_opp_put(opp); 1885 if (ret) { 1886 dev_err_probe(pci->dev, ret, 1887 "Failed to set OPP for freq %lu\n", 1888 max_freq); 1889 goto err_pm_runtime_put; 1890 } 1891 1892 pcie->use_pm_opp = true; 1893 } else { 1894 /* Skip ICC init if OPP is supported as it is handled by OPP */ 1895 ret = qcom_pcie_icc_init(pcie); 1896 if (ret) 1897 goto err_pm_runtime_put; 1898 } 1899 1900 ret = pcie->cfg->ops->get_resources(pcie); 1901 if (ret) 1902 goto err_pm_runtime_put; 1903 1904 pp->ops = &qcom_pcie_dw_ops; 1905 1906 ret = qcom_pcie_parse_ports(pcie); 1907 if (ret) { 1908 if (ret != -ENOENT) { 1909 dev_err_probe(pci->dev, ret, 1910 "Failed to parse Root Port: %d\n", ret); 1911 goto err_pm_runtime_put; 1912 } 1913 1914 /* 1915 * In the case of properties not populated in Root Port node, 1916 * fallback to the legacy method of parsing the Host Bridge 1917 * node. This is to maintain DT backwards compatibility. 1918 */ 1919 ret = qcom_pcie_parse_legacy_binding(pcie); 1920 if (ret) 1921 goto err_pm_runtime_put; 1922 } 1923 1924 platform_set_drvdata(pdev, pcie); 1925 1926 ret = dw_pcie_host_init(pp); 1927 if (ret) { 1928 dev_err(dev, "cannot initialize host\n"); 1929 goto err_phy_exit; 1930 } 1931 1932 qcom_pcie_icc_opp_update(pcie); 1933 1934 if (pcie->mhi) 1935 qcom_pcie_init_debugfs(pcie); 1936 1937 return 0; 1938 1939err_phy_exit: 1940 list_for_each_entry_safe(port, tmp, &pcie->ports, list) { 1941 phy_exit(port->phy); 1942 list_del(&port->list); 1943 } 1944err_pm_runtime_put: 1945 pm_runtime_put(dev); 1946 pm_runtime_disable(dev); 1947 1948 return ret; 1949} 1950 1951static int qcom_pcie_suspend_noirq(struct device *dev) 1952{ 1953 struct qcom_pcie *pcie; 1954 int ret = 0; 1955 1956 pcie = dev_get_drvdata(dev); 1957 if (!pcie) 1958 return 0; 1959 1960 /* 1961 * Set minimum bandwidth required to keep data path functional during 1962 * suspend. 1963 */ 1964 if (pcie->icc_mem) { 1965 ret = icc_set_bw(pcie->icc_mem, 0, kBps_to_icc(1)); 1966 if (ret) { 1967 dev_err(dev, 1968 "Failed to set bandwidth for PCIe-MEM interconnect path: %d\n", 1969 ret); 1970 return ret; 1971 } 1972 } 1973 1974 /* 1975 * Turn OFF the resources only for controllers without active PCIe 1976 * devices. For controllers with active devices, the resources are kept 1977 * ON and the link is expected to be in L0/L1 (sub)states. 1978 * 1979 * Turning OFF the resources for controllers with active PCIe devices 1980 * will trigger access violation during the end of the suspend cycle, 1981 * as kernel tries to access the PCIe devices config space for masking 1982 * MSIs. 1983 * 1984 * Also, it is not desirable to put the link into L2/L3 state as that 1985 * implies VDD supply will be removed and the devices may go into 1986 * powerdown state. This will affect the lifetime of the storage devices 1987 * like NVMe. 1988 */ 1989 if (!dw_pcie_link_up(pcie->pci)) { 1990 qcom_pcie_host_deinit(&pcie->pci->pp); 1991 pcie->suspended = true; 1992 } 1993 1994 /* 1995 * Only disable CPU-PCIe interconnect path if the suspend is non-S2RAM. 1996 * Because on some platforms, DBI access can happen very late during the 1997 * S2RAM and a non-active CPU-PCIe interconnect path may lead to NoC 1998 * error. 1999 */ 2000 if (pm_suspend_target_state != PM_SUSPEND_MEM) { 2001 ret = icc_disable(pcie->icc_cpu); 2002 if (ret) 2003 dev_err(dev, "Failed to disable CPU-PCIe interconnect path: %d\n", ret); 2004 2005 if (pcie->use_pm_opp) 2006 dev_pm_opp_set_opp(pcie->pci->dev, NULL); 2007 } 2008 return ret; 2009} 2010 2011static int qcom_pcie_resume_noirq(struct device *dev) 2012{ 2013 struct qcom_pcie *pcie; 2014 int ret; 2015 2016 pcie = dev_get_drvdata(dev); 2017 if (!pcie) 2018 return 0; 2019 2020 if (pm_suspend_target_state != PM_SUSPEND_MEM) { 2021 ret = icc_enable(pcie->icc_cpu); 2022 if (ret) { 2023 dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); 2024 return ret; 2025 } 2026 } 2027 2028 if (pcie->suspended) { 2029 ret = qcom_pcie_host_init(&pcie->pci->pp); 2030 if (ret) 2031 return ret; 2032 2033 pcie->suspended = false; 2034 } 2035 2036 qcom_pcie_icc_opp_update(pcie); 2037 2038 return 0; 2039} 2040 2041static const struct of_device_id qcom_pcie_match[] = { 2042 { .compatible = "qcom,pcie-apq8064", .data = &cfg_2_1_0 }, 2043 { .compatible = "qcom,pcie-apq8084", .data = &cfg_1_0_0 }, 2044 { .compatible = "qcom,pcie-ipq4019", .data = &cfg_2_4_0 }, 2045 { .compatible = "qcom,pcie-ipq5018", .data = &cfg_2_9_0 }, 2046 { .compatible = "qcom,pcie-ipq6018", .data = &cfg_2_9_0 }, 2047 { .compatible = "qcom,pcie-ipq8064", .data = &cfg_2_1_0 }, 2048 { .compatible = "qcom,pcie-ipq8064-v2", .data = &cfg_2_1_0 }, 2049 { .compatible = "qcom,pcie-ipq8074", .data = &cfg_2_3_3 }, 2050 { .compatible = "qcom,pcie-ipq8074-gen3", .data = &cfg_2_9_0 }, 2051 { .compatible = "qcom,pcie-ipq9574", .data = &cfg_2_9_0 }, 2052 { .compatible = "qcom,pcie-msm8996", .data = &cfg_2_3_2 }, 2053 { .compatible = "qcom,pcie-qcs404", .data = &cfg_2_4_0 }, 2054 { .compatible = "qcom,pcie-sa8255p", .data = &cfg_fw_managed }, 2055 { .compatible = "qcom,pcie-sa8540p", .data = &cfg_sc8280xp }, 2056 { .compatible = "qcom,pcie-sa8775p", .data = &cfg_1_34_0}, 2057 { .compatible = "qcom,pcie-sc7280", .data = &cfg_1_9_0 }, 2058 { .compatible = "qcom,pcie-sc8180x", .data = &cfg_1_9_0 }, 2059 { .compatible = "qcom,pcie-sc8280xp", .data = &cfg_sc8280xp }, 2060 { .compatible = "qcom,pcie-sdm845", .data = &cfg_2_7_0 }, 2061 { .compatible = "qcom,pcie-sdx55", .data = &cfg_1_9_0 }, 2062 { .compatible = "qcom,pcie-sm8150", .data = &cfg_1_9_0 }, 2063 { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, 2064 { .compatible = "qcom,pcie-sm8350", .data = &cfg_1_9_0 }, 2065 { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, 2066 { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, 2067 { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, 2068 { .compatible = "qcom,pcie-x1e80100", .data = &cfg_sc8280xp }, 2069 { } 2070}; 2071 2072static void qcom_fixup_class(struct pci_dev *dev) 2073{ 2074 dev->class = PCI_CLASS_BRIDGE_PCI_NORMAL; 2075} 2076DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0101, qcom_fixup_class); 2077DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0104, qcom_fixup_class); 2078DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0106, qcom_fixup_class); 2079DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0107, qcom_fixup_class); 2080DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x0302, qcom_fixup_class); 2081DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1000, qcom_fixup_class); 2082DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_QCOM, 0x1001, qcom_fixup_class); 2083 2084static const struct dev_pm_ops qcom_pcie_pm_ops = { 2085 NOIRQ_SYSTEM_SLEEP_PM_OPS(qcom_pcie_suspend_noirq, qcom_pcie_resume_noirq) 2086}; 2087 2088static struct platform_driver qcom_pcie_driver = { 2089 .probe = qcom_pcie_probe, 2090 .driver = { 2091 .name = "qcom-pcie", 2092 .suppress_bind_attrs = true, 2093 .of_match_table = qcom_pcie_match, 2094 .pm = &qcom_pcie_pm_ops, 2095 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2096 }, 2097}; 2098builtin_platform_driver(qcom_pcie_driver);
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